Renesas M38230GC-XXXFP Single-chip 8-bit cmos microcomputer Datasheet

3823 Group
REJ03B0146-0202
Rev.2.02
Jun.19.2007
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 3823 group is the 8-bit microcomputer based on the 740 family core technology.
The 3823 group has the LCD drive control circuit, an 8-channel A/
D converter, a serial interface, a watchdog timer, a ROM correction function, and as additional functions.
The various microcomputers in the 3823 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
FEATURES
●Basic machine-language instructions ...................................... 71
●The minimum instruction execution time ........................... 0.4 µs
(at f(XIN) = 10 MHz, High-speed mode)
●Memory size
ROM ............................................................... 16 K to 60 K bytes
RAM ................................................................. 640 to 2560 bytes
●ROM correction function .............................. 32 bytes ✕ 2 blocks
●Watchdog timer .............................................................. 8-bit ✕ 1
●Programmable input/output ports ............................................ 49
●Input ports .................................................................................. 5
●Software pull-up/pull-down resistors (Ports P0-P7 except port P4 0)
●Interrupts ................................................. 17 sources, 16 vectors
(includes key input interrupt)
●Key Input Interrupt (Key-on Wake-Up) ...................................... 8
●Timers ........................................................... 8-bit ✕ 3, 16-bit ✕ 2
●Serial interface ............ 8-bit ✕ 1 (UART or Clock-synchronized)
●A/D converter ............ 10-bit ✕ 8 channels or 8-bit ✕ 8 channels
●LCD drive control circuit
Bias ................................................................................... 1/2, 1/3
Duty ........................................................................... 1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output ........................................................................ 32
●Main clock generating circuits .............. Built-in feedback resistor
(connect to external ceramic resonator or quartz-crystal oscillator)
●Sub-clock generating circuits
(connect to external quartz-crystal oscillator or on-chip oscillator)
●Power source voltage
In frequency/2 mode (f(XIN) ≤ 10 MHz) ................... 4.5 to 5.5 V
In frequency/2 mode (f(XIN) ≤ 8 MHz) ..................... 4.0 to 5.5 V
In frequency/4 mode (f(XIN) ≤ 10 MHz) ................... 2.5 to 5.5 V
In frequency/4 mode (f(XIN) ≤ 8 MHz) ..................... 2.0 to 5.5 V
In frequency/4 mode (f(XIN) ≤ 5 MHz) ..................... 1.8 to 5.5 V
In frequency/8 mode (f(XIN) ≤ 10 MHz) ................... 2.5 to 5.5 V
In frequency/8 mode (f(XIN) ≤ 8 MHz) ..................... 2.0 to 5.5 V
In frequency/8 mode (f(XIN) ≤ 5 MHz) ..................... 1.8 to 5.5 V
In low-speed mode .................................................... 1.8 to 5.5 V
●Power dissipation
In frequency/2 mode ............................................... 18 mW (std.)
(at f(XIN) = 8 MHz, Vcc = 5 V, Ta = 25 °C)
In low-speed mode at XCIN ................................................ 18 µW (std.)
(at f(XIN) stopped, f(XCIN) = 32 kHz, Vcc = 2.5 V, Ta = 25 °C)
In low-speed mode at on-chip oscillator .................. 35 µW (std.)
(at f(XIN) stopped, f(XCIN) = stopped, Vcc = 2.5 V, Ta = 25 °C)
●Operating temperature range .................................. – 20 to 85 °C
APPLICATIONS
Camera, audio equipment, household appliances, consumer electronics, etc.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 1 of 73
3823 Group
SEG8
SEG9
SEG10
SEG11
P34/SEG12
P35/SEG13
P36/SEG14
P37/SEG15
P00/SEG16
P01/SEG17
P02/SEG18
P03/SEG19
P04/SEG20
P05/SEG21
P06/SEG22
P07/SEG23
P10/SEG24
P11/SEG25
P12/SEG26
P13/SEG27
P14/SEG28
P15/SEG29
P16/SEG30
P17/SEG31
PIN CONFIGURATION (TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VCC
VREF
AVSS
COM3
COM2
COM1
COM0
VL3
65
40
66
67
68
39
38
37
36
35
34
69
70
71
72
M3823XGX-XXXFP
M3823XGXFP
73
74
75
33
32
31
30
29
28
76
77
78
79
80
27
26
25
P20/KW0
P21/KW1
P22/KW2
P23/KW3
P24/KW4
P25/KW5
P26/KW6
P27/KW7
VSS
XOUT
XIN
P70/XCOUT
P71/XCIN
RESET
P40
P41/φ
VL2
VL1
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P57/ADT
P56/TOUT
P55/CNTR1
P54/CNTR0
P53/RTP1
P52/RTP0
P51/INT3
P50/INT2
P47/SRDY/SOUT
P46/SCLK
P45/TXD
P44/RXD
P43/INT1
P42/INT0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Package code : PRQP0080GB-A (80P6N-A) (80-pin plastic-molded QFP)
Fig. 1 M3823XGX-XXXFP pin configuration
42
41
44
43
52
51
50
49
48
47
46
45
55
40
39
38
37
36
35
61
62
63
64
65
66
67
68
69
70
34
33
32
31
30
29
28
27
26
25
24
23
M3823XGX-XXXHP
M3823XGXHP
71
72
73
74
75
76
77
78
79
22
21
20
19
18
17
15
16
11
12
13
14
8
9
10
7
4
5
6
P16/SEG30
P17/SEG31
P20/KW0
P21/KW1
P22/KW2
P23/KW3
P24/KW4
P25/KW5
P26/KW6
P27/KW7
VSS
XOUT
XIN
P70/XCOUT
P71/XCIN
RESET
P40
P41/φ
P42/INT0
P43/INT1
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P57/ADT
P56/TOUT
P55/CNTR1
P54/CNTR0
P53/RTP1
P52/RTP0
P51/INT3
P50/INT2
P47/SRDY/SOUT
P46/SCLK
P45/TXD
P44/RXD
3
80
1
2
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VCC
VREF
AVSS
COM3
COM2
COM1
COM0
VL3
VL2
VL1
54
53
60
59
58
57
56
SEG10
SEG11
P34/SEG12
P35/SEG13
P36/SEG14
P37/SEG15
P00/SEG16
P01/SEG17
P02/SEG18
P03/SEG19
P04/SEG20
P05/SEG21
P06/SEG22
P07/SEG23
P10/SEG24
P11/SEG25
P12/SEG26
P13/SEG27
P14/SEG28
P15/SEG29
PIN CONFIGURATION (TOP VIEW)
Package code : PLQP0080KB-A (80P6Q-A) (80-pin plastic-molded LQFP)
Fig. 2 M3823XGX-XXXHP pin configuration
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 2 of 73
3823 Group
Table 1 Performance overview
Function
Parameter
Number of basic instructions
71
Instruction execution time
0.4 µs (Minimum instruction, f(XIN) 10 MHz, High-speed mode)
Oscillation frequency
10 MHz (Maximum)
Memory sizes
ROM
16 K to 60 K bytes
RAM
640 to 2560 bytes
Input port
P34-P37, P40
4-bit ✕ 1, 1-bit ✕ 1
I/O port
P0-P2, P41-P47, P5, P6, P70, P71
(4 pins sharing SEG)
8-bit ✕ 5, 7-bit ✕ 1, 2 bit ✕ 1
(16 pins sharing SEG)
17 sources, 16 vectors (includes key input interrupt)
Interrupt
Timer
8-bit ✕ 3, 16-bit ✕ 2
Serial interface
8-bit ✕ 1 (UART or Clock-synchronized)
A/D converter
10-bit ✕ 8 channels or 8 bit ✕ 8 channels
Watchdog timer
8-bit ✕ 1
ROM correction function
32 bytes ✕ 2 blocks
LCD drive control
circuit
Bias
1/2, 1/3
Duty
2, 3, 4
Common output
4
Segment output
32
Main clock generating circuits
Built-in feedback resistor
(connect to external ceramic rasonator or quartz-crystal oscillator)
Sub-clock generating circuits
Built-in feedback resistor
(connect to external quartz-crystal oscillator or on-chip oscillator)
Power source voltage
Power dissipation
Input/Output
characteristics
In frequency/2 mode (f(XIN) ≤ 10MHz)
4.5 to 5.5V
In frequency/2 mode (f(XIN) ≤ 8MHz)
4.0 to 5.5V
In frequency/4 mode (f(XIN) ≤ 10MHz)
2.5 to 5.5V
In frequency/4 mode (f(XIN) ≤ 8MHz)
2.0 to 5.5V
In frequency/4 mode (f(XIN) ≤ 5MHz)
1.8 to 5.5V
In frequency/8 mode (f(XIN) ≤ 10MHz)
2.5 to 5.5V
In frequency/8 mode (f(XIN) ≤ 8MHz)
2.0 to 5.5V
In frequency/8 mode (f(XIN) ≤ 5MHz)
1.8 to 5.5V
In low-speed mode
1.8 to 5.5V
In frequency/2 mode
Std. 18 mW (Vcc = 5V, f(XIN) = 8MHz, Ta = 25 °C)
In low-speed mode at XCIN
Std. 18 µW (Vcc = 2.5V, f(XIN) = stopped, f(XCIN) = 32kHz, Ta = 25 °C)
In low-speed mode at on-chip oscillator
Std. 35 µW (Vcc = 2.5V, f(XIN) = stopped, f(XCIN) = stopped, Ta = 25 °C)
Input/Output withstand voltage
VCC
Output current
10mA
Operating temperature range
-20 to 85 °C
Device structure
CMOS sillicon gate
Package
80-pin plastic molded LQFP/QFP
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 3 of 73
XCIN
26 27
P7(2)
Clock generating
circuit
29
1
2
Watchdog
timer
5
6
7
8
A/D converter
(10/8)
Reset
I/O Port P6
3 4
P6(8)
XCIN
XCOUT
φ
Sub-Clock Sub-Clock
Input
Output
I/O Port P7
XCOUT
On-chip
oscillator
28
Main Clock Main Clock
Output XOUT
Input XIN
9 10 11 12 13 14 15 16
I/O Port P5
P5(8)
CNTR0,CNTR1
TOUT
PS
PCL
S
Y
X
A
72 73
PCH
C P U
25
RTP0,RTP1
Reset Input
RESET
VREF
AVSS
(0V)
ADT
page 4 of 73
INT2,INT3
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
I/O Port P4
17 18 19 20 21 22 23 24
Input Port P3
55 56 57 58
P3(4)
Timer 3(8)
Timer 2(8)
Timer Y(16)
Timer X(16)
ROM
Timer 1(8)
30
(0V)
VSS
SI/O(8)
Data bus
P4(8)
71
(5V)
VCC
INT0,INT1
φ,XCIN
Fig. 3 Functional block diagram
I/O Port P2
31 32 33 34 35 36 37 38
P2(8)
LCD display
RAM
(16 bytes)
RAM
P1(8)
I/O Port P1
P0(8)
I/O Port P0
47 48 49 50 51 52 53 54
LCD
drive control
circuit
39 40 41 42 43 44 45 46
ROM
correction
function
Key on wake up
FUNCTIONAL BLOCK DIAGRAM (Package type : PLQP0080KB-A)
79
80
VL 1
VL 2
VL 3
SEG0
SEG1
SEG2
67 SEG3
66 SEG4
65 SEG5
64 SEG6
63 SEG7
62 SEG8
61 SEG9
60 SEG10
59 SEG11
68
69
70
75
76
COM0
COM1
COM2
74
COM3
77
78
3823 Group
Real time port function
3823 Group
PIN DESCRIPTION
Table 2 Pin description (1)
Pin
Name
Function
Function except a port function
VCC, VSS
Power source
•Apply voltage of power source to VCC, and 0 V to VSS . (For the limits of VCC, refer to “Recommended operating conditions”).
VREF
Analog reference voltage
•Reference voltage input pin for A/D converter.
AVSS
Analog power
source
•GND input pin for A/D converter.
RESET
XIN
Reset input
•Reset input pin for active “L”.
Clock input
•Input and output pins for the main clock generating circuit.
XOUT
Clock output
•Connect to VSS.
•Feedback resistor is built in between XIN pin and XOUT pin.
•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
•This clock is used as the oscillating source of system clock.
VL1–VL3
LCD power
source
COM0–COM3
Common output
•Input 0 ≤ VL1 ≤ VL2 ≤ VL3 voltage.
•Input 0 – VL3 voltage to LCD.
•LCD common output pins.
•COM2 and COM3 are not used at 1/2 duty ratio.
•COM3 is not used at 1/3 duty ratio.
SEG0–SEG11
P00/SEG16–
P07/SEG23
Segment output
•LCD segment output pins.
I/O port P0
•8-bit I/O port.
•LCD segment output pins
•CMOS compatible input level.
•CMOS 3-state output structure.
P10/SEG24–
P17/SEG31
I/O port P1
P20/KW0 –
P27/KW7
I/O port P2
•I/O direction register allows each port to be individually
programmed as either input or output.
•Pull-down control is enabled.
•8-bit I/O port.
•CMOS compatible input level.
•Key input (key-on wake-up) interrupt
input pins
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
P34/SEG12 –
P37/SEG15
Input port P3
•4-bit input port.
•CMOS compatible input level.
•Pull-down control is enabled.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 5 of 73
•LCD segment output pins
3823 Group
Table 3 Pin description (2)
Pin
P40
Name
Input port P4
Function
•1-bit Input port.
Function except a port function
•QzROM program power pin
•CMOS compatible input level.
•7-bit I/O port.
•φ clock output pin
P42/INT0,
P43/INT1
P44/RXD,
P45/TXD,
P46/SCLK,
P47/SRDY/SOUT
I/O port P5
P50/INT2,
P51/INT3
•CMOS compatible input level.
•Interrupt input pins
P52/RTP0,
P53/RTP1
•CMOS 3-state output structure.
P41/φ
I/O port P4
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•8-bit I/O port.
•Pull-up control is enabled.
P56/TOUT
•Real time port function pins
•Timer X, Y function pins
•Timer 2 output pins
•A/D trigger input pins
P57/ADT
P60/AN0–
P67/AN7
•Interrupt input pins
•CMOS compatible input level.
•I/O direction register allows each pin to be individually
programmed as either input or output.
P54/CNTR0,
P55/CNTR1
•Serial interface function pins
I/O port P6
•8-bit I/O port.
•A/D conversion input pins
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
P70/XCOUT,
P71/XCIN
I/O port P7
•2-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 6 of 73
•Sub-clock generating circuit I/O pins.
(Connect a resonator. External clock
cannot be used.)
3823 Group
PART NUMBERING
Product
M3823 4 G
6
-XXX
FP
Package code
FP : PRQP0080GB-A package
HP : PLQP0080KB-A package
ROM number
Omitted in the shipped in blank version.
ROM/PROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
9:
A:
B:
C:
D:
E:
F:
36864 bytes
40960 bytes
45056 bytes
49152 bytes
53248 bytes
57344 bytes
61440 bytes
The first 128 bites and the last 2 bytes of ROM are
reserved areas ; they cannot be used.
Memory type
G : QzROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
A : 2560 bytes
Fig. 4 Part numbering
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 7 of 73
3823 Group
GROUP EXPANSION
Package
Mitsubishi plans to expand the 3823 group as follows:
PRQP0080GB-A ........................ 0.8 mm-pitch plastic molded QFP
PLQP0080KB-A ....................... 0.5 mm-pitch plastic molded LQFP
Memory Type
Support for QzROM version.
Memory Size
ROM size ........................................................... 16 K to 60 K bytes
RAM size ............................................................ 640 to 2560 bytes
Memory Expansion Plan
ROM size (bytes)
Mass production
M3823AGF
60K
56K
Mass production
M38239GC
48K
40K
Mass production
32K
M38238G8
28K
Mass production
M38235G6
24K
20K
Mass production
16K
M38234G4
12K
8K
4K
192 256
384
512
640
768
896
RAM size (bytes)
Fig. 5 Memory expansion plan
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 8 of 73
1,024
1,536
2,048
2,560
3823 Group
Currently products are listed below.
Table 4 List of products
Part No.
M3823AGF-XXXFP
M3823AGF-XXXHP
M3823AGFFP
M3823AGFHP
M38239GC-XXXFP
M38239GC-XXXHP
M38239GCFP
M38239GCHP
M38238G8-XXXFP
M38238G8-XXXHP
M38238G8FP
M38238G8HP
M38235G6-XXXFP
M38235G6-XXXHP
M38235G6FP
M38235G6HP
M38234G4-XXXFP
M38234G4-XXXHP
M38234G4FP
M38234G4HP
ROM size (bytes) ROM
size for User in ( )
RAM size
(bytes)
61440
(61310)
2560
(Note 1)
49152
(49022)
2048
(Note 2)
32768
(32638)
1536
(Note 2)
24576
(24446)
768
(Note 2)
16384
(16254)
640
(Note 2)
Note 1: RAM size includes RAM for LCD display and ROM corrections.
Note 2: RAM size includes RAM for LCD display.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 9 of 73
Package
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
Remarks
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
3823 Group
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
[Stack Pointer (S)]
The 3823 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
The central processing unit (CPU) has six registers. Figure 6
shows the 740 Family CPU register structure.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 7.
Store registers other than those described in Table 4 with program
when the user needs them during interrupts or subroutine calls.
[Program Counter (PC)]
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b0
b7
Y
b7
Index register Y
b0
S
b15
b7
PCH
Stack pointer
b0
Program counter
PCL
b7
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 6 740 Family CPU register structure
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 10 of 73
3823 Group
On-going Routine
Interrupt request
(Note)
M (S)
Execute JSR
Push return address
on stack
M (S)
(PCH)
(S)
(S) – 1
M (S)
(PCL)
(S)
(S)– 1
(S)
M (S)
(S)
M (S)
(S)
Subroutine
POP return
address from stack
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
(S) – 1
(PCL)
Push return address
on stack
(S) – 1
(PS)
Push contents of processor
status register on stack
(S) – 1
Interrupt
Service Routine
Execute RTS
(S)
(PCH)
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTI
Note: Condition for acceptance of an interrupt
(S)
(S) + 1
(PS)
M (S)
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
POP contents of
processor status
register from stack
POP return
address
from stack
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 7 Register push and pop at interrupt generation and subroutine call
Table 5 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PLA
Processor status register
PHP
PLP
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 11 of 73
3823 Group
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 6 Set and clear instructions of each bit of processor status register
C flag
Z flag
I flag
D flag
B flag
T flag
V flag
N flag
Set instruction
SEC
–
SEI
SED
–
SET
–
–
Clear instruction
CLC
–
CLI
CLD
–
CLT
CLV
–
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 12 of 73
3823 Group
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM (CM) : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 : Not available
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit)
Port XC switch bit (Note 1)
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit (Note 2)
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : f(XIN)/2 (frequency/2 mode), or f(XIN)/4 (frequency/4 mode) (Note 3)
1 : f(XIN)/8 (frequency/8 mode)
Internal system clock selection bit
0 : XIN–XOUT selected (frequency/2/4/8 mode)
1 : XCIN–XCOUT, or on-chip oscillator selected (low-speed mode) (Note 4)
Note 1: In low speed mode (XCIN is selected as the system clock φ), XCIN-XCOUT oscillation does not stop even if the port XC
switch bit is set to "0".
2: In frequency/2/4/8 mode, XIN-XOUT oscillation does not stop even if the main clock (XIN-XOUT) stop bit is set to "1".
3: When the system clock φ is divided by 4 of f(XIN), set the bit 6 in the CPU mode register to “0” after setting the bit 1
in the CPU mode extension register to “1”.
4: When using the on-chip oscillator in low-speed mode, set the bit 7 in the CPU mode register to “1” after setting the
bit 0 in the CPU mode extension register to “1”.
Fig. 8 Structure of CPU mode register
[CPU Mode Extension Register (EXPCM)] 002B16
f(XIN) divided by 4 for the system clock f and the on-chip oscillator
for the system clock f in low-speed mode can be selected by setting the CPU mode extension register. When the system clock f is
divided by 4 of f(XIN), set the bit 6 in the CPU mode register to “0”
after setting the bit 1 in the CPU mode extension register to “1”.
When using the on-chip oscillator in low-speed mode, set the bit 7
in the CPU mode register to “1” after setting the bit 0 in the CPU
mode extension register to “1”.
b7
b0
CPU mode extension register
(EXPCM : address 002B16)
On-chip oscillator control bit
0 : On-chip oscillator not used
(On -chip oscillator sotpping)
1 : On-chip oscillator used (Note 1)
(On -chip oscillator oscillating)
Frequency/4 mode control bit (Note 2)
0 : Frequency/2 mode φ = f(XIN)/2
1 : Frequency/4 mode φ = f(XIN)/4
Not used (returns “0” when read)
(Do not write “1” to this bit)
Note 1 : The on-chip oscillator is selected for the operation clock in low-speed mod regardless
of XCIN-XCOUT.
2 : Valid only when the main clock division ratio selection bit (bit 6 in the CPU mode
register) is set to "0".
When "1" (frequency/8 mode) is selected for the main clock division ratio selection bit or
when the internal system clock selection bit is set to 1, set "0" to the frequency/4 mode
control bit.
Fig. 9 Structure of CPU mode extension register
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 13 of 73
3823 Group
MEMORY
Special Function Register (SFR) Area
ROM Code Protect Address
“0016” is written into ROM code protect address (other than the
user ROM area) when selecting the protect bit write by using a serial programmer or selecting protect enabled for writing shipment
by Renesas Technology corp.. When “00 16” is set to the ROM
code protect address, the protect function is enabled, so that reading or writing from/to QzROM is disabled by a serial programmer.
As for the QzROM product in blank, the ROM code is protected by
selecting the protect bit write at ROM writing with a serial programmer.
As for the QzROM product shipped after writing, “0016” (protect
enabled) or “FF16” (protect disabled) is written into the ROM code
protect address when Renesas Technology corp. performs writing.
The writing of “00 16" or “FF16” can be selected as ROM option
setup (“MASK option” written in the mask file converter) when ordering.
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function register (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area.
Access to this area with only 2 bytes is possible in the special
page addressing mode.
RAM area
RAM size
(bytes)
000016
Address
XXXX16
SFR area
640
02BF16
004016
768
033F16
005016
1536
063F16
2048
083F16
2560
0A3F16
RAM
Zero page
LCD display RAM area
010016
XXXX16
0A0016
RAM 1 for ROM correction
RAM for ROM correction
ROM area
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
16384
C00016
C08016
24576
A00016
A08016
32768
800016
808016
49152
400016
408016
61440
100016
108016
0A1F16
0A2016
RAM 2 for ROM correction
0A4016
0A3F16
Not used
YYYY16
Reserved ROM area
ZZZZ16
ROM
FF0016
FFDC16
Interrupt vector area
FFFE16
FFFF16
Fig. 10 Memory map diagram
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 14 of 73
Reserved ROM area
Special page
3823 Group
000016 Port P0 register (P0)
000116 Port P0 direction register (P0D)
000216 Port P1 register (P1)
000316 Port P1 direction register (P1D)
000416 Port P2 register (P2)
002016 Timer X low-order register (TXL)
002116 Timer X high-order register (TXH)
002216 Timer Y low-order register (TYL)
002316 Timer Y high-order register (TYH)
002416 Timer 1 register (T1)
000516 Port P2 direction register (P2D)
000616 Port P3 register (P3)
000716
002516 Timer 2 register (T2)
002616 Timer 3 register (T3)
002716 Timer X mode register (TXM)
000816 Port P4 register (P4)
000916 Port P4 direction register (P4D)
000A16 Port P5 register (P5)
000B16 Port P5 direction register (P5D)
002816 Timer Y mode register (TYM)
002916 Timer 123 mode register (T123M)
002A16 φ output control register (CKOUT)
000C16 Port P6 register (P6)
000D16 Port P6 direction register (P6D)
002B16 CPU mode expansion register (EXPCM)
002C16 Temporary data register 0 (TD0)
002D16 Temporary data register 1 (TD1)
000E16 Port P7 register (P7)
000F16 Port P7 direction register (P7D)
001016 ROM correction address 1 high-order register (RCA1H)
002E16 Temporary data register 2 (TD2)
002F16 RRF register (RRFR)
003016 Peripheral function expansion register (EXP)
001116 ROM correction
001216 ROM correction
001316 ROM correction
001416 ROM correction
address 1 low-order register (RCA1L)
address 2 high-order register (RCA2H)
003116
003216
address 2 low-order register (RCA2L)
enable register (RCR)
003316
001516
001616 PULL register A (PULLA)
001716 PULL register B (PULLB)
001816 Transmit/Receive buffer register(TB/RB)
001916 Serial I/O status register (SIOSTS)
001A16 Serial I/O control register (SIO1CON)
001B16 UART control register (UARTCON)
001C16 Baud rate generator (BRG)
001D16
001E16
003416 AD control register (ADCON)
003516 AD conversion high-order register (ADH)
003616 AD conversion low-order register (ADL)
003716 Watchdog timer register (WDT)
003816 Segment output enable register (SEG)
003916 LCD mode register (LM)
003A16 Interrupt edge selection register (INTEDGE)
003B16 CPU mode register (CPUM)
003C16 Interrupt request register 1(IREQ1)
003D16 Interrupt request register 2(IREQ2)
003E16 Interrupt control register 1(ICON1)
003F16 Interrupt control register 2(ICON2)
001F16
Note: Do not access to the SFR area including nothing.
Fig. 11 Memory map of special function register (SFR)
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 15 of 73
3823 Group
I/O PORTS
Direction Registers (ports P2, P41-P47, and
P5-P7)
The 3823 group has 49 programmable I/O pins arranged in seven
I/O ports (ports P0–P2, P41–P4 7 and P5-P7). The I/O ports P2,
P41–P47 and P5-P7 have direction registers which determine the
input/output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
Direction Registers (ports P0 and P1)
Ports P0 and P1 have direction registers which determine the input/output direction of each individual port.
Each port in a direction register corresponds to one port, each port
can be set to be input or output. When “0” is written to the bit 0 of
a direction register, that port becomes an input port. When “1” is
written to that port, that port becomes an output port. Bits 1 to 7 of
ports P0 and P1 direction registers are not used.
Ports P3 and P40
These ports are only for input.
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL register B (address 0017 16), ports except for port P40 can control
either pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with
a program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 16 of 73
b7
b0
PULL register A
(PULLA: address 001616 )
P00–P07 pull-down
P10–P17 pull-down
P20–P27 pull-up
P34–P37 pull-down
P70, P71 pull-up
Not used (return “0” when read)
b7
b0
PULL register B
(PULLB : address 001716)
P41–P43 pull-up
P44–P47 pull-up
P50–P53 pull-up
P54–P57 pull-up
P60–P63 pull-up
P64–P67 pull-up
Not used (return “0” when read)
0: Disable
1: Enable
Note: The contents of PULL register A and PULL register B
do not affect ports programmed as the output port.
Fig. 12 Structure of PULL register A and PULL register B
3823 Group
Table 7 List of I/O port function
Non-Port Function
Pin
Name
Input/Output
I/O Format
P00/SEG16–
P07/SEG23
Port P0
Input/output,
individual ports
CMOS compatible
input level
CMOS 3-state output
LCD segment output
PULL register A
Segment output enable
register
P10/SEG24–
P17/SEG31
Port P1
P20/KW0–
P27/KW7
Port P2
Input/output,
individual bits
CMOS compatible
input level
CMOS 3-state output
Key input (key-on
wake-up) interrupt
input
PULL register A
Interrupt control register 2
(2)
P34/SEG12–
P37/SEG15
Port P3
Input
CMOS compatible
input level
LCD segment output
PULL register A
Segment output enable
register
(3)
P40
Port P4
Input
CMOS compatible
input level
QzROM program
power pin
Input/output,
individual bits
CMOS compatible
input level
CMOS 3-state output
φ clock output
XCIN frequency signal
output
PULL register B
φ output control register
P42/INT0,
P43/INT1
External interrupt input
PULL register B
Interrupt edge selection
register
(2)
P44/RXD
Serial I/O function
input/output
PULL register B
Serial I/O control register
Serial I/O status register
UART control register
Peripheral function
extension register
(6)
External interrupt input
PULL register B
Interrupt edge selection
register
(2)
P52/RTP0,
P53/RTP1
Real time port
function output
(10)
P54/CNTR0
Timer X function I/O
PULL register B
Timer X mode register
PULL register B
Timer X mode register
P55/CNTR1
Timer Y function input
(12)
P56/TOUT
Timer 2 function output
PULL register B
Timer Y mode register
PULL register B
Timer 123 mode register
P57/ADT
P60/AN0–
P67/AN7
A/D trigger input
(12)
Port P6
Input/output,
individual bits
A/D conversion input
PULL register B
A/D control register
P70/XCOUT
Port P7
Input/output,
individual bits
Sub-clock
generating circuit I/O
PULL register A
CPU mode register
(15)
LCD mode register
(17)
(18)
P41/φ
P45/TXD
P46/SCLK
P47/SRDY/SOUT
P50/INT2,
P51/INT3
Port P5
Input/output,
individual bits
P71/XCIN
COM0–COM3
SEG0–SEG11
Common
Segment
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
Output
LCD common output
Output
LCD segment output
Related SFRs
(4)
page 17 of 73
(5)
Peripheral function
extension register
Notes 1: For details of how to use double function ports as function I/O ports, refer to the applicable sections.
2: When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
Especially, power source current may increase during execution of the STP and WIT instructions.
Fix the unused input pins to “H” or “L” through a resistor.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
Diagram No.
(1)
(7)
(8)
(9)
(11)
(13)
(14)
(16)
3823 Group
(1) Ports P0, P1
(2) Ports P2, P42, P43, P50, P51
VL2/VL3
Pull-up control
VL1/VSS
Segment output enable bit
(Note)
Direction register
Direction register
Data bus
Data bus
Port latch
Port latch
Key input (Key-on wake-up) interrupt input
INT0–INT3 interrupt input
Pull-down control
Segment output enable bit
Note: Bit 0 of direction register.
(3) Ports P34–P37
(4) Port P40
VL2/VL3
QZROM programmable
power source
Data bus
VL1/VSS
Data bus
Pull-down control
Segment output enable bit
(6) Port P44
(5) Port P41
Pull-up control
Pull-up control
Serial I/O enable bit
Receive enable bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
φ output control bit
XCIN frequency signal
Output clock selection bit
φ
Serial I/O input
Fig. 13 Port block diagram (1)
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 18 of 73
3823 Group
(8) Port P46
(7) Port P45
P-Channel output disabled selection bit
P45/TxD, P47/SRDY/SOUT P-channel output disable bit
Pull-up control
Serial I/O enable bit
Transmit enable bit
Serial I/O clocksynchronized selection bit
Serial I/O enable bit
Pull-up control
Serial I/O mode selection bit
Serial I/O enable bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Asynchronous serial I/O output
Synchronous serial I/O output pin selection bit
Serial I/O output
Serial I/O clock output
Serial I/O clock input
(synchronous or asynchronous)
(10) Ports P52, P53
(9) Port P47
P-Channel output disabled selection bit
P45/TxD, P47/SRDY/SOUT P-channel output disable bit
Serial I/O mode selection bit
Serial I/O enable bit
SRDY,SOUT output enable bit
Pull-up control
Pull-up control
Direction register
Direction register
Data bus
Data bus
Port latch
Synchronous serial I/O output
Port latch
Real time port control bit
Data for real time port
Synchronous serial I/O output pin selection bit
Serial I/O ready output
(11) Port P54
(12) Ports P55, P57
Pull-up control
Pull-up control
Direction register
Direction register
Data bus
Port latch
Data bus
Timer X operating mode bit
(Pulse output mode selection)
Timer output
CNTR0 interrupt input
Fig. 14 Port block diagram (2)
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 19 of 73
Port latch
CNTR1 interrupt input
A/D trigger interrupt input
3823 Group
(14) Port P6
(13) Port P56
Pul-up control
Pull-up control
Direction register
Data bus
Direction register
Port latch
Data bus
Port latch
TOUT output control bit
Timer output
A/D conversion input
Analog input pin selection bit
(15) Port P70
(16) Port P71
Port XC switch bit + Pull-up control
Port XC switch bit + Pull-up control
Data bus
Port XC switch bit
Port XC switch bit
Direction register
Direction register
Port latch
Data bus
Port latch
Oscillation circuit
Sub-clock generating circuit input
Port P71
Port XC switch bit
(17) COM0–COM3
(18) SEG0–SEG11
VL2/VL3
VL3
VL1/VSS
VL2
VL1
The gate input signal of each transistor is
controlled by the LCD duty ratio and the
bias value.
Fig. 15 Port block diagram (3)
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 20 of 73
The voltage applied to the sources of
P-channel and N-channel transistors
is the controlled voltage by the bias
value.
3823 Group
Termination of unused pins
• Termination of common pins
I/O ports:
Select an input port or an output port and follow
each processing method.
Output ports: Open.
Input ports: If the input level become unstable, through current
flow to an input circuit, and the power supply current
may increase.
Especially, when expecting low consumption current
(at STP or WIT instruction execution etc.), pull-up or
pull-down input ports to prevent through current
(built-in resistor can be used). Pull-down the P4 0/
(VPP) pin.
We recommend processing unused pins through a
resistor which can secure IOH(avg) or IOL(avg).
Because, when an I/O port or a pin which have an
output function is selected as an input port, it may
operate as an output port by incorrect operation etc.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 21 of 73
3823 Group
Table 8 Termination of unused pins
Pin
P00/SEG16–P17/SEG23
P10/SEG24–P17/SEG31
P20/KW0–P27/KW7
Termination 1 (recommend)
I/O port
P34/SEG12–P37/SEG15
P40/(VPP)
P41/φ
P42/INT0
Input port
Input port (pull-down)
I/O port
P43/INT1
P44/RxD
P45/TxD
P46/SCLK
P47/SRDY/SOUT
P50/INT2
P51/INT3
P52/RTP0
P53/RTP1
P54/CNTR0
P55/CNTR1
P56/TOUT
P57/ADT
P60/AN0–P67/AN7
P70/XCOUT
P71/XCIN
VL3 (Note)
VL2 (Note)
VL1 (Note)
COM0–COM3
SEG0–SEG11
AVSS
VREF
XOUT
Connect to VSS
Connect to VSS
Connect to VSS
Open
Open
Connect to VSS
Connect to VCC or VSS
When an external clock is
input to the XIN pin, leave
the XOUT pin open.
Termination 2
When selecting SEG output, open.
When selecting KW function, perform
termination of input port.
When selecting SEG output, open.
–
When selecting φ output, open.
When selecting INT0 function,
perform termination of input port.
When selecting INT1 function,
perform termination of input port.
When selecting RXD function,
perform termination of input port.
When selecting TXD function,
perform termination of output port.
When selecting external clock input,
perform termination of input port.
When selecting SRDY function,
perform termination of output port.
When selecting INT2 function,
perform termination of input port.
When selecting INT3 function,
perform termination of input port.
When selecting RTP0 function,
perform termination of output port.
When selecting RTP1 function,
perform termination of output port.
When selecting CNTR0 input function,
perform termination of input port.
When selecting CNTR1 function,
perform termination of input port.
When selecting TOUT function,
perform termination of output port.
When selecting ADT function,
perform termination of input port.
When selecting AN function, these
pins can be opened. (A/D conversion
result cannot be guaranteed.)
Do not select XCIN-XCOUT oscillation
function by program.
–
–
–
–
–
–
–
–
Note : The termination of VL3, VL2 and VL1 is applied when the bit 3 of the LCD mode register is “0”
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 22 of 73
Termination 3
–
–
–
–
–
–
–
–
–
When selecting internal clock output,
perform termination of output port.
When selecting SOUT function,
perform termination of output port.
–
–
–
–
When selecting CNTR0 output function,
perform termination of output port.
–
–
–
–
–
–
–
–
–
–
–
–
–
3823 Group
An interrupt requests is accepted when all of the following
conditions are satisfied:
• Interrupt disable flag.................................“0”
• Interrupt disable request bit ..................... “1”
• Interrupt enable bit................................... “1”
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
and flag.
INTERRUPTS
The 3823 group interrupts are vector interrupts with a fixed priority scheme, and generated by 16 sources among 17 sources: 8
external, 8 internal, and 1 software.
The interrupt sources, vector addresses (1) , and interrupt priority
are shown in Table 9.
Each interrupt except the BRK instruction interrupt has the interrupt request bit and the interrupt enable bit. These bits and the
interrupt disable flag (I flag) control the acceptance of interrupt requests. Figure 16 shows an interrupt control diagram.
Table 9 Interrupt vector addresses and priority
Vector Addresses (Note 1)
Interrupt Source
Priority
High
Low
Reset (Note 2)
1
FFFD16
FFFC16
INT0
2
FFFB16
FFFA16
Interrupt Request
Generating Conditions
At reset
Non-maskable
At detection of either rising or
falling edge of INT0 input
External interrupt
(active edge selectable)
Remarks
INT1
3
FFF916
FFF816
At detection of either rising or
falling edge of INT1 input
External interrupt
(active edge selectable)
Serial I/O
reception
4
FFF716
FFF616
At completion of serial interface
data reception
Valid when serial interface is selected
Serial I/O
transmission
5
FFF516
FFF416
Valid when serial interface is selected
Timer X
6
FFF316
FFF216
At completion of serial interface
transmit shift or when transmission buffer is empty
At timer X underflow
Timer Y
7
FFF116
FFF016
At timer Y underflow
Timer 2
Timer 3
FFEF16
FFED16
FFEB16
FFEE16
FFEC16
FFEA16
At timer 2 underflow
CNTR0
8
9
10
At timer 3 underflow
At detection of either rising or
falling edge of CNTR0 input
External interrupt
(active edge selectable)
CNTR1
11
FFE916
FFE816
At detection of either rising or
falling edge of CNTR1 input
External interrupt
(active edge selectable)
Timer 1
INT2
12
FFE716
FFE616
At timer 1 underflow
13
FFE516
FFE416
At detection of either rising or
falling edge of INT2 input
External interrupt
(active edge selectable)
INT3
14
FFE316
FFE216
At detection of either rising or
falling edge of INT3 input
External interrupt
(active edge selectable)
Key input
(Key-on wake-up)
15
FFE116
FFE016
At falling of conjunction of input
level for port P2 (at input mode)
External interrupt
(Valid at falling)
ADT
16
FFDF16
FFDE16
At falling of ADT input
Valid when ADT interrupt is selected, External interrupt
(Valid at falling)
At completion of A/D conversion
Valid when A/D interrupt is selected
At BRK instruction execution
Non-maskable software interrupt
A/D conversion
BRK instruction
17
FFDD16
FFDC16
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 23 of 73
3823 Group
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
interrupt request
Fig. 16 Interrupt control diagram
Interrupt Disable Flag
Interrupt Source Selection
The interrupt disable flag is assigned to bit 2 of the processor status register. This flag controls the acceptance of all interrupt
requests except for the BRK instruction. When this flag is set to
“1”, the acceptance of interrupt requests is disabled. When it is set
to “0”, acceptance of interrupt requests is enabled. This flag is set
to “1” with the SET instruction and set to “0” with the CLI instruction.
When an interrupt request is accepted, the contents of the processor status register are pushed onto the stack while the interrupt
disable flag remaines set to “0”. Subsequently, this flag is automatically set to “1” and multiple interrupts are disabled.
To use multiple interrupts, set this flag to “0” with the CLI instruction within the interrupt processing routine.
The contents of the processor status register are popped off the
stack with the RTI instruction.
The following combinations can be selected by the interrupt
source selection bit of the AD control register (bit 6 of the address
003916).
Interrupt Request Bits
Once an interrupt request is generated, the corresponding interrupt request bit is set to “1” and remaines “1” until the request is
accepted. When the request is accepted, this bit is automatically
set to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to
“1”, by software.
Interrupt Enable Bits
The interrupt enable bits control the acceptance of the corresponding interrupt requests. When an interrupt enable bit is set to
“0”, the acceptance of the corresponding interrupt request is disabled. If an interrupt request occurs in this condition, the
corresponding interrupt request bit is set to “1”, but the interrupt
request is not accepted. When an interrupt enable bit is set to “1”,
acceptance of the corresponding interrupt request is enabled.
Each interrupt enable bit can be set to “0” or “1” by software.
The interrupt enable bit for an unused interrupt should be set to
“0”.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 24 of 73
• ADT or A/D conversion (refer Table 9)
3823 Group
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16)
INT0
INT1
INT2
INT3
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
Not used (return “0” when read)
b7
b0
0 : Falling edge active
1 : Rising edge active
Interrupt request register 1
(IREQ1 : address 003C16)
b7
b0
INT0 interrupt request bit
INT1 interrupt request bit
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Interrupt request register 2
(IREQ2 : address 003D16)
CNT R0 interrupt request bit
CNT R1 interrupt request bit
Timer 1 interrupt request bit
INT2 interrupt request bit
INT3 interrupt request bit
Key input interrupt request bit
ADT/AD conversion interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
Interrupt control register 1
(ICON1 : address 003E16)
INT0 interrupt enable bit
INT1 interrupt enable bit
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
b7
b0
Interrupt control register 2
(ICON2 : address 003F16)
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
Timer 1 interrupt enable bit
INT2 interrupt enable bit
INT3 interrupt enable bit
Key input interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 17 Structure of interrupt-related registers
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 25 of 73
3823 Group
Interrupt Request Generation, Acceptance,
and Handling
Interrupts have the following three phases.
(i) Interrupt Request Generation
An interrupt request is generated by an interrupt source (external interrupt signal input, timer underflow, etc.) and the
corresponding request bit is set to “1”.
(ii) Interrupt Request Acceptance
Based on the interrupt acceptance timing in each instruction
cycle, the interrupt control circuit determines acceptance conditions (interrupt request bit, interrupt enable bit, and interrupt
disable flag) and interrupt priority levels for accepting interrupt
requests. When two or more interrupt requests are generated
simultaneously, the highest priority interrupt is accepted. The
value of interrupt request bit for an unaccepted interrupt remains the same and acceptance is determined at the next
interrupt acceptance timing point.
(iii) Handling of Accepted Interrupt Request
The accepted interrupt request is processed.
■Notes
The interrupt request bit may be set to “1” in the following cases.
•When setting the external interrupt active edge
Related registers: Interrupt edge selection register
(address 003A16)
Timer X mode register (address 002716)
Timer Y mode register (address 002816)
If it is not necessary to generate an interrupt synchronized with
these settings, take the following sequence.
(1) Set the corresponding enable bit to “0” (disabled).
(2) Set the interrupt edge selection bit (the active edge switch
bit) or the interrupt source bit.
(3) Set the corresponding interrupt request bit to “0” after one or
more instructions have been executed.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
Interrupt request
generated
Interrupt request
acceptance
Interrupt routine
starts
Interrupt sequence
Figure 18 shows the time up to execution in the interrupt processing routine, and Figure 19 shows the interrupt sequence.
Figure 20 shows the timing of interrupt request generation, interrupt request bit, and interrupt request acceptance.
Interrupt Handling Execution
When interrupt handling is executed, the following operations are
performed automatically.
(1) Once the currently executing instruction is completed, an interrupt request is accepted.
(2) The contents of the program counters and the processor status
register at this point are pushed onto the stack area in order
from 1 to 3.
1. High-order bits of program counter (PCH)
2. Low-order bits of program counter (PCL)
3. Processor status register (PS)
(3) Concurrently with the push operation, the jump address of the
corresponding interrupt (the start address of the interrupt processing routine) is transferred from the interrupt vector to the
program counter.
(4) The interrupt request bit for the corresponding interrupt is set
to “0”. Also, the interrupt disable flag is set to “1” and multiple
interrupts are disabled.
(5) The interrupt routine is executed.
(6) When the RTI instruction is executed, the contents of the registers pushed onto the stack area are popped off in the order
from 3 to 1. Then, the routine that was before running interrupt
processing resumes.
As described above, it is necessary to set the stack pointer and
the jump address in the vector area corresponding to each interrupt to execute the interrupt processing routine.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 26 of 73
Stack push and
Vector fetch
Main routine
*
0 to 16 cycles
Interrupt handling
routine
7 cycles
7 to 23 cycles
* When executing DIV instruction
Fig. 18 Time up to execution in interrupt routine
Push onto stack
Vector fetch
Execute interrupt
routine
φ
SYNC
RD
WR
Address bus
Data bus
PC
Not used
S,SPS
S-1,SPS S-2,SPS
PCH
PCL
PS
BL
BH
AL
AL,AH
AH
SYNC : CPU operation code fetch cycle
(This is an internal signal that cannot be observed from the external unit.)
BL, BH: Vector address of each interrupt
AL, AH: Jump destination address of each interrupt
SPS : “0016” or “0116”
([SPS] is a page selected by the stack page selection bit of CPU mode register.)
Fig. 19 Interrupt sequence
3823 Group
Push onto stack
Vector fetch
Instruction cycle
Instruction cycle
Internal clock φ
SYNC
1
T1
2
IR1 T2
IR2 T3
T1 T2 T3: Interrupt acceptance timing points
IR1 IR2: Timings points at which the interrupt request bit is set to “1”.
Note: Period 2 indicates the last φ cycle during one instruction cycle.
(1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1.
(2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2.
The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt requests
are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2 separately.
Fig. 20 Timing of interrupt request generation, interrupt request bit, and interrupt acceptance
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 27 of 73
3823 Group
Key Input Interrupt (Key-on wake-up)
A Key-on wake-up interrupt request is generated by applying a
falling edge to any pin of port P2 that have been set to input mode.
In other words, it is gener1ated when AND of input level goes from
“1” to “0”. An example of using a key input interrupt is shown in
Figure 21, where an interrupt request is generated by pressing
one of the keys consisted as an active-low key matrix which inputs
to ports P20–P23.
Port PXX
“L” level output
PULL register A bit 2 = “1”
✽
✽✽
Port P27
direction register = “1”
Key input interrupt request
Port P27
latch
P27 output
Port P26
direction register = “1”
✽
✽✽
✽
✽✽
Port P26
latch
P26 output
Port P25
direction register = “1”
Port P25
latch
P25 output
Port P24
direction register = “1”
✽
✽✽
Port P24
latch
P24 output
✽
Port P23
direction register = “0”
✽✽
P23 input
✽
Port P22
direction register = “0”
✽✽
P22 input
✽
P20 input
Port P22
latch
Port P21
direction register = “0”
✽✽
P21 input
✽
Port P23
latch
Port P21
latch
Port P20
direction register = “0”
✽
Port P20
latch
✽ P-channel transistor for pull-up
✽✽ CMOS output buffer
Fig. 21 Connection example when using key input interrupt and port P2 block diagram
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 28 of 73
Port P2
Input reading circuit
3823 Group
responding to that timer is set to “1”.
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct
operation when reading during the write operation, or when writing
during the read operation.
TIMERS
The 3823 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is
continued. When a timer underflows, the interrupt request bit corReal time port
control bit “1”
Data bus
Q D
P52 data for real time port
Latch
“0”
P52 latch
Real time port
control bit “1”
Q D
P53 data for real time port
P52
P52 direction register
P53
Real time port
control bit “0”
Latch
“0”
P53 direction register
P53 latch
Timer X stop
control bit
CNTR0 active Timer X operatedge switch bit ing mode bits
“00”,“01”,“11”
“0”
P54/CNTR0
“10”
“1”
Pulse width
measurement
mode
CNTR0 active
edge switch bit “0”
“1”
P54 direction register
Timer X mode register
write signal
“1”
f(XIN)/16
(f(SUB)/16 in low-speed mode✽)
Timer X write
control bit
Timer X (low) latch (8)
Timer X (high) latch (8)
Timer X (low) (8)
Timer X (high) (8)
CNTR0
interrupt
request
Pulse output
mode
QS
Timer Y operating mode bits
“00”,“01”,“10”
T
Q
Pulse width HL continuously measurement mode
P54 latch
Rising edge detection
Period
measurement mode
Falling edge detection
f(XIN)/16
✽
(f(SUB)16 in low-speed mode )
P55/CNTR1
Timer Y stop
control bit
“00”,“01”,“11”
Timer Y (low) latch (8)
Timer Y (high) latch (8)
Timer Y (low) (8)
Timer Y (high) (8)
“10” Timer Y operating
mode bits
“1”
CNTR1
interrupt
request
“11”
Pulse output mode
CNTR1 active
edge switch bit
“0”
Timer X
interrupt
request
f(XIN)/16
(f(SUB)/16 in low-speed mode])
Timer 1 count source
selection bit
“0”
Timer 1 latch (8)
f(SUB)
Timer 2 count source
selection bit
Timer 2 latch (8)
“0”
Timer 1 (8)
“1”
Timer 2 (8)
“1”
Timer 2 write
control bit
Timer Y
interrupt
request
Timer 1
interrupt
request
Timer 2
interrupt
request
f(XIN)/16
(f(SUB)/16 in low-speed mode✽)
TOUT output TOUT output
active edge control bit
TOUT output switch bit
control bit
“0”
QS
P56/TOUT
P56 direction register
“1”
P56 latch
T
Q
f(XIN)/16(f(SUB)/16 in low-speed mode✽)
✽ f(SUB) is the source oscillation frequency in low-speed mode.
f(SUB) shows the oscillation frequency of XCIN or the on-chip
oscillator.
Internal clock φ is f(SUB)/2 in the low-speed mode.
Fig. 22 Timer block diagram
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 29 of 73
“0”
Timer 3 latch (8)
Timer 3 (8)
“1”
Timer 3 count
source selection bit
Timer 3
interrupt
request
3823 Group
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write and the real time port by
setting the timer X mode register.
(1) Timer Mode
The timer counts f(XIN)/16 (or f(SUB)/16 in low-speed mode).
f(SUB) is the source oscillation frequency in low-speed mode.
f(SUB) shows the oscillation frequency of XCIN or the on-chip oscillator. Internal clock φ is f(XCIN)/2 in the low-speed mode.
(2) Pulse Output Mode
Each time the timer underflows, a signal output from the CNTR0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode,
set the corresponding port P54 direction register to output mode.
●Real time port control
While the real time port function is valid, data for the real time port
are output from ports P5 2 and P5 3 each time the timer X
underflows. (However, after rewriting a data for real time port, if
the real time port control bit is changed from “0” to “1”, data are
output independent of the timer X operation.) If the data for the
real time port is changed while the real time port function is valid,
the changed data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction
registers to output mode.
■Note on CNTR 0 interrupt active edge
selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
(3) Event Counter Mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corresponding port P54 direction register to input mode.
(4) Pulse Width Measurement Mode
The count source is f(XIN)/16 (or f(SUB)/16 in low-speed mode). If
CNTR0 active edge switch bit is “0”, the timer counts while the input signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while
the input signal of CNTR0 pin is at “L”. When using a timer in this
mode, set the corresponding port P54 direction register to input
mode.
●Timer X write control
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
If the value is written in latch only, when writing in the timer latch at
the timer underflow, the value is set in the timer and the latch at
one time. Additionally, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow
of timer X are performed at the same timing.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 30 of 73
b7
b0
Timer X mode register
(TXM : address 002716)
Timer X write control bit
0 : Write value in latch and counter
1 : Write value in latch only
Real time port control bit
0 : Real time port function invalid
1 : Real time port function valid
P52 data for real time port
P53 data for real time port
Timer X operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNT R0 active edge switch bit
0 : Count at rising edge in event counter mode
Start from “H” output in pulse output mode
Measure “H” pulse width in pulse width
measurement mode
Falling edge active for CNTR0 interrupt
1 : Count at falling edge in event counter mode
Start from “L” output in pulse output mode
Measure “L” pulse width in pulse width
measurement mode
Rising edge active for CNTR0 interrupt
Timer X stop control bit
0 : Count start
1 : Count stop
Fig. 23 Structure of timer X mode register
3823 Group
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
b7
(1) Timer Mode
The timer counts f(XIN)/16 (or f(SUB)/16 in low-speed mode).
(2) Period Measurement Mode
CNTR 1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Except for the above-mentioned, the operation in period
measurement mode is the same as in timer mode.
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
The rising/falling timing of CNTR 1 pin input signal is found by
CNTR1 interrupt. When using a timer in this mode, set the corresponding port P55 direction register to input mode.
b0
Timer Y mode register
(TYM : address 002816)
Not used (return “0” when read)
Timer Y operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuously measurement
mode
CNT R1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge to falling edge
period in period measurement mode
Falling edge active for CNTR1 interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNT R1 interrupt
Timer Y stop control bit
0 : Count start
1 : Count stop
(3) Event Counter Mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corresponding port P55 direction register to input mode.
(4) Pulse Width HL Continuously Measurement
Mode
CNTR 1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the corresponding port P55 direction register to input mode.
■Note on CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR1 interrupt request is generated at both rising and
falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 31 of 73
Fig. 24 Structure of timer Y mode register
3823 Group
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected by a change of the count source. However, because changing the count source may cause an
inadvertent count down of the timer, rewrite the value of timer
whenever the count source is changed.
●Timer 2 write control
If the timer 2 write control bit is “0”, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
If the timer 2 write control bit is “1”, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
●Timer 2 output control
When the timer 2 (T OUT) is output enabled, an inversion signal
from the TOUT pin is output each time timer 2 underflows.
In this case, set the port shared with the TOUT pin to the output
mode.
■Notes on timer 1 to timer 3
When the count source of timer 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is generated
in count input of timer . If timer 1 output is selected as the count
source of timer 2 or timer 3, when timer 1 is written, the counting
value of timer 2 or timer 3 may be changed large because a thin
pulse is generated in timer 1 output.
Therefore, set the value of timer in the order of timer 1, timer 2
and timer 3 after the count source selection of timer 1 to 3.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 32 of 73
b7
b0
Timer 123 mode register
(T123M :address 002916)
TOUT output active edge switch bit
0 : Start at “H” output
1 : Start at “L” output
TOUT output control bit
0 : TOUT output disabled
1 : TOUT output enabled
Timer 2 write control bit
0 : Write data in latch and counter
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(SUB)/16 in low-speed mode)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(SUB)/16 in low-speed mode)
Timer 1 count source selection bit
0 : f(XIN)/16
(or f(SUB)/16 in low-speed mode)
1 : f(SUB)
Not used (return “0” when read)
Note: f(SUB) is the source oscillation frequency in low-speed
mode. f(SUB) shows the oscillation frequency of XCIN or
the on-chip oscillator.
Internal clock φ is f(SUB)/2 in the low-speed mode.
Fig. 25 Structure of timer 123 mode register
3823 Group
(1) Clock Synchronous Serial I/O Mode
SERIAL INTERFACE
Serial I/O
Clock synchronous serial I/O can be selected by setting the mode
selection bit of the serial I/O control register to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
The MSB first transfer is selected as the transfer direction by setting
the bit 0 in the peripheral function expansion register to “1”. Also, the
synchronous serial I/O output switches to the P47/SRDY/SOUT pin by
setting the bit 1 in the peripheral function expansion register to “1”.
Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
Data bus
T ransfer direction selection bit
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive shift register
P44/RXD
Address 001A16
Serial I/O control register
Address 001816
Receive buffer register
Shift clock
Clock control circuit
P46/SCLK
Serial I/O
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
f(XIN)
(f(SUB) in low-speed mode)
1/4
Baud rate generator
1/4
Address 001C16
Serial output pin selection bit
F/F
P47/SRDY1/SOUT
Clock control circuit
Falling-edge detector
Shift clock
Transmit shift register
P45/TXD
Serial output pin
Transfer direction
selection bit
selection bit
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Address 001916
Transmit buffer register
Address 001816
Serial I/O status register
Data bus
Note: f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation frequency of XCIN or the on-chip oscillator.
Fig. 26 Block diagram of clock synchronous serial I/O
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TXD
(or SOUT)
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RXD
D0
D1
D2
D3
D4
D5
D6
D7
TxD and RxD above shows the operation when selecting LSB first transfer.
Receive enable signal SRDY
Write signal to receive/transmit
buffer register (address 001816)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1 : T he transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE=1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the TXD pin.
3 : T he receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 27 Operation of clock synchronous serial I/O function
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 33 of 73
3823 Group
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
Data bus
Address 001816
OE
Serial I/O control register
Character length selection bit
P44/RXD
STdetector
7 bits
Address 001A16
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive buffer register
Receive shift register
1/16
8 bits
PE FE
UART control register
Address 001B16
SP detector
Clock control circuit
Serial I/O synchronous clock selection bit
P46/SCLK
BRG count source selection bit
f(XIN)
(f(SUB) in low-speed mode)
1/4
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16
ST/SP/PA generator
Transmit shift register shift completion flag (TSC)
1/16
P45/TXD
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
Character length selection bit
Transmit buffer empty flag (TBE)
Serial I/O status register Address 001916
Transmit buffer register
Address 001816
Data bus
Note: f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation frequency of XCIN or the on-chip oscillator.
Internal clock φ is f(SUB)/2 in the low-speed mode.
Fig. 28 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer write signal
TBE=0
TSC=0
TBE=1
Serial output TXD
TBE=0
TSC=1✽
TBE=1
ST
D0
D1
SP
ST
D0
1 start bit
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
✽Generated
RBF=0
RBF=1
Serial input RXD
ST
D0
D1
D1
SP
ST
D0
D1
SP
at 2nd bit in 2-stop-bit mode
RBF=1
SP
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1” by the setting of the transmit interrupt source
selection bit (TIC) of the serial I/O control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 29 Operation of UART serial I/O function
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 34 of 73
3823 Group
(3) Synchronous/Asynchronous Alternate
Transmit Mode
confirming that the transmit shift register is set to “1”, and then
______
changing the serial I/O mode selection bit. The SRDY output function cannot be used when the clock synchronous serial I/O is
selected. Also, when using the internal clock for the transfer clock
(the serial I/O synchronous clock selection bit is set to “0”), apply
“H” output to the P46 pin. The other operation is the same as clock
synchronous serial I/O mode and asynchronous serial I/O mode
(UART).
Synchronous/asynchronous alternate transmit mode is selected
by setting the transmit enable bit in the serial I/O control register to
“1” after setting the synchronous serial I/O output pin selection bit
in the peripheral function expansion register to “1”. Set the synchronous serial I/O output pin selection bit to “1” when the serial I/
O mode selection bit is set to “0”. In this mode, transmit cannot be
performed continuously. Write to the transmit buffer register after
P46/SCLK
Serial I/O synchronous
clock selection bit
BRG count source
selection bit
f(XIN)
(Note)
f(SUB) in low-speed mode
Baud rate generator
Frequency division
ratio 1/(n+1)
1/4
1/4
Clock control circuit
P47/SRDY/SOUT
(Synchronous output)
Serial I/O mode
selection bit (SIOM)
Transmit shift register shift
completion flag (TSC)
Shift clock
Transmit shift register
P45/TXD
(Asynchronous output)
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Transmit buffer register
Serial I/O status register
Address 001816
Address 001916
Date bus
Note: f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation frequency of XCIN or the on-chip oscillator.
Fig. 30 Block diagram of synchronous/asynchronous alternate transmit
TBE=1
TSC=0
TBE=1
TSC=0
TSC=0
P46/SCLK
TSC=0
TBE=1
P45/TXD
(Asynchronous output)
TBE=1
TSC=0
TSC=1
ST
D1
D1
D7
SP
ST
P47/SOUT
(synchronous output)
synchronous serial I/O
output selection bit
D0
TBE=0
TSC=1
D1
D6
D1
D1
D7
SP
D7
D0
TBE=0
TBE=0
TBE=0
Transmit buffer
write signal
Serial I/O mode
selection bit
Asynchronous transmit
Synchronous transmit
Fig. 31 Operation of synchronous/asynchronous alternate transmit function
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 35 of 73
Asynchronous transmit
Synchronous
transmit
3823 Group
[Transmit Buffer/Receive Buffer Register
(TB/RB)] 001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is
write-only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer
register is “0”.
[Serial I/O Status Register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE. Writing “0” to the serial I/O enable bit (SIOE) also clears all the status
flags, including the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift register shift completion flag
(bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O Control Register (SIOCON)] 001A16
The serial I/O control register contains eight control bits for the serial I/O function.
[UART Control Register (UARTCON) ]001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P45/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
■Notes on serial I/O
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission
enalbed, take the following sequence.
➀Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁Set the transmit enable bit to “1”.
➂Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➃Set the serial I/O transmit interrupt enable bit to “1” (enabled).
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 36 of 73
3823 Group
b7
b0
Serial I/O status register
(SIOSTS : address 001916)
b7
Serial I/O control register
(SIOCON : address 001A16)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
BRG count source selection bit (CSS)
0: f(XIN) (f(SUB) in low-speed mode)
1: f(XIN)/4 (f(SUB)/4 in low-speed mode)
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Serial I/O synchronization clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronized serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronized serial I/O is
selected.
External clock input divided by 16 when UART is selected.
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Parity error flag (PE)
0: No error
1: Parity error
SRDY, SOUT output enable bit (SRDY)
0: P47 pin operates as ordinary I/O pin
1: P47 pin operates as SRDY or SOUT output pin
Set the transmit disable bit and SRDY, SOUT output enable bits
to “0” to disable transmit when selecting SOUT. (Setting
peripheral function extension register is necessary when
selecting SOUT.)
Framing error flag (FE)
0: No error
1: Framing error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Summing error flag (SE)
0: (OE) U (PE) U (FE) =0
1: (OE) U (PE) U (FE) =1
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Not used (returns “1” when read)
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Overrun error flag (OE)
0: No error
1: Overrun error
b7
b0
b0 UART control register
(UARTCON : address 001B16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Serial I/O mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P44–P47 operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P44–P47 operate as serial I/O pins)
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD, P47/SRDY/SOUT P-channel output disable bit (POFF) (Note)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (return “1” when read)
Notes 1 : The peripheral function extension register is used to choose P45/TXD, P47/SRDY/SOUT.
2 : f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation frequency of XCIN or the on-chip oscillator.
Fig. 32 Structure of serial I/O control registers
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 37 of 73
3823 Group
A/D CONVERTER
[AD Conversion Register (ADH, ADL)] 003516
b7
b0
The AD conversion register is a read-only register that contains
the result of an A/D conversion. When reading this register during
an A/D conversion, the previous conversion result is read.The
high-order 8 bits of a conversion result is stored in the AD conversion high-order register (address 003516),and the low-order 2 bits
of the same result are stored in bit 7 and bit 6 of the AD conversion low-order register (address 003616).
The bit 0 in the AD conversion low-order register is used as the
conversion mode selection bit. 8-bit A/D mode is selected by setting this bit to “0” and 10-bit A/D mode is selected by setting it to
“1”.
Analog input pin selection bits
0 0 0 : P60/AN0
0 0 1 : P61/AN1
0 1 0 : P62/AN2
0 1 1 : P63/AN3
1 0 0 : P64/AN4
1 0 1 : P65/AN5
1 1 0 : P66/AN6
1 1 1 : P67/AN7
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
VREF input switch bit
0 : ON during conversion
1 : Always ON
AD external trigger valid bit
0 : A/D external trigger invalid
1 : A/D external trigger valid
Interrupt source selection bit
0 : Interrupt request at A/D
conversion completed
1 : Interrupt request at ADT
input falling
Not used (returns “0” when read)
[AD Control Register (ADCON)] 003416
The AD control register controls the A/D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 signals
the completion of an A/D conversion. The value of this bit remains
at “0” during an A/D conversion, then changes to “1” when the
A/D conversion is completed. Writing “0” to this bit starts the A/D
conversion. Bit 4 is the VREF input switch bit which controls connection of the resistor ladder and the reference voltage input pin
(VREF). The resistor ladder is always connected to VREF when bit
4 is set to "1". When bit 4 is set to “0”, the resistor ladder is cut off
from V REF except for A/D conversion performed. When bit 5,
which is the AD external trigger valid bit, is set to “1”, this bit enables A/D conversion even by a falling edge of an ADT input. Set
the P57/ADT pin to input mode (set "0" to bit 7 of port P5 direction
register) when using an A/D external trigger.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between
AVSS and VREF, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports P67/AN7–P60/
AN0, and inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the AD
conversion register. When an A/D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
The comparator is constructed linked to a capacitor. The conversion accuracy may be low because the charge is lost if the
conversion speed is not enough. Accordingly, set f(XIN) to at least
500kHz during A/D conversion in the middle-or high-speed mode.
Also, do not execute the STP or WIT instruction during an A/D
conversion.
In the low-speed mode, since the A/D conversion is executed by
the built-in self-oscillation circuit, the minimum value of f(XIN) frequency is not limited.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 38 of 73
AD control register
(ADCON : address 003416)
b7
b0
AD conversion low-order register
(ADL : address 003616)
Conversion mode selection bit
0 : 8 bit A/D mode
1 : 10 bit A/D mode
AD conversion speed selection bit
00 : f(XIN)/2
(this can be used in CPUM7 = “0” )
01 : f(XIN)
(this can be used in CPUM7 = “0” )
10 : On-chip oscillator
(this can be used in CPUM7 = “0”
and EXPCM0 = “1”)
11 : Disabled
Not used (returns “0” when read)
• In 10-bit A/D mode
A/D conversion data storage
• In 8-bit A/D mode
Not used (Indefinite at read)
Fig. 33 Structure of AD conversion-related registers
3823 Group
• 10 bit reading (Read address 003516 before 003616)
b7
AD conversion high-order register
(Address 003516) ADH
b0
b9 b8 b7 b6 b5 b4 b3 b2
b0
b7
AD conversion low-order register
(Address 003616) ADL
b1 b0
(High-order)
0
0
(low-order)
0
Conversion mode selection bit
AD conversion speed selection bit
Note: The bit 5 to bit 3 of address 003616 become "0" at reading.
• 8 bit reading (Read only address 003516)
b7
(Address 003516)
b0
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 34 A/D conversion register reading
Data bus
b7
b0
AD control register
P57/ADT
3
ADT/A/D interrupt
request
A/D control circuit
Channel selector
P60/SIN2/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
Comparator
AD conversion
high-order register
(Address 003516)
AD conversion
low-order register
(Address 003616)
Resistor ladder
AVSS VREF
Fig. 35 A/D converter block diagram
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 39 of 73
3823 Group
LCD DRIVE CONTROL CIRCUIT
The 3823 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
●LCD display RAM
●Segment output enable register
●LCD mode register
●Selector
●Timing controller
●Common driver
●Segment driver
●Bias control circuit
A maximum of 32 segment output pins and 4 common output pins
can be used.
Up to 128 pixels can be controlled for LCD display. When the LCD
b7
enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and
displays the data on the LCD panel.
Table 10 Maximum number of display pixels at each duty ratio
Duty ratio
2
3
4
Maximum number of display pixel
64 dots
or 8 segment LCD 8 digits
96 dots
or 8 segment LCD 12 digits
128 dots
or 8 segment LCD 16 digits
b0
Segment output enable register
(SEG : address 003816)
Segment output enable bit 0
0 : Input port P34–P37
1 : Segment output SEG12–SEG15
Segment output enable bit 1
0 : I/O port P00,P01
1 : Segment output SEG16, SEG17
Segment output enable bit 2
0 : I/O port P02–P07
1 : Segment output SEG18–SEG23
Segment output enable bit 3
0 : I/O port P10,P11
1 : Segment output SEG24, SEG25
Segment output enable bit 4
0 : I/O port P12
1 : Segment output SEG26
Segment output enable bit 5
0 : I/O port P13–P17
1 : Segment output SEG27–SEG31
Not used (returns “0” when read)
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b7
b0
LCD mode register
(LM : address 003916)
Duty ratio selection bits
0 0 : Not used
0 1 : 2 (use COM0, COM1)
1 0 : 3 (use COM0–COM2)
1 1 : 4 (use COM0–COM3)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Not used (returns “0” when read)
(Do not write “1” to this bit)
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(SUB)/32
1 : f(XIN)/8192 (or f(SUB)/8192 in low-speed
mode)
Note: LCDCK is a clock for a LCD timing controller.
f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation
frequency of XCIN or the on-chip oscillator.
Internal clock φ is f(SUB)/2 in the low-speed mode.
Fig. 36 Structure of segment output enable register and LCD mode register
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 40 of 73
Fig. 37 Block diagram of LCD controller/driver
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 41 of 73
SEG0
P34/SEG12
SEG1
SEG2
SEG3
COM0 COM1 COM2 COM3
LCDCK
LCD
divider
“1”
f(XIN)/8192( or f(SUB)/8192 in
low-speed mode)
LCDCK count source
selection bit
“0” f(SUB)/32
Note: f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation frequency of XCIN or the on-chip oscillator.
VSS VL1 VL2 VL3
VCC
2
Common Common Common Common
driver
driver
driver
driver
Timing controller
2
LCD circuit divider
division ratio selection bits
Duty ratio selection bits
LCD enable bit
LCD
enable bit
Bias control bit
Bias control
LCD display RAM
P16/SEG30 P17/SEG31
Segment Segment
driver
driver
Segment Segment Segment
driver
driver
driver
Segment
driver
Address
004F16
Selector Selector
Address
004116
Selector Selector Selector Selector
Address
004016
Data bus
3823 Group
3823 Group
Bias Control and Applied Voltage to LCD
Power Input Pins
To the LCD power input pins (VL1–VL3), apply the voltage shown
in Table 11 according to the bias value.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Table 11 Bias control and applied voltage to VL1–VL3
Bias value
1/3 bias
1/2 bias
VL3=VLCD
VL2=VL1=1/2 VLCD
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by
duty ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
Voltage value
VL3=VLCD
VL2=2/3 VLCD
VL1=1/3 VLCD
Note 1: V LCD is the maximum value of supplied voltage for the
LCD panel.
Table 12 Duty ratio control and common pins used
Duty
ratio
Duty ratio selection bit
Bit 1
Bit 0
Common pins used
2
0
1
3
1
0
COM0–COM2 (Note 2)
4
1
1
COM0–COM3
COM0, COM1 (Note 1)
Notes1: COM2 and COM3 are open.
2: COM3 is open.
Contrast control
VL3
Contrast control
VL3
R1
R4
VL2
VL2
R2
VL1
VL1
R3
R5
R4 = R5
R1 = R2 = R3
1/3 bias
1/2 bias
Fig. 38 Example of circuit at each bias
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 42 of 73
3823 Group
LCD Display RAM
LCD Drive Timing
Address 004016 to 004F16 is the designated RAM for the LCD display. When “1” are written to these addresses, the corresponding
segments of the LCD display panel are turned on.
The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the
following equation;
f(LCDCK) =
(frequency of count source for LCDCK)
(divider division ratio for LCD)
Frame frequency =
f(LCDCK)
(duty ratio)
B it
7
6
5
Address
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
4
3
2
1
SEG1
SEG0
SEG3
SEG2
SEG5
SEG4
SEG7
SEG6
SEG9
SEG8
SEG11
SEG10
SEG13
SEG12
SEG15
SEG17
SEG14
SEG16
SEG19
SEG18
SEG21
SEG20
SEG23
SEG22
SEG25
SEG24
SEG27
SEG26
SEG29
SEG31
SEG28
0
SEG30
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
Fig. 39 LCD display RAM map
STP Instruction Execution
Execution of the STP instruction sets the LCD enable bit (bit 3 of
the LCD mode register) to “0” and the LCD panel turns off.To
make the LCD panel turn on after returning from the stop mode,
set the LCD enable bit to “1”.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 43 of 73
3823 Group
Internal logic
LCDCK timing
1/4 duty
Voltage level
VL3
VL2=VL1
VSS
COM0
COM1
COM2
COM3
VL3
VSS
SEG0
OFF
COM3
ON
COM2
COM1
OFF
COM0
COM3
ON
COM2
COM1
COM0
1/3 duty
VL3
VL2=VL1
VSS
COM0
COM1
COM2
VL3
VSS
SEG0
ON
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
1/2 duty
VL3
VL2=VL1
VSS
COM0
COM1
VL3
VSS
SEG0
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM1
COM0
COM1
COM0
COM1
COM0
COM1
COM0
Fig. 40 LCD drive waveform (1/2 bias)
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 44 of 73
3823 Group
Internal logic
LCDCK timing
1/4 duty
Voltage level
VL3
VL2
VL1
VSS
COM0
COM1
COM2
COM3
VL3
SEG0
VSS
OFF
COM3
ON
COM2
COM1
OFF
COM0
COM3
ON
COM2
COM1
COM0
1/3 duty
VL3
VL2
VL1
VSS
COM0
COM1
COM2
VL3
SEG0
VSS
ON
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
1/2 duty
VL3
VL2
VL1
VSS
COM0
COM1
VL3
SEG0
VSS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM1
COM0
COM1
COM0
COM1
COM0
COM1
COM0
Fig. 41 LCD drive waveform (1/3 bias)
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 45 of 73
3823 Group
ROM CORRECTION FUNCTION
A part of program in ROM can be corrected.
Set the start address of the corrected ROM data (i.e. an Op code
address of the beginning instruction) to the ROM correction address low-order and high-order registers. The program for the
correction is stored in RAM for ROM correction.
When the program is being executed and the value of the program
counter matches with the set address value in the the ROM correction address registers,the program is branched to the start
address of RAM for ROM correction and then the correction program is executed. Use the JMP instruction (3-byte instruction) to
return the main program from the correction program.
The correctable area is up to two. There are two blocks of RAM for
ROM correction:
Block 1: Address 0A0016
Block 2: Address 0A2016
The ROM correction function is controlled by the ROM correction
enable register.
If the ROM correction function is not used, the ROM correction
vector may be used as normal RAM. When using the ROM correction vector as normal RAM, make sure to set bits 1 and 0 in the
ROM correction enable register to “0” (Disable).
Notes 1: When using the ROM correction function, set the ROM
correction address registers and then enable the ROM
correction with the ROM correction enable register.
2: Do not set addresses other than the ROM area in the
ROM correction address registers.
Do not set the same addresses in both the ROM correction address 1 registers and the ROM correction address
2 registers.
3: It is necessary to contain the process in the program to
transfer the correction program from an external
EEPROM and others to the RAM for ROM correction.
b7
ROM correction address 1 high-order register (RCA1H)
001016
ROM correction address 1 low-order register (RCA1L)
001116
ROM correction address 2 high-order register (RCA2H)
001216
ROM correction address 2 low-order register (RCA2L)
001316
Note: Do not set addressed other than the ROM area.
Fig. 42 ROM correction address register
0A0016
RAM 1 for ROM correction
0A1F16
0A2016
RAM 2 for ROM correction
0A3F16
Fig. 43 RAM for ROM correction
b0 ROM correction enable register (Address 001416) (Note)
RCR
Address 1 enable bit (RC0)
0 : Disable
1 : Enable
Address 2 enable bit (RC1)
0 : Disable
1 : Enable
Not used (returns “0” when read)
Note: Set the ROM correction address registers before enabling the ROM correction with the
ROM correction enable register.
Fig. 44 Structure of ROM correction enable register
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 46 of 73
3823 Group
φ CLOCK SYSTEM OUTPUT FUNCTION
The internal system clock φ or XCIN frequency signal can be output from port P41 by setting the φ output control register. Set bit 1
of the port P4 direction register to “1” when outputting φ clock.
b7
Set the bit 4 in the peripheral function expansion register to “1”
when the XCIN frequency signal is output.
b0
φ output control register
(CKOUT : address 002A16)
φ output control bit
0 : port function
1 : φ clock output or XCIN frequency signal output
Not used (return “0” when read)
Fig. 45 Structure of φ output control register
Temporary data register
RRF register
The temporary data register (addresses 002C16 to 002E16) is the
8-bit register and does not have the control function. It can be
used to store data temporarily. It is initialized after reset.
The RRF register (address 002F16)is the 8-bit register and does
not have the control function. As for the value written in this register, high-order 4 bits and low-order 4 bits interchange. It is
initialized after reset.
b7
b0
Temporary data register 0,1,2
(Address: 002C16, 002D16, 002E16)
TD0,TD1,TD2
DB0 data storage
DB1 data storage
DB2 data storage
DB3 data storage
DB4 data storage
DB5 data storage
DB6 data storage
DB7 data storage
b7
b0
RRF register (Address: 002F16)
RRFR
DB4 data storage
DB5 data storage
DB6 data storage
DB7 data storage
DB0 data storage
DB1 data storage
DB2 data storage
DB3 data storage
Fig. 46 Structure of temporary register, RPF register
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 47 of 73
3823 Group
WATCHDOG TIMER
executed, the watchdog timer does not operate.
When reading the watchdog timer control register is executed, the
contents of the high-order 6-bit counter and the STP instruction bit
(bit 6), and the count source selection bit (bit 7) are read out.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an
8-bit counter.
Bit 6 of Watchdog Timer Control Register
Initial Value of Watchdog Timer
• When bit 6 of the watchdog timer control register is “0”, the MCU
enters the stop mode by execution of STP instruction.
Just after releasing the stop mode, the watchdog timer restarts
counting (Note). When executing the WIT instruction, the watchdog timer does not stop.
• When bit 6 is “1”, execution of STP instruction causes an internal
reset. When this bit is set to “1” once, it cannot be rewritten to
“0” by program. Bit 6 is “0” at reset.
At reset or writing to the watchdog timer control register, each
watchdog timer is set to “FF16.” Instructions such as STA, LDM
and CLB to generate the write signals can be used.
The written data in bits 0 to 5 are not valid, and the above values
are set.
Bits 7 and 6 can be rewritten only once after reset.
After rewriting it is disable to write any data to this bit. These bits
become “0” after reset.
The time until the underflow of the watchdog timer register after
writing to the watchdog timer control register is executed is as follows (when the bit 7 of the watchdog timer control register is “0”) ;
Standard Operation of Watchdog Timer
The watchdog timer is in the stop state at reset and the watchdog
timer starts to count down by writing an optional value in the
watchdog timer control register. An internal reset occurs at an underflow of the watchdog timer. Then, reset is released after the
reset release time is elapsed, the program starts from the reset
vector address. Normally, writing to the watchdog timer control
register before an underflow of the watchdog timer is programmed. If writing to the watchdog timer control register is not
On-chip oscillator mode
control bit
On-chip oscillator
XCIN
“0”
Internal system clock
selection bit (bit 7 of
the CPU mode register)
1/1024
■ Note
The watchdog timer continues to count even during the wait time set
by timer 1 and timer 2 to release the stop state and in the wait
mode. Accordingly, do not underflow the watchdog timer in this time.
Data bus
Watchdog timer count
source selection bit
“0”
“1”
“1”
• at frequency/2/4/8 mode (f(XIN)) = 8 MHz): 32.768 ms
• at low-speed mode (f(XCIN) = 32 KHz): 8.19s
Watchdog timer L (2)
Watchdog timer H (6)
1/4
“FF16” is set when
watchdog timer control
register is written to.
XIN
Undefined instruction
Reset
STP instruction bit
STP instruction
RESET
Reset
circuit
Internal reset
Wait until reset release
Fig. 47 Block diagram of Watchdog timer
b7
b0
Watchdog timer control register (Address 003716)
WDTCON
Watchdog timer H (for read-out of high-order 6 bit)
“FF16” is set to watchdog timer by writing to these bits.
STP instruction function selection bit
0: Entering stop mode by execution of STP instruction
1: Internal reset by execution of STP instruction
Watchdog timer count source selection bit
0: f(XIN)/1024 (f(SUB)/1024 at low-speed mode)
Note : Bits 6 and 7 can be rewritten only once after reset.
1: f(XIN)/4 (f(SUB)/1024 at low-speed mode)
After rewriting it is disable to write any data to this bit.
Fig. 48 Structure of Watchdog timer control register
f(XIN)
=32msec (f(XIN)=8MHZ)
Internal reset
signal
Watchdog timer
detection
Fig. 49 Timing of reset output
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 48 of 73
3823 Group
PERIPHERAL FUNCTION EXTENSION REGISTER
The serial I/O transfer direction can be switched by setting the bit
0 in the peripheral function expansion register to “1”. This function
is valid only when the bit 6 in the serial I/O control register is set to
“1” (when the clock synchronous serial I/O is selected). P47 can
be selected as the output pin of the clock synchronous serial I/O
by setting the bit 1 in the peripheral function expansion register to
“1”. When setting P47 to the SOUT pin, set the bit 7 in the port P4
direction register to “1”. This function is valid only when the bit 6 in
the serial I/O control register to “1” (when the clock synchronous
serial I/O is selected). P-channel output of TXD and SOUT can be
disabled by the bits 2 and 3 in the peripheral function expansion
register. Set the bit 4 in the UART control register to “1” after selecting the pin to disable the P-channel output. XCIN frequency
signal can be output from the port P41 by setting the bit 4 in the
peripheral function expansion register to “1”. Set the bit 0 in the φ
output control register and the bit 1 in the port P4 direction register to “1” to output the XCIN frequency signal.
b7
b0
Peripheral function extension register (Address: 003016)
EXP
Transfer direction selection bit (valid when UART is used)
0 : LSB first
1 : MSB first
Synchronous serial I/O output pin selection bit
0:P45/TXD pin
1:P47/SRDY/SOUT pin
P-channel output disabled selection bit
00: P45/TXD pin
01: The bit 4 in the UART control register is invalid
10: P45/TXD pin or P47/SRDY/SOUT pin
11: P47/SRDY/SOUT pin
Output clock selection bit
0: φ clock output
1: XCIN frequency signal output
Not used (returns “0” when read)
(Do not write “1” to this bit)
Fig. 50 Structure of peripheral function extension register
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 49 of 73
3823 Group
RESET CIRCUIT
Power on
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between VCC(min.) and
5.5 V, and the quartz-crystal oscillator should be stable), reset is
released. After the reset is completed, the program starts from the
address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input
voltage meets VIL spec. when a power source voltage passes
VCC(min.).
RESET
VCC
Power
source
voltage
0V
Reset input
voltage
VIL spec.
0V
RESET
VCC
Power source voltage
detection circuit
Fig. 51 Reset Circuit Example
XIN
φ
RESET
Internal
reset
Reset address from
vector table
Address
?
Data
?
?
?
FFFC
FFFD
ADL
SYNC
XIN : about 8000 cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) =8•f(φ)
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 52 Reset Sequence
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 50 of 73
ADH, ADL
ADH
3823 Group
Register Contents
0016
(1)
Port P0 direction register
Address
000116
(2)
Port P1 direction register
000316
0016
(3)
Port P2 direction register
000516
0016
(4)
Port P4 direction register
000916
0016
(5)
Port P5 direction register
000B16
0016
(6)
Port P6 direction register
000D16
0016
(7)
Port P7 direction register
000F16
0016
(8)
ROM correctoin enable register (RCR)
001416
0016
(9)
PULL register A
001616
(10)
PULL register B
001716
(11)
Sirial I/O status register
001916
(12)
Sirial I/O control register
001A16
(13)
UART control register
001B16
(14)
Timer X high-order register
002016
F F1 6
(15)
Timer X low-order register
002116
F F1 6
(16)
Timer Y high-order register
002216
F F1 6
(17)
Timer Y low-order register
002316
F F1 6
(18)
Timer 1 register
002416
F F1 6
(19)
Timer 2 register
002516
0116
(20)
Timer 3 register
002616
F F1 6
(21)
Timer X mode register
002716
0016
(22)
Timer Y mode register
002816
0016
(23)
Timer 123 mode register
002916
0016
(24)
φ output control register
002A16
0016
(25)
CPU mode extension register
002B16
0016
(26)
Temporary data register 0
002C16
0016
(27)
Temporary data register 1
002D16
0016
(28)
Temporary data register 2
002E16
0016
(29)
RRF register
002F16
0016
(30)
Peripheral function extension register
003016
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0016
1
0
0
0
1
1
1
0
0
0016
0
0016
(31)
AD control register
003416
0
(32)
AD conversion low-order register
003616
✕
✕
0
0
0
0
0
0
(33)
Watchdog timer control register
003716
0
0
1
1
1
1
1
1
(34)
Segment output enable register
003816
0016
(35)
LCD mode register
003916
0016
(36)
Interrupt edge selection register
003A16
(37)
CPU mode register
003B16
0
0
0
(38)
Interrupt request register 1
003C16
0016
(39)
Interrupt request register 2
003D16
0016
(40)
Interrupt control register 1
003E16
0016
(41)
Interrupt control register 2
003F16
(42)
Processor status register
1
✕
✕
(43)
Program counter
(PS)
0
0
0
0
1
0
0
0
1
0
0
0016
1
0016
✕
✕
✕
✕
✕
(PCH)
Contents of address FFFD16
(PCL)
Contents of address FFFC16
Note: The contents of all other registers and RAM are undefined after reset, so they must be
initialized by software.
✕: undefined
Fig. 53 Initial status of microcomputer after reset
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 51 of 73
3823 Group
CLOCK GENERATING CIRCUIT
The 3823 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer's recommended values. The oscillation start voltage and the oscillation start time differ in
accordance with an oscillator, a circuit constant, or temperature,
etc.
When power supply voltage is low and the high frequency oscillator is used, an oscillation start will require sufficient conditions. No
external resistor is needed between XIN and XOUT since a feedback resistor exists on-chip. (an external feed-back resistor may
be needed depending on conditions.) However, an external feedback resistor is needed between XCIN and XCOUT since a resistor
does not exist between them.
To supply a clock signal externally, input it to the XIN pin and make
the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit
cannot directly input clocks that are externally generated. Accordingly, be sure to cause an external resonator to oscillate.
Immediately after poweron, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
XCIN XCOUT
XIN
XOUT
Rd
Rf
Rd
CCOUT
CCIN
CIN
COUT
Note : Insert a damping resistor if required. The resistance will vary
depending on the oscillator and the oscillation drive capacity
setting. Use the value recommended by the maker of the
oscillator. Also, if the oscillator manufacturer's data sheet
specifies that a feedback resistor be added external to the chip
though a feedback resistor exists on-chip, insert a feedback
resistor between XIN and XOUT following the instruction.
Fig. 54 Ceramic resonator circuit example
XCIN XCOUT
Rf
XIN
XOUT
Open
Rd
External oscillation circuit
CCIN
CCOUT
VCC
VSS
Fig. 55 External clock input circuit
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 52 of 73
Frequency Control
(1) frequency/8 Mode
The internal clock φ is the frequency of XIN divided by 8.
After reset, this mode is selected.
(2) frequency/4 Mode
The internal clock φ is the frequency of XIN divided by 4.
(3) frequency/2 Mode
The internal clock φ is half the frequency of XIN.
(4) Low-speed Mode
●The internal clock φ is the frequency of XIN or on-chip oscillation
frequency divided by 2.
●A low-power consumption operation can be realized by stopping
the main clock XIN in this mode. To stop the main clock, set bit 5
of the CPU mode register to “1”.
When the main clock XIN is restarted, set enough time for oscillation to stabilize by programming.
In low speed mode, the system clock φ can be switched to the
on-chip oscillator or XCIN. Use the on-chip oscillator control bit
(bit 0 in the CPU mode expansion register) for settings. To set
this bit to “0” from “1”, wait until XCIN oscillation stabilizes.
Note 1: If you switch the mode between frequency/2/4/8 mode
and low-speed, stabilize both XIN and XCIN oscillations.
The sufficient time is required for the sub-clock to stabilize, especially immediately after poweron and at
returning from stop mode. When switching the mode between middle/high-speed and low-speed, set the
frequency on condition that f(XIN) > 3f(XCIN).
2: In frequency/2/4/8 mode, XIN-X OUT oscillation does not
stop even if the main clock (XIN-XOUT) stop bit is set to
"1".
3: In low speed mode, XCIN-XCOUT oscillation does not stop
even if the port XC switch bit is set to "0".
3823 Group
Oscillation Control
(1) Stop Mode
(2) Wait Mode
If the WIT instruction is executed, only the system clock φ stops at
an "H" state. The states of main clock, on-chip oscillator and sub
clock are the same as the state before executing the WIT instruction, and oscillation does not stop. Since supply of system clock φ
is started immediately after the interrupt is received, the instruction can be executed immediately.
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and X IN and X CIN oscillators stop. Timer 1 is set to
“FF16” and timer 2 is set to “0116”.
Either X IN or X CIN divided by 16 is input to timer 1 as count
source, and the output of timer 1 is connected to timer 2. The bits
of the timer 123 mode register except bit 4 are cleared to “0”. Set
the timer 1 and timer 2 interrupt enable bits to disabled (“0”) before executing the STP instruction. Oscillator restarts at reset or
when an external interrupt is received, but the internal clock φ is
not supplied to the CPU until timer 2 underflows. This allows timer
for the clock circuit oscillation to stabilize.
Execution of the STP instruction sets the LCD enable bit (bit 3 of
the LCD mode register) to “0” and the LCD panel turns off.To
make the LCD panel turn on after returning from the stop mode,
set the LCD enable bit to “1”.
XCOUT
XCIN
“1”
On-chip
oscillator
XIN
“0”
Port XC
switch bit
On-chip oscillator
control bit
f(SUB)
Timer 1
Timer 2
XOUT Internal system clock selection bit count source
count source
(Note 2)
selection bit
(Note 1)
selection bit
“1”
“0”
“1” Low-speed mode
Timer 1
Timer 2
1/4
1/2
1/2
“0”
“0”
“1”
Frequency/2/4/8
mode
1/2
Main clock division
ratio selection bit
Frequency/4
“1” Frequency/8 mode
mode
control bit
Timing φ
(Internal system clock)
“0”
Main clock stop bit
Frequency/2/4
mode or lowspeed mode
Q
S
R
S
STP instruction
WIT
instruction
R
Q
Q S
R
STP instruction
Reset
Interrupt disable flag 1
Interrupt request
Notes 1: When using the low-speed mode, set the port XC switch bit to “1” .
2: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending
on conditions.
Fig. 56 Clock generating circuit block diagram
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 53 of 73
3823 Group
Rese
t
b7
“0
”
“0
“1
”
C
“ 0 M4
CM”
6
“1
“0
CM6
“1”
”
“0”
“0”
CM7 = 0 (8 MHz selected)
CM6 = 0 (Frequency/2/4)
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (Oscillating)
or EXPCM0 = 1
(On-chip oscillator oscillation)
“0
Low-power dissipation mode
(f(SUB)/2)
CM7 = 1 (32 kHz or on-chip
oscillator selected)
CM6 = 1 (Middle-speed)
CM5 = 1 (8 MHz stopped)
CM4 = 1 (Oscillating)
”
“0
”
CM6
“1”
Low-speed mode (f(SUB)/2)
“0”
C
“ 0 M5
CM”
“1
6
”
“1
”
“0
”
CM7 = 1 (32 kHz or on-chip
oscillator selected)
CM6 = 0 (High-speed)
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (Oscillating)
“0”
“0”
CM7 = 1 (32 kHz or on-chip
oscillator selected)
CM6 = 1 (Middle-speed)
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (Oscillating)
CM5
“1”
Frequency/2 mode (f(φ) = 4 MHz)
or frequency/4 mode (f(φ) = 2 MHz)
CM7
“1”
CM7
“1”
CM6
“1”
Low-speed mode (f(SUB)/2)
CM
” 6
“1 CM
”
“1
On-chip oscillator control bit
0 : On-chip oscillator not used
(on-chip oscillator stopping)
1 : On-chip oscillator used (Note 1)
(on-chip oscillator oscillating)
Frequency/4 mode control bit (Note 2)
(Valid only when high-speed mode)
0 : Frequency/2 mode φ = f(XIN)/2
1 : Frequency/4 mode φ = f(XIN)/4
”
“0”
(8 MHz selected)
(frequency/8)
(8 MHz oscillating)
(Oscillating)
or EXPCM0 = 1
(On-chip oscillator oscillation)
5
CPU mode extension register
(EXPCM : address: 002B16,)
Not used (returns “0” when read)
(Do not write “1” to this bit)
Frequency/8 mode (f(φ) = 1 MHz)
CM7 = 0
CM6 = 1
CM5 = 0
CM4 = 1
”
CM
”
“ 1 M6
C
”
“1
CM5
“1”
CM4
“1”
4
“0”
“0”
“0”
CM7 = 0 (8 MHz selected)
CM6 = 1 (Frequency/8)
CM5 = 0 (8 MHz oscillating)
CM4 = 0 (Stopped)
b4
Frequency/2 mode (f(φ) = 4 MHz)
or frequency/4 mode (f(φ) = 2 MHz)
CM7 = 0 (8 MHz selected)
CM6 = 0 (Frequency/2/4)
CM5 = 0 (8 MHz oscillating)
CM4 = 0 (Stopped)
CM4
“1”
CM6
“1”
Frequency/8 mode (f(φ) = 1 MHz)
Low-power dissipation mode
(f(SUB)/2)
“0”
CM7 = 1 (32 kHz or on-chip
oscillator selected)
CM6 = 0 (high-speed)
CM5 = 1 (8 MHz stopped)
CM4 = 1 (Oscillating)
Note 1 : The on-chip oscillator is selected for the operation clock
in low-speed mode regardless of XCIN-XCOUT.
2 : Valid only when the main clock division ratio selection bit
(bit 6 in the CPU mode register) is set to "0".
When "1" (frequency/8 mode) is selected for the main clock
division ratio selection bit or when the internal system clock
selection bit is set to 1, set "0" to the frequency/4 mode control bit.
b7
b4
CPU mode register
(CPUM : address 003B16)
CM4 :
0:
1:
CM5 :
0:
1:
CM6 :
0:
1:
CM7 :
0:
1:
Port Xc switch bit (Note 1)
I/O port (Oscillation stopped)
XCIN, XCOUT oscillating function
Main clock (XIN–XOUT) stop bit (Note 2)
Oscillating
Stopped
Main clock division ratio selection bit
f(XIN)/2 (frequency/2 mode),
or f(XIN)/4 (frequency/4 mode) (Note 3)
f(XIN)/8 (frequency/8 mode)
Internal system clock selection bit
XIN–XOUT selected (frequency/2/4/8 mode)
XCIN–XCOUT, or on-chip oscillator selected
(low-speed mode) (Note 4)
Note 1 : In low speed mode (XCIN is selected as the system clock φ),
XCIN-XCOUT oscillation does not stop even if the port XC switch bit
is set to "0".
2 : In frequency/2/4/8 mode, XIN-XOUT oscillation does not stop even if
the main clock (XIN-XOUT) stop bit is set to "1".
3 : When the system clock φ is divided by 4 of f(XIN), set the bit 6 in
the CPU mode register to “0” after setting the bit 1 in the CPU
mode extension register to “1”.
4 : When using the on-chip oscillator in low-speed mode, set the bit 7
in the CPU mode register to “1” after setting the bit 0 in the CPU
mode extension register to “1”.
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended.
3 : Timer and LCD operate in the wait mode.
4 : When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in frequency/2/4/8 mode.
5 : When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to frequency/2/4/8 mode.
7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
8 : f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation frequency of XCIN or the on-chip oscillator.
Internal clock φ is f(SUB)/2 in the low-speed mode.
9 : Set the CPU mode expansion register in advance when switching to low-speed mode which uses mode divided by 4 and on-chip oscillator.
10: In low speed mode, the system clock φ can be switched to the on-chip oscillator or XCIN. Use the on-chip oscillator control bit (bit 0 in the CPU mode
expansion register) for settings. To set this bit to "0" from "1", wait until XCIN oscillation stabilizes.
Fig. 57 State transitions of system clock
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 54 of 73
3823 Group
QzROM Writing Mode
In the QzROM writing mode, the user ROM area can be rewritten
while the microcomputer is mounted on-board by using a serial
programmer which is applicable for this microcomputer.
Table 13 lists the pin description (QzROM writing mode) and Figure 58 and Figure 59 show the pin connections.
Refer to Figure 60 and Figure 61 for examples of a connection
with a serial programmer.
Contact the manufacturer of your serial programmer for serial programmer. Refer to the user’s manual of your serial programmer
for details on how to use it.
Table 13 Pin description (QzROM writing mode)
Pin
Name
I/O
VCC, VSS
RESET
Power source
Reset input
XIN
Clock input
Input
Clock output
Output
Analog reference voltage Input
Analog power source
Input
I/O port
I/O
XOUT
VREF
AVSS
P00 –P07
P10 –P17
P20 –P27
P34 –P37
P41–P44
P50 –P57
P60 –P67
P40
P44
P42
P43
VPP input
ESDA input/output
ESCLK input
ESPGMB input
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
Input
Input
Input
I/O
Input
Input
page 55 of 73
Function
• Apply 1.8 to 5.5 V to VCC, and 0 V to VSS.
• Reset input pin for active “L”. Reset occurs when RESET pin is hold at an “L” level
for 16 cycles or more of XIN.
• Set the same termination as the single-chip mode.
• Input the reference voltage of A/D converter to VREF.
• Connect AVss to Vss.
• Input “H” or “L” level signal or leave the pin open.
• QzROM programmable power source pin.
• Serial data I/O pin.
• Serial clock input pin.
• Read/program pulse input pin.
SEG8
SEG9
SEG10
SEG11
P34/SEG12
P35/SEG13
P36/SEG14
P37/SEG15
P00/SEG16
P01/SEG17
P02/SEG18
P03/SEG19
P04/SEG20
P05/SEG21
P06/SEG22
P07/SEG23
P10/SEG24
P11/SEG25
P12/SEG26
P13/SEG27
P14/SEG28
P15/SEG29
P16/SEG30
P17/SEG31
3823 Group
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
GND
65
40
66
67
39
38
68
37
69
70
36
71
35
34
M3823XGX-XXXFP
M3823XGXFP
72
73
74
33
32
31
75
30
76
29
77
28
78
27
79
80
26
25
P20/KW0
P21/KW1
P22/KW2
P23/KW3
P24/KW4
P25/KW5
P26/KW6
P27/KW7
VSS
XOU
TXIN
P70/XCOUT
P71/XCIN
RESET
P40
P41/φ
GND
*
VCC
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VCC
VREF
AVSS
COM3
COM2
COM1
COM0
VL3
RESET
VPP
VL2
VL1
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P57/ADT
P56/TOUT
P55/CNTR1
P54/CNTR0
P53/RTP1
P52/RTP0
P51/INT3
P50/INT2
P47/SRDY/SOUT
P46/SCLK
P45/TXD
P44/RXD
P43/INT1
P42/INT0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
*: Connect to oscillation circuit.
: QzROM pin
ESDA
ESCLK
ESPGMB
PRQP0080GB-A (80P6N-A)
69
70
42
41
52
51
50
49
48
47
46
45
55
54
53
44
43
34
33
32
31
30
29
28
27
26
25
24
23
M3823XGX-XXXHP
M3823XGXHP
71
72
73
74
75
76
77
78
79
22
21
ESDA
PLQP0080KB-A (80P6Q-A)
Fig. 59 Pin connection diagram (M3823XGX-XXXHP)
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 56 of 73
P16/SEG30
P17/SEG31
P20/KW0
P21/KW1
P22/KW2
P23/KW3
P24/KW4
P25/KW5
P26/KW6
P27/KW7
VSS
XOUT
XIN
P70/XCOUT
P71/XCIN
RESET
P40
P41/φ
P42/INT0
P43/INT1
GND
RESET
VPP
ESCLK
ESPGMB
20
19
18
15
16
17
12
13
14
11
8
9
10
7
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P57/ADT
P56/TOUT
P55/CNTR1
P54/CNTR0
P53/RTP1
P52/RTP0
P51/INT3
P50/INT2
P47/SRDY/SOUT
P46/SCLK
P45/TXD
P44/RXD
4
5
6
80
1
2
GND
40
39
38
37
36
35
61
62
63
64
65
66
67
68
3
VCC
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VCC
VREF
AVSS
COM3
COM2
COM1
COM0
VL3
VL2
VL1
*
60
59
58
57
56
SEG10
SEG11
P34/SEG12
P35/SEG13
P36/SEG14
P37/SEG15
P00/SEG16
P01/SEG17
P02/SEG18
P03/SEG19
P04/SEG20
P05/SEG21
P06/SEG22
P07/SEG23
P10/SEG24
P11/SEG25
P12/SEG26
P13/SEG27
P14/SEG28
P15/SEG29
Fig. 58 Pin connection diagram (M3823XGX-XXXFP)
*: Connect to oscillation circuit.
: QzROM pin
3823 Group
3823 Group
Vcc
Vcc
P40
4.7 kΩ
4.7 kΩ
P44 (ESDA)
P42 (ESCLK)
P43 (ESPGMB)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RESET
circuit
*1
RESET
Vss
AVss
X IN
XOUT
Set the same termination as
the single-chip mode.
* 1 : Open-collector buffer
Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.
Fig. 60 When using E8 programmer, connection example
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 57 of 73
3823 Group
3823 Group
T_VDD
Vcc
T_VPP
P40
4.7 kΩ
T_TXD
4.7 kΩ
T_RXD
P44 (ESDA)
T_SCLK
P42 (ESCLK)
T_BUSY
T_PGM/OE/MD
N.C.
P43 (ESPGMB)
RESET circuit
T_RESET
GND
RESET
Vss
AVss
X IN
XOUT
Set the same termination as the
single-chip mode.
Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.
Fig. 61 When using programmer of Sisei Electronics System Co., LTD, connection example
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 58 of 73
3823 Group
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.
Initialize these flags at the beginning of the program.
Interrupt
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt
request register, execute at least one instruction before performing a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direction registers.
Serial Interface
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1”.
Serial I/O continues to output the final bit from the TXD pin after
transmission is completed.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 59 of 73
A/D Converter
The comparator is constructed linked to a capacitor. The conversion accuracy may be low because the charge is lost if the
conversion speed is not enough. Accordingly, set f(XIN) to at least
500kHz during A/D conversion in the middle-or high-speed mode.
Also, do not execute the STP or WIT instruction during an A/D
conversion.
In the low-speed mode, since the A/D conversion is executed by
the on-chip oscillator, the minimum value of f(XIN) frequency is not
limited.
LCD Drive Control Circuit
Execution of the STP instruction sets the LCD enable bit (bit 3 of
the LCD mode register) to “0” and the LCD panel turns off.To
make the LCD panel turn on after returning from the stop mode,
set the LCD enable bit to “1”.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency.
3823 Group
Countermeasures against noise
Noise
(1) Shortest wiring length
➀ Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin
as short as possible. Especially, connect a capacitor across the
RESET pin and the VSS pin with the shortest possible wiring
(within 20mm).
● Reason
The width of a pulse input into the RESET pin is determined by
the timing necessary conditions. If noise having a shorter pulse
width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is completely initialized. This may cause a program runaway.
Noise
Reset
circuit
RESET
VSS
VSS
N.G.
Reset
circuit
VSS
RESET
VSS
XIN
XOUT
VSS
N.G.
Fig. 62 Wiring for the RESET pin
➁ Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins
as short as possible.
• Make the length of wiring (within 20 mm) across the grounding
lead of a capacitor which is connected to an oscillator and the
VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS
patterns.
● Reason
If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway.
Also, if a potential difference is caused by the noise between
the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 60 of 73
O.K.
Fig. 63 Wiring for clock I/O pins
(2) Connection of bypass capacitor across VSS line and VCC line
In order to stabilize the system operation and avoid the latch-up,
connect an approximately 0.1 µF bypass capacitor across the VSS
line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC pin
at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin
with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS
line and VCC line.
• Connect the power source wiring via a bypass capacitor to the
VSS pin and the VCC pin.
VCC
O.K.
XIN
XOUT
VSS
VSS
N.G.
VCC
VSS
O.K.
Fig. 64 Bypass capacitor across the VSS line and the VCC line
3823 Group
(3) Oscillator concerns
In order to obtain the stabilized operation clock on the user system
and its condition, contact the oscillator manufacturer and select
the oscillator and oscillation circuit constants. Be careful especially when range of votage and temperature is wide.
Also, take care to prevent an oscillator that generates clocks for a
microcomputer operation from being affected by other signals.
➀ Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as
possible from signal lines where a current larger than the tolerance of current value flows.
● Reason
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When a
large current flows through those signal lines, strong noise occurs because of mutual inductance.
➁ Installing oscillator away from signal lines where potential levels
change frequently
Install an oscillator and a connecting pattern of an oscillator
away from signal lines where potential levels change frequently.
Also, do not cross such signal lines over the clock lines or the
signal lines which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as
the CNTR pin signal line) may affect other lines at signal rising
edge or falling edge. If such lines cross over a clock line, clock
waveforms may be deformed, which causes a microcomputer
failure or a program runaway.
(4) Analog input
The analog input pin is connected to the capacitor of a voltage
comparator. Accordingly, sufficient accuracy may not be obtained
by the charge/discharge current at the time of A/D conversion
when the analog signal source of high-impedance is connected to
an analog input pin. In order to obtain the A/D conversion result
stabilized more, please lower the impedance of an analog signal
source, or add the smoothing capacitor to an analog input pin.
(5) Difference of memory size
When memory size differ in one group, actual values such as an
electrical characteristics, A/D conversion accuracy, and the amount
of -proof of noise incorrect operation may differ from the ideal values.
When these products are used switching, perform system evaluation for each product of every after confirming product specification.
(6) Wiring to P40/(VPP) pin
When using P40/(VPP) pin as an input port, connect an approximately
5 kΩ resistor to the P40/(VPP) pin the shortest possible in series.
When not using P40/(VPP) pin, connect the pin the shortest possible to the GND pattern which is supplied to the Vss pin of the
microcomputer. In addition connecting an approximately 5 kΩ resistor in series to the GND could improve noise immunity. In this
case as well as the above mention, connect the pin the shortest
possible to the GND pattern which is supplied to the Vss pin of the
microcomputer.
● Reason
The P40/(VPP) pin of the QzROM version is the power source input pin
for the built-in QzROM. When programming in the QzROM, the impedance of the VPP pin is low to allow the electric current for writing to
flow into the built-in QzROM. Because of this, noise can enter easily. If
noise enters the P40/(VPP) pin, abnormal instruction codes or data are
read from the QzROM, which may cause a program runaway.
➀ Keeping oscillator away from large current signal lines
Microcomputer
(1) When using P40/(VPP) pin as an input port
The shortest
Mutual inductance
M
Approx. 5kΩ
P40/(VPP)
XIN
XOUT
VSS
Large
current
VSS
(Note)
(Note)
GND
➁ Installing oscillator away from signal lines where potential
levels change frequently
(2) When not using P40/(VPP) pin
The shortest
Do not cross
CNTR
XIN
XOUT
VSS
P40/(VPP)
(Note)
Approx. 5kΩ
VSS
(Note)
The shortest
N.G.
Fig. 65 Wiring for a large current signal line/Wiring of signal
lines where potential levels change frequently
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 61 of 73
Note. Shows the microcomputer's pin.
Fig. 66 Wiring for the P40/(VPP) pin
3823 Group
NOTES ON USE
Power Source Voltage
NOTES ON QzROM
Notes On QzROM Writing Orders
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the power source voltage is less than
the recommended operating conditions and design a system not
to cause errors to the system by this unstable operation.
When ordering the QzROM product shipped after writing, submit
the mask file (extension: .msk) which is made by the mask file
converter MM.
Be sure to set the ROM option ("MASK option" written in the mask
file converter) setup when making the mask file by using the mask
file converter MM.
LCD drive power supply
As for the QzROM product shipped after writing, the ROM code
protect is specified according to the ROM option setup data in the
mask file which is submitted at ordering.
The ROM option setup data in the mask file is “0016” for protect
enabled or “FF16” for protect disabled. Therefore, the contents of
the ROM code protect address (other than the user ROM area) of
the QzROM product shipped after writing is “0016” or “FF16”.
Note that the mask file which has nothing at the ROM option data
or has the data other than “0016” and “FF16” can not be accepted.
Power supply capacitor may be insufficient with the division resistance for LCD power supply,and the characteristic of the LCD panel.In
this case,there is the method of connecting the bypass capacitor
about 0.1 –0.33µF to V L1 –VL3 pins.The example of a strengthening
measure of the LCD drive power supply is shown in Figure 67.
• Connect by the shortest
possible wiring.
• Connect the bypass capacitor
to the VL1 –VL3 pins as short
as possible.
(Referential value:0.1–0.33µ F)
VL3
VL2
VL1
3823 Group
Fig. 67 Strengthening measure example of LCD drive power supply
Product shipped in blank
As for the product shipped in blank, Renesas does not perform the
writing test to user ROM area after the assembly process though
the QzROM writing test is performed enough before the assembly
process. Therefore, a writing error of approx.0.1 % may occur.
Moreover, please note the contact of cables and foreign bodies on a
socket, etc. because a writing environment may cause some writing errors.
Overvoltage
~
~
Make sure that voltage exceeding the Vcc pin voltage is not applied to other pins. In particular, ensure that the state indicated by
bold lines in figure below does not occur for pin P40 (VPP power
source pin for QzROM) during power-on or power-off. Otherwise
the contents of QzROM could be rewritten.
1.8V
1.8V
~
~
VCC pin voltage
P40 pin voltage
“L” input
~
~
P40 pin voltage
“H” input
(1) Input voltage to other MCU pins rises before Vcc pin voltage.
(2) Input voltage to other MCU pins falls after Vcc pin voltage.
Note: The internal circuitry is unstable when Vcc is below the minimum voltage specification of 1.
8 V (shaded portion), so particular care should be exercised regarding overvoltage.
Fig. 68 Timing Diagram (Applies to section indicated by bold line.)
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 62 of 73
Notes On ROM Code Protect
(QzROM product shipped after writing)
DATA REQUIRED FOR QzROM WRITING
ORDERS
The following are necessary when ordering a QzROM product
shipped after writing:
1. QzROM Writing Confirmation Form*
2. Mark Specification Form*
3. ROM data...........Mask file
* For the QzROM writing confirmation form and the mark specification form, refer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com).
Note that we cannot deal with special font marking (customer's
trademark etc.) in QzROM microcomputer.
3823 Group
ELECTRICAL CHARACTERISTICS
Table 14 Absolute maximum ratings
Symbol
VCC
VI
Parameter
Power source voltage
Input voltage P00–P07, P10–P17, P20–P27,
P34–P37, P40–P47, P50–P57
P60–P67, P70, P71
VI
VI
VI
VI
VO
Input voltage
Input voltage
Input voltage
Input voltage
Output voltage
VO
Output voltage P34–P37
VO
Output voltage P20–P27, P41–P47,P50–P57,
P60–P67, P70, P71
Output voltage SEG0–SEG11
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
VO
VO
Pd
Topr
Tstg
VL1
VL2
VL3
RESET, XIN
P00–P07, P10–P17
Conditions
All voltages are based on VSS.
When an input voltage is measured, output transistors are cut
off.
At output port
At segment output
At segment output
Ta = 25°C
Ratings
–0.3 to 6.5
Unit
V
–0.3 to VCC +0.3
V
–0.3 to VL2
VL1 to VL3
VL2 to 6.5
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VL3
–0.3 to VL3
V
V
V
V
V
V
V
–0.3 to VCC +0.3
V
–0.3 to VL3
–0.3 to VCC +0.3
300
–20 to 85
–40 to 150
V
V
mW
°C
°C
Table 15 Recommended operating conditions (1)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
VCC
VSS
VL 3
VREF
AVSS
VIA
Parameter
Power source voltage
(Note 1)
Frequency/2 mode
f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 5 MHz
f(XIN) = 2.5 MHz
Frequency/4 mode f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 5 MHz
Frequency/8 mode f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 5 MHz
Low-speed mode (OCO included)
Power source voltage
LCD power voltage
A/D conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
Note : When the A/D converter is used, refer to the recommended operating condition for A/D converter.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 63 of 73
Min.
4.5
4.0
2.0
1.8
2.5
2.0
1.8
2.5
2.0
1.8
1.8
Limits
Typ.
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
0
Max.
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
VCC
2.5
1.8
0
AVSS
VREF
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
3823 Group
Table 16 Recommended operating conditions (2)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
VIH
“H” input voltage
VIH
VIH
VIH
VIL
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
VIL
VIL
VIL
“L” input voltage
“L” input voltage
“L” input voltage
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
P00–P07, P10–P17,P34–P37, P40, P41, P45, P47, P52,
P53,P56,P60–P67,P70,P71 (CM4= 0)
P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
RESET
XIN
P00–P07, P10–P17,P34–P37, P40, P41, P45, P47, P52, P53,
P56,P60–P67,P70,P71 (CM4= 0)
P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
RESET
XIN
page 64 of 73
Min.
0.7VCC
Limits
Typ.
Max.
VCC
Unit
V
0.8VCC
0.8VCC
0.8VCC
0
VCC
VCC
VCC
0.3 VCC
V
V
V
V
0
0
0
0.2 VCC
0.2 VCC
0.2 VCC
V
V
V
3823 Group
Table 17 Recommended operating conditions (3)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
f(CNTR0)
f(CNTR1)
f(XIN)
f(XCIN)
Parameter
Min.
Limits
Typ.
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“H” peak output current
“H” peak output current
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17 (Note 2)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 2)
“L” peak output current
P00–P07, P10–P17 (Note 2)
“L” peak output current
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 2)
“H” average output current
P00–P07, P10–P17 (Note 3)
“H” average output current
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 3)
“L” average output current
P00–P07, P10–P17 (Note 3)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
“L” average output current
(Note 3)
(4.5 V ≤ VCC ≤ 5.5 V)
Input frequency for timers X and Y
(duty cycle 50%)
(4.0 V ≤ VCC ≤ 4.5 V)
(2.0 V ≤ VCC ≤ 4.0 V)
(VCC ≤ 2.0 V)
Frequency/2 mode
Main clock input oscillation frequency
(4.5 V ≤ VCC ≤ 5.5 V)
(duty cycle 50%)
(Note 4)
Frequency/2 mode
(4.0 V ≤ VCC ≤ 4.5 V)
Frequency/2 mode
(2.0 V ≤ VCC ≤ 4.0 V)
Frequency/2 mode
(1.8 V ≤ VCC ≤ 2.0 V)
Frequency/4 mode
(2.5 V ≤ VCC ≤ 5.5 V)
Frequency/4 mode
(2.0 V ≤ VCC ≤ 2.5 V)
Frequency/4 mode
(1.8 V ≤ VCC ≤ 2.0 V)
Frequency/8 mode
(2.5 V ≤ VCC ≤ 5.5 V)
Frequency/8 mode
(2.0 V ≤ VCC ≤ 2.5 V)
Frequency/8 mode
(1.8 V ≤ VCC ≤ 2.0 V)
Sub-clock input oscillation frequency
(duty cycle 50%)
(Note 5)
Max.
Unit
–40
–40
40
40
–20
–20
20
20
–2
–5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
5
10
mA
mA
–1.0
mA
–2.5
mA
2.5
5.0
mA
mA
5.0
2 ✕ VCC – 4
0.75 ✕ VCC + 1
6.25 ✕ VCC - 10
10.0
MHz
MHz
MHz
MHz
MHz
4 ✕ VCC – 8
MHz
1.5 ✕ VCC + 2 MHz
12.5 ✕ VCC - 20 MHz
10.0
MHz
4 ✕ VCC
MHz
15 ✕ VCC – 22 MHz
10.0
MHz
4 ✕ VCC
MHz
15 ✕ VCC – 22 MHz
32.768
80
kHz
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value
measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: When the A/D converter is used, refer to the recommended operating condition for A/D converter.
5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 65 of 73
3823 Group
Table 18 Electrical characteristics (1)
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
VOH
“H” output voltage
P00–P07, P10–P17
VOH
“H” output voltage
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
“L” output voltage
P00–P07, P10–P7
VOL
“L” output voltage
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
VOL
Test conditions
IOH = –2.5 mA
IOH = –0.6 mA
VCC = 2.5 V
IOH = –5 mA
IOH = –1.25 mA
IOH = –1.25 mA
VCC = 2.5 V
IOL = 5 mA
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.5 V
IOL = 10 mA
IOL = 2.5 mA
IOL = 2.5 mA
VCC = 2.5 V
Min.
Limits
Typ.
Max.
Unit
VCC–2.0
V
VCC–1.0
V
VCC–2.0
VCC–0.5
V
V
VCC–1.0
V
2.0
0.5
V
V
1.0
V
2.0
0.5
V
V
1.0
V
VT+ – VT–
Hysteresis
INT0–INT3, ADT, CNTR0, CNTR1, P20–P27
0.5
V
VT+ – VT–
Hysteresis
SCLK, RXD
0.5
V
VT+ – VT–
Hysteresis
RESET
0.5
V
IIH
“H” input current
P00–P07, P10–P17, P34–P37
IIH
IIH
IIH
IIL
IIL
IIL
IIL
VRAM
Note:
RESET : VCC = 2.0 V to 5.5 V
VI = VCC
Pull-downs “off”
VCC = 5 V, VI = VCC
Pull-downs “on”
VCC = 3 V, VI = VCC
Pull-downs “on”
“H” input current
P20–P27, P40–P47, P50–P57, P60–P67,
P70, P71 (Note)
VI = VCC
“H” input current RESET
“H” input current XIN
“L” input current
P00–P07, P10–P17, P34–P37,P40
“L” input current
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
VI = VCC
VI = VCC
VI = VSS
“L” input current RESET
“L” input current XIN
RAM hold voltage
VI = VSS
Pull-ups “off”
VCC = 5 V, VI = VSS
Pull-ups “on”
VCC = 3 V, VI = VSS
Pull-ups “on”
VI = VSS
VI = VSS
When clock is stopped
5.0
µA
30
70
140
µA
6.0
25
45
µA
5.0
µA
5.0
µA
µA
–5.0
µA
–5.0
µA
4.0
–30
–70
–140
µA
–6.0
–25
–45
µA
–5.0
µA
5.5
µA
V
–4.0
1.8
When “1” is set to the port XC switch bit (bit 4 at address 003B16) of CPU mode register, the drive ability of port P7 0 is different from the value above
mentioned.
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 66 of 73
3823 Group
Table 19 Electrical characteristics (2)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
ICC
f(XIN) = 10 MHz
Limits
Typ.
4.3
Max.
8.6
f(XIN) = 8 MHz
3.7
7.4
mA
f(XIN) = 4 MHz
2.5
5.0
mA
f(XIN) = 4 MHz
0.8
1.6
mA
f(XIN) = 2 MHz
0.4
0.8
mA
f(XIN) = 10 MHz
2.9
5.8
mA
f(XIN) = 8 MHz
2.5
5.0
mA
f(XIN) = 4 MHz
1.7
3.4
mA
f(XIN) = 10 MHz
1.0
2.0
mA
f(XIN) = 8 MHz
0.8
1.6
mA
f(XIN) = 4 MHz
0.5
1.0
mA
f(XIN) = 2 MHz
0.3
0.6
mA
f(XIN) = 10 MHz
2.2
4.4
mA
f(XIN) = 8 MHz
1.9
3.8
mA
f(XIN) = 4 MHz
1.4
2.8
mA
f(XIN) = 2 MHz
1.0
2.0
mA
f(XIN) = 10 MHz
0.7
1.4
mA
f(XIN) = 8 MHz
0.6
1.2
mA
f(XIN) = 4 MHz
0.4
0.8
mA
f(XIN) = 2 MHz
0.2
0.4
mA
f(XIN) = 10 MHz
1.35
2.7
mA
mode
f(XIN) = 8 MHz
1.2
2.4
mA
In WIT state
f(XIN) = 4 MHz
0.9
1.8
mA
f(XIN) = 2 MHz
0.8
1.6
mA
f(XIN) = 10 MHz
0.35
0.7
mA
f(XIN) = 8 MHz
0.3
0.6
mA
f(XIN) = 4 MHz
0.2
0.4
mA
f(XIN) = 2 MHz
0.15
0.3
mA
f(XCIN) = 32 kHz
13
26
µA
On-chip oscillator
80
240
µA
f(XCIN) = 32 kHz
7
14
µA
On-chip oscillator
14
42
µA
f(XCIN) = 32 kHz
5.5
11
µA
On-chip oscillator
20
60
µA
f(XCIN) = 32 kHz
3.5
7
µA
On-chip oscillator
3.5
10
µA
VCC = 5 V, all modes
500
VCC = 2.5 V, all modes
50
Parameter
Power source current
Test conditions
Frequency/2 mode
VCC = 5.0 V
VCC = 2.5 V
Frequency/4 mode
VCC = 5.0 V
VCC = 2.5 V
Frequency/8 mode
VCC = 5.0 V
VCC = 2.5 V
Frequency/2/4/8
VCC = 5.0 V
VCC = 2.5 V
Low-speed mode
VCC = 5.0 V
f(XIN) = stopped
VCC = 2.5 V
Low-speed mode
VCC = 5.0 V
f(XIN) = stopped
In WIT state
VCC = 2.5 V
Current increased at
A/D converter operating
All oscillation stopped
Ta = 25 °C, Output transistors “off” (in STP state)
Min.
0.1
All oscillation stopped
Ta = 85 °C, Output transistors “off” (in STP state)
ROCO
On-chip oscillator oscillatoin
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 67 of 73
VCC = 2.5 V, Ta = 25 °C
80
Unit
mA
µA
µA
1.0
µA
10
µA
kHz
3823 Group
Table 20 A/D converter characteristics (1) (in 8 bit A/D mode)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
–
ABS
tCONV
RLADDER
IVREF
IIA
Parameter
Resolution
Absolute accuracy
(excluding quantization error)
Test conditions
ADL2 = “0”, ADL1 = “0”, CPUM7 = “0”
2.2 V ≤ VCC = VREF ≤ 5.5 V
f(XIN) = 2 ✕ VCC MHz ≤ 10 MHz
ADL2 = “0”, ADL1 = “0”, CPUM7 = “0”
2.0 V ≤ VCC = VREF < 2.2 V
f(XIN) = 4.4 MHz
ADL2 = “0”, ADL1 = “1”, CPUM7 = “0”
VCC = VREF = 4.0 to 5.5 V
f(XIN) = 2 ✕ VCC MHz ≤ 10 MHz
ADL2 = “1”, ADL1 = “0”, CPUM7 = “1” and EXPCM0 = “1”
VCC = VREF = 1.8 to 2.2 V
f(XIN) = 8 MHz (ADL2 = “0”, ADL1 = “0”, CPUM7 = “0”)
Conversion time
Ladder resistor
Reference power source input current VREF = 5 V
Analog port input current
Limits
Min. Typ.
Max.
8
±2
12
50
35
150
Unit
Bits
LSB
±3
LSB
±3
LSB
±4
LSB
TC(XIN)✕100
100
200
5.0
µs
kΩ
µA
µA
Table 21 A/D converter characteristics (2) (in 10 bit A/D mode)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
–
ABS
tCONV
RLADDER
IVREF
IIA
Parameter
Resolution
Absolute accuracy
(excluding quantization error)
Test conditions
ADL2 = “0”, ADL1 = “0”, CPUM7 = “0”
2.2 V ≤ VCC = VREF ≤ 5.5 V
f(XIN) = 2 ✕ VCC MHz ≤ 10 MHz
ADL2 = “0”, ADL1 = “1”, CPUM7 = “0”
VCC = VREF = 4.0 to 5.5 V
f(XIN) = 2 ✕ VCC MHz ≤ 10 MHz
ADL2 = “1”, ADL1 = “0”, CPUM7 = “1” and EXPCM0 = “1”
VCC = VREF = 1.8 to 2.2 V
f(XIN) = 8 MHz (ADL2 = “0”, ADL1 = “0”, CPUM7 = “0”)
Conversion time
Ladder resistor
Reference power source input current VREF = 5 V
Analog port input current
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 68 of 73
Limits
Min. Typ.
Max.
10
±4
12
50
35
150
Unit
Bits
LSB
±4
LSB
±4
LSB
TC(XIN)✕100
100
200
5.0
kΩ
µA
µA
µs
3823 Group
Table 22 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
tw(RESET)
tc(XIN)
Reset input “L” pulse width
Main clock input cycle time (XIN input)
twH(XIN)
Main clock input “H” pulse width
twL(XIN)
Main clock input “L” pulse width
tc(CNTR)
CNTR0, CNTR1 input cycle time
twH(CNTR)
CNTR0, CNTR1 input “H” pulse width
twL(CNTR)
CNTR0, CNTR1 input “L” pulse width
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(RXD–SCLK)
th(SCLK–RXD)
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
Min.
4.0 ≤
4.5 ≤
4.0 ≤
4.5 ≤
4.0 ≤
4.5 ≤
4.0 ≤
4.5 ≤
4.0 ≤
4.5 ≤
4.0 ≤
4.5 ≤
Vcc <
Vcc ≤
Vcc <
Vcc ≤
Vcc <
Vcc ≤
Vcc <
Vcc ≤
Vcc <
Vcc ≤
Vcc <
Vcc ≤
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
1000/(4 ✕ VCC–8)
100
45
40
45
40
1000/(2 ✕ VCC–4)
200
105
85
105
85
80
80
800
370
370
220
100
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this limits value by four when bit 6 of address 001A16 is “0” (UART).
Table 23 Timing requirements (2)
(VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
tw(RESET)
tc(XIN)
Reset input “L” pulse width
Main clock input cycle time (XIN input)
twH(XIN)
Main clock input “H” pulse width
twL(XIN)
Main clock input “L” pulse width
tc(CNTR)
CNTR0, CNTR1 input cycle time
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(RXD–SCLK)
th(SCLK–RXD)
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
Min.
2.0 ≤ Vcc ≤ 4.0 V
Vcc < 2.0 V
2.0 ≤ Vcc ≤ 4.0 V
Vcc < 2.0 V
2.0 ≤ Vcc ≤ 4.0 V
Vcc < 2.0 V
2.0 ≤ Vcc ≤ 4.0 V
Vcc < 2.0 V
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this limits value by four when bit 6 of address 001A16 is “0” (UART).
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 69 of 73
Limits
Typ.
2
125
1000/(10 ✕ VCC–12)
50
70
50
70
1000/VCC
1000/(5 ✕ VCC–8)
tc(CNTR)/2–20
tc(CNTR)/2–20
230
230
2000
950
950
400
200
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3823 Group
Table 24 Switching characteristics (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
twH(SCLK)
twL(SCLK)
td(SCLK–TXD)
tv(SCLK–TXD)
tr(SCLK)
tf(SCLK)
Parameter
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note)
Serial I/O output valid time (Note)
Serial I/O clock output rising time
Serial I/O clock output falling time
Min.
tC (SCLK)/2–30
tC (SCLK)/2–30
Limits
Typ.
Max.
140
–30
30
30
Unit
ns
ns
ns
ns
ns
ns
Note : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Table 25 Switching characteristics (2)
(VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
twH(SCLK)
twL(SCLK)
td(SCLK–TXD)
tv(SCLK–TXD)
tr(SCLK)
tf(SCLK)
Parameter
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note)
Serial I/O output valid time (Note)
Serial I/O clock output rising time
Serial I/O clock output falling time
Min.
tC (SCLK)/2–100
tC (SCLK)/2–100
Limits
Typ.
Max.
350
–30
100
100
Note : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Measurement output pin
1 kΩ
100 pF
Measurement output pin
CMOS output
100 pF
N-channel open-drain output (Note)
Note: When bit 4 of the UART control register
(address 001B16) is “1”. (N-channel opendrain output mode)
Fig. 69 Circuit for measuring output switching characteristics
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 70 of 73
Unit
ns
ns
ns
ns
ns
ns
3823 Group
tC(CNTR)
tWH(CNTR)
CNTR0, CNTR1
tWL(CNTR)
0.8VCC
0.2VCC
tWH(INT)
INT0–INT3
tWL(INT)
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
XIN
0.8VCC
0.2VCC
tC(SCLK)
tf
tr
tWL(SCLK)
SCLK
0.8VCC
0.2VCC
tsu(RXD-SCLK)
RXD
th(SCLK-RXD)
0.8VCC
0.2VCC
td(SCLK-TXD)
TXD
Fig. 70 Timing diagram
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
tWH(SCLK)
page 71 of 73
tv(SCLK-TXD)
3823 Group
PACKAGE OUTLINE
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas
Technology website.
JEITA Package Code
P-QFP80-14x20-0.80
RENESAS Code
PRQP0080GB-A
Previous Code
80P6N-A
MASS[Typ.]
1.6g
HD
*1
D
64
41
65
HE
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
ZE
*2
E
40
Reference
Symbol
80
25
1
ZD
24
D
E
A2
HD
HE
A
A1
bp
c
c
Index mark
A
A2
F
*3
y
bp
L
A1
e
Detail F
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 72 of 73
e
y
ZD
ZE
L
Dimension in Millimeters
Min Nom Max
19.8 20.0 20.2
13.8 14.0 14.2
2.8
22.5 22.8 23.1
16.5 16.8 17.1
3.05
0.1 0.2
0
0.3 0.35 0.45
0.13 0.15 0.2
0°
10°
0.65 0.8 0.95
0.10
0.8
1.0
0.4 0.6 0.8
3823 Group
JEITA Package Code
P-LQFP80-12x12-0.50
RENESAS Code
PLQP0080KB-A
Previous Code
80P6Q-A
MASS[Typ.]
0.5g
HD
*1
D
60
41
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
40
61
bp
c
HE
*2
E
c1
b1
Reference
Symbol
ZE
Terminal cross section
80
21
1
20
ZD
Index mark
bp
c
A
*3
A1
y
e
A2
F
L
x
L1
Detail F
Rev.2.02 Jun 19, 2007
REJ03B0146-0202
page 73 of 73
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
11.9 12.0 12.1
11.9 12.0 12.1
1.4
13.8 14.0 14.2
13.8 14.0 14.2
1.7
0.1 0.2
0
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
10°
0.5
0.08
0.08
1.25
1.25
0.3 0.5 0.7
1.0
REVISION HISTORY
Rev.
3823 GROUP DATA SHEET
Date
Description
Summary
Page
1.00
05/13/05
2.00
05/07/07
First edition
6
8
9
14
40
49
52
54
55
60
2.01
05/11/08
6
61
65-66
2.02
07/06/19
−
6
8
9
10
15
22
23-27
46
48
51
52
53
54
55-58
58
59
63
66
Table 3 is partly revised
Fig.5 is partly added
Table 4 is revised
“ROM Code Protect Address” is added
Fig.10 is revised
“STP instruction Execution” is revised
“Oscillation Control” (1) Stop Mode is partly revised
“LCD drive Control Circuit” is revised
“(6) Wiring to P40/(VPP) pin” is revised
Fig.59 is revised
Fig.60 is partly deleted
“NOTES ON QzROM” is added
Table 18 is partly added
Table 3 is partly revised
Table 19, 20 are partly revised
PACKAGE OUTLINE revised
“RENESAS TECHNICAL UPDATE” reflected:
TN-740-A111A/E
Table 3: Function except a port function; •Serial I/O function pins → •Serial interface function pins
Fig. 5 M38234G4, M38235G6: Under development → Mass production
Note deleted
Table 4: Under development deleted
FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU):
Description added
Fig. 11: Note added
CPU mode extension register (002B16) → CPU mode expansion register
Peripheral function extension register (003016) → Peripheral function
expansion register
Table 8: AVSS added, Note revised
INTERRUPTS: Description revised, Fig. 18-20 added
ROM CORRECTION FUNCTION: Description added
Initial Value of Watchdog Timer: Description added
Standard Operation of Watchdog Timer: A part of description deleted
Bit 6 and bit 7 of Watchdog Timer Control Register: added and revised
Fig. 48 revised, Note added
Fig. 53: Port P0 direction register (000016) → (000116)
Frequency Control: Description revised
Fig. 56: revised
Fig. 57: revised
QzROM Writing Mode: added
Processor Status Register: added
Overvoltage: Description revised and Fig. 68 added
Table 15
VCC: Frequency/4 mode → Frequency/8 mode
VREF: Limits Min. 2.0 → 1.8
Table 18: VRAM added
(1/2)
REVISION HISTORY
Rev.
3823 GROUP DATA SHEET
Date
Description
Summary
Page
2.02
07/06/19
67
72
Table 19
ROCO: Ta = 25 °C added
Note added
(2/2)
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
http://www.renesas.com
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .7.0