Freescale MC3S12XF512J0MLHR S12x microcontroller Datasheet

MC9S12XF512 Reference Manual
Covers
MC9S12XF512
MC9S12XF384
MC9S12XF256
MC9S12XF128
S12X
Microcontrollers
MC9S12XF512V1RM
Rev.1.19
18-May-2010
freescale.com
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most
current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
A full list of family members and options is included in the appendices.
The following revision history table summarizes changes contained in this document.
This document contains information for all constituent modules, with the exception of the S12 CPU. For S12 CPU
information please refer to the CPU S12 Reference Manual.
Revision History
Date
Revision
Level
06-Dec-2007
1.12
Updated memory map description for family parts (1.1.4 MC9S12XF512 - Address Mapping)
Updated derivative differences w.r.t. DFlash size (D.1 Memory Sizes and Package Options S12XF Family)
12-Dec-2007
1.13
Add FTM BG (384K2/256K2)
08-Jan-2008
1.14
Remove table for Module Run Supply Currents (A-10)
Remove 3.3V columns in Table A-27, 3.0V columns in Table A-28
Add FTM BG (128K2)
15-Jan-2008
1.15
Fixed typo in detailed register map (SPI1/SPI1DRH)
Import updated BGs
VREG, ECT, INT, DBG
Fixed typo in Table 1-6
05-Mar-2008
1.16
Updated ordering info for 112 LQFP
02-Oct-2008
1.17
Updated NVM timing parameter section for brownout case
Specified time delay from RESET to start of CPU code execution
Added NVM patch Part IDs
Enhanced ECT GPIO / timer function transitioning description
CRG section updated
01-Mar-2010
1.18
Updated PIM,FTM,XGATE,MSCAN,DBG,BDM,ADC,CRG sections
Corrected startup from reset min cycle count
18-May-2010
1.19
Updated ECT section (see ECT revision history table)
Description
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2008,2009,2010. All rights reserved.
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Chapter 1
MC9S12XF-Family Reference Manual. . . . . . . . . . . . . . . . . . . . 23
Chapter 2
S12XE Clocks and Reset Generator (S12XECRG) . . . . . . . . . 83
Chapter 3
Voltage Regulator (S12VREGL3V3V1) . . . . . . . . . . . . . . . . . . 113
Chapter 4
384 KByte Flash Module (S12XFTM384K2V1) . . . . . . . . . . . . 131
Chapter 5
Pierce Oscillator (S12OSCLCPV2) . . . . . . . . . . . . . . . . . . . . . 193
Chapter 6
Security (S12XFSECV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Chapter 7
Interrupt (S12XINTV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Chapter 8
256 KByte Flash Module (S12XFTM256K2XFV1) . . . . . . . . . . 221
Chapter 9
512 KByte Flash Module (S12XFTM512K3V1) . . . . . . . . . . . . 281
Chapter 10
128 KByte Flash Module (S12XFTM128K2XFV1) . . . . . . . . . . 343
Chapter 11
Memory Mapping Control (S12XMMCV4) WITH FLEXRAY . . 403
Chapter 12
Clock Generation Module using IPLL (CGMIPLL) . . . . . . . . . 447
Chapter 13
FlexRay Communication Controller (FLEXRAY) . . . . . . . . . . 457
Chapter 14
XGATE (S12XGATEV3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Chapter 15
Background Debug Module (S12XBDMV2) . . . . . . . . . . . . . . 731
Chapter 16
S12X Debug (S12XDBGV3) Module . . . . . . . . . . . . . . . . . . . . 757
Chapter 17
Memory Protection Unit (S12XMPUV2) . . . . . . . . . . . . . . . . . 801
Chapter 18
External Bus Interface (S12XEBIV4) . . . . . . . . . . . . . . . . . . . . 815
Chapter 19
Port Integration Module (S12XFPIMV2) . . . . . . . . . . . . . . . . . 835
Chapter 20
Pulse Width Modulator with Fault Protection (PMF15B6C) . 901
Chapter 21
Scalable Controller Area Network (S12MSCANV2) . . . . . . . . 957
Chapter 22
1013
Enhanced Programmable Interrupt Timer (S12XEPIT24B8CV1)
Chapter 23
Serial Communication Interface (S12SCIV5) . . . . . . . . . . . . 1033
Chapter 24
Analog-to-Digital Converter (ADC12B16C) . . . . . . . . . . . . . 1069
Chapter 25
Serial Peripheral Interface (S12SPIV5) . . . . . . . . . . . . . . . . . 1095
Chapter 26
Enhanced Capture Timer (ECT16B8CV3). . . . . . . . . . . . . . . 1125
Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177
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Appendix B Package Physical Dimension Information. . . . . . . . . . . . . . 1235
Appendix C PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238
Appendix D Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
Appendix E Detailed Register Address Map. . . . . . . . . . . . . . . . . . . . . . . 1244
Appendix F Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288
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Chapter 1
MC9S12XF-Family Reference Manual
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.1.3 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.1.4 MC9S12XF512 - Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.1.5 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.1.6 Part ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.2.1 System Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
1.2.3 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.2.4 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.2.5 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.2.6 TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.2.7 BKGD / MODC — Background Debug and Mode Pin . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.2.8 Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.2.9 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.4.1 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.4.2 Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
1.4.3 Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
1.6.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
1.6.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
1.6.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
EPIT External Trigger Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ATD External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
MPU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
VREG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
1.10.1 Temperature Sensor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
BDM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
FlexRay IPLL (CGMIPLL) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
1.12.1 CGMIPLL function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
1.12.2 Entry into and exit from low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Chapter 2
S12XE Clocks and Reset Generator (S12XECRG)
2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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2.2
2.3
2.4
2.5
2.6
2.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.2.1 VDDPLL, VSSPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.2.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.4.1 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.4.2 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2.4.3 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
2.5.1 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
2.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Chapter 3
Voltage Regulator (S12VREGL3V3V1)
3.1
3.2
3.3
3.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
3.2.1 VDDR — Regulator Power Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
3.2.2 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
3.2.3 VDD, VSS — Regulator Output1 (Core Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 116
3.2.4 VDDF — Regulator Output2 (NVM Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.2.5 VDDPLL, VSSPLL — Regulator Output3 (PLL) Pins . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.2.6 VDDX — Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.2.7 VREGEN — Optional Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.2.8 VREG_API — Optional Autonomous Periodical Interrupt Output Pin . . . . . . . . . . . . . . 117
Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
3.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
3.4.2 Regulator Core (REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
3.4.3 Low-Voltage Detect (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
3.4.4 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
3.4.5 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
3.4.6 HTD - High Temperature Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
3.4.7 Regulator Control (CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
3.4.8 Autonomous Periodical Interrupt (API) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
3.4.9 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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3.4.10 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
3.4.11 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Chapter 4
384 KByte Flash Module (S12XFTM384K2V1)
4.1
4.2
4.3
4.4
4.5
4.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
4.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.4.2 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
4.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
4.4.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
4.4.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
4.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
4.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 192
4.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 192
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Chapter 5
Pierce Oscillator (S12OSCLCPV2)
5.1
5.2
5.3
5.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
5.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
5.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . 194
5.2.2 EXTAL and XTAL — Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
5.4.1 Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
5.4.2 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
5.4.3 Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
5.4.4 Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Chapter 6
Security (S12XFSECV2)
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
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6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Reprogramming the Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Complete Memory Erase (Special Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Chapter 7Interrupt (S12XINTV2)
7.1
7.2
7.3
7.4
7.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
7.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
7.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
7.4.1 S12X Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
7.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
7.4.3 XGATE Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
7.4.4 Priority Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
7.4.5 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
7.4.6 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
7.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
7.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
7.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Chapter 8
256 KByte Flash Module (S12XFTM256K2XFV1)
8.1
8.2
8.3
8.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
8.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
8.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
8.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
8.4.2 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
8.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
8.4.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
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8.6
8.4.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
8.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
8.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 280
8.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 280
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Chapter 9
512 KByte Flash Module (S12XFTM512K3V1)
9.1
9.2
9.3
9.4
9.5
9.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
9.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
9.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
9.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
9.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
9.4.2 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
9.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
9.4.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
9.4.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
9.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
9.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 341
9.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 341
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Chapter 10
128 KByte Flash Module (S12XFTM128K2XFV1)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
10.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
10.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
10.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
10.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
10.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
10.4.2 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
10.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
10.4.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
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10.4.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
10.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
10.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
10.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 402
10.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 402
10.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Chapter 11
Memory Mapping Control (S12XMMCV4) SUPPORTING FLEXRAY
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
11.1.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
11.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
11.1.3 S12X Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
11.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
11.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
11.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
11.4.1 MCU Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
11.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
11.4.3 Chip Access Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
11.4.4 Chip Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
11.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
11.5.1 CALL and RTC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
11.5.2 Port Replacement Registers (PRRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
11.5.3 On-Chip ROM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Chapter 12
Clock Generation Module using IPLL (CGMIPLL)
Block Description
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
12.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
12.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
12.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
12.2.1 VDDPLL, VSSPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
12.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
12.4.1 Examples of IPLL divider settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
12.4.2 IPLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
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12.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
12.5.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Chapter 13FlexRay Communication Controller (FLEXRAY)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
13.1.1 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
13.1.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
13.1.3 Color Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
13.1.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
13.1.5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
13.1.6 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
13.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
13.3 Controller Host Interface Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
13.4 Protocol Engine Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
13.4.1 Oscillator Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
13.4.2 PLL Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
13.4.3 PLL Lock Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
13.5 Memory Map and Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
13.5.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
13.5.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
13.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
13.6.1 Message Buffer Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
13.6.2 Physical Message Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
13.6.3 Message Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
13.6.4 FlexRay Memory Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
13.6.5 Physical Message Buffer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
13.6.6 Individual Message Buffer Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
13.6.7 Individual Message Buffer Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
13.6.8 Individual Message Buffer Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
13.6.9 Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
13.6.10Channel Device Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
13.6.11External Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
13.6.12Sync Frame ID and Sync Frame Deviation Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
13.6.13MTS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
13.6.14Sync Frame and Startup Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
13.6.15Sync Frame Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
13.6.16Strobe Signal Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
13.6.17Timer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
13.6.18Slot Status Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
13.6.19Interrupt Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
13.6.20Lower Bit Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
13.7 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
13.7.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
13.7.2 Shut Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
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13.7.4
13.7.5
13.7.6
Number of Usable Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Protocol Control Command Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
Protocol Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Message Buffer Search on Simple Message Buffer Configuration . . . . . . . . . . . . . . . . 612
Chapter 14
XGATE (S12XGATEV3)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
14.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
14.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
14.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
14.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
14.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
14.4.1 XGATE RISC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
14.4.2 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
14.4.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
14.4.4 Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
14.4.5 Software Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
14.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
14.5.1 Incoming Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
14.5.2 Outgoing Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
14.6 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
14.6.1 Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
14.6.2 Leaving Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
14.7 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
14.8 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
14.8.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
14.8.2 Instruction Summary and Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
14.8.3 Cycle Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
14.8.4 Thread Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
14.8.5 Instruction Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
14.8.6 Instruction Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
14.9 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
14.9.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
14.9.2 Code Example (Transmit "Hello World!" on SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
14.9.3 Stack Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Chapter 15
Background Debug Module (S12XBDMV2)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
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15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
15.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
15.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
15.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
15.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
15.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
15.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
15.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
15.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
15.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
15.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
15.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
15.4.10Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
15.4.11Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
Chapter 16
S12X Debug (S12XDBGV3) Module
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
16.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
16.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
16.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
16.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
16.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
16.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
16.4.1 S12XDBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
16.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
16.4.3 Trigger Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
16.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
16.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
16.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
16.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
Chapter 17
Memory Protection Unit (S12XMPUV2)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
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17.2
17.3
17.4
17.5
17.1.1 Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
17.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
17.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
17.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
17.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
17.4.1 Protection Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
17.4.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
17.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
Chapter 18
External Bus Interface (S12XEBIV4)
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
18.1.1 Glossary or Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
18.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
18.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
18.4.1 Operating Modes and External Bus Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
18.4.2 Internal Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
18.4.3 Accesses to Port Replacement Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
18.4.4 Stretched External Bus Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
18.4.5 Data Select and Data Direction Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
18.4.6 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
18.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
18.5.1 Normal Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
18.5.2 Emulation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
Chapter 19
Port Integration Module (S12XFPIMV2)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
19.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
19.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
19.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
19.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
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19.3.3 Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
19.3.4 Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849
19.3.5 Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
19.3.6 Port B Data Direction Register (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
19.3.7 Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
19.3.8 Port D Data Register (PORTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
19.3.9 Port C Data Direction Register (DDRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
19.3.10Port D Data Direction Register (DDRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
19.3.11Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
19.3.12Port E Data Direction Register (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
19.3.13S12X_EBI ports, BKGD pin Pull-up Control Register (PUCR) . . . . . . . . . . . . . . . . . . 855
19.3.14S12X_EBI ports Reduced Drive Register (RDRIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
19.3.15ECLK Control Register (ECLKCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858
19.3.16PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
19.3.17IRQ Control Register (IRQCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
19.3.18PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
19.3.19Port K Data Register (PORTK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
19.3.20Port K Data Direction Register (DDRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
19.3.21Port T Data Register (PTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
19.3.22Port T Input Register (PTIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
19.3.23Port T Data Direction Register (DDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
19.3.24Port T Reduced Drive Register (RDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
19.3.25Port T Pull Device Enable Register (PERT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
19.3.26Port T Polarity Select Register (PPST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
19.3.27PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
19.3.28PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
19.3.29Port S Data Register (PTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
19.3.30Port S Input Register (PTIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
19.3.31Port S Data Direction Register (DDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
19.3.32Port S Reduced Drive Register (RDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
19.3.33Port S Pull Device Enable Register (PERS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
19.3.34Port S Polarity Select Register (PPSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
19.3.35Port S Wired-Or Mode Register (WOMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
19.3.36PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
19.3.37Port M Data Register (PTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
19.3.38Port M Input Register (PTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
19.3.39Port M Data Direction Register (DDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
19.3.40Port M Reduced Drive Register (RDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
19.3.41Port M Pull Device Enable Register (PERM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
19.3.42Port M Polarity Select Register (PPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
19.3.43Port M Wired-Or Mode Register (WOMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
19.3.44PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
19.3.45Port P Data Register (PTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
19.3.46Port P Input Register (PTIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
19.3.47Port P Data Direction Register (DDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
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19.3.48Port P Reduced Drive Register (RDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
19.3.49Port P Pull Device Enable Register (PERP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
19.3.50Port P Polarity Select Register (PPSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
19.3.51PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
19.3.52PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
19.3.53Port H Data Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
19.3.54Port H Input Register (PTIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
19.3.55Port H Data Direction Register (DDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
19.3.56Port H Reduced Drive Register (RDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
19.3.57Port H Pull Device Enable Register (PERH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
19.3.58Port H Polarity Select Register (PPSH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
19.3.59PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
19.3.60PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
19.3.61Port J Data Register (PTJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
19.3.62Port J Input Register (PTIJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
19.3.63Port J Data Direction Register (DDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
19.3.64Port J Reduced Drive Register (RDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
19.3.65Port J Pull Device Enable Register (PERJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
19.3.66Port J Polarity Select Register (PPSJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
19.3.67PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
19.3.68PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
19.3.69Port AD Data Register 0 (PT0AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
19.3.70Port AD Data Register 1 (PT1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
19.3.71Port AD Data Direction Register 0 (DDR0AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
19.3.72Port AD Data Direction Register 1 (DDR1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
19.3.73Port AD Reduced Drive Register 0 (RDR0AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
19.3.74Port AD Reduced Drive Register 1 (RDR1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
19.3.75Port AD Pull Up Enable Register 0 (PER0AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
19.3.76Port AD Pull Up Enable Register 1 (PER1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
19.3.77PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
19.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
19.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
19.4.3 Pins and Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
19.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899
19.5.1 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899
Chapter 20
Pulse Width Modulator with Fault Protection (PMF15B6C) Module
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
20.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
20.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
20.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
20.2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
20.2.1 PWM0–PWM5 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
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20.4
20.5
20.6
20.7
20.8
20.2.2 FAULT0–FAULT3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
20.2.3 IS0–IS2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
20.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
20.4.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
20.4.2 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
20.4.3 PWM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
20.4.4 Independent or Complementary Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 934
20.4.5 Deadtime Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
20.4.6 Software Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
20.4.7 PWM Generator Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947
20.4.8 Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
Chapter 21
Freescale’s Scalable Controller Area Network (S12MSCANV2)
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
21.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
21.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
21.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
21.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
21.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
21.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
21.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
21.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
21.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
21.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
21.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
21.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
21.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
21.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
21.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
21.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
21.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
21.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
21.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
21.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
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Chapter 22
Enhanced Programmable Interrupt Timer (S12XEPIT24B8CV1)
22.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
22.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
22.2.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
22.2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
22.2.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
22.2.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
22.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
22.4 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
22.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
22.5.1 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
22.5.2 Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
22.5.3 Hardware Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
22.5.4 External Input Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
22.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
22.6.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
22.6.2 Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
22.6.3 Flag Clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
22.7 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
Chapter 23
Serial Communication Interface (S12SCIV5)
23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
23.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
23.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
23.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
23.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
23.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
23.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
23.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
23.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
23.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
23.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
23.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
23.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
23.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
23.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
23.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
23.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
23.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
23.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
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23.5.1
23.5.2
23.5.3
23.5.4
23.5.5
Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066
Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
Chapter 24
Analog-to-Digital Converter (ADC12B16C)
Block Description
24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
24.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
24.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
24.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
24.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
24.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
24.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
24.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
24.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
24.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
24.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
24.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
24.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093
24.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094
Chapter 25
Serial Peripheral Interface (S12SPIV5)
25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
25.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
25.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
25.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096
25.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096
25.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
25.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
25.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
25.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098
25.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098
25.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098
25.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098
25.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
25.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110
25.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111
25.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
25.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113
25.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
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25.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
25.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
25.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
Chapter 26
Enhanced Capture Timer (ECT16B8CV3)
26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
26.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
26.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
26.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
26.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
26.2.1 IOC7 — Input Capture and Output Compare Channel 7 . . . . . . . . . . . . . . . . . . . . . . . 1127
26.2.2 IOC6 — Input Capture and Output Compare Channel 6 . . . . . . . . . . . . . . . . . . . . . . . 1127
26.2.3 IOC5 — Input Capture and Output Compare Channel 5 . . . . . . . . . . . . . . . . . . . . . . . 1128
26.2.4 IOC4 — Input Capture and Output Compare Channel 4 . . . . . . . . . . . . . . . . . . . . . . . 1128
26.2.5 IOC3 — Input Capture and Output Compare Channel 3 . . . . . . . . . . . . . . . . . . . . . . . 1128
26.2.6 IOC2 — Input Capture and Output Compare Channel 2 . . . . . . . . . . . . . . . . . . . . . . . 1128
26.2.7 IOC1 — Input Capture and Output Compare Channel 1 . . . . . . . . . . . . . . . . . . . . . . . 1128
26.2.8 IOC0 — Input Capture and Output Compare Channel 0 . . . . . . . . . . . . . . . . . . . . . . . 1128
26.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
26.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
26.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
26.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
26.4.1 Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
26.4.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
26.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176
Appendix A
Electrical Characteristics
A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180
A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181
A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
A.2.1 ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
A.2.2 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
A.2.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
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A.3 NVM, Flash and Emulated EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
A.3.1 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
A.3.2 NVM Reliability Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207
A.4 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210
A.5 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210
A.5.1 Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210
A.5.2 Capacitive Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210
A.5.3 Chip Power-up and Voltage Drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211
A.6 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213
A.6.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213
A.6.2 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215
A.6.3 Phase Locked Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216
A.7 External Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
A.7.1 MSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
A.7.2 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
A.7.3 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
Appendix B
Package Physical Dimension Information.
B.1 144-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235
B.2 112-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236
B.3 64-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237
Appendix C
PCB Layout Guidelines
Appendix D
Derivative Differences
D.1 Memory Sizes and Package Options S12XF - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
D.2 Pinout explanations: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243
Appendix E
Detailed Register Address Map
Appendix F
Ordering Information
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Chapter 1
MC9S12XF-Family Reference Manual
1.1
Introduction
Targeted at actuators, sensors and other distributed nodes in the FlexRay network for Chassis and Body
Electronics, the MC9S12XF-Family delivers 32-bit performance with all the advantages and efficiencies
of a 16-bit MCU. The design goal was to retain the low cost, power consumption, EMC and code-size
efficiency advantages currently enjoyed by users of Freescale Semiconductor's other 16-bit MC9S12 MCU
families.
Based around an enhanced S12X core, the MC9S12XF-Family runs 16-bit wide accesses without wait
states for all peripherals and memories. The MC9S12XF-Family also features a new flexible interrupt
handler, which allows multilevel nested interrupts.
The MC9S12XF-Family features the performance boosting enhanced XGATE co-processor. The XGATE
is programmable in “C” language and runs at twice the bus frequency of the S12. It’s instruction set is
optimized for data movement, logic and bit manipulation instructions. Any peripheral module can be
serviced by the XGATE.
The MC9S12XF-Family features a Memory Protection Unit (MPU).
The MC9S12XF-Family features a FlexRay module for high speed serial communication supporting
various bit rates up to 10 Mbit/s. The FlexRay internal clock can be generated from crystals ranging from
4MHz to 40MHz1. The 64-pin LQFP allows interfacing to a single FlexRay channel. The 64-pin LQFP
(10mm x 10mm) is intended for those applications challenged by the size constraint of some satellite
FlexRay modules. The 112-pin LQFP offers an increase in the number of I/Os as well as 16 A/D channels.
In addition to that the 144-pin LQFP provides a full 16-bit wide non-multiplexed external bus interface
with the pins usable as general purpose I/O in single-chip modes.
The MC9S12XF-Family features the MSCAN module with a FIFO receiver buffer arrangement, and input
filters optimized for Gateway applications handling numerous message identifiers.
The MC9S12XF-Family provides Flash memory sizes from 128K to 512K plus Data Flash and enhanced
EEPROM functionality (EE-Emulation) with built in Error Correcting Code (ECC). The memory uses
Freescale Semiconductor's industry-leading, full automotive qualified SG-Flash.
The inclusion of a frequency modulated PLL circuit allows power consumption and performance to be
adjusted to suit operational requirements and allows optimization of the radiated emissions (EMC).
The ATD now offers 12 Bit resolution at a faster conversion rate down to 3µs per channel.
The MC9S12XF512 is available in 144-Pin LQFP, 112-Pin LQFP and 64-Pin LQFP package.
1. 8MHz
- 16MHz recommended for low jitter
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NOTE
The 144-Pin LQFP version will not be qualified for production and is
intended to be used for emulation (development tools) only.
See Table 1-9 for information about port and peripheral availability by package option.
1.1.1
Features
Features of the MC9S12XF-Family are listed here. Please see Table 1-1 for memory options and Table 12 for the peripheral features that are available on the different family members.
The system includes these distinctive features:
• 16-Bit CPU12X
— Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions
(MEM, WAV, WAVR, REV, REVW) which have been removed.
— Enhanced indexed addressing
— Additional (superset) instructions to improve 32-bit calculations and semaphore handling
— Access large data segments independent of PPAGE
• Enhanced Interrupt Module
— Eight levels of nested interrupts
— Flexible assignment of interrupt sources to each interrupt level
— One non-maskable high priority interrupt (XIRQ)
— Wake-up Interrupt Inputs
• Memory Protection Unit (MPU)
— 4 address regions definable per active program task
— Address range granularity as low as 256-bytes
— Protection Attributes
– No write
– No execute
— Non-maskable interrupt on access violation
• XGATE
— Programmable, high performance I/O coprocessor module – up to 100 MIPS RISC
performance
— Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states
— Performs logical, shifts, arithmetic, and bit operations on data
— Can interrupt the HCS12X CPU signalling transfer completion
— Triggers from any hardware module as well as from the CPU possible
— Two interrupt levels to service high priority tasks
— Enables Full CAN capability when used in conjunction with MSCAN module
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•
— Full LIN master or slave capability when used in conjunction with the integrated LIN SCI
module
System Integrity Support
— Power-on reset (POR)
— Illegal address detection with reset
— Low-voltage detection with interrupt or reset
— Computer Operating Properly (COP) watchdog
– Configurable as window COP for enhanced failure detection
– Can be initialized out of reset using option bits located in Flash
— Clock monitor supervising the correct function of the oscillator
Memory Options
— 128K, 256k, 384K and 512K byte Flash
— 2K, 4K byte Emulated EEPROM
— 16K, 20K, 24K and 32K Byte RAM
— Program Flash General Features
– 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit fault
correction and double fault detection
– Erase sector size 1024 bytes
– Automated program and erase algorithm
– Security option to prevent unauthorized access
– Sense-amp margin level setting for reads
— Data Flash General Features
– Up to 32K bytes of D-Flash memory with 256-byte sectors for user access.
– Dedicated commands to access D-Flash memory over EEE operation
– Single bit fault correction and double fault detection within a word during read operations
– Automated program and erase algorithm with verify and generation of ECC parity bits
– Fast sector erase and word program operation
– Ability to program up to four words in a burst sequence
— Emulated EEPROM General Features
– Automatic EEE file handling using internal Memory Controller
– Automatic transfer of valid EEE data from D-Flash memory to buffer RAM on reset
– Ability to monitor the number of outstanding EEE related buffer RAM words left to be
programmed into D-Flash memory
– Ability to disable EEE operation and allow priority access to the D-Flash memory
– Ability to cancel all pending EEE operations to allow priority access to the D-Flash memory
Oscillator (OSC_LCP)
— Loop Control Pierce oscillator utilizing a 4MHz to 16MHz crystal
— Good noise immunity
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•
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•
•
— Full-swing Pierce option utilizing a 2MHz to 40MHz crystal
— Transconductance sized for optimum start-up margin for typical crystals
Clock and Reset Generator (CRG)
— Phase-locked-loop (IPLL) clock frequency multiplier
— Internally filtered. No external components required
— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)
— Fast wake up from STOP in self clock mode for power saving and immediate program
execution
Non-Multiplexed External Bus (144 Pin package only)
— 16 data bits wide
— Support for external WAIT input or internal wait cycles to adapt MCU speed to peripheral
speed requirements
— Up to four chip select outputs to select 16K, 768K, 2M and 4MByte address spaces
— Supports glue less interface to popular asynchronous RAMs and Flash devices
— External address space 4MByte for Data and Program space
FlexRay Module (FR)
— FlexRay protocol implementation according to FlexRay V2.1 Protocol Implementation
document
— Optimized programmers model to fit small address footprint
— Supports Data Rates of 2.5, 5, 8 and 10MBit/s
— The FlexRay clock can be derived from crystals ranging from 4MHz to 40MHz for cost and
EMC optimization
— FlexRay clocking independent from the CPU and XGATE bus frequency. Clock is generated
by a “dedicated” IPLL.
— Up to two channels for fault tolerant systems (see Table 1-2 Peripheral Feature Summary of
MC9S12XF-Family Members)
— Single channel operation on channel A, configurable to run FlexRay channel A or channel B
protocol
— 32 configurable message buffers
— Message buffers can be configured as Receive, single buffered Transmit or double buffered
Transmit message buffer
— Message buffer header, status and payload data stored in System RAM
— 2 independent message buffer segments
— Size of message buffer payload data section configurable from 0 up to 254 bytes
— 2 independent receive FIFOs, 1 per channel
— Six separate interrupt channels for Receive, receive FIFO channel A, receive FIFO channel B,
Transmit, Error and Wake-up
— Internal signals can be routed to I/O pins to ease debugging
Analog-to-Digital Converter (ATD)
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— 8/10/12 Bit resolution
— Multiplexer for 16 analog input channels
— 3µs, 12-bit single conversion time
— Left or right justified result data
— External and internal conversion trigger capability
— Internal oscillator for conversion in Stop Modes
— Wake-up from low power modes on analog comparison > or <= match
Enhanced Capture Timer (ECT)
— 8 x 16-bit channels for input capture or output compare
— 16-bit free-running counter with 8-bit precision prescaler
— 16-bit modulus down counter with 8-bit precision prescaler
— 4 x 8-bit or 2 x 16-bit pulse accumulators
— Four channels have enhanced input capture capabilities:
– Delay counter for noise immunity
– 16-bit capture buffer
– 8-bit pulse accumulator buffer
Enhanced Periodic Interrupt Timer (EPIT)
— Up to 8 timers with independent time-out periods
— Time-out periods selectable between 1 and 224 bus clock cycles
— Time-out interrupt and peripheral triggers
Real Time Interrupt (RTI)
— Real Time Interrupt for task scheduling purposes or cyclic wake-up
— Can be active in Pseudo Stop mode for low power precision timing tasks
Asynchronous Periodic Interrupt (API)
— Available in all modes including Full Stop mode
— Trimmable to +-5% accuracy
— Time-out periods range from 0.2ms to ~13s with a 0.2ms resolution
Pulse Width Modulator with Fault detection (PMF)
— Six channel Pulse width Modulator with Fault protection (PMF) optimized for electrical motor
control
— Three independent 15-bit counters with synchronous mode
— Complementary channel operation
— Edge and center aligned PWM signals
— Programmable dead time insertion
— Integral reload rates from 1 to 16
— Up to four fault protection shut down input pins depending on the package option
— Up to three current sense input pins depending on the package option (see Table 1-9 Port and
Peripheral Availability by Package Option)
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•
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Multi-scalable Controller Area Networks (MSCAN)
— CAN 2.0 A, B software compatible
– Standard and extended data frames
– 0 - 8 bytes data length
– Programmable bit rate up to 1 Mbps
— Five receive buffers with FIFO storage scheme
— Three transmit buffers with internal prioritization
— Flexible identifier acceptance filter programmable as:
– 2 x 32-bit
– 4 x 16-bit
– 8 x 8-bit
— Wake-up with integrated low pass filter option
— Loop back for self test
— Listen-only mode to monitor CAN bus
— Bus-off recovery by software intervention or automatically
— 16-bit time stamp of transmitted/received messages
Serial Peripheral Interface (SPI)
— Up to two SPI modules (see Table 1-2 Peripheral Feature Summary of MC9S12XF-Family
Members)
— Configurable 8 or 16-bit data size
— Full-duplex or single-wire bidirectional
— Double-buffered transmit and receive
— Master or Slave mode
— MSB-first or LSB-first shifting
— Serial clock phase and polarity options
Serial Communication Interfaces (SCI)
— Up to two SCI modules (see Table 1-2 Peripheral Feature Summary of MC9S12XF-Family
Members)
— Full-duplex or single wire operation
— Standard mark/space non-return-to-zero (NRZ) format
— Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
— 13-bit baud rate selection
— Programmable character length
— Programmable polarity for transmitter and receiver
— Receive wakeup on active edge
— Break detect and transmit collision detect supporting LIN
Background Debug Module (BDM)
— Background debug controller (BDM) with single-wire interface
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– Non-intrusive memory access commands
– Supports in-circuit programming of on-chip non-volatile memory
– Supports security
Debugger (DBG)
— Four comparators A, B, C and D
– Each can monitor CPU or XGATE busses
– A and C compares 23-bit address bus and 16-bit data bus with mask register
– B and D compares 23-bit address bus only
– Three modes: simple address/data match, inside address range or outside address range
— 64 x 64-bit circular trace buffer to capture change-of-flow addresses or address and data of
every access
— Tag-type or force-type hardware breakpoint requests
Input/Output
— up to 110 general-purpose input/output (I/O) pins depending on the package option and 2 inputonly pins
— Hysteresis and configurable pull up/pull down device on all input pins
— Configurable drive strength on all output pins
Package Options
— 144-pin low-profile quad flat-pack (LQFP)1
— 112-pin low-profile quad flat-pack (LQFP)
— 64-pin low-profile quad flat-pack (LQFP)
On-Chip Voltage Regulator
— Three parallel, linear voltage regulators with bandgap reference providing VDDPLL, 1.8V
logic and 2.8V Flash supply
— Low-voltage detect (LVD) with low-voltage interrupt (LVI)
— Power-on reset (POR) circuit
— 3.3V and 5V range operation
— Low-voltage reset (LVR)
Operating Conditions
— Ambient temperature range –40 C to 85 C
— Temperature Options:
– –40 C to 105 C
– –40 C to 125 C
50MHz maximum CPU bus frequency, 100MHz maximum XGATE bus frequency
1. The 144-Pin LQFP version will not be qualified for production and is intended to be used for emulation (development tools) only.
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Table 1-1. Package and Memory Options of MC9S12XF-Family Members
Device
Package
Flash
RAM
EEEPROM
512K
32K
4K
384K
24K
4K
256K
20K
2K
128K
16K
2K
144 LQFP
9S12XF512
112 LQFP
64 LQFP
144 LQFP
9S12XF384
112 LQFP
64 QFP
144 LQFP
9S12XF256
112 LQFP
64 QFP
144 LQFP
9S12XF128
112 LQFP
64 QFP
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1.1.2
Block Diagram
CPU12X
XTAL
Amplitude Controlled
Low Power Pierce or
Full drive Pierce
Oscillator
PLL with Frequency
Modulation option
PTK
EWAIT
ADDR[22:16]
ADDR[15:8]
PC[7:0]
PTC
ADDR[7:0]
DATA[15:8]
PD[7:0]
DATA[7:0]
EPIT
8ch 16-bit Timer
Enhanced Multilevel
Interrupt Module
MPU
Memory Protection
4 Regions
XIRQ
IRQ
RW/WE
LSTRB/LDS
ECLK
MODA/TAGLO/RE
MODB/TAGHI
XCLKS/ECLKX2
PTD
PB[7:0]
PTA
PA[7:0]
PTB
PK[7:0]
PTE
TEST
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
Reset Generation
and Test Entry
Non-Multiplexed External Bus Interface
RESET
Clock Monitor
COP Watchdog
Periodic Interrupt
Async. Periodic Int.
X
EXTAL
XGATE
BKGD
Debug Module
Single-wire Background 4 address breakpoints
Debug Module
2 data breakpoints
512 Byte Trace Buffer
MOSI
SCK
Synchronous Serial IF
SS
RXCAN
CAN0
TXCAN
msCAN 2.0B
FAULT2
FAULT3
MISO
SPI1
MOSI
Synchronous SCK
Serial IF
SS
PMF0
PMF1
15-bit 6-channel
PMF2
Pulse Width Modulation PMF3
with Fault Protection
PMF4
PMF5
FAULT0
FAULT1
IS0
IS1
IS2
STB0
STB1
STB2
STB3
FlexRay
Channel A
RXD_A
TXD_A
TXE_A
Channel B
RXD_B
TXD_B
TXE_B
PTAD0
PTS
Voltage Regulator
PT[7:0]
PTM
IOC[7:0]
16-bit 8 channel
Enhanced Capture Timer
RXD
SCI0
TXD
Asynchronous Serial IF
RXD
SCI1
TXD
Asynchronous Serial IF
SPI0
MISO
PTP
2K … 4K bytes Emulated EEPROM
VDDR
VDD1
VDDF
VDDPLL
PAD[15:0]
PTJ
8/10/12-bit 16-channel AN[15:0]
Analog-Digital Converter
ECT
16K … 32K bytes RAM
PTH
ATD
128K … 512K bytes Flash
PTT
Figure 1-1 shows a block diagram of the MC9S12XF-Family devices
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
Figure 1-1. MC9S12XF-Family Block Diagram1
1. See Section 1.2, “Signal Description“ to get more information with regard to I/O muxing variants.
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Chapter 1 MC9S12XF-Family Reference Manual
Table 1-2. Peripheral Feature Summary of MC9S12XF-Family Members
Package
FlexRay
ECT
PIT
CAN
SCI
SPI
A/D
PMF
144 LQFP
2-ch
8ch
8ch
1
2
2
16-ch
6-ch
4 Fault Inputs
3 Current Sense
112 LQFP
2-ch
8ch
8ch
1
2
2
16-ch
6-ch
4 Fault Inputs
3 Current Sense
64 LQFP
1-ch
8ch
8ch
1
1
1
8-ch
6-ch
0 Fault Inputs
0 Current Sense
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Chapter 1 MC9S12XF-Family Reference Manual
1.1.3
Device Memory Map
Table 1-3 shows the device register memory map.
Table 1-3. Device Memory Map
Address
Module
Size
(Bytes)
0x0000 - 0x0009
PIM (Port Integration Module)
10
0x000A - 0x000B
MMC (Memory Map Control)
2
0x000C - 0x000D
PIM (Port Integration Module)
2
0x000E - 0x000F
EBI (External Bus Interface)
2
0x0010 - 0x0017
MMC (Memory Map Control)
10
0x0018 - 0x0019
Reserved
2
0x001A - 0x001B
Device ID register
2
0x001C - 0x001F
PIM (Port Integration Module)
4
0x0020 - 0x002F
DBG (Debug Module)
16
0x0030 - 0x0031
Reserved
2
0x0032 - 0x0033
PIM (Port Integration Module)
2
0x0034 - 0x003F
CRG (Clock and Reset Generator)
12
0x0040 - 0x007F
ECT (Enhanced Capture Timer 16-bit 8 channel)s
64
0x0080 - 0x00AF
ATD (Analog to Digital Converter 10-bit 16 channel)
48
0x00B0 - 0x00C7
Reserved
24
0x00C8 - 0x00CF
SCI0 (Serial Communications Interface)
8
0x00D0 - 0x00D7
SCI1 (Serial Communications Interface)
8
0x00D8 - 0x00DF
Serial Peripheral Interface (SPI0)
8
0x00E0 - 0x00EF
Reserved
16
0x00F0 - 0x00F7
Serial Peripheral Interface (SPI1)
8
0x00F8 - 0x00FF
Reserved
8
0x0100–0x0113
FTM control register
20
0x0114–0x011F
MPU (memory protection unit)
12
0x0120 - 0x012F
INT (Interrupt Module)
16
0x0130 - 0x013F
Reserved
16
0x0140 - 0x017F
CAN (Freescale Scalable Can)
64
0x0180 - 0x01FF
Reserved
128
0x0200 - 0x023F
PMF (Pulse With Modulator with Fault Protection)
64
0x0240 - 0x027F
PIM (Port Integration Module)
64
0x0280 - 0x02EF
Reserved
112
0x02F0 - 0x02F7
Voltage Regulator
8
0x02F8 - 0x02FF
Reserved
8
0x0300 - 0x0307
FlexRay IPLL
8
0x0308 - 0x033F
Reserved
56
0x0340 - 0x036F
Enhanced Periodic Interrupt Timer
48
0x0370 - 0x037F
Reserved
16
0x0380 - 0x03BF
XGATE
64
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Chapter 1 MC9S12XF-Family Reference Manual
Table 1-3. Device Memory Map
Address
Module
Size
(Bytes)
0x03C0 - 0x03FF
Reserved
64
0x0400 - 0x05FF
FlexRay
512
0x0600 - 0x07FF
Reserved
512
NOTE
Reserved register space shown in Table 1-3 is not allocated to any module.
This register space is reserved for future use. Writing to these locations has
no effect. Read access to these locations returns zero.
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Chapter 1 MC9S12XF-Family Reference Manual
1.1.4
MC9S12XF512 - Address Mapping
Figure 1-2 shows S12XE CPU & BDM local address translation to the global memory map. It indicates
also the location of the internal resources in the memory map.
EEEPROM size is presented like a fixed 256 KByte in the memory map.
Table 1-4. 9S12XF512 Dependent Memory Parameters
Device
FLASH_LOW
PPAGE(1)
RAM_LOW
RPAGE(2)
DF_HIGH
9S12XF512
0x78_0000
32
0x0F_8000
8
0x10_7FFF
1. Number of 16K pages addressable via PPAGE register
2. Number of 4K pages addressing the RAM. RAM can also be mapped to 0x4000 - 0x7FFF
EPAGE
32
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35
Chapter 1 MC9S12XF-Family Reference Manual
CPU and BDM
Local Memory Map
Global Memory Map
0x00_0000
0x00_07FF
2K REGISTERS
CS3
Unimplemented
RAM
0x0000
0x0800
0x0C00
0x1000
RAMSIZE
RAM_LOW
RAM
2K REGISTERS
1K EEPROM window
EPAGE
0x0F_FFFF
1K EEPROM (FF)
4K RAM window
256 K EEEPROM
RESOURCES
RPAGE
0x2000
8K RAM
0x13_F800
0x13_FBFF
0x13_FC00
0x13_FFFF
0x4000
FE
FF
CS2
Unpaged
16K FLASH
0x1F_FFFF
External
Space
CS1
0x8000
PPAGE
0x3F_FFFF
0xC000
CS0
16K FLASH window
Unimplemented
FLASH
Unpaged
16K FLASH
FLASH_LOW
Reset Vectors
FLASH
NOTE: On smaller derivatives the flash
memory map is split into 2 ranges separated
by an unimplemeted range, as depicted by
the dashed lines. For more information
refer to tables below and MMC section.
FLASHSIZE
0xFFFF
0x7F_FFFF
Figure 1-2. MC9S12XF512 Global Memory Map
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Chapter 1 MC9S12XF-Family Reference Manual
Unimplemented RAM pages are mapped externally in expanded modes. Accessing unimplemented RAM
pages in single chip modes causes an illegal address reset if the MPU is not configured to flag an MPU
protection error in that range.
Accessing unimplemented FLASH pages in single chip modes causes an illegal address reset if the MPU
is not configured to flag an MPU protection error in that range.
The range between 0x10_0000 and 0x13_FFFF is mapped to EEEPROM resources. The actual
EEEPROM and dataflash block sizes are listed in Table 1-6 . Within EEEPROM resource range an address
range exists which is neither used by EEEPROM resources nor remapped to external resources via chip
selects (see the FTM/MMC descriptions for details).
The fixed 8K RAM default location in the global map is 0x0F_E000 - 0x0F_FFFF. This is subject to
remapping when configuring the local address map for a larger RAM access range.
Memory map Figure 1-3 shows XGATE local address translation to the global memory map. It indicates
also the location of used internal resources in the memory map.
Table 1-5. XGATE Resources (9S12XF512)
Internal Resource
Size /KByte
$Address
XGATE RAM
32K
XGRAM_LOW = 0x0F_8000
FLASH
30K(1)
XGFLASH_HIGH = 0x78_8000
1. This value is calculated by the following formula: (64K - 2K - XGRAMSIZE)
Table 1-6. Derivative Dependent Memory Parameters
Device
FLASH_LOW
PPAGE
(1)
RAM_LOW
RPAGE
(2)
EE_LOW
DF_HIGH
EPAGE
9S12XF512
0x78_0000
32
0x0F_8000
8
0x13_F000
0x10_7FFF
4(3) + 32(4)
9S12XF384
0x78_0000(5)
24
0x0F_A000
6
0x13_F000
0x10_7FFF
4 + 32
9S12XF256
0x78_0000(6)
16
0x0F_B000
5
0x13_F800
0x10_7FFF
2 + 32
9S12XF128
0x78_0000(7)
8
0x0F_C000
4
0x13_F800
0x10_7FFF
2 + 32
1. Number of 16K pages addressable via PPAGE register
2. Number of 4K pages addressing the RAM. RAM can also be mapped to 0x4000 - 0x7FFF
3. Number of 1K pages addressing the Cache RAM via the EPAGE register counting downwards from 0xFF
4. Number of 1K pages addressing the Data flash via the EPAGE register starting upwards from 0x00
5. The 384K memory map is split into a 128K block from 0x78_0000 to 0x79_FFFF and a 256K block from 0x7C_0000 to
0x7F_FFFF
6. The 256K memory map is split into a 128K block from 0x78_0000 to 0x79_FFFF and a 128K block from 0x7E_0000 to
0x7F_FFFF
7. The 128K memory map is split into a 64K block from 0x78_0000 to 0x78_FFFF and a 64K block from 0x7F_0000 to
0x7F_FFFF
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Chapter 1 MC9S12XF-Family Reference Manual
Table 1-7. Derivative Dependent Flash Block Mapping
Device
0x78_0000
0x7A_0000
0x7C_0000
0x7E_0000
9S12XF512
B1S
B1N
B0
9S12XF384
B1S
—
B0
9S12XF256
B1S
—
—
B0(128K)
9S12XF128
B1S (64K)
—
—
B0 (64K)
Block B1 is divided into two 128K blocks. The XGATE is always mapped to block B1S.
On the 9S12XF128 the flash is divided into two 64K blocks B0 and B1S, the B1S range extending from
0x78_0000 to 0x78_FFFF, the B0 range extending from 0x7F_0000 to 0x7F_FFFF.
The block B0 is a reduced size 128K block on the 256K derivative. On the larger derivatives B0 is a 256K
block. The block B0 is a reduced size 64K block on the 128K derivative.
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Chapter 1 MC9S12XF-Family Reference Manual
XGATE
Local Memory Map
Global Memory Map
0x00_0000
Registers
0x00_07FF
XGRAM_LOW
0x0800
RAM
0x0F_FFFF
RAMSIZE
Registers
XGRAMSIZE
0x0000
FLASH
RAM
0x78_0800
0xFFFF
FLASHSIZE
FLASH
XGFLASH_HIGH
0x7F_FFFF
Figure 1-3. XGATE Global Address Mapping
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Chapter 1 MC9S12XF-Family Reference Manual
1.1.4.1
FlexRay Address Mapping
Memory map 1 Figure 1-4 shows FlexRay address mapping to the global memory map. It indicates also
the location of the internal resources in the memory map.
The FlexRay address mapping can be configured via MPU descriptors. It is possible to set-up up to 4
descriptors giving the FlexRay module access to 4 different regions of RAM with different permissions.
This is not reflected in Figure 1-4 for complexity reasons. For more details refer to the MPU section.
NOTE
The FlexRay module can only access system ram space.
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Chapter 1 MC9S12XF-Family Reference Manual
FLEXRAY
Local Memory Map
Global Memory Map
RAMSIZE
RAM
FLXRAMSIZE
0x00_0000
FLXRAMSIZE
0x0F_FFFF
RAM
Unimplemented
area
FLXRAMSIZE is the memory area defined by the LOW_ADDR
and HIGH_ADDR settings in the corresponding MPU
descriptor register (Figure 17-8. MPU Descriptor Register 0
(MPUDESC0) and following registers).
0x7F_FFFF
Figure 1-4. FLEXRAY Global Address Mapping
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Chapter 1 MC9S12XF-Family Reference Manual
1.1.5
Detailed Register Map
For the detailed register map refer to Appendix E Detailed Register Address Map.
1.1.6
Part ID Assignment
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B).
The read-only value is a unique part ID for each revision of the chip. Table 1-8 shows the assigned part ID
number and Mask Set number.
The Version ID is a word located in a flash information row at 0x40_00E8. The version ID number
indicates a specific version of internal NVM variables used to patch NVM errata. The default is no patch
(0xFFFF).
Table 1-8. Part ID Assignment for MC9S12XF512
Device
Mask Set Number
MC9S12XF512
0M64J
MC9S12XF512
1M64J
MC9S12XF512
2M64J
1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor — non full — mask set revision
2. See customer errata for more information w.r.t. patch code.
Part ID(1)
Version ID
$D480
$D481
$D481
0xFFFF
0xFFFF
0x0006(2)
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Chapter 1 MC9S12XF-Family Reference Manual
1.2
Signal Description
This section describes signals that connect off chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals. It is built from the signal description sections of the block
guides of the individual IP blocks contained in the system.
1.2.1
System Pinout
Figure 1-5 is a pinout diagram of the system. The diagram must include the names of all signals that are
connected by system pins.
NOTE
Pin
• 56 of the 144-Pin LQFP
• 46 of the 112-Pin LQFP
• 26 of the 64-Pin LQFP
must not be connected to VDD, VSS or any other component. Freescale test
structures are bonded to this pin.
Keep this pin (according to package type) open.
NOTE
The VDD pins provide 1.8V derived from the internal voltage regulator.
Usage of an external voltage regulator is not allowed.
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43
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
NC =No internal Connection
MC9S12XF512
144LQFP
NOTE
The 144-Pin LQFP version
will not be qualified for
production and is intended
to be used for emulation
(development tools) only.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VRH
VDDA
PAD15/AN15
PAD07/AN7
PAD14/AN14
PAD06/AN6
PAD13/AN13
PAD05/AN5
PAD12/AN12
PAD04/AN4
PAD11/AN11
PAD03/AN3
PAD10/AN10
PAD02/AN2
PAD09/AN9
PAD01/AN1
PAD08/AN08
PAD00/AN0
VSS2
VDD
PA7/ADDR15
PA6/ADDR14
PA5/ADDR13
PA4/ADDR12
PK7/EWAIT/ROMCTL
PK6/ADDR22/ACC2
PK5/ADDR21/ACC1
PK4/ADDR20/ACC0
PK3/ADDR19/IQSTAT3
PK2/ADDR18/IQSTAT2
PK1/ADDR17/IQSTAT1
PK0/ADDR16/IQSTAT0
PH3
PH2/TXE_A
PH1/TXD_A
PH0/RXD_A
ADDR2/PB2
ADDR3/PB3
MODC/BKGD
ECLKX2/XCLKS/PE7
TAGHI/MODB/PE6
RE/TAGLO/MODA/PE5
ECLK/PE4
EROMCTL/LDS/LSTRB/PE3
WE/RW/PE2
RXD_B/PH4
TXD_B/PH5
TXE_B/PH6
PH7
VDDX2
VSSX2
VSS3
VDDR
RESET
VDDPLL
(Freescale Test)
VSSPLL
EXTAL
XTAL
TEST
ADDR4/PB4
ADDR5/PB5
ADDR6/PB6
ADDR7/PB7
ADDR8/PA0
ADDR9/PA1
ADDR10/PA2
ADDR11/PA3
VDDX4
VSSX4
IRQ/PE1
XIRQ/PE0
PMF1/PP1
PMF0/PP0
DATA3/PD3
DATA2/PD2
DATA1/PD1
DATA0/PD0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
IS0/PJ0
IS1/PJ1
IS2/PJ2
VDDF
VSS1
VSSX3
VDDX3
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
DATA8/PC0
DATA9/PC1
DATA10/PC2
DATA11/PC3
DATA12/PC4
DATA13/PC5
DATA14/PC6
DATA15/PC7
STB0/PJ3
STB1/PJ4
STB2/PJ5
STB3/PJ6
PJ7
UDS/ADDR0/PB0
ADDR1/PB1
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PP2/PMF2
PP3/PMF3
PP4/PMF4
PP5/PMF5
PP6/FAULT0
PP7/FAULT1
PD4/DATA4
PD5/DATA5
PD6/DATA6
PD7/DATA7
VDDX1
VSSX1
PM0/RXCAN0
PM1/TXCAN0
NC
NC
PM2/FAULT2/CS0
PM3/FAULT3/CS1
PM4/MISO1/CS2
PM5/MOSI1
PM6/SCK1
PM7/SS1/CS3
NC
NC
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4/MISO0
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
NC
NC
VSSA
VRL
Chapter 1 MC9S12XF-Family Reference Manual
Pins shown in BOLD are not available on the 64-pin package option
Pins shown in ITALICS are not available on the 112-pin and 64-pin package options
Figure 1-5. MC9S12XF-Family Pin Assignments 144-pin LQFP Package1
1. The 144-Pin LQFP version will not be qualified for production and is intended to be used for emulation (development tools) only.
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NC =No internal Connection
MC9S12XF512
112LQFP
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
VRH
VDDA
PAD15/AN15
PAD07/AN7
PAD14/AN14
PAD06/AN6
PAD13/AN13
PAD05/AN5
PAD12/AN12
PAD04/AN4
PAD11/AN11
PAD03/AN3
PAD10/AN10
PAD02/AN2
PAD09/AN09
PAD01/AN1
PAD08/AN08
PAD00/AN0
VSS2
VDD
PA7
PA6
PA5
PA4
PH3
PH2/TXE_A
PH1/TXD_A
PH0/RXD_A
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MODC/BKGD
ECLKX2/XCLKS/PE7
PE6
PE5
ECLK/PE4
PE3
PE2
RXD_B/PH4
TXD_B/PH5
TXE_B/PH6
PH7
VDDX2
VSSX2
VSS3
VDDR
RESET
VDDPLL
(Freesscale Test)
VSSPLL
EXTAL
XTAL
TEST
PA0
PA1
PA2
PA3
IRQ/PE1
XIRQ/PE0
PMF1/PP1
PMF0/PP0
PD3
PD2
PD1
PD0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
IS0/PJ0
IS1/PJ1
IS2/PJ2
VDDF
VSS1
VSSX3
VDDX3
OC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
STB0/PJ3
STB1/PJ4
STB2/PJ5
STB3/PJ6
PJ7
UDS/ADDR0/PB0
ADDR1/PB1
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
PP2/PMF2
PP3/PMF3
PP4/PMF4
PP5/PMF5
PP6/FAULT0
PP7/FAULT1
PD4
PD5
VDDX1
VSSX1
PM0/RXCAN0
PM1/TXCAN0
PM2/FAULT2/CS0
PM3/FAULT3/CS1
PM4/MISO1/CS2
PM5/MOSI1
PM6/SCK1
PM7/SS1/CS3
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4/MISO0
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
VSSA
VRL
Chapter 1 MC9S12XF-Family Reference Manual
Pins shown in BOLD are not available on the 64-pin package option
Figure 1-6. MC9S12XF-Family Pin Assignments 112-pin LQFP Package
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
45
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PP2/PMF2
PP3/PMF3
PP4/PMF4
PP5/PMF5
VDDX1
VSSX1
PM0/RXCAN0
PM1/TXCAN0
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4/MISO0
PS1/TXD0
PS0/RXD0
VSSA
VRL
Chapter 1 MC9S12XF-Family Reference Manual
NC =No internal Connection
MC9S12XF512
64LQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VRH
VDDA
PAD07/AN7
PAD06/AN6
PAD05/AN5
PAD04/AN4
PAD03/AN3
PAD02/AN2
PAD01/AN1
PAD00/AN0
VSS2
VDD
PH3
PH2/TXE_A
PH1/TXD_A
PH0/RXD_A
MODC/BKGD
XCLKS/PE7
ECLK/PE4
VDDX2
VSSX2
VSS3
VDDR
RESET
VDDPLL
(Freescale Test)
VSSPLL
EXTAL
XTAL
TEST
IRQ/PE1
XIRQ/PE0
PMF1/PP1
PMF0/PP0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDDF
VSS1
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
STB0/PJ3
STB1/PJ4
STB2/PJ5
STB3/PJ6
Figure 1-7. MC9S12XF-Family Pin Assignments 64-pin LQFP Package
Table 1-9. Port and Peripheral Availability by Package Option
Port
144 LQFP
112 LQFP
64 LQFP
Port AD/ADC Channels
16/16
16/16
8/8
Port A pins
8
8
0
Port B pins
8
2
0
Port C pins
8
0
0
Port D pins
8
6
0
Port E pins inc. IRQ/XIRQ input only
8
8
4
Port H/FlexRay Channels
8/A+B
8/A+B
4/A
Port J/PMF Current Sense
8/3
8/3
4/0
Port K pins
8
0
0
Port M/CAN/PMF Fault Inputs/SPI
8/1/2/1
8/1/2/1
2/1/0/0
MC9S12XF - Family Reference Manual, Rev.1.19
46
Freescale Semiconductor
Chapter 1 MC9S12XF-Family Reference Manual
Table 1-9. Port and Peripheral Availability by Package Option
Port
144 LQFP
112 LQFP
64 LQFP
Port P/PMF channels/PMF Fault Inputs
8/6/2
8/6/2
6/6/0
Port S/SCI/SPI
8/2/1
8/2/1
6/1/1
Port T/Timer Channels
8/8
8/8
8/8
VDDX/VSSX
4/4
3/3
2/2
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
47
Chapter 1 MC9S12XF-Family Reference Manual
1.2.2
Signal Properties Summary
Table 1-10. Signal Properties
Pin Number
L
Q
F
P
144
Pin
Name
Funct.
1
Pin
Name
Funct.
2
Pin
Name
Funct.
3
Pin
Name
Funct.
4
Function
Power
Supply
Termination
out of Reset
I/O
(1)
L
Q
F
P
112
L
Q
F
P
64
1
1
1
PP1
PMF1
—
—
2
2
2
PP0
PMF0
—
—
VDDX
I/O
3
3
—
PD3
DATA3
—
—
VDDX
I/O
4
4
—
PD2
DATA2
—
—
VDDX
I/O
5
5
—
PD1
DATA1
—
—
VDDX
I/O
6
6
—
PD0
DATA0
—
—
VDDX
I/O
7
7
3
PT0
IOC0
—
—
VDDX
I/O
8
8
4
PT1
IOC1
—
—
VDDX
I/O
9
9
5
PT2
IOC2
—
—
VDDX
I/O
10
10
6
PT3
IOC3
—
—
VDDX
I/O
11
11
PJ0
IS0
—
—
VDDX
I/O
VDDX
I/O
VDDX
I/O
CTRL(2)
Port P I/O, PMF Channels 0/1 VDDX(4) I/O
Port D I/O, Data Bus
Port T I/O, Timer channels
Port T I/O, Current status pins
for top/bottom pulse width
correction
12
12
PJ1
IS1
—
—
13
13
PJ2
IS2
—
—
14
14
7
VDDF(5)
—
—
—
NVM Power Supply 2.8V
15
15
8
VSS1
—
—
—
Digital Ground Supply 1.8V
16
16
—
VSSX3
—
—
—
I/O Ground Supply 3-5V
17
17
—
VDDX3
—
—
—
I/O Power Supply 3-5V
18
18
9
PT4
IOC4
19
19
10
PT5
IOC5
—
—
20
20
11
PT6
IOC6
—
21
21
12
PT7
IOC7
—
—
VDDX
I/O
VDDX
I/O
—
VDDX
I/O
—
VDDX
I/O
Port T I/O, Timer channels
Reset(3)
State
PERP
PPSP
disabled
PUCR
disabled
PERT
PPST
disabled
PERJ
PPSJ
Up
PERT
PPST
disabled
MC9S12XF - Family Reference Manual, Rev.1.19
48
Freescale Semiconductor
Chapter 1 MC9S12XF-Family Reference Manual
Table 1-10. Signal Properties
Pin Number
L
Q
F
P
144
Pin
Name
Funct.
1
Pin
Name
Funct.
2
Pin
Name
Funct.
3
Pin
Name
Funct.
4
Function
Power
Supply
I/O
(1)
L
Q
F
P
112
L
Q
F
P
64
22
—
—
PC0
DATA8
—
—
VDDX
I/O
23
—
—
PC1
DATA9
—
—
VDDX
I/O
24
—
—
PC2
DATA10
—
—
VDDX
I/O
25
—
—
PC3
DATA11
—
—
VDDX
I/O
VDDX
I/O
Port C I/O, Data Bus
Termination
out of Reset
CTRL(2)
Reset(3)
State
PUCR
disabled
PERJ
PPSJ
Up
PUCR
disabled
26
—
—
PC4
DATA12
—
—
27
—
—
PC5
DATA13
—
—
VDDX
I/O
28
—
—
PC6
DATA14
—
—
VDDX
I/O
29
—
—
PC7
DATA15
—
—
VDDX
I/O
30
22
13
PJ3
STB0
—
—
Port J I/O, FR Strobe Signal 0
VDDX
I/O
31
23
14
PJ4
STB1
—
—
Port J I/O, FR Strobe Signal 1
VDDX
I/O
32
24
15
PJ5
STB2
—
—
Port J I/O, FR Strobe Signal 2
VDDX
I/O
33
25
16
PJ6
STB3
—
—
Port J I/O, FR Strobe Signal 3
VDDX
I/O
34
26
—
PJ7
—
—
—
Port J I/O
VDDX
I/O
35
27
—
PB0
ADDR0
UDS
IVD0(6)
VDDX
I/O
36
28
—
PB1
ADDR1
—
IVD1
VDDX
I/O
37
—
—
PB2
ADDR2
—
IVD2
VDDX
I/O
38
—
—
PB3
ADDR3
—
IVD3
VDDX
I/O
39
29
17
BKGD
MODC
—
—
Background Debug,
VDDX
I/O
PUCR
Up
40
30
18
PE7
XCLKS
ECLKX2
—
Port E I/O, Clock Select
System clock output
VDDX
I/O
PUCR
Up
41
31
—
PE6
MODB
TAGHI
—
Port E I/O, System clock
output, Clock Select
VDDX
I/O
While RESET
pin is low:
Down
42
32
—
PE5
MODA
TAGLO
RE
Port E I/O, System clock
output, Clock Select
VDDX
I/O
While RESET
pin is low:
Down
43
33
19
PE4
ECLK
—
—
Port E I/O, Bus Clock Output
VDDX
I/O
Port B I/O, Address Bus,
Internal Visibility Data
PUCR
Up
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
49
Chapter 1 MC9S12XF-Family Reference Manual
Table 1-10. Signal Properties
Pin Number
L
Q
F
P
144
Pin
Name
Funct.
1
Pin
Name
Funct.
2
Pin
Name
Funct.
3
Pin
Name
Funct.
4
Function
Power
Supply
Termination
out of Reset
I/O
(1)
L
Q
F
P
112
L
Q
F
P
64
44
34
—
PE3
LSTRB
LDS
EROMCTL
Port E I/O, Low Byte Data
strobe, EROMON control
VDDX
I/O
45
35
—
PE2
RW
WE
—
Port E I/O, synchrounous
Read/Write, asynchronous
write
VDDX
I/O
46
36
—
PH4
RXD_B
—
—
Port H I/O, FR Receive Data
Channel B
VDDX
I/O
47
37
—
PH5
TXD_B
—
—
Port H I/O, FR Transmit Data
Channel B
VDDX
I/O
48
38
—
PH6
TXE_B
—
—
Port H I/O, FR Transmit Data
Channel B
VDDX
I/O
49
39
—
PH7
—
—
—
Port H I/O
VDDX
I/O
50
40
20
VDDX2
—
—
—
I/O Power Supply 3-5V
51
41
21
VSSX2
—
—
—
I/O Ground Supply 3-5V
52
42
22
VSS3
—
—
—
Digital Ground Supply 1.8V
53
43
23
VDDR
—
—
—
Voltage Regulator Power Supply 3-5V
54
44
24
RESET
—
—
—
55
45
25
VDDPLL
—
—
—
56
46
26
NC
—
—
—
57
47
27
VSSPLL
—
—
—
58
48
28
EXTAL
—
—
—
59
49
29
XTAL
—
—
—
60
50
30
TEST
—
—
—
61
—
—
PB4
ADDR4
IVD4
—
External Reset
VDDX
CTRL(2)
Reset(3)
State
PUCR
Up
PERH
PPSH
disabled
I/O
Up
PLL & OSC Power Supply 1.8V
—
—
—
—
VDDPLL
NA
NA
VDDPLL
NA
NA
VDDX
RESET
PIN
Down
PUCR
disabled
PLL & OSC Ground Supply 1.8V
Oscillator Pins
Test Input
Port B I/O, Address Bus,
Internal Visibility Data
VDDX
I/O
VDDX
I/O
62
—
—
PB5
ADDR5
IVD5
—
63
—
—
PB6
ADDR6
IVD6
—
VDDX
I/O
64
—
—
PB7
ADDR7
IVD7
—
VDDX
I/O
MC9S12XF - Family Reference Manual, Rev.1.19
50
Freescale Semiconductor
Chapter 1 MC9S12XF-Family Reference Manual
Table 1-10. Signal Properties
Pin Number
L
Q
F
P
144
Pin
Name
Funct.
1
Pin
Name
Funct.
2
Pin
Name
Funct.
3
Pin
Name
Funct.
4
(1)
L
Q
F
P
112
L
Q
F
P
64
65
51
—
PA0
ADDR8
IVD8
—
66
52
—
PA1
ADDR9
IVD9
—
67
53
—
PA2
ADDR10
IVD10
68
54
—
PA3
ADDR11
69
—
—
VDDX4
70
—
—
71
55
72
Function
Power
Supply
Port A I/O, Address Bus,
Internal Visibility Data
I/O
VDDX
I/O
VDDX
I/O
—
VDDX
I/O
IVD11
—
VDDX
I/O
—
—
—
I/O Power Supply 3-5V
VSSX4
—
—
—
I/O Ground Supply 3-5V
31
PE1
IRQ
—
—
Port E Input, Maskable
Interrupt
VDDX
I
56
32
PE0
XIRQ
—
—
Port E Input, Non Maskable
Interrupt
VDDX
I
73
57
33
PH0
RXD_A
—
—
Port H I/O, FR Receive Data
Channel A
VDDX
I/O
74
58
34
PH1
TXD_A
—
—
Port H I/O, FR Transmit Data
Channel A
VDDX
I/O
75
59
35
PH2
TXE_A
—
—
Port H I/O, FR Transmit Data
Channel A
VDDX
I/O
76
60
36
PH3
—
—
—
Port H I/O
VDDX
I/O
77
—
—
PK0
ADDR16
IQSTAT0
—
VDDX
I/O
78
—
—
PK1
ADDR17
IQSTAT1
—
VDDX
I/O
79
—
—
PK2
ADDR18
IQSTAT2
—
VDDX
I/O
80
—
—
PK3
ADDR19
IQSTAT3
—
VDDX
I/O
81
—
—
PK4
ADDR20
ACC0
—
VDDX
I/O
82
—
—
PK5
ADDR21
ACC1
—
VDDX
I/O
83
—
—
PK6
ADDR22
ACC2
—
VDDX
I/O
84
—
—
PK7
EWAIT
ROMCTL
—
Port K I/O, EWAIT input, ROM
On Control
VDDX
I/O
85
61
—
PA4
ADDR12
IVD12
—
VDDX
I/O
86
62
—
PA5
ADDR13
IVD13
—
Port A I/O, Address Bus,
Internal Visibility Data
VDDX
I/O
87
63
—
PA6
ADDR14
IVD14
—
VDDX
I/O
88
64
—
PA7
ADDR15
IVD15
—
VDDX
I/O
Extended Address, PIPE
status
Port K I/O, Extended
Addresses,Access Source for
external Access
Termination
out of Reset
CTRL(2)
Reset(3)
State
PUCR
disabled
PUCR
Up
PERH
PPSH
disabled
PUCR
Up
PUCR
disabled
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
51
Chapter 1 MC9S12XF-Family Reference Manual
Table 1-10. Signal Properties
Pin Number
L
Q
F
P
144
Pin
Name
Funct.
1
Pin
Name
Funct.
2
Pin
Name
Funct.
3
Pin
Name
Funct.
4
Function
Power
Supply
Termination
out of Reset
I/O
(1)
L
Q
F
P
112
L
Q
F
P
64
89
65
37
VDD
—
—
—
Digital Power Supply 1.8V
90
66
38
VSS2
—
—
—
Digital Ground Supply 1.8V
91
67
39
PAD00
AN0
—
—
92
68
—
PAD08
AN8
—
—
93
69
40
PAD01
AN1
—
94
70
—
PAD09
AN9
95
71
41
PAD02
96
72
—
97
73
98
CTRL(2)
Port AD Inputs of ATD, Analog
Inputs of ATD
VDDA
Reset(3)
State
VDDA
I/O PER0AD
PER1AD
I/O
disabled
—
VDDA
I/O
—
—
VDDA
I/O
AN2
—
—
VDDA
I/O
PAD10
AN10
—
—
VDDA
I/O
42
PAD03
AN3
—
—
VDDA
I/O
74
—
PAD11
AN11
—
—
VDDA
I/O
99
75
43
PAD04
AN4
—
—
VDDA
I/O
100
76
—
PAD12
AN12
—
—
VDDA
I/O
101
77
44
PAD05
AN5
—
—
VDDA
I/O
102
78
—
PAD13
AN13
—
—
VDDA
I/O
103
79
45
PAD06
AN6
—
—
VDDA
I/O
104
80
—
PAD14
AN14
—
—
VDDA
I/O
105
81
46
PAD07
AN7
—
—
VDDA
I/O
106
82
—
PAD15
AN15
—
—
VDDA
I/O
107
83
47
VDDA
—
—
—
Analog Power Supply 5V
108
84
48
VRH
—
—
—
5V Reference voltages for the analog-to-digital converter.
109
85
49
VRL
—
—
—
0V Reference voltages for the analog-to-digital converter.
110
86
50
VSSA
—
—
—
Analog Power Ground 5V
111
—
—
NC
—
—
—
Not connected
—
—
—
—
112
—
—
NC
—
—
—
Not connected
—
—
—
—
MC9S12XF - Family Reference Manual, Rev.1.19
52
Freescale Semiconductor
Chapter 1 MC9S12XF-Family Reference Manual
Table 1-10. Signal Properties
Pin Number
L
Q
F
P
144
Pin
Name
Funct.
1
Pin
Name
Funct.
2
Pin
Name
Funct.
3
Pin
Name
Funct.
4
Function
Power
Supply
I/O
(1)
L
Q
F
P
112
L
Q
F
P
64
113
87
51
PS0
RXD0
—
—
Port S I/O, TXD of SCI0
VDDX
I/O
114
88
52
PS1
TXD0
—
—
Port S I/O, RXD of SCI0
VDDX
I/O
115
89
—
PS2
RXD1
—
—
Port S I/O, TXD of SCI1
VDDX
I/O
116
90
—
PS3
TXD1
—
—
Port S I/O, RXD of SCI1
VDDX
I/O
117
91
53
PS4
MISO0
—
—
Port S I/O, MISO of SPI0
VDDX
I/O
118
92
54
PS5
MOSI0
—
—
Port S I/O, MOSI of SPI0
VDDX
I/O
119
93
55
PS6
SCK0
—
—
Port S I/O, SCK of SPI0
VDDX
I/O
120
94
56
PS7
SS0
—
—
Port S I/O, SS of SP0
VDDX
I/O
121
—
—
NC
—
—
—
Not connected
—
122
—
—
NC
—
—
—
Not connected
123
95
—
PM7
SS1
CS3
—
124
96
—
PM6
SCK1
—
125
97
—
PM5
MOSI1
126
98
—
PM4
127
99
—
128 100
129
130
Termination
out of Reset
CTRL(2)
Reset(3)
State
PERS
PPSS
Up
—
—
—
—
—
—
—
Port M I/O, SS of SPI1, Chip
Select 3
VDDX
I/O
PERM
PPSM
disabled
—
Port M I/O, SCK of SPI1
VDDX
I/O
—
—
Port M I/O, MOSI of SPI1
VDDX
I/O
MISO1
CS2
—
Port M I/O, MISO of SPI1,
Chip Select 2
VDDX
I/O
PM3
FAULT3
CS1
—
Port M I/O, PMF Fault 3, Chip
Select 1
VDDX
I/O
—
PM2
FAULT2
CS0
—
Port M I/O, PMF Fault 2, Chip
Select 0
VDDX
I/O
—
—
NC
—
—
—
Not connected
—
—
—
—
—
—
NC
—
—
—
Not connected
—
—
—
—
131 101
57
PM1
TXCAN0
—
—
Port M I/O, CAN TX
VDDX
I/O
disabled
132 102
58
PM0
RXCAN0
—
—
Port M I/O, CAN RX
VDDX
I/O
PERM
PPSM
133 103
59
VSSX1
—
—
—
I/O Ground Supply 3-5V
134 104
60
VDDX1
—
—
—
5V power sypply
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
53
Chapter 1 MC9S12XF-Family Reference Manual
Table 1-10. Signal Properties
Pin Number
L
Q
F
P
144
Pin
Name
Funct.
1
Pin
Name
Funct.
2
Pin
Name
Funct.
3
Pin
Name
Funct.
4
(1)
L
Q
F
P
112
L
Q
F
P
64
135
—
—
PD7
DATA7
—
—
136
—
—
PD6
DATA6
—
—
Function
Power
Supply
Termination
out of Reset
I/O
VDDX
I/O
VDDX
I/O
CTRL(2)
Reset(3)
State
PUCR
disabled
PERP
PPSP
disabled
Port D I/O, Data Bus
137 105
—
PD5
DATA5
—
—
VDDX
I/O
138 106
—
PD4
DATA4
—
—
VDDX
I/O
139 107
—
PP7
FAULT1
—
—
Port P I/O, PMF Fault 1
VDDX
I/O
140 108
—
PP6
FAULT0
—
—
Port P I/O, PMF Fault 0
VDDX
I/O
141 109
61
PP5
PMF5
—
—
Port P I/O, PMF Channel 5
VDDX
I/O
142 110
62
PP4
PMF4
—
—
Port P I/O, PMF Channel 4
VDDX
I/O
143 111
63
PP3
PMF3
—
—
Port P I/O, PMF Channel 3
VDDX
I/O
144 112 64
PP2
PMF2
—
—
Port P I/O, PMF Channel 2
VDDX I/O
1. The 144-Pin LQFP version will not be qualified for production and is intended to be used for emulation (development tools) only.
2. Register bit in the Port Integration Module which controls the behavior
3. State after reset (disabled, pull Up, pull Down)
4. VDDX = VDDX1,VDDX2,VDDX3,VDDX4
5. VDDF must not be connected to VDD
6. Internal visability is only available on the 144-LQFP Package
NOTE
For devices assembled in 144-pin, 112-pin and 64-pin packages all non-bonded
out pins should be configured as outputs after reset in order to avoid current
leakage through I/O structures of floating inputs. Refer to Table 1-10 for affected
pins.
NOTE
VDDF must not be connected to VDD.
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1.2.3
Detailed Signal Descriptions
1.2.4
EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal driver output.
1.2.5
RESET — External Reset Pin
The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a
known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has an
internal pullup device.
1.2.6
TEST — Test Pin
This input only pin is reserved for test. This pin has a pulldown device.
NOTE
The TEST pin must be tied to VSS in all applications.
1.2.7
BKGD / MODC — Background Debug and Mode Pin
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It
is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit
at the rising edge of RESET. The BKGD pin has a pullup device.
NOTE
An additional lower-ohm pullup is required as the on-chip pullup device is
not intended to drive the debug line in the case of BDM communication.
1.2.8
1.2.8.1
Port Pins
PAD00 - PAD15 / AN00 - AN15 — Port AD I/0 Pin of ATD
PAD00 - PAD15 are general purpose inputs or outputs and analog inputs AN00 - AN15 of the analog to
digital converter ATD.
1.2.8.2
PA[7:0] / ADDR[15:8] / IVD[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external address bus. In MCU emulation modes of operation, these pins are used for external
address bus and internal visibility read data.
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1.2.8.3
PB[7:1] / ADDR[7:1] / IVD[7:1] — Port B I/O Pins
PB7-PB1 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external address bus. In MCU emulation modes of operation, these pins are used for external
address bus and internal visibility read data.
1.2.8.4
PB0 / ADDR0 / UDS / IVD[0] — Port B I/O Pin
PB0 is a general purpose input or output pin. In MCU expanded modes of operation, this pin is used for
the external address bus ADDR0 or as upper data strobe signal. In MCU emulation modes of operation,
this pin is used for external address bus ADDR0 and internal visibility read data IVD0.
1.2.8.5
PC[7:0] / DATA [15:8] — Port C I/O Pins
PC7-PC0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external data bus.
The input voltage thresholds for PC[7:0] can be configured to reduced levels, to allow data from an external
3.3V peripheral to be read by the MCU operating at 5.0V. The input voltage thresholds for PC[7:0] are
configured to reduced levels out of reset in expanded and emulation modes. The input voltage thresholds
for PC[7:0] are configured to 5V levels out of reset in normal modes.
1.2.8.6
PD[7:0] / DATA [7:0] — Port D I/O Pins
PD7-PD0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external data bus.
The input voltage thresholds for PD[7:0] can be configured to reduced levels, to allow data from an
external 3.3V peripheral to be read by the MCU operating at 5.0V. The input voltage thresholds for
PD[7:0] are configured to reduced levels out of reset in expanded and emulation modes. The input voltage
thresholds for PC[7:0] are configured to 5V levels out of reset in normal modes.
1.2.8.7
PE7 / ECLKX2 / XCLKS — Port E I/O
PE7 is a general-purpose input or output pin. ECLKX2 is a free running clock of twice the internal bus
frequency, available by default in emulation modes and when enabled in other modes. The XCLKS is an
input signal which controls whether a crystal in combination with the internal loop controlled Pierce
oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used (refer to Oscillator
Configuration). An internal pullup is enabled during reset.
1.2.8.8
PE6 / MODB / TAGHI — Port E I/O
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is an input with a
pull-down device which is only active when RESET is low. TAGHI is used to tag the high half of the
instruction word being read into the instruction queue.
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The input voltage threshold for PE6 can be configured to reduced levels, to allow data from an external
3.3V peripheral to be read by the MCU operating at 5.0V. The input voltage threshold for PE6 is
configured to reduced levels out of reset in expanded and emulation modes.
1.2.8.9
PE5 / MODA / TAGLO / RE — Port E I/O
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
Read Enable RE output. This pin is an input with a pull-down device which is only active when RESET is
low. TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
The input voltage threshold for PE5 can be configured to reduced levels, to allow data from an external
3.3V peripheral to be read by the MCU operating at 5.0V. The input voltage threshold for PE5 is
configured to reduced levels out of reset in expanded and emulation modes.
1.2.8.10
PE4 / ECLK — Port E I/O
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK.
ECLK can be used as a timing reference.
1.2.8.11
PE3 / LSTRB / LDS / EROMCTL — Port E I/O
PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB or LDS can
be used for the low byte strobe function to indicate the type of bus access. At the rising edge of RESET
the state of this pin is latched to the EROMON bit.
1.2.8.12
PE2 / R/W / WE— Port E I/O
PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the
read/write output signal or write enable output signal for the external bus. It indicates the direction of data
on the external bus.
1.2.8.13
PE1 / IRQ — Port E Input
PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
1.2.8.14
PE0 / XIRQ — Port E Input
PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
1.2.8.15
PH7— Port H I/O
PH7 is a general purpose input or output pin.
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1.2.8.16
PH6 / TXE_B — Port H I/O
PH6 is a general purpose input or output pin. It can be configured as FlexRay TXEN_B pin which indicates
to the Bus Driver that the FlexRay module is attempting to transmit data on channel B.
1.2.8.17
PH5 / TXD_B — Port H I/O
PH5 is a general purpose input or output pin. It can be configured as FlexRay data transmit channel B.
1.2.8.18
PH4 / RXD_B — Port H I/O
PH4 is a general purpose input or output pin. It can be configured as FlexRay data receive channel B.
1.2.8.19
PH3 — Port H I/O
PH3 is a general purpose input or output pin.
1.2.8.20
PH2 / TXE_A — Port H I/O
PH6 is a general purpose input or output pin. It can be configured as FlexRay TXEN_A pin which indicates
to the Bus Driver that the FlexRay module is attempting to transmit data on channel A.
1.2.8.21
PH1 / TXD_A — Port H I/O
PH1 is a general purpose input or output pin. It can be configured as FlexRay data transmit channel A.
1.2.8.22
PH0 / RXD_A — Port H I/O
PH0 is a general purpose input or output pin. It can be configured as FlexRay data receive channel A.
1.2.8.23
PJ7 — PORT J I/O
PJ7 is a general purpose input or output pin.
1.2.8.24
PJ6 / STB3 — PORT J I/O
PJ6 is a general purpose input or output pin. It can be configured as FlexRay Strobe Signal 3 (STB3).
1.2.8.25
PJ5 / STB2 — PORT J I/O
PJ5 is a general purpose input or output pin. It can be configured as FlexRay Strobe Signal 2 (STB2).
1.2.8.26
PJ4 / STB1— PORT J I/O
PJ4 is a general purpose input or output pin. It can be configured as FlexRay Strobe Signal 1 (STB1).
1.2.8.27
PJ3 / STB0 — PORT J I/O
PJ4 is a general purpose input or output pin. It can be configured as FlexRay Strobe Signal 1 (STB0).
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1.2.8.28
PJ2 / IS2 — PORT J I/O
PJ2 is a general purpose input or output pin. It can be configured as PMF current status bit for top/bottom
pulse width correction (IS2).
1.2.8.29
PJ1 / IS1 — PORT J I/O
PJ1 is a general purpose input or output pin. It can be configured as PMF current status bit for top/bottom
pulse width correction (IS1).
1.2.8.30
PJ0 / IS0 — PORT J I/O
PJ0 is a general purpose input or output pin. It can be configured as PMF current status bit for top/bottom
pulse width correction (IS0).
1.2.8.31
PK7 / EWAIT / ROMCTL — Port K I/O
PK7 is a general purpose input or output pin. During MCU emulation modes and normal expanded modes
of operation, this pin is used to enable the Flash EEEPROM memory in the memory map (ROMCTL). At
the rising edge of RESET, the state of this pin is latched to the ROMON bit. The EWAIT input signal
maintains the external bus access until the external device is ready to capture data (write) or provide data
(read).
The input voltage threshold for PK7 can be configured to reduced levels, to allow data from an external
3.3V peripheral to be read by the MCU operating at 5.0V.
1.2.8.32
PK[6:4] / ADDR[22:20] / ACC[2:0] — Port K I/O
PK[6:4] are general purpose input or output pins. During MCU expanded modes of operation, the
ACC[2:0] signals are used to indicate the access source of the bus cycle . This pins also provide the
expanded addresses ADDR[22:20] for the external bus. In Emulation modes ACC[2:0] is available and is
time multiplexed with the high addresses
1.2.8.33
PK[3:0] / ADDR[19:16] / IQSTAT[3:0] — Port K I/O
PK3-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins
provide the expanded address ADDR[19:16] for the external bus and carry instruction pipe information.
1.2.8.34
PM7 / SS1 / CS3 — Port M I/O
PM7 is a general purpose input or output pin. It can be configured as SS pin for SPI1 (SS1). It can be
configured as Chip Select 3 (CS3).
1.2.8.35
PM6 / SCK1 — Port M I/O
PM6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 1 (SPI1).
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1.2.8.36
PM5 / MOSI1 — Port M I/O
PM5 is a general purpose input or output pin. It can be configured as master output (during master mode)
or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
1.2.8.37
PM4 / MISO1 / CS2 — Port M I/O
PM4 is a general purpose input or output pin. It can be configured as master input (during master mode)
or slave output pin (during slave mode) MISO of the Serial Peripheral Interface 1 (SPI1). It can be
configured as Chip Select 2 (CS2).
1.2.8.38
PM3 / FAULT3 / CS1 — Port M I/O
PM3 is a general purpose input or output pin. It can be configured as PMF FAULT3 input pin. The FAULT
inputs are used to disable selected PWM outputs. It can be configured as Chip Select 1 (CS1).
1.2.8.39
PM2 / FAULT2 / CS0 — Port M I/O
PM2 is a general purpose input or output pin. It can be configured as PMF FAULT2 input pin. The FAULT
inputs are used to disable selected PWM outputs. It can be configured as Chip Select 0 (CS0).
1.2.8.40
PM1 / TXCAN0 — Port M I/O
PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Freescale Scalable Controller Area Network controller (MCAN).
1.2.8.41
PM0 / RXCAN0 — Port M I/O
PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Freescale Scalable Controller Area Network controller (MSCAN).
1.2.8.42
PP7 / FAULT1 — Port P I/O
PP7 is a general purpose input or output pin. I It can be configured as PMF FAULT1 input pin. The FAULT
inputs are used to disable selected PWM outputs.
1.2.8.43
PP6 / FAULT0 — Port P I/O
PP6 is a general purpose input or output pin. It can be configured as PMF FAULT0 input pin. The FAULT
inputs are used to disable selected PWM outputs.
1.2.8.44
PP5 / PMF5 — Port P I/O
PP5 is a general purpose input or output pin. It can be configured to work as PWM output channel 5 of the
PMF module.
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1.2.8.45
PP4 / PMF4 — Port P I/O
PP4 is a general purpose input or output pin. It can be configured to work as PWM output channel 4 of the
PMF module.
1.2.8.46
PP3 / PMF3 — Port P I/O
PP3 is a general purpose input or output pin. It can be configured to work as PWM output channel 3 of the
PMF module.
1.2.8.47
PP2 / PMF2 — Port P I/O
PP2 is a general purpose input or output pin. It can be configured to work as PWM output channel 2 of the
PMF module.
1.2.8.48
PP1 / PMF1 — Port P I/O
PP1 is a general purpose input or output pin. It can be configured to work as PWM output channel 1 of the
PMF module.
1.2.8.49
PP0 / PMF0 — Port P I/O
PP0 is a general purpose input or output pin. It can be configured to work as PWM output channel 0 of the
PMF module.
1.2.8.50
PS7 / SS0 — Port S I/O
PS7 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial
Peripheral Interface (SPI0).
1.2.8.51
PS6 / SCK0 — Port S I/O
PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 0 (SPI0).
1.2.8.52
PS5 / MOSI0 — Port S I/O
PS5 is a general purpose input or output pin. It can be configured as master output (during master mode)
or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
1.2.8.53
PS4 / MISO0 — Port S I/O
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or
slave output pin (during slave mode) MISO of the Serial Peripheral Interface 0 (SPI0).
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1.2.8.54
PS3 / TXD1 — Port S I/O
PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 1 (SCI1).
1.2.8.55
PS2 / RXD1 — Port S I/O
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 1 (SCI1).
1.2.8.56
PS1 / TXD0 — Port S I/O
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 0 (SCI0).
1.2.8.57
PS0 / RXD0 — Port S I/O
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 0 (SCI0).
1.2.8.58
PT7 / IOC7 — Port T I/O
PT7 is a general purpose input or output pin. It can be configured as input capture or output compare pin
IOC7 of the Enhanced Capture Timer (ECT).
1.2.8.59
PT6-PT3 / IOC6-IOC3 — Port T I/O
PT6-PT3 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC6-IOC3 of the Enhanced Capture Timer (ECT).
1.2.8.60
PT2-PT0 / IOC2-IOC0 — Port T I/O
PT2-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC2-IOC0 of the Enhanced Capture Timer (ECT).
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1.2.9
Power Supply Pins
The power and ground pins of the MC9S12XF512 are described below.
Because fast signal transitions place high, short-duration current demands on the power supply, use bypass
capacitors with high-frequency characteristics and place them as close to the MCU as possible.
NOTE
All VSS pins must be connected together in the application.
1.2.9.1
VDDX1 - VDDX4 / VSSX1 - VSSX4 — Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration
current demands on the power supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are
loaded.
1.2.9.2
VDDR — Power Pin for Internal Voltage Regulator
Input to the internal voltage regulator. Because fast signal transitions place high, short-duration current
demands on the power supply, use bypass capacitors with high-frequency characteristics and place them
as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded.
NOTE
Usage of an external voltage regulator is not allowed.
1.2.9.3
VDDF - NVM Power Pin
Power is supplied to the MCU NVM through VDDF. The voltage supply of nominally 2.8V is derived from
the internal voltage regulator when enabled. Connecting additional load to this pin is not permitted when
the internal regulator is enabled.
NOTE
VDDF must not be connected to VDD.
1.2.9.4
VDD / VSS1 - VSS2 - VSS3 — Core Power Pins
Use bypass capacitors with high-frequency characteristics because fast signal transitions place high, shortduration current demands on the power supply, and place them as close to the MCU as possible. This 1.8V
supply is derived from the internal voltage regulator when enabled. Connecting additional load to this pin
is not permitted when the internal regulator is enabled.
NOTE
VDD must not be connected to VDDF.
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1.2.9.5
VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to
digital converters.
1.2.9.6
VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
1.2.9.7
VDDPLL, VSSPLL — Power Supply Pins for PLL
These pins provide operating voltage and ground for the oscillator and the phased-locked loop. The voltage
supply of nominally 1.8V is derived from the internal voltage regulator when enabled. This allows the
supply voltage to the oscillator and PLL to be bypassed independently. This voltage is generated by the
internal voltage regulator. No static external loading of these pins is permitted.
NOTE
Connecting additional load to this pin is not permitted when the internal
regulator is enabled.
Table 1-11. MC9S12XF512 Power and Ground Connection Summary
Pin Number
144-pin
LQFP(1)
112-pin LQFP
64-pin LQFP
Nominal
Voltage
VDDF
14
14
7
2.8 V
Internal power and ground
generated by internal regulator for
the internal NVM.
VDD
89
65
37
1.8 V
VSS1, 2, 3
15, 90, 52
15, 66, 42
8, 38, 22
0V
Internal power and ground
generated by internal regulator for
the internal core.
VDDR
53
43
23
5.0 V
External power supply internal
voltage regulator
VDDX1
134
104
60
5.0 V
VSSX1
133
103
59
0V
External power and ground, supply
to pin drivers
VDDX2
50
40
20
5.0 V
VSSX2
52
41
21
0V
Mnemonic
VDDX3
17
17
—
5.0 V
VSSX3
16
16
—
0V
VDDX4
69
—
—
5.0 V
VSSX4
70
—
—
0V
VDDA
107
83
47
5.0 V
VSSA
110
86
50
0V
Description
External power and ground, supply
to pin drivers
External power and ground, supply
to pin drivers
External power and ground, supply
to pin drivers
Operating voltage and ground for
the analog-to-digital converters
and the reference for the internal
voltage regulator, allows the supply
voltage to the A/D to be bypassed
independently.
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Pin Number
144-pin
LQFP(1)
112-pin LQFP
64-pin LQFP
Nominal
Voltage
VRL
109
85
49
0V
VRH
108
84
48
5.0 V
VDDPLL
55
45
25
1.8 V
Mnemonic
Description
Reference voltages for the analogto-digital converter.
Provides operating voltage and
ground
for the phased-locked loop.
VSSPLL
57
47
27
0V
This allows the supply voltage to
the PLL to be bypassed
independently. Internal power and
ground generated by internal
regulator.
1. The 144-Pin LQFP version will not be qualified for production and is intended to be used for emulation
(development tools) only.
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1.3
System Clock Description
The Clock and Reset Generator module (CRG) provides the internal clock signals for the core and all
peripheral modules. shows the clock connections from the CRG to all modules.
Consult the CRG Block User Guide for details on clock generation.
SCI0 . . SCI 1
SPI0 . . SPI1
CAN
FlexRay
PMF
ATD
bus clock
EXTAL
EPIT
CGM
IPLL1
VREG/API2
ECT
CRG
oscillator clock
PIM
XTAL
core clock
RAM
S12X
XGATE
BDM
FTM
Figure 1-8. Clock Connections
1
PLL for FlexRay protocol engine. This PLL is independent from the system PLL (CRG) and has to be configured accordingly.
Refer to Chapter 12, “Clock Generation Module using IPLL (CGMIPLL) Block Description“, Chapter 13, “FlexRay
Communication Controller (FLEXRAY)“ and Section 1.12, “FlexRay IPLL (CGMIPLL) Configuration“ for details how to
configure the FlexRay IPLL.
2 Internal Oscillator for API (see 3.4.8 Autonomous Periodical Interrupt (API)).
The system clock can be supplied in several ways enabling a range of system operating frequencies to be
supported:
• The on-chip phase locked loop (PLL)
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•
•
the PLL self clocking
the oscillator
The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and
bus clock. As shown in Figure 1-8, these system clocks are used throughout the MCU to drive the core,
the memories, and the peripherals.
The Program Flash memory and the Data Flash are supplied by the bus clock and the oscillator clock. The
oscillator clock is used as a time base to derive the program and erase times for the NVM’s.
The CAN modules may be configured to have their clock sources derived either from the bus clock or
directly from the oscillator clock. This allows the user to select its clock based on the required jitter
performance.
In order to ensure the presence of the clock the MCU includes an on-chip clock monitor connected to the
output of the oscillator. The clock monitor can be configured to invoke the PLL self-clocking mode or to
generate a system reset if it is allowed to time out as a result of no oscillator clock being present.
In addition to the clock monitor, the MCU also provides a clock quality checker which performs a more
accurate check of the clock. The clock quality checker counts a predetermined number of clock edges
within a defined time window to insure that the clock is running. The checker can be invoked following
specific events such as on wake-up or clock monitor failure.
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1.4
Modes of Operation
The MCU can operate in different modes associated with MCU resource mapping and bus interface
configuration. These are described in 1.4.1 Chip Configuration Summary.
The MCU can operate in different power modes to facilitate power saving when full system performance
is not required. These are described in 1.4.2 Power Modes.
Some modules feature a software programmable option to freeze the module status whilst the background
debug module is active to facilitate debugging. This is described in 1.4.3 Freeze Mode.
The “system state” for the XCPU is always Supervisor State (see Chapter 17 Memory Protection Unit
(S12XMPUV2)).
1.4.1
Chip Configuration Summary
The MCU can operate in six different modes associated with resource configuration. The different modes,
the state of ROMCTL and EROMCTL signal on rising edge of RESET and the security state of the MCU
affect the following device characteristics:
• External bus interface configuration
• Flash in memory map, or not
• Debug features enabled or disabled
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA signals
during reset (see Table 1-12 ). The MODC, MODB, and MODA bits in the MODE register show the
current operating mode and provide limited mode switching during operation. The states of the MODC,
MODB, and MODA signals are latched into these bits on the rising edge of RESET.
In normal expanded mode and in emulation modes the ROMON and the EROMON bits in the MISC
register defines if the on chip flash memory is the memory map, or not. (See Table 1-12 .) For a detailed
explanation of the ROMON and EROMON bits refer to the MMC description.
The state of the ROMCTL signal is latched into the ROMON bit in the MMCCTL1 register on the rising
edge of RESET. The state of the EROMCTL signal is latched into the EROMON bit in the MMCCTL1
register on the rising edge of RESET.
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Table 1-12. Chip Modes and Data Sources
Chip Modes
Data Source(1)
MODC
MODB
MODA
ROMCTL
EROMCTL
Normal single chip
1
0
0
X
X
Internal
Special single chip
0
0
0
Emulation single chip
0
0
1
X
0
Emulation memory
X
1
Internal Flash
Normal expanded
1
0
1
0
X
External application
1
X
Internal Flash
0
X
External application
1
0
Emulation memory
1
1
Internal Flash
0
X
External application
Emulation expanded
Special test
0
0
1
1
1
0
1
X
Internal Flash
1. Internal means resources inside the MCU are read/written.
Internal Flash means Flash resources inside the MCU are read/written.
Emulation memory means resources inside the emulator are read/written (PRU registers, Flash replacement, RAM,
EEEPROM, and register space are always considered internal).
External application means resources residing outside the MCU are read/written.
1.4.1.1
Normal Expanded Mode
Ports K, A, and B are configured as a 23-bit address bus, ports C and D are configured as a 16-bit data bus,
and port E provides bus control and status signals. This mode allows 16-bit external memory and
peripheral devices to be interfaced to the system. The fastest external bus rate is one half of the internal
bus rate.
1.4.1.2
Normal Single-Chip Mode
There is no external bus in this mode. The processor program is executed from internal memory. Ports A,
B,C,D, K, and most pins of port E are available as general-purpose I/Os.
1.4.1.3
Special Single-Chip Mode
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The
background debug module BDM is active in this mode. The CPU executes a monitor program located in
an on-chip ROM. BDM firmware waits for additional serial commands through the BKGD pin. There is
no external bus after reset in this mode.
1.4.1.4
Emulation of Expanded Mode
Developers use this mode for emulation systems in which the users target application is normal expanded
mode. Code is executed from external memory or from internal memory depending on the state of
ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.
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1.4.1.5
Emulation of Single-Chip Mode
Developers use this mode for emulation systems in which the user’s target application is normal singlechip mode. Code is executed from external memory or from internal memory depending on the state of
ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.
1.4.1.6
Special Test Mode
Freescale internal use only.
1.4.2
Power Modes
The MCU features two main low-power modes. Consult the respective module description for module
specific behavior in system stop, system pseudo stop, and system wait mode. An important source of
information about the clock system is the Clock and Reset Generator description (CRG).
1.4.2.1
System Stop Modes
The system stop modes are entered if the CPU executes the STOP instruction and the S bit in the CCR
register is cleared unless either the XGATE is active or an NVM command is active. The XGATE is active
if it executes a thread or the XGFACT bit in the XGMCTL register is set. Depending on the state of the
PSTP bit in the CLKSEL register the MCU goes into pseudo stop mode or full stop mode. Please refer to
CRG description. Asserting RESET, XIRQ, IRQ or any other interrupt that is not masked causes the
system to exit the stop mode. System stop modes can be exited by XGATE or CPU activity independently,
depending on the configuration of the interrupt request. If System-Stop is exited on an XGATE request
then, as long as the XGATE does not set an interrupt flag on the CPU and the XGATE fake activity bit
(FACT) remains cleared, once XGATE activity is completed System Stop mode will automatically be reentered.
If the CPU executes the STOP instruction whilst XGATE is active or an NVM command is being
processed, then the system clocks continue running until XGATE/NVM activity is completed. If a nonmasked CPU-serviced interrupt occurs within this time then the system does not effectively enter stop
mode although the STOP instruction has been executed.
1.4.2.2
Full Stop Mode
The oscillator is stopped in this mode. By default all clocks are switched off and all counters and dividers
remain frozen. The Autonomous Periodic Interrupt (API) and ADC module may be enabled to self wake
the device. A Fast wake up mode is available to allow the device to wake from Full Stop mode immediately
on the PLL internal clock without starting the oscillator clock.
1.4.2.3
Pseudo Stop Mode
In this mode the system clocks are stopped but the oscillator is still running and the real time interrupt
(RTI) and watchdog (COP), API and ATD modules may be enabled. Other peripherals are turned off. This
mode consumes more current than system stop mode but, as the oscillator continues to run, the full speed
wake up time from this mode is significantly shorter.
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1.4.2.4
XGATE Fake Activity Mode
This mode is entered if the CPU executes the STOP instruction when the XGATE is not executing a thread
and the XGFACT bit in the XGMCTL register is set. The oscillator remains active and any enabled
peripherals continue to function.
1.4.2.5
Wait Mode
This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU clock is switched off. All peripherals and the XGATE can be active in
system wait mode. For further power consumption the peripherals can individually turn off their local
clocks. Asserting RESET, XIRQ, IRQ or any other interrupt that is not masked and is not routed to XGATE
ends system wait mode.
1.4.2.6
Run Mode
Although this is not a low-power mode, unused peripheral modules should not be enabled in order to save
power.
1.4.3
Freeze Mode
The enhanced capture timer, COP, pulse width modulator, analog-to-digital converter, and the periodic
interrupt timer provide a software programmable option to freeze the module status when the background
debug module is active. This is useful when debugging application software. For detailed description of
the behavior of the ADC, ECT, COP and EPIT when the background debug module is active consult the
corresponding Block Guides.
1.5
Security
The MCU security feature allows the protection of on chip NVM memories and RAM. For a detailed
description of the security features refer to the S12X9SEC description.
1.6
Resets and Interrupts
Consult the S12XCPU manual and the S12XINT description for information on exception processing.
1.6.1
Resets
Resets are explained in detail in the Clock Reset Generator (CRG) description.
1.6.2
Vectors
Table 1-13 lists all interrupt sources and vectors in the default order of priority. The interrupt module
(S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each
I-bit maskable service request is a configuration register. It selects if the service request is enabled, the
service request priority level and whether the service request is handled either by the S12X CPU or by the
XGATE module. IRQ is I-bit maskable and cannot be serviced by the XGATE.
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Table 1-13. Interrupt Vector Locations (Sheet 1 of 4)
Vector Address(1)
XGATE
Channel ID(2)
Interrupt Source
CCR
Mask
Local Enable
$FFFE
—
System reset or illegal access reset
None
None
$FFFC
—
Clock monitor reset
None
PLLCTL (CME, SCME)
$FFFA
—
COP watchdog reset
None
COP rate select
Vector base + $F8
—
Unimplemented instruction trap
None
None
Vector base+ $F6
—
SWI
None
None
Vector base+ $F4
—
XIRQ
X Bit
None
Vector base+ $F2
—
IRQ
I bit
IRQCR (IRQEN)
Vector base+ $F0
$78
Real time interrupt
I bit
CRGINT (RTIE)
Vector base+ $EE
$77
Enhanced capture timer channel 0
I bit
TIE (C0I)
Vector base + $EC
$76
Enhanced capture timer channel 1
I bit
TIE (C1I)
Vector base+ $EA
$75
Enhanced capture timer channel 2
I bit
TIE (C2I)
Vector base+ $E8
$74
Enhanced capture timer channel 3
I bit
TIE (C3I)
Vector base+ $E6
$73
Enhanced capture timer channel 4
I bit
TIE (C4I)
Vector base+ $E4
$72
Enhanced capture timer channel 5
I bit
TIE (C5I)
Vector base + $E2
$71
Enhanced capture timer channel 6
I bit
TIE (C6I)
Vector base+ $E0
$70
Enhanced capture timer channel 7
I bit
TIE (C7I)
Vector base+ $DE
$6F
Enhanced capture timer overflow
I bit
TSRC2 (TOF)
Vector base+ $DC
$6E
Pulse accumulator A overflow
I bit
PACTL (PAOVI)
Vector base + $DA
$6D
Pulse accumulator input edge
I bit
PACTL (PAI)
Vector base + $D8
$6C
SPI0
I bit
SPI0CR1 (SPIE, SPTIE)
Vector base+ $D6
$6B
SCI0
I bit
SCI0CR2
(TIE, TCIE, RIE, ILIE)
Vector base + $D4
$6A
SCI1
I bit
SCI1CR2
(TIE, TCIE, RIE, ILIE)
I bit
ATDCTL2 (ASCIE)
Vector Base + $D2
Vector base + $D0
Reserved
$68
ATD
Vector Base + $CE
Reserved
Vector Base + $CC
Reserved
Vector base + $CA
$65
Modulus down counter underflow
I bit
MCCTL (MCZI)
Vector base + $C8
$64
Pulse accumulator B overflow
I bit
PBCTL (PBOVI)
Vector base + $C6
$63
CRG PLL lock
I bit
CRGINT (LOCKIE)
Vector base + $C4
$62
CRG self-clock mode
I bit
CRGINT (SCMIE)
Vector base + $C2
$61
CGM IPLL change of lock
I bit
CGMFLG (LOCKIE)
I bit
SPI1CR1 (SPIE, SPTIE)
Vector base + $C0
Vector base + $BE
Reserved
$5F
SPI1
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Table 1-13. Interrupt Vector Locations (Sheet 2 of 4)
Vector Address(1)
XGATE
Channel ID(2)
Vector base + $BC
$5E
Vector base + $BA
$5D
FLASH Fault Detect
I bit
FCNFG2 (FDIE)
Vector base + $B8
$5C
FLASH
I bit
FCNFG (CCIE, CBEIE)
Vector base + $B6
$5B
CAN wake-up
I bit
CANRIER (WUPIE)
Vector base + $B4
$5A
CAN errors
I bit
CANRIER (CSCIE, OVRIE)
Vector base + $B2
$59
CAN receive
I bit
CANRIER (RXFIE)
Vector base + $B0
$58
CAN transmit
I bit
CANTIER (TXEIE[2:0])
Vector base + $AE
$57
Reserved
Vector base + $AC
$56
Reserved
Vector base + $AA
$55
Reserved
Vector base + $A8
$54
Reserved
Vector Base + $A6
$53
FlexRay Transmit Message Buffer Interrupt
I-Bit
GIFER (TBIE)
Vector Base + $A4
$52
FlexRay Receive Message Buffer Interrupt
I-Bit
GIFER (RBIE)
Vector Base + $A2
$51
FlexRay Receive FIFO channel A Not
Empty Interrupt
I-Bit
GIFER (FNEAIE)
Vector Base + $A0
$50
FlexRay Receive FIFO channel B Not
Empty Interrupt
I-Bit
GIFER (FNEBIE)
Vector Base + $9E
$4F
FlexRay Wakeup Interrupt
I-Bit
GIFER (WUPIE)
Vector Base+ $9C
$4E
FlexRay CHI Interrupt
I-Bit
GIFER (CHIE)
Vector Base+ $9A
$4D
FlexRay Protocol Interrupt
I-Bit
GIFER (PRIE)
Vector Base + $98
$4C
PMF Generator A Reload
I-Bit
PMFENCA (PWMRIEA)
Vector Base + $96
$4B
PMF Generator B Reload
I-Bit
PMFENCB (PWMRIEB)
Vector Base + $94
$4A
PMF Generator C Reload
I-Bit
PMFENCC (PWMRIEC)
Vector Base + $92
$49
PMF Fault 0
I-Bit
PMFFCTL (FIE0)
Vector Base + $90
$48
PMF Fault 1
I-Bit
PMFFCTL (FIE1)
Vector Base + $8E
$47
PMF Fault 2
I-Bit
PMFFCTL (FIE2)
Vector Base+ $8C
$46
PMF Fault 3
I-Bit
PMFFCTL (FIE3)
CCR
Mask
Interrupt Source
Local Enable
Reserved
Vector Base + $8A
Reserved
Vector Base + $88
Reserved
Vector Base + $86
Reserved
Vector Base + $84
Reserved
Vector Base + $82
Reserved
Vector base + $80
$40
Low-voltage interrupt (LVI)
I bit
VREGCTRL (LVIE)
Vector base + $7E
$3F
Autonomous periodical interrupt (API)
I bit
VREGAPICTRL (APIE)
Vector base + $7C
Reserved
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Table 1-13. Interrupt Vector Locations (Sheet 3 of 4)
Vector Address(1)
XGATE
Channel ID(2)
Interrupt Source
CCR
Mask
Local Enable
Vector base + $7A
$3D
Periodic interrupt timer channel 0
I bit
PITINTE (PINTE0)
Vector base + $78
$3C
Periodic interrupt timer channel 1
I bit
PITINTE (PINTE1)
Vector base + $76
$3B
Periodic interrupt timer channel 2
I bit
PITINTE (PINTE2)
Vector base + $74
$3A
Periodic interrupt timer channel 3
I bit
PITINTE (PINTE3)
Vector base + $72
$39
XGATE software trigger 0
I bit
XGMCTL (XGIE)
Vector base + $70
$38
XGATE software trigger 1
I bit
XGMCTL (XGIE)
Vector base + $6E
$37
XGATE software trigger 2
I bit
XGMCTL (XGIE)
Vector base + $6C
$36
XGATE software trigger 3
I bit
XGMCTL (XGIE)
Vector base + $6A
$35
XGATE software trigger 4
I bit
XGMCTL (XGIE)
Vector base + $68
$34
XGATE software trigger 5
I bit
XGMCTL (XGIE)
Vector base + $66
$33
XGATE software trigger 6
I bit
XGMCTL (XGIE)
Vector base + $64
$32
XGATE software trigger 7
I bit
XGMCTL (XGIE)
Vector base + $62
Reserved
Vector base + $60
Reserved
Vector base + $5E
$2F
Periodic interrupt timer channel 4
I bit
PITINTE (PINTE4)
Vector base + $5C
$2E
Periodic interrupt timer channel 5
I bit
PITINTE (PINTE5)
Vector base + $5A
$2D
Periodic interrupt timer channel 6
I bit
PITINTE (PINTE6)
Vector base + $58
$2C
Periodic interrupt timer channel 7
I bit
PITINTE (PINTE7)
Vector base + $56
$2B
Input Trigger Interrupt
I bit
PITTRIGIE
I bit
ATDCTL2 (ACMPIE)
Vector base + $54
Reserved
Vector base + $52
Reserved
Vector base + $50
Reserved
Vector base+ $4E
Reserved
Vector base + $4C
Reserved
Vector base+ $4A
Reserved
Vector base+ $48
Reserved
Vector base+ $46
Reserved
Vector base+ $44
Reserved
Vector base + $42
Reserved
Vector base+ $40
Reserved
Vector base+ $3E
Reserved
Vector base + $3C
Vector base + $18
to
Vector base + $3A
$1E
ATD Compare Interrupt
Reserved
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Table 1-13. Interrupt Vector Locations (Sheet 4 of 4)
Vector Address(1)
XGATE
Channel ID(2)
Interrupt Source
CCR
Mask
Local Enable
Vector base + $16
—
XGATE software error interrupt
None
None
Vector base + $14
—
MPU Access Error
None
None
Vector base + $12
—
System Call Interrupt (SYS)
—
None
—
None
Vector base + $10
—
Spurious interrupt
1. 16 bits vector address based
2. For detailed description of XGATE channel ID refer to XGATE Block Guide
1.6.3
Effects of Reset
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block
descriptions for register reset states.
On each reset, the Flash module executes a reset sequence to load Flash configuration registers and
initialize the buffer RAM EEE partition, if required.
1.6.3.1
Flash Configuration Reset Sequence Phase (Core Hold Phase)
On each reset, the Flash module will hold CPU activity while loading Flash module registers and
configuration from the Flash memory. The duration of this phase is given as tRST in the device electrical
parameter specification. If double faults are detected in the reset phase, Flash module protection and
security may be active on leaving reset. This is explained in more detail in the Flash (FTM) module section.
1.6.3.2
EEE Reset Sequence Phase (Core Active Phase)
During this phase of the reset sequence (following on from the core hold phase) the CPU can execute
instructions while the FTM initialization completes and, if configured for EEE operation, the EEE RAM
is loaded with valid data from the D-Flash EEE partition. Completion of this phase is indicated by the
CCIF flag in the FTM FSTAT register becoming set. If the CPU accesses any EEE RAM location before
the CCIF flag is set, the CPU is stalled until the FTM reset sequence is complete and the EEE RAM data
is valid. Once the CCIF flag is set, indicating the end of this phase, the EEE RAM can be accessed without
impacting the CPU and FTM commands can be executed.
1.6.3.3
Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.6.3.4
I/O Pins
Refer to the PIM block description for reset configurations of all peripheral module ports.
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1.6.3.5
Memory
The RAM arrays are not initialized out of reset with exception of the EEE buffer RAM (providing the EEE
functionality is enabled).
1.6.3.6
COP Configuration
The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge
of RESET from the Flash register FOPT. See Table 1-14 and Table 1-15 for coding. The FOPT register
is loaded from the Flash configuration field byte at global address $7FFF0E during the reset sequence.
If the MCU is secured and COP is enabled, the COP timeout rate is always set to the longest period
(CR[2:0] = 111) after COP reset and after any reset into Special Single Chip mode.
Table 1-14. Initial COP Rate Configuration
NV[2:0] in
FCTL Register
CR[2:0] in
COPCTL Register
000
111
001
110
010
101
011
100
100
011
101
010
110
001
111
000
Table 1-15. Initial WCOP Configuration
NV[3] in
FCTL Register
WCOP in
COPCTL Register
1
0
0
1
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1.7
EPIT External Trigger Input
The start of the timer channels can be aligned to an external trigger event. Four trigger event sources can
be connected. The MC9S12XF Family uses two sources for external trigger events. See Table 1-16 and
the EPIT block guide for more details.
Table 1-16. External Trigger Input Sources
External Trigger
Input
Connectivity
EPIT Register Settings
PITTRIGSRC[1:0]
TRIGIN0
EPIT - Hardware Trigger 0
00
TRIGIN1
Start of PWM Cycle Channel A
01
TRIGIN2
ECT Input Capture/Output Compare Interrupt 0
10
TRIGIN3
Not Connected
1. No effect as external trigger input is tied.
11 (1)
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1.8
ATD External Trigger Input Connection
The ATD module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The
external trigger allows the user to synchronize ATD conversion to external trigger events. Table 1-17
shows the connection of the external trigger inputs.
Table 1-17. ATD0 External Trigger Sources
External Trigger
Input
Connectivity
ETRIG0
Start of PWM Cycle Channel A(1)
ETRIG1
EPIT - Combined Trigger(2)
ETRIG2
EPIT - Hardware Trigger 0(3)
ETRIG3
EPIT - Hardware Trigger 1(4)
1. Indicates start of new PWM cycle.
2. Selectable hardware trigger. One of eight EPIT channels can be selected. The trigger interval
is started via a PMF output.
3. Interrupt timer hardware trigger channel 0
4. Interrupt timer hardware trigger channel 1
Consult the EPIT block description for more information about hardware trigger generation.
Consult the ATD block description for information about the analog-to-digital converter module. ATD
block description refererences to freeze mode are equivalent to active BDM mode.
1.9
MPU Configuration
The MPU can handle 3 bus masters (CPU + XGATE + FlexRay). The MPU covers the system ram address
space. See MPU documentation for more details.
Table 1-18. MPU Configuration
Parameter
Parameter
Value
Number of Descriptors
4
8
Descripter Granularity(1)
1. Number of least significant address bits to
treat as constant.
NOTE
• The FlexRay module is Master 3 (MSTR3)
• CPU user state is not supported
on this device.
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1.10
VREG Configuration
The VREGEN connection of the voltage regulator is tied internally to VDDR such that the voltage
regulator is always enabled with VDDR connected to a positive supply voltage. The device must be
configured with the internal voltage regulator enabled. Operation in conjunction with an external voltage
regulator is not supported.
The autonomous periodic interrupt clock output is mapped to PortT[5].
The API trimming register APITR is loaded on rising edge of RESET from the Flash IFR option field at
global address 0x40_00F0 bits[5:0] during the reset sequence. Currently factory programming of this IFR
range is not supported.
1.10.1
Temperature Sensor Configuration
The VREG high temperature trimming register bits VREGHTTR[3:0] are loaded from the Flash IFR
option field at global address 0x40_00F0 bits[11:8] during the reset sequence. To use the high temperature
interrupt within the specified limits (THTIA and THTID) these bits must be programmed to 0x8. Currently
factory programming of this IFR range is not supported. Note that the API trimming bits are also loaded
from 0x40_00F0[5:0].
The device temperature can be monitored on ADC0 channel[17].
The internal bandgap reference voltage can also be mapped to ADC0 analog input channel[17]. The
voltage regulator VSEL bit when set, maps the bandgap and, when clear, maps the temperature sensor to
ADC0 channel[17].
Read access to reserved VREG register space returns “0”. Write accesses have no effect. This device does
not support access abort of reserved VREG register space.
1.11
BDM Configuration
The BDM alternative clock corresponds to the oscillator clock.
1.12
FlexRay IPLL (CGMIPLL) Configuration
MC9S12XF512 features a dedicated internal PLL for the FlexRay protocol engine. The IPLL hard IP and
the register map for the configuration registers is identical to the system IPLL.
The usage of an dedicated internal PLL allows to use cheaper crystal devices and to achieve lower
radiation.
1.12.1
CGMIPLL function
The CGMIPLL module supplies the clock to the FlexRay controller. The FlexRay controller can only
operate according to FlexRay specification when it is supplied with stable 80MHz clock. The CGMIPLL
must be configured to provide an 80MHz clock on its output (see Chapter 12, “Clock Generation Module
using IPLL (CGMIPLL) Block Description“ for more details) and the FlexRay controller must be
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configured to use the CGMIPLL as its clock source (bit CLKSEL in register MCR, see section 13.5.2.4,
“Module Configuration Register (MCR)“ for more details).
It is the responsibility of the software to ensure that a stable 80MHz clock is supplied to the FlexRay
controller while it is enabled.
NOTE
FlexRay applications have to use the FlexRay IPLL as clock source for the
FlexRay protocol engine. The option to use the crystal as clock source is
only intended for test purposes.
The CGMIPLL has to be configured for 80MHz to guarantee FlexRay
functionality.
FlexRay needs a stable clock. Make sure the PLL is locked before enabling
FlexRay and make sure it remains locked while FlexRay is running.
Frequency modulation should be turned off on the FlexRay IPLL.
1.12.2
Entry into and exit from low power modes
To ensure correct entry into stop mode the software should perform the following steps:
1. Shut down the FlexRay Controller (see 13.7.2 Shut Down Sequence for more details)
2. Turn off the CGMIPLL module by clearing the PLLON bit in the CGMCTL register (see section
12.3.2.4 CGMIPLL Control Register (CGMCTL) for more details)
3. Perform additional application specific tasks and enter low power mode
Once the microcontroller is woken-up from the low power mode the firmware should perform the
following steps:
1. Turn on the CGMIPLL module by setting the PLLON bit in the CGMCTL register
2. Wait for the CGMIPLL to achieve lock by waiting for the LOCK bit in the CGMCTL register to
become set
3. Re-initialize the FlexRay controller (see 13.7.1 Initialization Sequence for more details)
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1.13
Oscillator Configuration
The XCLKS is an input signal which controls whether a crystal in combination with the internal loop
controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock
circuitry is used. For this device XCLKS is mapped to PE7.
The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check
is ongoing. This is the case for:
• Power on reset or low-voltage reset
• Clock monitor reset
• Any reset while in self-clock mode or full stop mode
The selected oscillator configuration is frozen with the rising edge of the RESET pin in any of these above
described reset cases.
EXTAL
C1
MCU
Crystal or
Ceramic Resonator
XTAL
C2
VSSPLL
Figure 1-9. Loop Controlled Pierce Oscillator Connections (XCLKS = 1)
EXTAL
C1
MCU
RB
RS
Crystal or
Ceramic Resonator
XTAL
C2
RB=1MΩ ; RS specified by crystal vendor
VSSPLL
Figure 1-10. Full Swing Pierce Oscillator Connections (XCLKS = 0)
EXTAL
CMOS-Compatible
External Oscillator
MCU
XTAL
Not Connected
Figure 1-11. External Clock Connections (XCLKS = 0)
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Chapter 2
S12XE Clocks and Reset Generator (S12XECRG)
Table 2-1. Revision History
Revision
Number
Revision
Date
V01.00
26 Oct. 2005
V01.01
02 Nov 2006
2.4.1.1/2-100
Table “Examples of IPLL Divider settings”: corrected $32 to $31
V01.02
4 Mar. 2008
2.4.1.4/2-103
2.4.3.3/2-107
Corrected details
V01.03
1 Sep. 2008
Table 2-14
V01.04
20 Nov. 2008
2.3.2.4/2-89
S12XECRG Flags Register: corrected address to Module Base + 0x0003
V01.05
19. Sep 2009
2.5.1/2-109
Modified Note below Table 2-17./2-109
2.1
Sections
Affected
Description of Changes
Initial release
added 100MHz example for PLL
Introduction
This specification describes the function of the Clocks and Reset Generator (S12XECRG).
2.1.1
Features
The main features of this block are:
• Phase Locked Loop (IPLL) frequency multiplier with internal filter
— Reference divider
— Post divider
— Configurable internal filter (no external pin)
— Optional frequency modulation for defined jitter and reduced emission
— Automatic frequency lock detector
— Interrupt request on entry or exit from locked condition
— Self Clock Mode in absence of reference clock
• System Clock Generator
— Clock Quality Check
— User selectable fast wake-up from Stop in Self-Clock Mode for power saving and immediate
program execution
— Clock switch for either Oscillator or PLL based system clocks
• Computer Operating Properly (COP) watchdog timer with time-out clear window.
• System Reset generation from the following possible sources:
— Power on reset
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Chapter 2 S12XE Clocks and Reset Generator (S12XECRG)
•
2.1.2
— Low voltage reset
— Illegal address reset
— COP reset
— Loss of clock reset
— External pin reset
Real-Time Interrupt (RTI)
Modes of Operation
This subsection lists and briefly describes all operating modes supported by the S12XECRG.
• Run Mode
All functional parts of the S12XECRG are running during normal Run Mode. If RTI or COP
functionality is required the individual bits of the associated rate select registers (COPCTL,
RTICTL) have to be set to a non zero value.
• Wait Mode
In this mode the IPLL can be disabled automatically depending on the PLLWAI bit.
• Stop Mode
Depending on the setting of the PSTP bit Stop Mode can be differentiated between Full Stop Mode
(PSTP = 0) and Pseudo Stop Mode (PSTP = 1).
— Full Stop Mode
The oscillator is disabled and thus all system and core clocks are stopped. The COP and the
RTI remain frozen.
— Pseudo Stop Mode
The oscillator continues to run and most of the system and core clocks are stopped. If the
respective enable bits are set the COP and RTI will continue to run, else they remain frozen.
• Self Clock Mode
Self Clock Mode will be entered if the Clock Monitor Enable Bit (CME) and the Self Clock Mode
Enable Bit (SCME) are both asserted and the clock monitor in the oscillator block detects a loss of
clock. As soon as Self Clock Mode is entered the S12XECRG starts to perform a clock quality
check. Self Clock Mode remains active until the clock quality check indicates that the required
quality of the incoming clock signal is met (frequency and amplitude). Self Clock Mode should be
used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock
is causing severe system conditions.
2.1.3
Block Diagram
Figure 2-1 shows a block diagram of the S12XECRG.
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Illegal Address Reset
S12X_MMC
Power on Reset
Voltage
Regulator
Low Voltage Reset
ICRG
RESET
CM Fail
Clock
Monitor
OSCCLK
EXTAL
Oscillator
XTAL
COP Timeout
XCLKS
Reset
Generator
Clock Quality
Checker
System Reset
Bus Clock
Core Clock
COP
RTI
Oscillator Clock
Registers
PLLCLK
VDDPLL
IPLL
VSSPLL
Real Time Interrupt
Clock and Reset Control
PLL Lock Interrupt
Self Clock Mode
Interrupt
Figure 2-1. Block diagram of S12XECRG
2.2
Signal Description
This section lists and describes the signals that connect off chip.
2.2.1
VDDPLL, VSSPLL
These pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the IPLL circuitry. This allows
the supply voltage to the IPLL to be independently bypassed. Even if IPLL usage is not required VDDPLL
and VSSPLL must be connected to properly.
2.2.2
RESET
RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been
triggered.
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2.3
Memory Map and Registers
This section provides a detailed description of all registers accessible in the S12XECRG.
2.3.1
Module Memory Map
Figure 2-2 gives an overview on all S12XECRG registers.
Address
Name
0x0000
SYNR
0x0001
REFDV
0x0002
POSTDIV
0x0003
CRGFLG
0x0004
CRGINT
0x0005
CLKSEL
0x0006
PLLCTL
0x0007
RTICTL
0x0008
COPCTL
0x0009
FORBYP2
0x000A
CTCTL2
0x000B
ARMCOP
Bit 7
R
W
R
W
R
6
5
4
3
VCOFRQ[1:0]
SYNDIV[5:0]
REFFRQ[1:0]
REFDIV[5:0]
0
0
0
RTIF
PORF
LVRF
W
R
0
0
W
R
RTIE
LOCKIF
LOCKIE
LOCK
0
XCLKS
0
PLLON
FM1
FM0
FSTWKP
RTDEC
RTR6
RTR5
RTR4
RTR3
WCOP
RSBCK
0
0
0
0
0
0
0
0
0
0
R
0
0
W
Bit 7
Bit 6
W
R
W
R
W
R
W
R
PLLSEL
PSTP
CME
1
Bit 0
POSTDIV[4:0]
W
R
2
PLLWAI
ILAF
0
0
SCMIF
SCMIE
SCM
0
RTIWAI
COPWAI
PRE
PCE
SCME
RTR2
RTR1
RTR0
CR2
CR1
CR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WRTMASK
W
R
W
2. FORBYP and CTCTL are intended for factory test purposes only.
= Unimplemented or Reserved
Figure 2-2. CRG Register Summary
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
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2.3.2
Register Descriptions
This section describes in address order all the S12XECRG registers and their individual bits.
2.3.2.1
S12XECRG Synthesizer Register (SYNR)
The SYNR register controls the multiplication factor of the IPLL and selects the VCO frequency range.
Module Base + 0x0000
7
6
5
4
3
2
1
0
0
0
0
R
VCOFRQ[1:0]
SYNDIV[5:0]
W
Reset
0
0
0
0
0
Figure 2-3. S12XECRG Synthesizer Register (SYNR)
Read: Anytime
Write: Anytime except if PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit.
( SYNDIV + 1 )
f VCO = 2 × f OSC × ------------------------------------( REFDIV + 1 )
f VCO
f PLL = -----------------------------------2 × POSTDIV
f PLL
f BUS = ------------2
NOTE
fVCO must be within the specified VCO frequency lock range. F.BUS (Bus
Clock) must not exceed the specified maximum. If POSTDIV = $00 then
fPLL is same as fVCO (divide by one).
The VCOFRQ[1:0] bit are used to configure the VCO gain for optimal stability and lock time. For correct
IPLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in Table 2-2. Setting the VCOFRQ[1:0] bits wrong can result in a non functional IPLL
(no locking and/or insufficient stability).
Table 2-2. VCO Clock Frequency Selection
VCOCLK Frequency Ranges
VCOFRQ[1:0]
32MHz <= fVCO<= 48MHz
00
48MHz < fVCO<= 80MHz
01
Reserved
10
80MHz < fVCO <= 120MHz
11
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2.3.2.2
S12XECRG Reference Divider Register (REFDV)
The REFDV register provides a finer granularity for the IPLL multiplier steps.
Module Base + 0x0001
7
6
5
4
3
2
1
0
0
0
0
R
REFFRQ[1:0]
REFDIV[5:0]
W
Reset
0
0
0
0
0
Figure 2-4. S12XECRG Reference Divider Register (REFDV)
Read: Anytime
Write: Anytime except when PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit.
f OSC
f REF = -----------------------------------( REFDIV + 1 )
The REFFRQ[1:0] bit are used to configure the internal PLL filter for optimal stability and lock time. For
correct IPLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in Figure 2-3. Setting the REFFRQ[1:0] bits wrong can result in a non functional IPLL
(no locking and/or insufficient stability).
Table 2-3. Reference Clock Frequency Selection
2.3.2.3
REFCLK Frequency Ranges
REFFRQ[1:0]
1MHz <= fREF <= 2MHz
00
2MHz < fREF <= 6MHz
01
6MHz < fREF <= 12MHz
10
fREF >12MHz
11
S12XECRG Post Divider Register (POSTDIV)
The POSTDIV register controls the frequency ratio between the VCOCLK and PLLCLK. The count in the
final divider divides VCOCLK frequency by 1 or 2*POSTDIV. Note that if POSTDIV = $00 fPLL= fVCO
(divide by one).
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Module Base + 0x0002
R
7
6
5
0
0
0
4
3
2
1
0
0
0
2
1
0
ILAF
SCMIF
0
0
POSTDIV[4:0]
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-5. S12XECRG Post Divider Register (POSTDIV)
Read: Anytime
Write: Anytime except if PLLSEL = 1
f VCO
f PLL = -------------------------------------( 2xPOSTDIV )
NOTE
If POSTDIV = $00 then fPLL is identical to fVCO (divide by one).
2.3.2.4
S12XECRG Flags Register (CRGFLG)
This register provides S12XECRG status bits and flags.
Module Base + 0x0003
7
6
5
4
RTIF
PORF
LVRF
LOCKIF
0
Note 1
Note 2
Note 3
R
3
LOCK
SCM
W
Reset
0
0
1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by system reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset.
= Unimplemented or Reserved
Figure 2-6. S12XECRG Flags Register (CRGFLG)
Read: Anytime
Write: Refer to each bit for individual write conditions
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Table 2-4. CRGFLG Field Descriptions
Field
Description
7
RTIF
Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing
a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request.
0 RTI time-out has not yet occurred.
1 RTI time-out has occurred.
6
PORF
Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing
a 1. Writing a 0 has no effect.
0 Power on reset has not occurred.
1 Power on reset has occurred.
5
LVRF
Low Voltage Reset Flag — LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by
writing a 1. Writing a 0 has no effect.
0 Low voltage reset has not occurred.
1 Low voltage reset has occurred.
4
LOCKIF
IPLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared
by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE=1), LOCKIF causes an interrupt request.
0 No change in LOCK bit.
1 LOCK bit has changed.
3
LOCK
Lock Status Bit — LOCK reflects the current state of IPLL lock condition. This bit is cleared in Self Clock Mode.
Writes have no effect.
0 VCOCLK is not within the desired tolerance of the target frequency.
1 VCOCLK is within the desired tolerance of the target frequency.
2
ILAF
Illegal Address Reset Flag — ILAF is set to 1 when an illegal address reset occurs. Refer to S12XMMC Block
Guide for details. This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Illegal address reset has not occurred.
1 Illegal address reset has occurred.
1
SCMIF
0
SCM
2.3.2.5
Self Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This flag can only be
cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE=1), SCMIF causes an interrupt request.
0 No change in SCM bit.
1 SCM bit has changed.
Self Clock Mode Status Bit — SCM reflects the current clocking mode. Writes have no effect.
0 MCU is operating normally with OSCCLK available.
1 MCU is operating in Self Clock Mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK
running at its minimum frequency fSCM.
S12XECRG Interrupt Enable Register (CRGINT)
This register enables S12XECRG interrupt requests.
Module Base + 0x0004
7
R
6
5
0
0
RTIE
4
3
2
0
0
LOCKIE
1
0
0
SCMIE
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-7. S12XECRG Interrupt Enable Register (CRGINT)
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Read: Anytime
Write: Anytime
Table 2-5. CRGINT Field Descriptions
Field
7
RTIE
Description
Real Time Interrupt Enable Bit
0 Interrupt requests from RTI are disabled.
1 Interrupt will be requested whenever RTIF is set.
4
LOCKIE
Lock Interrupt Enable Bit
0 LOCK interrupt requests are disabled.
1 Interrupt will be requested whenever LOCKIF is set.
1
SCMIE
Self Clock Mode Interrupt Enable Bit
0 SCM interrupt requests are disabled.
1 Interrupt will be requested whenever SCMIF is set.
2.3.2.6
S12XECRG Clock Select Register (CLKSEL)
This register controls S12XECRG clock selection. Refer toFigure 2-16 for more details on the effect of
each bit.
Module Base + 0x0005
7
6
PLLSEL
PSTP
0
0
R
5
4
XCLKS
0
3
2
1
0
RTIWAI
COPWAI
0
0
0
PLLWAI
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 2-8. S12XECRG Clock Select Register (CLKSEL)
Read: Anytime
Write: Refer to each bit for individual write conditions
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Table 2-6. CLKSEL Field Descriptions
Field
7
PLLSEL
6
PSTP
Description
PLL Select Bit
Write: Anytime.
Writing a one when LOCK=0 has no effect. This prevents the selection of an unstable PLLCLK as SYSCLK.
PLLSEL bit is cleared when the MCU enters Self Clock Mode, Stop Mode or Wait Mode with PLLWAI bit set.
It is recommended to read back the PLLSEL bit to make sure PLLCLK has really been selected as
SYSCLK, as LOCK status bit could theoretically change at the very moment writing the PLLSEL bit.
0 System clocks are derived from OSCCLK (fBUS = fOSC / 2).
1 System clocks are derived from PLLCLK (fBUS = fPLL / 2).
Pseudo Stop Bit
Write: Anytime
This bit controls the functionality of the oscillator during Stop Mode.
0 Oscillator is disabled in Stop Mode.
1 Oscillator continues to run in Stop Mode (Pseudo Stop).
Note: Pseudo Stop Mode allows for faster STOP recovery and reduces the mechanical stress and aging of the
resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption.
5
XCLKS
Oscillator Configuration Status Bit — This read-only bit shows the oscillator configuration status.
0 Loop controlled Pierce Oscillator is selected.
1 External clock / full swing Pierce Oscillator is selected.
3
PLLWAI
PLL Stops in Wait Mode Bit
Write: Anytime
If PLLWAI is set, the S12XECRG will clear the PLLSEL bit before entering Wait Mode. The PLLON bit remains
set during Wait Mode but the IPLL is powered down. Upon exiting Wait Mode, the PLLSEL bit has to be set
manually if PLL clock is required.
0 IPLL keeps running in Wait Mode.
1 IPLL stops in Wait Mode.
1
RTIWAI
RTI Stops in Wait Mode Bit
Write: Anytime
0 RTI keeps running in Wait Mode.
1 RTI stops and initializes the RTI dividers whenever the part goes into Wait Mode.
0
COPWAI
COP Stops in Wait Mode Bit
Normal modes: Write once
Special modes: Write anytime
0 COP keeps running in Wait Mode.
1 COP stops and initializes the COP counter whenever the part goes into Wait Mode.
2.3.2.7
S12XECRG IPLL Control Register (PLLCTL)
This register controls the IPLL functionality.
Module Base + 0x0006
7
6
5
4
3
2
1
0
CME
PLLON
FM1
FM0
FSTWKP
PRE
PCE
SCME
1
1
0
0
0
0
0
1
R
W
Reset
Figure 2-9. S12XECRG IPLL Control Register (PLLCTL)
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Read: Anytime
Write: Refer to each bit for individual write conditions
Table 2-7. PLLCTL Field Descriptions
Field
Description
7
CME
Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1.
0 Clock monitor is disabled.
1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or Self Clock
Mode.
Note: Operating with CME=0 will not detect any loss of clock. In case of poor clock quality this could cause
unpredictable operation of the MCU!
In Stop Mode (PSTP=0) the clock monitor is disabled independently of the CME bit setting and any loss
of external clock will not be detected.
Also after wake-up from stop mode (PSTP = 0) with fast wake-up enabled (FSTWKP = 1) the clock monitor
is disabled independently of the CME bit setting and any loss of external clock will not be detected.
6
PLLON
Phase Lock Loop On Bit — PLLON turns on the IPLL circuitry. In Self Clock Mode, the IPLL is turned on, but
the PLLON bit reads the last written value. Write anytime except when PLLSEL = 1.
0 IPLL is turned off.
1 IPLL is turned on.
5, 4
FM1, FM0
IPLL Frequency Modulation Enable Bit — FM1 and FM0 enable additional frequency modulation on the
VCOCLK. This is to reduce noise emission. The modulation frequency is fref divided by 16. Write anytime except
when PLLSEL = 1. See Table 2-8 for coding.
3
FSTWKP
Fast Wake-up from Full Stop Bit — FSTWKP enables fast wake-up from full stop mode. Write anytime. If SelfClock Mode is disabled (SCME = 0) this bit has no effect.
0 Fast wake-up from full stop mode is disabled.
1 Fast wake-up from full stop mode is enabled. When waking up from full stop mode the system will immediately
resume operation in Self-Clock Mode (see Section 2.4.1.4, “Clock Quality Checker”). The SCMIF flag will not
be set. The system will remain in Self-Clock Mode with oscillator and clock monitor disabled until FSTWKP bit
is cleared. The clearing of FSTWKP will start the oscillator, the clock monitor and the clock quality check. If
the clock quality check is successful, the S12XECRG will switch all system clocks to OSCCLK. The SCMIF
flag will be set. See application examples in Figure 2-19 and Figure 2-20.
2
PRE
RTI Enable During Pseudo Stop Bit — PRE enables the RTI during Pseudo Stop Mode.
Write anytime.
0 RTI stops running during Pseudo Stop Mode.
1 RTI continues running during Pseudo Stop Mode.
Note: If the PRE bit is cleared the RTI dividers will go static while Pseudo Stop Mode is active. The RTI dividers
will not initialize like in Wait Mode with RTIWAI bit set.
1
PCE
COP Enable During Pseudo Stop Bit — PCE enables the COP during Pseudo Stop Mode.
Write anytime.
0 COP stops running during Pseudo Stop Mode
1 COP continues running during Pseudo Stop Mode
Note: If the PCE bit is cleared the COP dividers will go static while Pseudo Stop Mode is active. The COP
dividers will not initialize like in Wait Mode with COPWAI bit set.
0
SCME
Self Clock Mode Enable Bit
Normal modes: Write once
Special modes: Write anytime
SCME can not be cleared while operating in Self Clock Mode (SCM = 1).
0 Detection of crystal clock failure causes clock monitor reset (see Section 2.5.1.1, “Clock Monitor Reset”).
1 Detection of crystal clock failure forces the MCU in Self Clock Mode (see Section 2.4.2.2, “Self Clock Mode”).
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Chapter 2 S12XE Clocks and Reset Generator (S12XECRG)
Table 2-8. FM Amplitude selection
FM1
2.3.2.8
FM Amplitude /
fVCO Variation
FM0
0
0
FM off
0
1
±1%
1
0
±2%
1
1
±4%
S12XECRG RTI Control Register (RTICTL)
This register selects the timeout period for the Real Time Interrupt.
Module Base + 0x0007
7
6
5
4
3
2
1
0
RTDEC
RTR6
RTR5
RTR4
RTR3
RTR2
RTR1
RTR0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-10. S12XECRG RTI Control Register (RTICTL)
Read: Anytime
Write: Anytime
NOTE
A write to this register initializes the RTI counter.
Table 2-9. RTICTL Field Descriptions
Field
Description
7
RTDEC
Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
0 Binary based divider value. See Table 2-10
1 Decimal based divider value. See Table 2-11
6–4
RTR[6:4]
Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See Table 210 and Table 2-11.
3–0
RTR[3:0]
Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity.Table 2-10 and Table 2-11 show all possible divide values selectable by the
RTICTL register. The source clock for the RTI is OSCCLK.
Table 2-10. RTI Frequency Divide Rates for RTDEC = 0
RTR[6:4] =
RTR[3:0]
0000 (÷1)
000
(OFF)
001
(210)
010
(211)
011
(212)
100
(213)
101
(214)
110
(215)
111
(216)
OFF(1)
210
211
212
213
214
215
216
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Table 2-10. RTI Frequency Divide Rates for RTDEC = 0
RTR[6:4] =
RTR[3:0]
000
(OFF)
001
(210)
010
(211)
011
(212)
100
(213)
101
(214)
110
(215)
111
(216)
0001 (÷2)
OFF
2x210
2x211
2x212
2x213
2x214
2x215
2x216
0010 (÷3)
OFF
3x210
3x211
3x212
3x213
3x214
3x215
3x216
0011 (÷4)
OFF
4x210
4x211
4x212
4x213
4x214
4x215
4x216
0100 (÷5)
OFF
5x210
5x211
5x212
5x213
5x214
5x215
5x216
0101 (÷6)
OFF
6x210
6x211
6x212
6x213
6x214
6x215
6x216
0110 (÷7)
OFF
7x210
7x211
7x212
7x213
7x214
7x215
7x216
0111 (÷8)
OFF
8x210
8x211
8x212
8x213
8x214
8x215
8x216
1000 (÷9)
OFF
9x210
9x211
9x212
9x213
9x214
9x215
9x216
1001 (÷10)
OFF
10x210
10x211
10x212
10x213
10x214
10x215
10x216
1010 (÷11)
OFF
11x210
11x211
11x212
11x213
11x214
11x215
11x216
1011 (÷12)
OFF
12x210
12x211
12x212
12x213
12x214
12x215
12x216
1100 (÷13)
OFF
13x210
13x211
13x212
13x213
13x214
13x215
13x216
1101 (÷14)
OFF
14x210
14x211
14x212
14x213
14x214
14x215
14x216
1110 (÷15)
OFF
15x210
15x211
15x212
15x213
15x214
15x215
15x216
1111 (÷16)
OFF
16x210
16x211
16x212
16x213
16x214
16x215
16x216
1. Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility.
Table 2-11. RTI Frequency Divide Rates for RTDEC=1
RTR[6:4] =
RTR[3:0]
000
(1x103)
001
(2x103)
010
(5x103)
011
(10x103)
100
(20x103)
101
(50x103)
110
(100x103)
111
(200x103)
0000 (÷1)
1x103
2x103
5x103
10x103
20x103
50x103
100x103
200x103
0001 (÷2)
2x103
4x103
10x103
20x103
40x103
100x103
200x103
400x103
0010 (÷3)
3x103
6x103
15x103
30x103
60x103
150x103
300x103
600x103
0011 (÷4)
4x103
8x103
20x103
40x103
80x103
200x103
400x103
800x103
0100 (÷5)
5x103
10x103
25x103
50x103
100x103
250x103
500x103
1x106
0101 (÷6)
6x103
12x103
30x103
60x103
120x103
300x103
600x103
1.2x106
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Table 2-11. RTI Frequency Divide Rates for RTDEC=1
RTR[6:4] =
RTR[3:0]
000
(1x103)
001
(2x103)
010
(5x103)
011
(10x103)
100
(20x103)
101
(50x103)
110
(100x103)
111
(200x103)
0110 (÷7)
7x103
14x103
35x103
70x103
140x103
350x103
700x103
1.4x106
0111 (÷8)
8x103
16x103
40x103
80x103
160x103
400x103
800x103
1.6x106
1000 (÷9)
9x103
18x103
45x103
90x103
180x103
450x103
900x103
1.8x106
1001 (÷10)
10 x103
20x103
50x103
100x103
200x103
500x103
1x106
2x106
1010 (÷11)
11 x103
22x103
55x103
110x103
220x103
550x103
1.1x106
2.2x106
1011 (÷12)
12x103
24x103
60x103
120x103
240x103
600x103
1.2x106
2.4x106
1100 (÷13)
13x103
26x103
65x103
130x103
260x103
650x103
1.3x106
2.6x106
1101 (÷14)
14x103
28x103
70x103
140x103
280x103
700x103
1.4x106
2.8x106
1110 (÷15)
15x103
30x103
75x103
150x103
300x103
750x103
1.5x106
3x106
1111 (÷16)
16x103
32x103
80x103
160x103
320x103
800x103
1.6x106
3.2x106
2.3.2.9
S12XECRG COP Control Register (COPCTL)
This register controls the COP (Computer Operating Properly) watchdog.
Module Base + 0x0008
7
6
WCOP
RSBCK
R
W
Reset1
5
4
3
0
0
0
2
1
0
CR2
CR1
CR0
0
0
0
WRTMASK
0
0
0
0
0
1. Refer to Device User Guide (Section: S12XECRG) for reset values of WCOP, CR2, CR1 and CR0.
= Unimplemented or Reserved
Figure 2-11. S12XECRG COP Control Register (COPCTL)
Read: Anytime
Write:
1. RSBCK: anytime in special modes; write to “1” but not to “0” in all other modes
2. WCOP, CR2, CR1, CR0:
— Anytime in special modes
— Write once in all other modes
– Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.
– Writing WCOP to “0” has no effect, but counts for the “write once” condition.
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The COP time-out period is restarted if one these two conditions is true:
1. Writing a non zero value to CR[2:0] (anytime in special modes, once in all other modes) with
WRTMASK = 0.
or
2. Changing RSBCK bit from “0” to “1”.
Table 2-12. COPCTL Field Descriptions
Field
Description
7
WCOP
Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected
period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during
this window, $55 can be written as often as desired. Once $AA is written after the $55, the time-out logic restarts
and the user must wait until the next window before writing to ARMCOP. Table 2-13 shows the duration of this
window for the seven available COP rates.
0 Normal COP operation
1 Window COP operation
6
RSBCK
COP and RTI Stop in Active BDM Mode Bit
0 Allows the COP and RTI to keep running in Active BDM mode.
1 Stops the COP and RTI counters whenever the part is in Active BDM mode.
5
Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits
WRTMASK while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of
WCOP and CR[2:0].
0 Write of WCOP and CR[2:0] has an effect with this write of COPCTL
1 Write of WCOP and CR[2:0] has no effect with this write of COPCTL.
(Does not count for “write once”.)
2–0
CR[2:0]
COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see Table 2-13). Writing a
nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time-out
causes a system reset. This can be avoided by periodically (before time-out) reinitialize the COP counter via the
ARMCOP register.
While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at
highest time-out period (2 24 cycles) in normal COP mode (Window COP mode disabled):
1) COP is enabled (CR[2:0] is not 000)
2) BDM mode active
3) RSBCK = 0
4) Operation in emulation or special modes
Table 2-13. COP Watchdog Rates(1)
CR2
CR1
CR0
OSCCLK
Cycles to Timeout
0
0
0
COP disabled
0
0
1
2 14
0
1
0
2 16
0
1
1
2 18
1
0
0
2 20
1
0
1
2 22
1
1
0
2 23
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Table 2-13. COP Watchdog Rates(1)
CR2
CR1
OSCCLK
Cycles to Timeout
CR0
1
1
1
2 24
1. OSCCLK cycles are referenced from the previous COP time-out reset
(writing $55/$AA to the ARMCOP register)
2.3.2.10
Reserved Register (FORBYP)
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special
modes can alter the S12XECRG’s functionality.
Module Base + 0x0009
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 2-12. Reserved Register (FORBYP)
Read: Always read $00 except in special modes
Write: Only in special modes
2.3.2.11
Reserved Register (CTCTL)
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special test
modes can alter the S12XECRG’s functionality.
Module Base + 0x000A
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 2-13. Reserved Register (CTCTL)
Read: Always read $00 except in special modes
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Write: Only in special modes
2.3.2.12
S12XECRG COP Timer Arm/Reset Register (ARMCOP)
This register is used to restart the COP time-out period.
Module Base + 0x000B
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Reset
Figure 2-14. S12XECRG ARMCOP Register Diagram
Read: Always reads $00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period
you must write $55 followed by a write of $AA. Other instructions may be executed between these
writes but the sequence ($55, $AA) must be completed prior to COP end of time-out period to
avoid a COP reset. Sequences of $55 writes or sequences of $AA writes are allowed. When the
WCOP bit is set, $55 and $AA writes must be done in the last 25% of the selected time-out period;
writing any value in the first 75% of the selected period will cause a COP reset.
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2.4
Functional Description
2.4.1
Functional Blocks
2.4.1.1
Phase Locked Loop with Internal Filter (IPLL)
The IPLL is used to run the MCU from a different time base than the incoming OSCCLK. Figure 2-15
shows a block diagram of the IPLL.
REFCLK
REFDIV[5:0]
EXTAL
REDUCED
CONSUMPTION
OSCILLATOR
OSCCLK
REFERENCE
PROGRAMMABLE
DIVIDER
XTAL
CLOCK
MONITOR
Supplied by:
FBCLK
LOCK
LOCK
DETECTOR
VDDPLL/VSSPLL
PDET
PHASE
DETECTOR
UP
CPUMP
AND
FILTER
DOWN
VCO
VCOCLK
LOOP
PROGRAMMABLE
DIVIDER
POST
PROGRAMMABLE
DIVIDER
PLLCLK
SYNDIV[5:0]
VDDPLL/VSSPLL
POSTDIV[4:0]
VDD/VSS
Figure 2-15. IPLL Functional Diagram
For increased flexibility, OSCCLK can be divided in a range of 1 to 64 to generate the reference frequency
REFCLK using the REFDIV[5:0] bits. This offers a finer multiplication granularity. Based on the
SYNDIV[5:0] bits the IPLL generates the VCOCLK by multiplying the reference clock by a multiple of
2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2,4,6,8,...
to 62 to generate the PLLCLK.
.
SYNDIV + 1
f PLL = 2 × f OSC × -----------------------------------------------------------------------------[ REFDIV + 1 ] [ 2 × POSTDIV ]
NOTE
Although it is possible to set the dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
If (PLLSEL = 1) then fBUS = fPLL / 2.
IF POSTDIV = $00 the fPLL is identical to fVCO (divide by one)
Several examples of IPLL divider settings are shown in Table 2-14. Shaded rows indicated that these
settings are not recommended. The following rules help to achieve optimum stability and shortest lock
time:
• Use lowest possible fVCO / fREF ratio (SYNDIV value).
• Use highest possible REFCLK frequency fREF.
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Table 2-14. Examples of IPLL Divider Settings
fOSC
REFDIV[5:0]
fREF
4MHz
$01
2MHz
01
$18
100MHz
11
$00
100MHz 50 MHz
8MHz
$03
2MHz
01
$18
100MHz
11
$00
100MHz 50 MHz
4MHz
$00
4MHz
01
$09
80MHz
01
$00
80MHz
40MHz
8MHz
$00
8MHz
10
$04
80MHz
01
$00
80MHz
40MHz
4MHz
$00
4MHz
01
$03
32MHz
00
$01
16MHz
8MHz
4MHz
$01
2MHz
01
$18
100MHz
11
$01
50MHz
25MHz
4MHz
$03
1MHz
00
$18
50MHz
01
$00
50MHz
25MHz
4MHz
$03
1MHz
00
$31
100MHz
11
$01
50MHz
25MHz
2.4.1.1.1
REFFRQ[1:0] SYNDIV[5:0]
fVCO
VCOFRQ[1:0] POSTDIV[4:0]
fPLL
fBUS
IPLL Operation
The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is
divided in a range of 1 to 64 (REFDIV+1) to output the REFCLK. The VCO output clock, (VCOCLK) is
fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2
x (SYNDIV +1)] to output the FBCLK. The VCOCLK is fed to the final programmable divider and is
divided in a range of 1,2,4,6,8,... to 62 (2*POSTDIV) to output the PLLCLK. See Figure 2-15.
The phase detector then compares the FBCLK, with the REFCLK. Correction pulses are generated based
on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the
internal filter capacitor, based on the width and direction of the correction pulse.
The user must select the range of the REFCLK frequency and the range of the VCOCLK frequency to
ensure that the correct IPLL loop bandwidth is set.
The lock detector compares the frequencies of the FBCLK, and the REFCLK. Therefore, the speed of the
lock detector is directly proportional to the reference clock frequency. The circuit determines the lock
condition based on this comparison.
If IPLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and then check
the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously (during
IPLL start-up, usually) or at periodic intervals. In either case, only when the LOCK bit is set, the PLLCLK
can be selected as the source for the system and core clocks. If the IPLL is selected as the source for the
system and core clocks and the LOCK bit is clear, the IPLL has suffered a severe noise hit and the software
must take appropriate action, depending on the application.
• The LOCK bit is a read-only indicator of the locked state of the IPLL.
• The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆Lock, and is cleared
when the VCO frequency is out of a certain tolerance, ∆unl.
• Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling
the LOCK bit.
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2.4.1.2
System Clocks Generator
PLLSEL or SCM
PLLCLK
PHASE
LOCK
LOOP (IIPLL)
STOP
1
SYSCLK
÷2
SCM
EXTAL
1
OSCILLATOR
Core Clock
0
WAIT(RTIWAI),
STOP(PSTP, PRE),
RTI ENABLE
CLOCK PHASE
GENERATOR
Bus Clock
RTI
OSCCLK
0
WAIT(COPWAI),
STOP(PSTP, PCE),
COP ENABLE
XTAL
COP
Clock
Monitor
STOP
Oscillator
Clock
Gating
Condition
= Clock Gate
Figure 2-16. System Clocks Generator
The clock generator creates the clocks used in the MCU (see Figure 2-16). The gating condition placed on
top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the
setting of the respective configuration bits.
The peripheral modules use the Bus Clock. Some peripheral modules also use the Oscillator Clock. If the
MCU enters Self Clock Mode (see Section 2.4.2.2, “Self Clock Mode”) Oscillator clock source is switched
to PLLCLK running at its minimum frequency fSCM. The Bus Clock is used to generate the clock visible
at the ECLK pin. The Core Clock signal is the clock for the CPU. The Core Clock is twice the Bus Clock.
But note that a CPU cycle corresponds to one Bus Clock.
IPLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the IPLL output
clock drives SYSCLK for the main system including the CPU and peripherals. The IPLL cannot be turned
off by clearing the PLLON bit, if the IPLL clock is selected. When PLLSEL is changed, it takes a
maximum of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks
freeze and CPU activity ceases.
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2.4.1.3
Clock Monitor (CM)
If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block
generates a clock monitor fail event. The S12XECRG then asserts self clock mode or generates a system
reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is
detected no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by
the CME control bit.
2.4.1.4
Clock Quality Checker
The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker
provides a more accurate check in addition to the clock monitor.
A clock quality check is triggered by any of the following events:
• Power on reset (POR)
• Low voltage reset (LVR)
• Wake-up from Full Stop Mode (exit full stop)
• Clock Monitor fail indication (CM fail)
A time window of 50000 PLLCLK cycles1 is called check window.
A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that
osc ok immediately terminates the current check window. See Figure 2-17 as an example.
CHECK WINDOW
1
3
2
49999
50000
PLLCLK
1
2
3
4
5
4096
OSCCLK
4095
OSC OK
Figure 2-17. Check Window Example
1. IPLL is running at self clock mode frequency fSCM.
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The Sequence for clock quality check is shown in Figure 2-18.
CM FAIL
CLOCK OK
NO
EXIT FULL STOP
POR
LVR
YES
SCME=1 &
FSTWKP=1
?
NO
NUM = 0
FSTWKP = 0
?
ENTER SCM
YES
CLOCK MONITOR RESET
ENTER SCM
NUM = 50
YES
CHECK WINDOW
SCM
ACTIVE?
NUM = NUM-1
YES
OSC OK
?
NUM = 0
NO
NO
NUM > 0
?
YES
NO
SCME = 1
?
NO
YES
SCM
ACTIVE?
YES
SWITCH TO OSCCLK
NO
EXIT SCM
Figure 2-18. Sequence for Clock Quality Check
NOTE
Remember that in parallel to additional actions caused by Self Clock Mode
or Clock Monitor Reset1 handling the clock quality checker continues to
check the OSCCLK signal.
NOTE
The Clock Quality Checker enables the IPLL and the voltage regulator
(VREG) anytime a clock check has to be performed. An ongoing clock
quality check could also cause a running IPLL (fSCM) and an active VREG
during Pseudo Stop Mode.
1. A Clock Monitor Reset will always set the SCME bit to logical’1’.
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2.4.1.5
Computer Operating Properly Watchdog (COP)
The COP (free running watchdog timer) enables the user to check that a program is running and
sequencing properly. When the COP is being used, software is responsible for keeping the COP from
timing out. If the COP times out it is an indication that the software is no longer being executed in the
intended sequence; thus a system reset is initiated (see Section 2.4.1.5, “Computer Operating Properly
Watchdog (COP)”). The COP runs with a gated OSCCLK. Three control bits in the COPCTL register
allow selection of seven COP time-out periods.
When COP is enabled, the program must write $55 and $AA (in this order) to the ARMCOP register
during the selected time-out period. Once this is done, the COP time-out period is restarted. If the program
fails to do this and the COP times out, the part will reset. Also, if any value other than $55 or $AA is
written, the part is immediately reset.
Windowed COP operation is enabled by setting WCOP in the COPCTL register. In this mode, writes to
the ARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period.
A premature write will immediately reset the part.
If PCE bit is set, the COP will continue to run in Pseudo Stop Mode.
2.4.1.6
Real Time Interrupt (RTI)
The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting
RTIE=1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated
OSCCLK. At the end of the RTI time-out period the RTIF flag is set to one and a new RTI time-out period
starts immediately.
A write to the RTICTL register restarts the RTI time-out period.
If the PRE bit is set, the RTI will continue to run in Pseudo Stop Mode.
2.4.2
2.4.2.1
Operation Modes
Normal Mode
The S12XECRG block behaves as described within this specification in all normal modes.
2.4.2.2
Self Clock Mode
If the external clock frequency is not available due to a failure or due to long crystal start-up time, the Bus
Clock and the Core Clock are derived from the PLLCLK running at self clock mode frequency fSCM; this
mode of operation is called Self Clock Mode. This requires CME = 1 and SCME = 1, which is the default
after reset. If the MCU was clocked by the PLLCLK prior to entering Self Clock Mode, the PLLSEL bit
will be cleared. If the external clock signal has stabilized again, the S12XECRG will automatically select
OSCCLK to be the system clock and return to normal mode. See Section 2.4.1.4, “Clock Quality Checker”
for more information on entering and leaving Self Clock Mode.
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NOTE
In order to detect a potential clock loss the CME bit should always be
enabled (CME = 1).
If CME bit is disabled and the MCU is configured to run on PLLCLK, a loss
of external clock (OSCCLK) will not be detected and will cause the system
clock to drift towards lower frequencies. As soon as the external clock is
available again the system clock ramps up to its IPLL target frequency. If
the MCU is running on external clock any loss of clock will cause the
system to go static.
2.4.3
Low Power Options
This section summarizes the low power options available in the S12XECRG.
2.4.3.1
Run Mode
This is the default mode after reset.
The RTI can be stopped by setting the associated rate select bits to zero.
The COP can be stopped by setting the associated rate select bits to zero.
2.4.3.2
Wait Mode
The WAI instruction puts the MCU in a low power consumption stand-by mode depending on setting of
the individual bits in the CLKSEL register. All individual Wait Mode configuration bits can be superposed.
This provides enhanced granularity in reducing the level of power consumption during Wait Mode.
Table 2-15 lists the individual configuration bits and the parts of the MCU that are affected in Wait Mode.
Table 2-15. MCU Configuration During Wait Mode
PLLWAI
RTIWAI
COPWAI
IPLL
Stopped
—
—
RTI
—
Stopped
—
COP
—
—
Stopped
After executing the WAI instruction the core requests the S12XECRG to switch MCU into Wait Mode.
The S12XECRG then checks whether the PLLWAI bit is asserted. Depending on the configuration the
S12XECRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit and disables
the IPLL.
There are two ways to restart the MCU from Wait Mode:
1. Any reset
2. Any interrupt
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2.4.3.3
Stop Mode
All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE and PSTP bit. The
oscillator is disabled in STOP mode unless the PSTP bit is set. If the PRE or PCE bits are set, the RTI or
COP continues to run in Pseudo Stop Mode. In addition to disabling system and core clocks the
S12XECRG requests other functional units of the MCU (e.g. voltage-regulator) to enter their individual
power saving modes (if available).
If the PLLSEL bit is still set when entering Stop Mode, the S12XECRG will switch the system and core
clocks to OSCCLK by clearing the PLLSEL bit. Then the S12XECRG disables the IPLL, disables the core
clock and finally disables the remaining system clocks.
If Pseudo Stop Mode is entered from Self-Clock Mode the S12XECRG will continue to check the clock
quality until clock check is successful. In this case the IPLL and the voltage regulator (VREG) will remain
enabled. If Full Stop Mode (PSTP = 0) is entered from Self-Clock Mode the ongoing clock quality check
will be stopped. A complete timeout window check will be started when Stop Mode is left again.
There are two ways to restart the MCU from Stop Mode:
1. Any reset
2. Any interrupt
If the MCU is woken-up from Full Stop Mode by an interrupt and the fast wake-up feature is enabled
(FSTWKP=1 and SCME=1), the system will immediately (no clock quality check) resume operation in
Self-Clock Mode (see Section 2.4.1.4, “Clock Quality Checker”). The SCMIF flag will not be set for this
special case. The system will remain in Self-Clock Mode with oscillator disabled until FSTWKP bit is
cleared. The clearing of FSTWKP will start the oscillator and the clock quality check. If the clock quality
check is successful, the S12XECRG will switch all system clocks to oscillator clock. The SCMIF flag will
be set. See application examples in Figure 2-19 and Figure 2-20.
Because the IPLL has been powered-down during Stop Mode the PLLSEL bit is cleared and the MCU runs
on OSCCLK after leaving Stop-Mode. The software must manually set the PLLSEL bit again, in order to
switch system and core clocks to the PLLCLK.
NOTE
In Full Stop Mode or Self-Clock Mode caused by the fast wake-up feature
the clock monitor and the oscillator are disabled.
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CPU resumes program execution immediately
Instruction
STOP
STOP
FSTWKP=1 SCME=1
STOP
Interrupt
IRQ service
IRQ service
IRQ service
Interrupt
Interrupt
Power Saving
Oscillator Clock
Oscillator Disabled
PLL Clock
Core Clock
Self-Clock Mode
Figure 2-19. Fast Wake-up from Full Stop Mode: Example 1
.
CPU resumes program execution immediately
Instruction
Frequent Uncritical
Frequent Critical
Instructions
Instructions Possible
IRQ Service
STOP
FSTWKP=1 SCME=1
IRQ Interrupt FSTWKP=0 SCMIE=1
SCM Interrupt
Clock Quality Check
Oscillator Clock
Oscillator Disabled Osc Startup
PLL Clock
Self-Clock Mode
Core Clock
Figure 2-20. Fast Wake-up from Full Stop Mode: Example 2
2.5
Resets
All reset sources are listed in Table 2-16. Refer to MCU specification for related vector addresses and
priorities.
Table 2-16. Reset Summary
Reset Source
Local Enable
Power on Reset
None
Low Voltage Reset
None
External Reset
None
Illegal Address Reset
None
Clock Monitor Reset
PLLCTL (CME=1, SCME=0)
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Table 2-16. Reset Summary
2.5.1
Reset Source
Local Enable
COP Watchdog Reset
COPCTL (CR[2:0] nonzero)
Description of Reset Operation
The reset sequence is initiated by any of the following events:
• Low level is detected at the RESET pin (External Reset).
• Power on is detected.
• Low voltage is detected.
• Illegal Address Reset is detected (see S12XMMC Block Guide for details).
• COP watchdog times out.
• Clock monitor failure is detected and Self-Clock Mode was disabled (SCME=0).
Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles
(see Figure 2-21). Since entry into reset is asynchronous it does not require a running SYSCLK. However,
the internal reset circuit of the S12XECRG cannot sequence out of current reset condition without a
running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional
SYSCLK cycles depending on the internal synchronization latency. After 128+n SYSCLK cycles the
RESET pin is released. The reset generator of the S12XECRG waits for additional 64 SYSCLK cycles and
then samples the RESET pin to determine the originating source. Table 2-17 shows which vector will be
fetched.
Table 2-17. Reset Vector Selection
Sampled RESET Pin
Clock Monitor
COP
(64 cycles after release) Reset Pending Reset Pending
Vector Fetch
1
0
0
POR / LVR /
Illegal Address Reset/
External Reset
1
1
X
Clock Monitor Reset
1
0
1
COP Reset
0
X
X
POR / LVR /
Illegal Address Reset/ External Reset
with rise of RESET pin
NOTE
External circuitry connected to the RESET pin should be able to raise the
signal to a valid logic one within 64 SYSCLK cycles after the low drive is
released by the MCU. If this requirement is not adhered to the reset source
will always be recognized as “External Reset” even if the reset was initially
caused by an other reset source.
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The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long
reset sequence. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles
(External Reset), the internal reset remains asserted longer.
Figure 2-21. RESET Timing
RESET
)(
)(
ICRG drives RESET pin low
)
)
SYSCLK
(
128+n cycles
possibly
SYSCLK
not
running
2.5.1.1
RESET pin
released
)
(
(
64 cycles
with n being
min 3 / max 6
cycles depending
on internal
synchronization
delay
possibly
RESET
driven low
externally
Clock Monitor Reset
The S12XECRG generates a Clock Monitor Reset in case all of the following conditions are true:
• Clock monitor is enabled (CME = 1)
• Loss of clock is detected
• Self-Clock Mode is disabled (SCME = 0).
The reset event asynchronously forces the configuration registers to their default settings. In detail the
CME and the SCME are reset to logical ‘1’ (which changes the state of the SCME bit. As a consequence
the S12XECRG immediately enters Self Clock Mode and starts its internal reset sequence. In parallel the
clock quality check starts. As soon as clock quality check indicates a valid Oscillator Clock the
S12XECRG switches to OSCCLK and leaves Self Clock Mode. Since the clock quality checker is running
in parallel to the reset generator, the S12XECRG may leave Self Clock Mode while still completing the
internal reset sequence.
2.5.1.2
Computer Operating Properly Watchdog (COP) Reset
When COP is enabled, the S12XECRG expects sequential write of $55 and $AA (in this order) to the
ARMCOP register during the selected time-out period. Once this is done, the COP time-out period restarts.
If the program fails to do this the S12XECRG will generate a reset.
2.5.1.3
Power On Reset, Low Voltage Reset
The on-chip voltage regulator detects when VDD to the MCU has reached a certain level and asserts power
on reset or low voltage reset or both. As soon as a power on reset or low voltage reset is triggered the
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S12XECRG performs a quality check on the incoming clock signal. As soon as clock quality check
indicates a valid Oscillator Clock signal the reset sequence starts using the Oscillator clock. If after 50
check windows the clock quality check indicated a non-valid Oscillator Clock the reset sequence starts
using Self-Clock Mode.
Figure 2-22 and Figure 2-23 show the power-up sequence for cases when the RESET pin is tied to VDD
and when the RESET pin is held low.
Clock Quality Check
(no Self-Clock Mode)
RESET
)(
Internal POR
)(
128 SYSCLK
Internal RESET
64 SYSCLK
)(
Figure 2-22. RESET Pin Tied to VDD (by a Pull-up Resistor)
Clock Quality Check
(no Self Clock Mode)
)(
RESET
Internal POR
)(
128 SYSCLK
Internal RESET
)(
64 SYSCLK
Figure 2-23. RESET Pin Held Low Externally
2.6
Interrupts
The interrupts/reset vectors requested by the S12XECRG are listed in Table 2-18. Refer to MCU
specification for related vector addresses and priorities.
Table 2-18. S12XECRG Interrupt Vectors
Interrupt Source
CCR
Mask
Local Enable
Real time interrupt
I bit
CRGINT (RTIE)
LOCK interrupt
I bit
CRGINT (LOCKIE)
SCM interrupt
I bit
CRGINT (SCMIE)
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2.6.1
2.6.1.1
Description of Interrupt Operation
Real Time Interrupt
The S12XECRG generates a real time interrupt when the selected interrupt time period elapses. RTI
interrupts are locally disabled by setting the RTIE bit to zero. The real time interrupt flag (RTIF) is set to1
when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit.
The RTI continues to run during Pseudo Stop Mode if the PRE bit is set to 1. This feature can be used for
periodic wakeup from Pseudo Stop if the RTI interrupt is enabled.
2.6.1.2
IPLL Lock Interrupt
The S12XECRG generates a IPLL Lock interrupt when the LOCK condition of the IPLL has changed,
either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting
the LOCKIE bit to zero. The IPLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has
changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
2.6.1.3
Self Clock Mode Interrupt
The S12XECRG generates a Self Clock Mode interrupt when the SCM condition of the system has
changed, either entered or exited Self Clock Mode. SCM conditions are caused by a failing clock quality
check after power on reset (POR) or low voltage reset (LVR) or recovery from Full Stop Mode (PSTP =
0) or Clock Monitor failure. For details on the clock quality check refer to Section 2.4.1.4, “Clock Quality
Checker”. If the clock monitor is enabled (CME = 1) a loss of external clock will also cause a SCM
condition (SCME = 1).
SCM interrupts are locally disabled by setting the SCMIE bit to zero. The SCM interrupt flag (SCMIF) is
set to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.
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Voltage Regulator (S12VREGL3V3V1)
Table 3-1. Revision History Table
Rev. No.
Date
(Item No.) (Submitted By)
Sections
Affected
Substantial Change(s)
V01.02
09 Sep 2005
Updates for API external access and LVR flags.
V01.03
23 Sep 2005
VAE reset value is 1.
V01.04
08 Jun 2007
Added temperature sensor to customer information
3.1
Introduction
Module VREG_3V3 is a tri output voltage regulator that provides two separate 1.84V (typical) supplies
differing in the amount of current that can be sourced and a 2.82V (typical) supply. The regulator input
voltage range is from 3.3V up to 5V (typical).
3.1.1
Features
Module VREG_3V3 includes these distinctive features:
• Three parallel, linear voltage regulators with bandgap reference
• Low-voltage detect (LVD) with low-voltage interrupt (LVI)
• Power-on reset (POR)
• Low-voltage reset (LVR)
• High Temperature Detect (HTD) with High Temperature Interrupt (HTI)
• Autonomous periodical interrupt (API)
3.1.2
Modes of Operation
There are three modes VREG_3V3 can operate in:
1. Full performance mode (FPM) (MCU is not in stop mode)
The regulator is active, providing the nominal supply voltages with full current sourcing capability.
Features LVD (low-voltage detect), LVR (low-voltage reset), and POR (power-on reset) and HTD
(High Temperature Detect) are available. The API is available.
2. Reduced power mode (RPM) (MCU is in stop mode)
The purpose is to reduce power consumption of the device. The output voltage may degrade to a
lower value than in full performance mode, additionally the current sourcing capability is
substantially reduced. Only the POR is available in this mode, LVD, LVR and HTD are disabled.
The API is available.
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3. Shutdown mode
Controlled by VREGEN (see device level specification for connectivity of VREGEN).
This mode is characterized by minimum power consumption. The regulator outputs are in a highimpedance state, only the POR feature is available, LVD, LVR and HTD are disabled. The API
internal RC oscillator clock is not available.
This mode must be used to disable the chip internal regulator VREG_3V3, i.e., to bypass the
VREG_3V3 to use external supplies.
3.1.3
Block Diagram
Figure 3-1 shows the function principle of VREG_3V3 by means of a block diagram. The regulator core
REG consists of three parallel subblocks, REG1, REG2 and REG3, providing three independent output
voltages.
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Chapter 3 Voltage Regulator (S12VREGL3V3V1)
Figure 3-1. VREG_3V3 Block Diagram
VBG
VDDPLL
REG3
VSSPLL
REG
VDDR
VDDA
VDDF
REG2
VSSA
VDD
REG1
VSS
LVD
LVR
LVR
POR
POR
VDDX
C
HTD
VREGEN
CTRL
API
Rate
Select
HTI
LVI
API
API
Bus Clock
LVD: Low Voltage Detect
REG: Regulator Core
LVR: Low Voltage Reset
CTRL: Regulator Control
POR: Power-on Reset
API: Auto. Periodical Interrupt
HTD: High Temperature Detect
PIN
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3.2
External Signal Description
Due to the nature of VREG_3V3 being a voltage regulator providing the chip internal power supply
voltages, most signals are power supply signals connected to pads.
Table 3-2 shows all signals of VREG_3V3 associated with pins.
Table 3-2. Signal Properties
Name
Function
Reset State
Pull Up
VDDR
Power input (positive supply)
—
—
VDDA
Quiet input (positive supply)
—
—
VSSA
Quiet input (ground)
—
—
VDDX
Power input (positive supply)
—
—
VDD
Primary output (positive supply)
—
—
VSS
Primary output (ground)
—
—
Secondary output (positive supply)
—
—
VDDPLL
Tertiary output (positive supply)
—
—
VSSPLL
Tertiary output (ground)
—
—
Optional Regulator Enable
—
—
VREG Autonomous Periodical
Interrupt output
—
—
VDDF
VREGEN (optional)
VREG_API
(optional)
NOTE
Check device level specification for connectivity of the signals.
3.2.1
VDDR — Regulator Power Input Pins
Signal VDDR is the power input of VREG_3V3. All currents sourced into the regulator loads flow through
this pin. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDR and VSSR
(if VSSR is not available VSS) can smooth ripple on VDDR.
For entering Shutdown Mode, pin VDDR should also be tied to ground on devices without VREGEN pin.
3.2.2
VDDA, VSSA — Regulator Reference Supply Pins
Signals VDDA/VSSA, which are supposed to be relatively quiet, are used to supply the analog parts of the
regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling
capacitor (100 nF...220 nF, X7R ceramic) between VDDA and VSSA can further improve the quality of
this supply.
3.2.3
VDD, VSS — Regulator Output1 (Core Logic) Pins
Signals VDD/VSS are the primary outputs of VREG_3V3 that provide the power supply for the core logic.
These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R ceramic).
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In Shutdown Mode an external supply driving VDD/VSS can replace the voltage regulator.
3.2.4
VDDF — Regulator Output2 (NVM Logic) Pins
Signals VDDF/VSS are the secondary outputs of VREG_3V3 that provide the power supply for the NVM
logic. These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R
ceramic).
In Shutdown Mode an external supply driving VDDF/VSS can replace the voltage regulator.
3.2.5
VDDPLL, VSSPLL — Regulator Output3 (PLL) Pins
Signals VDDPLL/VSSPLL are the secondary outputs of VREG_3V3 that provide the power supply for
the PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors
(100 nF...220 nF, X7R ceramic).
In Shutdown Mode, an external supply driving VDDPLL/VSSPLL can replace the voltage regulator.
3.2.6
VDDX — Power Input Pin
Signals VDDX/VSS are monitored by VREG_3V3 with the LVR feature.
3.2.7
VREGEN — Optional Regulator Enable Pin
This optional signal is used to shutdown VREG_3V3. In that case, VDD/VSS and VDDPLL/VSSPLL
must be provided externally. Shutdown mode is entered with VREGEN being low. If VREGEN is high,
the VREG_3V3 is either in Full Performance Mode or in Reduced Power Mode.
For the connectivity of VREGEN, see device specification.
NOTE
Switching from FPM or RPM to shutdown of VREG_3V3 and vice versa
is not supported while MCU is powered.
3.2.8
VREG_API — Optional Autonomous Periodical Interrupt Output Pin
This pin provides the signal selected via APIEA if system is set accordingly. See 3.3.2.3, “Autonomous
Periodical Interrupt Control Register (VREGAPICL) and 3.4.8, “Autonomous Periodical Interrupt (API)
for details.
For the connectivity of VREG_API, see device specification.
3.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in VREG_3V3.
If enabled in the system, the VREG_3V3 will abort all read and write accesses to reserved registers within
it’s memory slice. See device level specification for details.
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3.3.1
Module Memory Map
A summary of the registers associated with the VREG_3V3 sub-block is shown in Table 3-3. Detailed
descriptions of the registers and bits are given in the subsections that follow
Address
Name
Bit 7
0
6
0
5
4
3
0
2
HTDS
VSEL
VAE
HTEN
0
0
0
0
LVDS
0
0
APIFES
APIEA
APIFE
1
Bit 0
HTIE
HTIF
LVIE
LVIF
APIE
APIF
0
0
0x02F0
R
VREGHTCL
W
0x02F1
VREGCTRL
0x02F2
VREGAPIC R
L
W
APICLK
0x02F3
VREGAPIT R
R
W
APITR5
APITR4
APITR3
APITR2
APITR1
APITR0
0x02F4
VREGAPIR R
H
W
APIR15
APIR14
APIR13
APIR12
APIR11
APIR10
APIR9
APIR8
0x02F5
VREGAPIR R
L
W
APIR7
APIR6
APIR5
APIR4
APIR3
APIR2
APIR1
APIR0
0
0
0
0
0
0
0
0
0
0
0
HTTR3
HTTR2
HTTR1
HTTR0
R
W
0x02F6
Reserved
06
R
W
0x02F7
VREGHTTR
R
W
HTOEN
Table 3-3. Register Summary
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3.3.2
Register Descriptions
This section describes all the VREG_3V3 registers and their individual bits.
3.3.2.1
HT Control Register (VREGHTCL)
0x02F0
R
7
6
0
0
W
Reset
0
0
5
4
3
VSEL
VAE
HTEN
0
1
0
2
1
0
HTIE
HTIF
0
0
HTDS
0
= Unimplemented or Reserved
3.3.2.2
Control Register (VREGCTRL)
Table 3-4. VREGHTCL Field Descriptions
Field
7, 6
Reserved
5
VSEL
4
VAE
Description
These reserved bits are used for test purposes and writable only in special modes.
They must remain clear for correct temperature sensor operation.
Voltage Access Select Bit — If set, the bandgap reference voltage VBG can be accessed internally (i.e.
multiplexed to an internal Analog to Digital Converter channel). . The internal access must be enabled by bit
VAE. See device level specification for connectivity.
0 An internal voltage can be accessed internally if VAE is set.
1 Bandgap reference voltage VBG can be accessed internally if VAE is set.
Voltage Access Enable Bit — If set, the voltage selected by bit VSEL can be accessed internally (i.e.
multiplexed to an internal Analog to Digital Converter channel). See device level specification for connectivity.
0 Voltage selected by VSEL can not be accessed internally (i.e. External analog input is connected to Analog
to Digital Converter channel).
1 Voltage selected by VSEL can be accessed internally.
3
HTEN
High Temperature Enable Bit — If set the temperature sense is enabled.
0 The temperature sense is disabled.
1 The temperature sense is enabled.
2
HTDS
High Temperature Detect Status Bit —
0 Temperature TDIE is below level THTID or RPM or Shutdown Mode.
1 Temperature TDIE is above level THTIA and FPM.
1
HTIE
High Temperature Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever HTIF is set.
0
HTIF
High Temperature Interrupt Flag —
0 No change in HTDS bit.
1 HTDS bit has changed.
Note: On entering the reduced power mode the HTIF is not cleared by the VREG.
The VREGCTRL register allows the configuration of the VREG_3V3 low-voltage detect features.
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0x02F1
R
7
6
5
4
3
2
0
0
0
0
0
LVDS
0
0
0
0
0
W
Reset
0
1
0
LVIE
LVIF
0
0
= Unimplemented or Reserved
Figure 3-2. Control Register (VREGCTRL)
Table 3-5. VREGCTRL Field Descriptions
Field
Description
2
LVDS
Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect.
0 Input voltage VDDA is above level VLVID or RPM or shutdown mode.
1 Input voltage VDDA is below level VLVIA and FPM.
1
LVIE
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
0
LVIF
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
Note: On entering the Reduced Power Mode the LVIF is not cleared by the VREG_3V3.
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3.3.2.3
Autonomous Periodical Interrupt Control Register (VREGAPICL)
The VREGAPICL register allows the configuration of the VREG_3V3 autonomous periodical interrupt
features.
0x02F2
7
R
W
Reset
APICLK
0
6
5
0
0
0
0
4
3
2
1
0
APIES
APIEA
APIFE
APIE
APIF
0
0
0
0
0
= Unimplemented or Reserved
Figure 3-3. Autonomous Periodical Interrupt Control Register (VREGAPICL)
Table 3-6. VREGAPICL Field Descriptions
Field
7
APICLK
Description
Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source for the API. Writable only if
APIFE = 0; APICLK cannot be changed if APIFE is set by the same write operation.
0 Autonomous periodical interrupt clock used as source.
1 Bus clock used as source.
4
APIES
Autonomous Periodical Interrupt External Select Bit — Selects the waveform at the external pin.If set, at the
external pin a clock is visible with 2 times the selected API Period (Table 3-10). If not set, at the external pin will
be a high pulse at the end of every selected period with the size of half of the min period (Table 3-10). See device
level specification for connectivity.
0 At the external periodic high pulses are visible, if APIEA and APIFE is set.
1 At the external pin a clock is visible, if APIEA and APIFE is set.
3
APIEA
Autonomous Periodical Interrupt External Access Enable Bit — If set, the waveform selected by bit APIES
can be accessed externally. See device level specification for connectivity.
0 Waveform selected by APIES can not be accessed externally.
1 Waveform selected by APIES can be accessed externally, if APIFE is set.
2
APIFE
Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer
when set.
0 Autonomous periodical interrupt is disabled.
1 Autonomous periodical interrupt is enabled and timer starts running.
1
APIE
Autonomous Periodical Interrupt Enable Bit
0 API interrupt request is disabled.
1 API interrupt will be requested whenever APIF is set.
0
APIF
Autonomous Periodical Interrupt Flag — APIF is set to 1 when the in the API configured time has elapsed.
This flag can only be cleared by writing a 1 to it. Clearing of the flag has precedence over setting.
Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request.
0 API timeout has not yet occurred.
1 API timeout has occurred.
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3.3.2.4
Autonomous Periodical Interrupt Trimming Register (VREGAPITR)
The VREGAPITR register allows to trim the API timeout period.
0x02F3
7
R
W
Reset
6
5
4
3
2
APITR5
APITR4
APITR3
APITR2
APITR1
APITR0
01
01
01
01
01
01
1
0
0
0
0
0
1. Reset value is either 0 or preset by factory. See Section 1 (Device Overview) for details.
= Unimplemented or Reserved
Figure 3-4. Autonomous Periodical Interrupt Trimming Register (VREGAPITR)
Table 3-7. VREGAPITR Field Descriptions
Field
7–2
APITR[5:0]
Description
Autonomous Periodical Interrupt Period Trimming Bits — See Table 3-8 for trimming effects.
Table 3-8. Trimming Effect of APIT
Bit
Trimming Effect
APITR[5]
Increases period
APITR[4]
Decreases period less than APITR[5] increased it
APITR[3]
Decreases period less than APITR[4]
APITR[2]
Decreases period less than APITR[3]
APITR[1]
Decreases period less than APITR[2]
APITR[0]
Decreases period less than APITR[1]
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3.3.2.5
Autonomous Periodical Interrupt Rate High and Low Register
(VREGAPIRH / VREGAPIRL)
The VREGAPIRH and VREGAPIRL register allows the configuration of the VREG_3V3 autonomous
periodical interrupt rate.
0x02F4
R
W
Reset
7
6
5
4
3
2
1
0
APIR15
APIR14
APIR13
APIR12
APIR11
APIR10
APIR9
APIR8
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 3-5. Autonomous Periodical Interrupt Rate High Register (VREGAPIRH)
0x02F5
R
W
Reset
7
6
5
4
3
2
1
0
APIR7
APIR6
APIR5
APIR4
APIR3
APIR2
APIR1
APIR0
0
0
0
0
0
0
0
0
Figure 3-6. Autonomous Periodical Interrupt Rate Low Register (VREGAPIRL)
Table 3-9. VREGAPIRH / VREGAPIRL Field Descriptions
Field
Description
15-0
APIR[15:0]
Autonomous Periodical Interrupt Rate Bits — These bits define the timeout period of the API. See Table 310 for details of the effect of the autonomous periodical interrupt rate bits. Writable only if APIFE = 0 of
VREGAPICL register.
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Chapter 3 Voltage Regulator (S12VREGL3V3V1)
Table 3-10. Selectable Autonomous Periodical Interrupt Periods
APICLK
APIR[15:0]
Selected Period
0
0000
0.2 ms(1)
0
0001
0.4 ms1
0
0002
0.6 ms1
0
0003
0.8 ms1
0
0004
1.0 ms1
0
0005
1.2 ms1
0
.....
0
FFFD
13106.8 ms1
0
FFFE
13107.0 ms1
0
FFFF
13107.2 ms1
1
0000
2 * bus clock period
1
0001
4 * bus clock period
1
0002
6 * bus clock period
1
0003
8 * bus clock period
1
0004
10 * bus clock period
1
0005
12 * bus clock period
1
.....
.....
1
FFFD
131068 * bus clock period
1
FFFE
131070 * bus clock period
.....
1
FFFF
131072 * bus clock period
1. When trimmed within specified accuracy. See electrical specifications for details.
The period can be calculated as follows depending of APICLK:
Period = 2*(APIR[15:0] + 1) * 0.1 ms or period = 2*(APIR[15:0] + 1) * bus clock period
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Chapter 3 Voltage Regulator (S12VREGL3V3V1)
3.3.2.6
Reserved 06
The Reserved 06 is reserved for test purposes.
0x02F6
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 3-7. Reserved 06
3.3.2.7
HTTrimming Register (VREGHTTR)
The VREGHTTR register allows to trim the VREGL3V3 temperature sense.
Fiption
0x02F7
7
R
W
Reset
HTOEN
0
6
5
4
0
0
0
0
0
0
3
2
1
0
HTTR3
HTTR2
HTTR1
HTTR0
01
01
01
01
1. Reset value is either 0 or preset by factory. See Section 1 (Device Overview) for details.
= Unimplemented or Reserved
Figure 3-8. VREGHTTR
Table 3-11. VREGHTTR field descriptions
Field
7
HTOEN
3–0
HTTR[3:0]
Description
High Temperature Offeset Enable Bit — 01
High Temperature Trimming Bits — See Table 3-12 for trimming effects.
Table 3-12. Trimming Effect
Bit
Trimming Effect
HTTR[3]
Increases VHT twice of HTTR[2]
HTTR[2]
Increases VHT twice of HTTR[1]
HTTR[1]
Increases VHT twice of HTTR[0]
HTTR[0]
Increases VHT (to compensate Temperature Offset)
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Chapter 3 Voltage Regulator (S12VREGL3V3V1)
3.4
3.4.1
Functional Description
General
Module VREG_3V3 is a voltage regulator, as depicted in Figure 3-1. The regulator functional elements
are the regulator core (REG), a low-voltage detect module (LVD), a control block (CTRL), a power-on
reset module (POR), and a low-voltage reset module (LVR).
3.4.2
Regulator Core (REG)
Respectively its regulator core has three parallel, independent regulation loops (REG1,REG2 and REG3).
REG1 and REG3 differ only in the amount of current that can be delivered.
The regulators are linear regulator with a bandgap reference when operated in Full Performance Mode.
They act as a voltage clamp in Reduced Power Mode. All load currents flow from input VDDR to VSS or
VSSPLL. The reference circuits are supplied by VDDA and VSSA.
3.4.2.1
Full Performance Mode
In Full Performance Mode, the output voltage is compared with a reference voltage by an operational
amplifier. The amplified input voltage difference drives the gate of an output transistor.
3.4.2.2
Reduced Power Mode
In Reduced Power Mode, the gate of the output transistor is connected directly to a reference voltage to
reduce power consumption. Mode switching from reduced power to full performance requires a transition
time of tvup, if the voltage regulator is enabled.
3.4.3
Low-Voltage Detect (LVD)
Subblock LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input
voltage (VDDA–VSSA) and continuously updates the status flag LVDS. Interrupt flag LVIF is set whenever
status flag LVDS changes its value. The LVD is available in FPM and is inactive in Reduced Power Mode
or Shutdown Mode.
3.4.4
Power-On Reset (POR)
This functional block monitors VDD. If VDD is below VPORD, POR is asserted; if VDD exceeds VPORD,
the POR is deasserted. POR asserted forces the MCU into Reset. POR Deasserted will trigger the poweron sequence.
3.4.5
Low-Voltage Reset (LVR)
Block LVR monitors the supplies VDD, VDDX and VDDF. If one (or more) drops below it’s
corresponding assertion level, signal LVR asserts; if all VDD,VDDX and VDDF supplies are above their
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Chapter 3 Voltage Regulator (S12VREGL3V3V1)
corresponding deassertion levels, signal LVR deasserts. The LVR function is available only in Full
Performance Mode.
3.4.6
HTD - High Temperature Detect
Subblock HTD is responsible for generating the high temperature interrupt (HTI). HTD monitors the die
temperature TDIE and continuously updates the status flag HTDS.
Interrupt flag HTIF is set whenever status flag HTDS changes its value.
The HTD is available in FPM and is inactive in Reduced Power Mode and Shutdown Mode.
The HT Trimming bits HTTR[3:0] can be set so that the temperature offset is zero, if accurate temperature
measurement is desired.
See Table 22-12 for the trimming effect of APITR.
3.4.7
Regulator Control (CTRL)
This part contains the register block of VREG_3V3 and further digital functionality needed to control the
operating modes. CTRL also represents the interface to the digital core logic.
3.4.8
Autonomous Periodical Interrupt (API)
Subblock API can generate periodical interrupts independent of the clock source of the MCU. To enable
the timer, the bit APIFE needs to be set.
The API timer is either clocked by a trimmable internal RC oscillator or the bus clock. Timer operation
will freeze when MCU clock source is selected and bus clock is turned off. See CRG specification for
details. The clock source can be selected with bit APICLK. APICLK can only be written when APIFE is
not set.
The APIR[15:0] bits determine the interrupt period. APIR[15:0] can only be written when APIFE is
cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[15:0] bits. When
the configured time has elapsed, the flag APIF is set. An interrupt, indicated by flag APIF = 1, is triggered
if interrupt enable bit APIE = 1. The timer is started automatically again after it has set APIF.
The procedure to change APICLK or APIR[15:0] is first to clear APIFE, then write to APICLK or
APIR[15:0], and afterwards set APIFE.
The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency
is desired.
See Table 3-8 for the trimming effect of APITR.
NOTE
The first period after enabling the counter by APIFE might be reduced by
API start up delay tsdel. The API internal RC oscillator clock is not available
if VREG_3V3 is in Shutdown Mode.
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Chapter 3 Voltage Regulator (S12VREGL3V3V1)
It is possible to generate with the API a waveform at an external pin by enabling the API by setting APIFE
and enabling the external access with setting APIEA. By setting APIES the waveform can be selected. If
APIES is set, then at the external pin a clock is visible with 2 times the selected API Period (Table 3-10).
If APIES is not set, then at the external pin will be a high pulse at the end of every selected period with the
size of half of the min period (Table 3-10). See device level specification for connectivity.
3.4.9
Resets
This section describes how VREG_3V3 controls the reset of the MCU.The reset values of registers and
signals are provided in Section 3.3, “Memory Map and Register Definition”. Possible reset sources are
listed in Table 3-13.
Table 3-13. Reset Sources
3.4.10
3.4.10.1
Reset Source
Local Enable
Power-on reset
Always active
Low-voltage reset
Available only in Full Performance Mode
Description of Reset Operation
Power-On Reset (POR)
During chip power-up the digital core may not work if its supply voltage VDD is below the POR
deassertion level (VPORD). Therefore, signal POR, which forces the other blocks of the device into reset,
is kept high until VDD exceeds VPORD. The MCU will run the start-up sequence after POR deassertion.
The power-on reset is active in all operation modes of VREG_3V3.
3.4.10.2
Low-Voltage Reset (LVR)
For details on low-voltage reset, see Section 3.4.5, “Low-Voltage Reset (LVR)”.
3.4.11
Interrupts
This section describes all interrupts originated by VREG_3V3.
The interrupt vectors requested by VREG_3V3 are listed in Table 3-14. Vector addresses and interrupt
priorities are defined at MCU level.
Table 3-14. Interrupt Vectors
Interrupt Source
Local Enable
Low-voltage interrupt (LVI)
LVIE = 1; available only in Full Performance
Mode
High Temperature Interrupt (HTI)
HTIE=1;
available only in Full Performance Mode
Autonomous periodical interrupt (API)
APIE = 1
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Chapter 3 Voltage Regulator (S12VREGL3V3V1)
3.4.11.1
Low-Voltage Interrupt (LVI)
In FPM, VREG_3V3 monitors the input voltage VDDA. Whenever VDDA drops below level VLVIA, the
status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when VDDA rises above level VLVID. An
interrupt, indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable
bit LVIE = 1.
NOTE
On entering the Reduced Power Mode, the LVIF is not cleared by the
VREG_3V3.
3.4.11.2
HTI - High Temperature Interrupt
In FPM VREGL3V3 monitors the die temperature TDIE. Whenever TDIE exceeds level THTIA the status
bit HTDS is set to 1. Vice versa, HTDS is reset to 0 when TDIE get below level THTID. An interrupt,
indicated by flag HTIF=1, is triggered by any change of the status bit HTDS if interrupt enable bit HTIE=1.
NOTE
On entering the Reduced Power Mode the HTIF is not cleared by the
VREGL3V3.
3.4.11.3
Autonomous Periodical Interrupt (API)
As soon as the configured timeout period of the API has elapsed, the APIF bit is set. An interrupt, indicated
by flag APIF = 1, is triggered if interrupt enable bit APIE = 1.
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Chapter 4
384 KByte Flash Module (S12XFTM384K2V1)
Table 4-1. Revision History
Revision
Number
Revision
Date
V01.10
29 Nov 2007
V01.11
19 Dec 2007
Sections
Affected
- Cleanup
4.4.2/4-167
4.4.2/4-167
4.3.1/4-136
V01.12
25 Sep 2009
4.1/4-131
4.3.2.1/4-143
4.4.2.4/4-170
4.4.2.7/4-173
4.4.2.12/4-177
4.4.2.12/4-177
4.4.2.12/4-177
4.4.2.20/4-186
4.3.2/4-141
4.3.2.1/4-143
4.4.1.2/4-162
4.6/4-192
4.1
Description of Changes
- Updated Command Error Handling tables based on parent-child relationship
with FTM512K3
- Corrected Error Handling table for Full Partition D-Flash, Partition D-Flash,
and EEPROM Emulation Query commands
- Corrected P-Flash IFR Accessibility table
- Clarify single bit fault correction for P-Flash phrase
- Expand FDIV vs OSCCLK Frequency table
- Add statement concerning code runaway when executing Read Once
command from Flash block containing associated fields
- Add statement concerning code runaway when executing Program Once
command from Flash block containing associated fields
- Add statement concerning code runaway when executing Verify Backdoor
Access Key command from Flash block containing associated fields
- Relate Key 0 to associated Backdoor Comparison Key address
- Change “power down reset” to “reset”
- Add ACCERR condition for Disable EEPROM Emulation command
The following changes were made to clarify module behavior related to Flash
register access during reset sequence and while Flash commands are active:
- Add caution concerning register writes while command is active
- Writes to FCLKDIV are allowed during reset sequence while CCIF is clear
- Add caution concerning register writes while command is active
- Writes to FCCOBIX, FCCOBHI, FCCOBLO registers are ignored during
reset sequence
Introduction
The FTM384K2 module implements the following:
• 384 Kbytes of P-Flash (Program Flash) memory, consisting of 2 physical Flash blocks, intended
primarily for nonvolatile code storage
• 32 Kbytes of D-Flash (Data Flash) memory, consisting of 1 physical Flash block, that can be used
as nonvolatile storage to support the built-in hardware scheme for emulated EEPROM, as basic
Flash memory primarily intended for nonvolatile data storage, or as a combination of both
• 4 Kbytes of buffer RAM, consisting of 1 physical RAM block, that can be used as emulated
EEPROM using a built-in hardware scheme, as basic RAM, or as a combination of both
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The Flash memory is ideal for single-supply applications allowing for field reprogramming without
requiring external high voltage sources for program or erase operations. The Flash module includes a
memory controller that executes commands to modify Flash memory contents or configure module
resources for emulated EEPROM operation. The user interface to the memory controller consists of the
indexed Flash Common Command Object (FCCOB) register which is written to with the command, global
address, data, and any required command parameters. The memory controller must complete the execution
of a command before the FCCOB register can be written to with a new command.
CAUTION
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
The RAM and Flash memory may be read as bytes, aligned words, or misaligned words. Read access time
is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. For Flash memory,
an erased bit reads 1 and a programmed bit reads 0.
It is not possible to read from a Flash block while any command is executing on that specific Flash block.
It is possible to read from a Flash block while a command is executing on a different Flash block.
Both P-Flash and D-Flash memories are implemented with Error Correction Codes (ECC) that can resolve
single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that
programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read
by phrase, only one single bit fault in the phrase containing the byte or word accessed will be corrected.
4.1.1
Glossary
Buffer RAM — The buffer RAM constitutes the volatile memory store required for EEE. Memory space
in the buffer RAM not required for EEE can be partitioned to provide volatile memory space for
applications.
Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including
program and erase) on the Flash memory.
D-Flash Memory — The D-Flash memory constitutes the nonvolatile memory store required for EEE.
Memory space in the D-Flash memory not required for EEE can be partitioned to provide nonvolatile
memory space for applications.
D-Flash Sector — The D-Flash sector is the smallest portion of the D-Flash memory that can be erased.
The D-Flash sector consists of four 64 byte rows for a total of 256 bytes.
EEE (Emulated EEPROM) — A method to emulate the small sector size features and endurance
characteristics associated with an EEPROM.
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Chapter 4 384 KByte Flash Module (S12XFTM384K2V1)
EEE IFR — Nonvolatile information register located in the D-Flash block that contains data required to
partition the D-Flash memory and buffer RAM for EEE. The EEE IFR is visible in the global memory map
by setting the EEEIFRON bit in the MMCCTL1 register.
NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters
required for Flash command execution.
Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes eight
ECC bits for single bit fault correction and double bit fault detection within the phrase.
P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications.
P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased.
Each P-Flash sector contains 1024 bytes.
Program IFR — Nonvolatile information register located in the P-Flash block that contains the Device
ID, Version ID, and the Program Once field. The Program IFR is visible in the global memory map by
setting the PGMIFRON bit in the MMCCTL1 register.
4.1.2
Features
4.1.2.1
•
•
•
•
•
•
384 Kbytes of P-Flash memory composed of one 256 Kbyte Flash block and one 128 Kbyte Flash
block. The 256 Kbyte Flash block consists of two 128 Kbyte sections each divided into 128 sectors
of 1024 bytes. The 128 Kbyte Flash block is divided into 128 sectors of 1024 bytes.
Single bit fault correction and double bit fault detection within a 64-bit phrase during read
operations
Automated program and erase algorithm with verify and generation of ECC parity bits
Fast sector erase and phrase program operation
Ability to program up to one phrase in each P-Flash block simultaneously
Flexible protection scheme to prevent accidental program or erase of P-Flash memory
4.1.2.2
•
•
•
•
•
•
D-Flash Features
Up to 32 Kbytes of D-Flash memory with 256 byte sectors for user access
Dedicated commands to control access to the D-Flash memory over EEE operation
Single bit fault correction and double bit fault detection within a word during read operations
Automated program and erase algorithm with verify and generation of ECC parity bits
Fast sector erase and word program operation
Ability to program up to four words in a burst sequence
4.1.2.3
•
•
P-Flash Features
Emulated EEPROM Features
Up to 4 Kbytes of emulated EEPROM (EEE) accessible as 4 Kbytes of RAM
Flexible protection scheme to prevent accidental program or erase of data
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Chapter 4 384 KByte Flash Module (S12XFTM384K2V1)
•
•
•
•
•
Automatic EEE file handling using an internal Memory Controller
Automatic transfer of valid EEE data from D-Flash memory to buffer RAM on reset
Ability to monitor the number of outstanding EEE related buffer RAM words left to be
programmed into D-Flash memory
Ability to disable EEE operation and allow priority access to the D-Flash memory
Ability to cancel all pending EEE operations and allow priority access to the D-Flash memory
4.1.2.4
•
Up to 4 Kbytes of RAM for user access
4.1.2.5
•
•
•
4.1.3
User Buffer RAM Features
Other Flash Module Features
No external high-voltage power supply required for Flash memory program and erase operations
Interrupt generation on Flash command completion and Flash error detection
Security mechanism to prevent unauthorized access to the Flash memory
Block Diagram
The block diagram of the Flash module is shown in Figure 4-1.
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Chapter 4 384 KByte Flash Module (S12XFTM384K2V1)
Flash
Interface
Command
Interrupt
Request
Registers
Error
Interrupt
Request
Protection
16bit
internal
bus
P-Flash Block 0
32Kx72
16Kx72
16Kx72
sector 0
sector 1
sector 0
sector 1
sector 127
sector 127
Security
Oscillator
Clock (XTAL)
P-Flash
Block 1
16Kx72
Clock
Divider FCLK
XGATE
sector 0
sector 1
Memory
Controller
CPU
Scratch RAM
512x16
Buffer RAM
2Kx16
sector 127
D-Flash
16Kx22
sector 0
sector 1
sector 127
Tag RAM
128x16
Figure 4-1. FTM384K2 Block Diagram
4.2
External Signal Description
The Flash module contains no signals that connect off-chip.
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Chapter 4 384 KByte Flash Module (S12XFTM384K2V1)
4.3
Memory Map and Registers
This section describes the memory map and registers for the Flash module. Read data from unimplemented
memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space
in the Flash module will be ignored by the Flash module.
4.3.1
Module Memory Map
The S12X architecture places the P-Flash memory between global addresses 0x78_0000 and 0x7F_FFFF
as shown in Table 4-2. The P-Flash memory map is shown in Figure 4-2.
Table 4-2. P-Flash Memory Addressing
Global Address
Size
(Bytes)
0x7C_0000 – 0x7F_FFFF
256 K
P-Flash Block 0
Contains Flash Configuration Field
(see Table 4-3)
0x7A_0000 – 0x7B_FFFF
128 K
No P-Flash Memory
0x78_0000 – 0x79_FFFF
128 K
P-Flash Block 1
Description
The FPROT register, described in Section 4.3.2.9, can be set to protect regions in the Flash memory from
accidental program or erase. Three separate memory regions, one growing upward from global address
0x7F_8000 in the Flash memory (called the lower region), one growing downward from global address
0x7F_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash
memory, can be activated for protection. The Flash memory addresses covered by these protectable regions
are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader
code since it covers the vector space. Default protection settings as well as security information that allows
the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in
Table 4-3.
Table 4-3. Flash Configuration Field(1)
Global Address
Size
(Bytes)
0x7F_FF00 – 0x7F_FF07
8
0x7F_FF08 –
0x7F_FF0B(2)
4
0x7F_FF0C2
1
P-Flash Protection byte.
Refer to Section 4.3.2.9, “P-Flash Protection Register (FPROT)”
0x7F_FF0D2
1
EEE Protection byte
Refer to Section 4.3.2.10, “EEE Protection Register (EPROT)”
0x7F_FF0E2
1
Flash Nonvolatile byte
Refer to Section 4.3.2.14, “Flash Option Register (FOPT)”
Description
Backdoor Comparison Key
Refer to Section 4.4.2.12, “Verify Backdoor Access Key Command,” and
Section 4.5.1, “Unsecuring the MCU using Backdoor Key Access”
Reserved
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Chapter 4 384 KByte Flash Module (S12XFTM384K2V1)
Table 4-3. Flash Configuration Field(1)
Global Address
Size
(Bytes)
Description
Flash Security byte
Refer to Section 4.3.2.2, “Flash Security Register (FSEC)”
1. Older versions may have swapped protection byte addresses
2. 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in
the 0x7F_FF08 - 0x7F_FF0B reserved field should be programmed to 0xFF.
0x7F_FF0F2
1
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Chapter 4 384 KByte Flash Module (S12XFTM384K2V1)
P-Flash START = 0x78_0000
0x79_FFFF
Flash Protected/Unprotected Region
352 Kbytes
0x7C_0000
0x7F_8000
0x7F_8400
0x7F_8800
0x7F_9000
Flash Protected/Unprotected Lower Region
1, 2, 4, 8 Kbytes
0x7F_A000
Flash Protected/Unprotected Region
8 Kbytes (up to 29 Kbytes)
0x7F_C000
0x7F_E000
Flash Protected/Unprotected Higher Region
2, 4, 8, 16 Kbytes
0x7F_F000
0x7F_F800
P-Flash END = 0x7F_FFFF
Flash Configuration Field
16 bytes (0x7F_FF00 - 0x7F_FF0F)
Figure 4-2. P-Flash Memory Map
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Chapter 4 384 KByte Flash Module (S12XFTM384K2V1)
Table 4-4. Program IFR Fields
Global Address
(PGMIFRON)
Size
(Bytes)
0x40_0000 – 0x40_0007
8
Device ID
0x40_0008 – 0x40_00E7
224
Reserved
0x40_00E8 – 0x40_00E9
2
Version ID
0x40_00EA – 0x40_00FF
22
Reserved
0x40_0100 – 0x40_013F
64
Program Once Field
Refer to Section 4.4.2.7, “Program Once Command”
0x40_0140 – 0x40_01FF
192
Reserved
Field Description
Table 4-5. P-Flash IFR Accessibility
Global Address
(PGMIFRON)
Size
(Bytes)
0x40_0000 – 0x40_01FF
512
XBUS0 (PBLK0)(1)
0x40_0200 – 0x40_03FF
512
Unimplemented
0x40_0400 – 0x40_05FF
512
Unimplemented
0x40_0600 – 0x40_07FF
512
1. Refer to Table 4-4 for more details.
Accessed From
XBUS1 (PBLK1)
Table 4-6. EEE Resource Fields
Global Address
Size
(Bytes)
0x10_0000 – 0x10_7FFF
32,768
D-Flash Memory (User and EEE)
0x10_8000 – 0x11_FFFF
98,304
Reserved
0x12_0000 – 0x12_007F
128
0x12_0080 – 0x12_0FFF
3,968
Reserved
0x12_1000 – 0x12_1EFF
3,840
Reserved
0x12_1F00 – 0x12_1FFF
256
0x12_2000 – 0x12_3BFF
7,168
Reserved
0x12_3C00 – 0x12_3FFF
1,024
Memory Controller Scratch RAM (TMGRAMON1 = 1)
0x12_4000 – 0x12_DFFF
40,960
Reserved
0x12_E000 – 0x12_FFFF
8,192
Reserved
0x13_0000 – 0x13_EFFF
61,440
Reserved
0x13_F000 – 0x13_FFFF
1. MMCCTL1 register bit
4,096
Buffer RAM (User and EEE)
Description
EEE Nonvolatile Information Register (EEEIFRON(1) = 1)
EEE Tag RAM (TMGRAMON1 = 1)
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Chapter 4 384 KByte Flash Module (S12XFTM384K2V1)
D-Flash START = 0x10_0000
D-Flash User Partition
D-Flash Memory
32 Kbytes
D-Flash EEE Partition
D-Flash END = 0x10_7FFF
0x12_0000
0x12_1000
0x12_2000
0x12_4000
EEE Nonvolatile Information Register (EEEIFRON)
128 bytes
EEE Tag RAM (TMGRAMON)
256 bytes
Memory Controller Scratch RAM (TMGRAMON)
1024 bytes
0x12_E000
0x12_FFFF
Buffer RAM START = 0x13_F000
Buffer RAM User Partition
0x13_FE00
0x13_FE40
0x13_FE80
0x13_FEC0
0x13_FF00
0x13_FF40
0x13_FF80
0x13_FFC0
Buffer RAM END = 0x13_FFFF
Buffer RAM
4 Kbytes
Buffer RAM EEE Partition
Protectable Region (EEE only)
64, 128, 192, 256, 320, 384, 448, 512 bytes
Figure 4-3. EEE Resource Memory Map
The Full Partition D-Flash command (see Section 4.4.2.15) is used to program the EEE nonvolatile
information register fields where address 0x12_0000 defines the D-Flash partition for user access and
address 0x12_0004 defines the buffer RAM partition for EEE operations.
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Table 4-7. EEE Nonvolatile Information Register Fields
Global Address
(EEEIFRON)
Size
(Bytes)
0x12_0000 – 0x12_0001
2
D-Flash User Partition (DFPART)
Refer to Section 4.4.2.15, “Full Partition D-Flash Command”
0x12_0002 – 0x12_0003
2
D-Flash User Partition (duplicate(1))
0x12_0004 – 0x12_0005
2
Buffer RAM EEE Partition (ERPART)
Refer to Section 4.4.2.15, “Full Partition D-Flash Command”
0x12_0006 – 0x12_0007
2
Buffer RAM EEE Partition (duplicate1)
Description
0x12_0008 – 0x12_007F
120
Reserved
1. Duplicate value used if primary value generates a double bit fault when read during the reset sequence.
4.3.2
Register Descriptions
The Flash module contains a set of 20 control and status registers located between Flash module base +
0x0000 and 0x0013. A summary of the Flash module registers is given in Figure 4-4 with detailed
descriptions in the following subsections.
CAUTION
Writes to any Flash register must be avoided while a Flash command is
active (CCIF=0) to prevent corruption of Flash register contents and
Memory Controller behavior.
Address
& Name
0x0000
FCLKDIV
0x0001
FSEC
0x0002
FCCOBIX
0x0003
FECCRIX
0x0004
FCNFG
0x0005
FERCNFG
7
R
6
5
4
3
2
1
0
FDIV6
FDIV5
FDIV4
FDIV3
FDIV2
FDIV1
FDIV0
KEYEN1
KEYEN0
RNV5
RNV4
RNV3
RNV2
SEC1
SEC0
0
0
0
0
0
CCOBIX2
CCOBIX1
CCOBIX0
ECCRIX2
ECCRIX1
ECCRIX0
FDFD
FSFD
DFDIE
SFDIE
FDIVLD
W
R
W
R
W
R
0
0
0
0
0
W
R
0
0
CCIE
0
0
IGNSF
W
R
0
ERSERIE
PGMERIE
EPVIOLIE
ERSVIE1
ERSVIE0
W
Figure 4-4. FTM384K2 Register Summary
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Address
& Name
0x0006
FSTAT
0x0007
FERSTAT
0x0008
FPROT
0x0009
EPROT
0x000A
FCCOBHI
0x000B
FCCOBLO
0x000C
ETAGHI
0x000D
ETAGLO
0x000E
FECCRHI
0x000F
FECCRLO
0x0010
FOPT
0x0011
FRSV0
0x0012
FRSV1
0x0013
FRSV2
7
R
6
5
4
3
2
1
0
ACCERR
FPVIOL
MGBUSY
RSVD
MGSTAT1
MGSTAT0
EPVIOLIF
ERSVIF1
ERSVIF0
DFDIF
SFDIF
FPHDIS
FPHS1
FPHS0
FPLDIS
FPLS1
FPLS0
RNV5
RNV4
EPDIS
EPS2
EPS1
EPS0
0
CCIF
W
R
0
ERSERIF
PGMERIF
W
R
RNV6
FPOPEN
W
R
RNV6
EPOPEN
W
R
CCOB15
CCOB14
CCOB13
CCOB12
CCOB11
CCOB10
CCOB9
CCOB8
CCOB7
CCOB6
CCOB5
CCOB4
CCOB3
CCOB2
CCOB1
CCOB0
ETAG15
ETAG14
ETAG13
ETAG12
ETAG11
ETAG10
ETAG9
ETAG8
ETAG7
ETAG6
ETAG5
ETAG4
ETAG3
ETAG2
ETAG1
ETAG0
ECCR15
ECCR14
ECCR13
ECCR12
ECCR11
ECCR10
ECCR9
ECCR8
ECCR7
ECCR6
ECCR5
ECCR4
ECCR3
ECCR2
ECCR1
ECCR0
NV7
NV6
NV5
NV4
NV3
NV2
NV1
NV0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Figure 4-4. FTM384K2 Register Summary (continued)
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Chapter 4 384 KByte Flash Module (S12XFTM384K2V1)
Address
& Name
7
6
5
4
3
2
1
0
= Unimplemented or Reserved
Figure 4-4. FTM384K2 Register Summary (continued)
4.3.2.1
Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
Offset Module Base + 0x0000
7
R
6
5
4
3
2
1
0
0
0
0
FDIVLD
FDIV[6:0]
W
Reset
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-5. Flash Clock Divider Register (FCLKDIV)
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
Table 4-8. FCLKDIV Field Descriptions
Field
7
FDIVLD
6–0
FDIV[6:0]
Description
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms. Table 4-9 shows recommended values for FDIV[6:0] based on OSCCLK frequency.
Please refer to Section 4.4.1, “Flash Command Operations,” for more information.
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
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Table 4-9. FDIV vs OSCCLK Frequency
OSCCLK Frequency
(MHz)
MIN(1)
MAX
FDIV[6:0]
(2)
OSCCLK Frequency
(MHz)
MIN
1
MAX
FDIV[6:0]
2
OSCCLK Frequency
(MHz)
MIN
1
MAX
FDIV[6:0]
2
33.60
34.65
0x20
67.20
68.25
0x40
1.60
2.10
0x01
34.65
35.70
0x21
68.25
69.30
0x41
2.40
3.15
0x02
35.70
36.75
0x22
69.30
70.35
0x42
3.20
4.20
0x03
36.75
37.80
0x23
70.35
71.40
0x43
4.20
5.25
0x04
37.80
38.85
0x24
71.40
72.45
0x44
5.25
6.30
0x05
38.85
39.90
0x25
72.45
73.50
0x45
6.30
7.35
0x06
39.90
40.95
0x26
73.50
74.55
0x46
7.35
8.40
0x07
40.95
42.00
0x27
74.55
75.60
0x47
8.40
9.45
0x08
42.00
43.05
0x28
75.60
76.65
0x48
9.45
10.50
0x09
43.05
44.10
0x29
76.65
77.70
0x49
10.50
11.55
0x0A
44.10
45.15
0x2A
77.70
78.75
0x4A
11.55
12.60
0x0B
45.15
46.20
0x2B
78.75
79.80
0x4B
12.60
13.65
0x0C
46.20
47.25
0x2C
79.80
80.85
0x4C
13.65
14.70
0x0D
47.25
48.30
0x2D
80.85
81.90
0x4D
14.70
15.75
0x0E
48.30
49.35
0x2E
81.90
82.95
0x4E
15.75
16.80
0x0F
49.35
50.40
0x2F
82.95
84.00
0x4F
16.80
17.85
0x10
50.40
51.45
0x30
84.00
85.05
0x50
17.85
18.90
0x11
51.45
52.50
0x31
85.05
86.10
0x51
18.90
19.95
0x12
52.50
53.55
0x32
86.10
87.15
0x52
19.95
21.00
0x13
53.55
54.60
0x33
87.15
88.20
0x53
21.00
22.05
0x14
54.60
55.65
0x34
88.20
89.25
0x54
22.05
23.10
0x15
55.65
56.70
0x35
89.25
90.30
0x55
23.10
24.15
0x16
56.70
57.75
0x36
90.30
91.35
0x56
24.15
25.20
0x17
57.75
58.80
0x37
91.35
92.40
0x57
25.20
26.25
0x18
58.80
59.85
0x38
92.40
93.45
0x58
26.25
27.30
0x19
59.85
60.90
0x39
93.45
94.50
0x59
27.30
28.35
0x1A
60.90
61.95
0x3A
94.50
95.55
0x5A
28.35
29.40
0x1B
61.95
63.00
0x3B
95.55
96.60
0x5B
29.40
30.45
0x1C
63.00
64.05
0x3C
96.60
97.65
0x5C
30.45
31.50
0x1D
64.05
65.10
0x3D
97.65
98.70
0x5D
31.50
32.55
0x1E
65.10
66.15
0x3E
98.70
99.75
0x5E
32.55
33.60
0x1F
66.15
67.20
1. FDIV shown generates an FCLK frequency of >0.8 MHz
0x3F
99.75
100.80
0x5F
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2. FDIV shown generates an FCLK frequency of 1.05 MHz
4.3.2.2
Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
Offset Module Base + 0x0001
7
R
6
5
4
KEYEN[1:0]
3
2
1
RNV[5:2]
0
SEC[1:0]
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 4-6. Flash Security Register (FSEC)
All bits in the FSEC register are readable but not writable.
During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the
Flash configuration field at global address 0x7F_FF0F located in P-Flash memory (see Table 4-3) as
indicated by reset condition F in Figure 4-6. If a double bit fault is detected while reading the P-Flash
phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be
set to leave the Flash module in a secured state with backdoor key access disabled.
Table 4-10. FSEC Field Descriptions
Field
Description
7–6
Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the
KEYEN[1:0] Flash module as shown in Table 4-11.
5–2
RNV[5:2}
Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements.
1–0
SEC[1:0]
Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 4-12. If the
Flash module is unsecured using backdoor key access, the SEC bits are forced to 10.
Table 4-11. Flash KEYEN States
KEYEN[1:0]
Status of Backdoor Key Access
00
DISABLED
01
DISABLED(1)
10
ENABLED
11
DISABLED
1. Preferred KEYEN state to disable backdoor key access.
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Chapter 4 384 KByte Flash Module (S12XFTM384K2V1)
Table 4-12. Flash Security States
SEC[1:0]
Status of Security
00
SECURED
01
SECURED(1)
10
UNSECURED
11
SECURED
1. Preferred SEC state to set MCU to secured state.
The security function in the Flash module is described in Section 4.5.
4.3.2.3
Flash CCOB Index Register (FCCOBIX)
The FCCOBIX register is used to index the FCCOB register for Flash memory operations.
Offset Module Base + 0x0002
R
7
6
5
4
3
0
0
0
0
0
2
1
0
CCOBIX[2:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-7. FCCOB Index Register (FCCOBIX)
CCOBIX bits are readable and writable while remaining bits read 0 and are not writable.
Table 4-13. FCCOBIX Field Descriptions
Field
Description
2–0
CCOBIX[1:0]
Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register
array is being read or written to. See Section 4.3.2.11, “Flash Common Command Object Register (FCCOB),”
for more details.
4.3.2.4
Flash ECCR Index Register (FECCRIX)
The FECCRIX register is used to index the FECCR register for ECC fault reporting.
Offset Module Base + 0x0003
R
7
6
5
4
3
0
0
0
0
0
2
1
0
ECCRIX[2:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-8. FECCR Index Register (FECCRIX)
ECCRIX bits are readable and writable while remaining bits read 0 and are not writable.
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Table 4-14. FECCRIX Field Descriptions
Field
Description
2-0
ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is
ECCRIX[2:0] being read. See Section 4.3.2.13, “Flash ECC Error Results Register (FECCR),” for more details.
4.3.2.5
Flash Configuration Register (FCNFG)
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU or XGATE.
Offset Module Base + 0x0004
7
R
6
5
0
0
CCIE
4
3
2
0
0
IGNSF
1
0
FDFD
FSFD
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-9. Flash Configuration Register (FCNFG)
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
Table 4-15. FCNFG Field Descriptions
Field
Description
7
CCIE
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 4.3.2.7)
4
IGNSF
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section 4.3.2.8).
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
generated
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Table 4-15. FCNFG Field Descriptions (continued)
Field
Description
1
FDFD
Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array
read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The
FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual
double bit fault is detected.
0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see
Section 4.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG
register is set (see Section 4.3.2.6)
0
FSFD
Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array
read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. The
FECCR registers will not be updated during the Flash array read operation with FSFD set unless an actual single
bit fault is detected.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 4.3.2.7)
and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section 4.3.2.6)
4.3.2.6
Flash Error Configuration Register (FERCNFG)
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
Offset Module Base + 0x0005
7
6
R
5
4
3
2
1
0
EPVIOLIE
ERSVIE1
ERSVIE0
DFDIE
SFDIE
0
0
0
0
0
0
ERSERIE
PGMERIE
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 4-10. Flash Error Configuration Register (FERCNFG)
All assigned bits in the FERCNFG register are readable and writable.
Table 4-16. FERCNFG Field Descriptions
Field
Description
7
ERSERIE
EEE Erase Error Interrupt Enable — The ERSERIE bit controls interrupt generation when a failure is detected
during an EEE erase operation.
0 ERSERIF interrupt disabled
1 An interrupt will be requested whenever the ERSERIF flag is set (see Section 4.3.2.8)
6
PGMERIE
EEE Program Error Interrupt Enable — The PGMERIE bit controls interrupt generation when a failure is
detected during an EEE program operation.
0 PGMERIF interrupt disabled
1 An interrupt will be requested whenever the PGMERIF flag is set (see Section 4.3.2.8)
4
EPVIOLIE
EEE Protection Violation Interrupt Enable — The EPVIOLIE bit controls interrupt generation when a
protection violation is detected during a write to the buffer RAM EEE partition.
0 EPVIOLIF interrupt disabled
1 An interrupt will be requested whenever the EPVIOLIF flag is set (see Section 4.3.2.8)
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Table 4-16. FERCNFG Field Descriptions (continued)
Field
Description
3
ERSVIE1
EEE Error Type 1 Interrupt Enable — The ERSVIE1 bit controls interrupt generation when a change state error
is detected during an EEE operation.
0 ERSVIF1 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF1 flag is set (see Section 4.3.2.8)
2
ERSVIE0
EEE Error Type 0 Interrupt Enable — The ERSVIE0 bit controls interrupt generation when a sector format error
is detected during an EEE operation.
0 ERSVIF0 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF0 flag is set (see Section 4.3.2.8)
1
DFDIE
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see Section 4.3.2.8)
0
SFDIE
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 4.3.2.8)
1 An interrupt will be requested whenever the SFDIF flag is set (see Section 4.3.2.8)
4.3.2.7
Flash Status Register (FSTAT)
The FSTAT register reports the operational status of the Flash module.
Offset Module Base + 0x0006
7
6
R
5
4
0
CCIF
ACCERR
FPVIOL
0
0
3
2
MGBUSY
RSVD
0
0
1
0
MGSTAT[1:0]
W
Reset
1
0
0(1)
01
= Unimplemented or Reserved
Figure 4-11. Flash Status Register (FSTAT)
1. Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 4.6).
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
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Table 4-17. FSTAT Field Descriptions
Field
Description
7
CCIF
Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The
CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command
completion or command violation.
0 Flash command in progress
1 Flash command has completed
5
ACCERR
Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory
caused by either a violation of the command write sequence (see Section 4.4.1.2) or issuing an illegal Flash
command or when errors are encountered while initializing the EEE buffer ram during the reset sequence.
While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by
writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.
0 No access error detected
1 Access error detected
4
FPVIOL
Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an
address in a protected area of P-Flash memory during a command write sequence. The FPVIOL bit is cleared
by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not
possible to launch a command or start a command write sequence.
0 No protection violation detected
1 Protection violation detected
3
MGBUSY
Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller.
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0) or is handling internal EEE operations
2
RSVD
Reserved Bit — This bit is reserved and always reads 0.
1–0
Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error
MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See Section 4.4.2,
“Flash Command Description,” and Section 4.6, “Initialization” for details.
4.3.2.8
Flash Error Status Register (FERSTAT)
The FERSTAT register reflects the error status of internal Flash operations.
Offset Module Base + 0x0007
7
6
5
ERSERIF
PGMERIF
0
0
R
4
3
2
1
0
EPVIOLIF
ERSVIF1
ERSVIF0
DFDIF
SFDIF
0
0
0
0
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 4-12. Flash Error Status Register (FERSTAT)
All flags in the FERSTAT register are readable and only writable to clear the flag.
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Table 4-18. FERSTAT Field Descriptions
Field
Description
7
ERSERIF
EEE Erase Error Interrupt Flag — The setting of the ERSERIF flag occurs due to an error in a Flash erase
command that resulted in the erase operation not being successful during EEE operations. The ERSERIF flag
is cleared by writing a 1 to ERSERIF. Writing a 0 to the ERSERIF flag has no effect on ERSERIF. While
ERSERIF is set, it is possible to write to the buffer RAM EEE partition but the data written will not be transferred
to the D-Flash EEE partition.
0 Erase command successfully completed on the D-Flash EEE partition
1 Erase command failed on the D-Flash EEE partition
6
PGMERIF
EEE Program Error Interrupt Flag — The setting of the PGMERIF flag occurs due to an error in a Flash
program command that resulted in the program operation not being successful during EEE operations. The
PGMERIF flag is cleared by writing a 1 to PGMERIF. Writing a 0 to the PGMERIF flag has no effect on
PGMERIF. While PGMERIF is set, it is possible to write to the buffer RAM EEE partition but the data written will
not be transferred to the D-Flash EEE partition.
0 Program command successfully completed on the D-Flash EEE partition
1 Program command failed on the D-Flash EEE partition
4
EPVIOLIF
EEE Protection Violation Interrupt Flag —The setting of the EPVIOLIF flag indicates an attempt was made to
write to a protected area of the buffer RAM EEE partition. The EPVIOLIF flag is cleared by writing a 1 to
EPVIOLIF. Writing a 0 to the EPVIOLIF flag has no effect on EPVIOLIF. While EPVIOLIF is set, it is possible to
write to the buffer RAM EEE partition as long as the address written to is not in a protected area.
0 No EEE protection violation
1 EEE protection violation detected
3
ERSVIF1
EEE Error Interrupt 1 Flag —The setting of the ERSVIF1 flag indicates that the memory controller was unable
to change the state of a D-Flash EEE sector. The ERSVIF1 flag is cleared by writing a 1 to ERSVIF1. Writing a
0 to the ERSVIF1 flag has no effect on ERSVIF1. While ERSVIF1 is set, it is possible to write to the buffer RAM
EEE partition but the data written will not be transferred to the D-Flash EEE partition.
0 No EEE sector state change error detected
1 EEE sector state change error detected
2
ERSVIF0
EEE Error Interrupt 0 Flag —The setting of the ERSVIF0 flag indicates that the memory controller was unable
to format a D-Flash EEE sector for EEE use. The ERSVIF0 flag is cleared by writing a 1 to ERSVIF0. Writing a
0 to the ERSVIF0 flag has no effect on ERSVIF0. While ERSVIF0 is set, it is possible to write to the buffer RAM
EEE partition but the data written will not be transferred to the D-Flash EEE partition.
0 No EEE sector format error detected
1 EEE sector format error detected
1
DFDIF
Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was
detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation
was attempted on a Flash block that was under a Flash command operation. The DFDIF flag is cleared by writing
a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.
0 No double bit fault detected
1 Double bit fault detected or an invalid Flash array read operation attempted
0
SFDIF
Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag
indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation
or that a Flash array read operation was attempted on a Flash block that was under a Flash command operation.
The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF.
0 No single bit fault detected
1 Single bit fault detected and corrected or an invalid Flash array read operation attempted
4.3.2.9
P-Flash Protection Register (FPROT)
The FPROT register defines which P-Flash sectors are protected against program and erase operations.
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Offset Module Base + 0x0008
7
R
6
5
4
3
2
1
0
RNV6
FPOPEN
FPHDIS
FPHS[1:0]
FPLDIS
FPLS[1:0]
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 4-13. Flash Protection Register (FPROT)
The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected
region can only be increased (see Section 4.3.2.9.1, “P-Flash Protection Restrictions,” and Table 4-23).
During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte
in the Flash configuration field at global address 0x7F_FF0C located in P-Flash memory (see Table 4-3)
as indicated by reset condition ‘F’ in Figure 4-13. To change the P-Flash protection that will be loaded
during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash
protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase
containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and
remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected.
Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error
and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible
if any of the P-Flash sectors contained in the same P-Flash block are protected.
Table 4-19. FPROT Field Descriptions
Field
Description
7
FPOPEN
Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or
erase operations as shown in Table 4-20 for the P-Flash block.
0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the
corresponding FPHS and FPLS bits
1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the
corresponding FPHS and FPLS bits
6
RNV[6]
Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements.
5
FPHDIS
Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a
protected/unprotected area in a specific region of the P-Flash memory ending with global address 0x7F_FFFF.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
4–3
FPHS[1:0]
Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area
in P-Flash memory as shown inTable 4-21. The FPHS bits can only be written to while the FPHDIS bit is set.
2
FPLDIS
1–0
FPLS[1:0]
Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a
protected/unprotected area in a specific region of the P-Flash memory beginning with global address
0x7F_8000.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area
in P-Flash memory as shown in Table 4-22. The FPLS bits can only be written to while the FPLDIS bit is set.
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Table 4-20. P-Flash Protection Function
Function(1)
FPOPEN
FPHDIS
FPLDIS
1
1
1
No P-Flash Protection
1
1
0
Protected Low Range
1
0
1
Protected High Range
1
0
0
Protected High and Low Ranges
0
1
1
Full P-Flash Memory Protected
0
1
0
Unprotected Low Range
0
0
1
Unprotected High Range
0
0
0
Unprotected High and Low Ranges
1. For range sizes, refer to Table 4-21 and Table 4-22.
Table 4-21. P-Flash Protection Higher Address Range
FPHS[1:0]
Global Address Range
Protected Size
00
0x7F_F800–0x7F_FFFF
2 Kbytes
01
0x7F_F000–0x7F_FFFF
4 Kbytes
10
0x7F_E000–0x7F_FFFF
8 Kbytes
11
0x7F_C000–0x7F_FFFF
16 Kbytes
Table 4-22. P-Flash Protection Lower Address Range
FPLS[1:0]
Global Address Range
Protected Size
00
0x7F_8000–0x7F_83FF
1 Kbyte
01
0x7F_8000–0x7F_87FF
2 Kbytes
10
0x7F_8000–0x7F_8FFF
4 Kbytes
11
0x7F_8000–0x7F_9FFF
8 Kbytes
All possible P-Flash protection scenarios are shown in Figure 4-14. Although the protection scheme is
loaded from the Flash memory at global address 0x7F_FF0C during the reset sequence, it can be changed
by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single
chip mode while providing as much protection as possible if reprogramming is not required.
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FPHDIS = 0
FPLDIS = 1
FPHDIS = 0
FPLDIS = 0
7
6
5
4
3
2
1
0
FPLS[1:0]
FPHDIS = 1
FPLDIS = 0
0x7F_8000
0x7F_FFFF
Scenario
FPHS[1:0]
Scenario
FLASH START
FPHDIS = 1
FPLDIS = 1
FPOPEN = 1
Chapter 4 384 KByte Flash Module (S12XFTM384K2V1)
FPHS[1:0]
0x7F_8000
FPOPEN = 0
FPLS[1:0]
FLASH START
0x7F_FFFF
Unprotected region
Protected region with size
defined by FPLS
Protected region
not defined by FPLS, FPHS
Protected region with size
defined by FPHS
Figure 4-14. P-Flash Protection Scenarios
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4.3.2.9.1
P-Flash Protection Restrictions
The general guideline is that P-Flash protection can only be added and not removed. Table 4-23 specifies
all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
Table 4-23. P-Flash Protection Scenario Transitions
To Protection Scenario(1)
From
Protection
Scenario
0
1
2
3
0
X
X
X
X
X
1
X
4
X
X
X
X
X
X
X
X
6
6
7
X
3
5
5
X
X
2
4
X
X
X
X
X
X
X
X
X
X
7
1. Allowed transitions marked with X, see Figure 4-14 for a definition of the scenarios.
4.3.2.10
EEE Protection Register (EPROT)
The EPROT register defines which buffer RAM EEE partition areas are protected against writes.
Offset Module Base + 0x0009
7
6
R
5
4
3
2
1
0
RNV[6:4]
EPOPEN
EPDIS
EPS[2:0]
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 4-15. EEE Protection Register (EPROT)
All bits in the EPROT register are readable and writable except for RNV[6:4] which are only readable. The
EPOPEN and EPDIS bits can only be written to the protected state. The EPS bits can be written anytime
until the EPDIS bit is cleared. If the EPOPEN bit is cleared, the state of the EPDIS and EPS bits is
irrelevant.
During the reset sequence, the EPROT register is loaded from the EEE protection byte in the Flash
configuration field at global address 0x7F_FF0D located in P-Flash memory (see Table 4-3) as indicated
by reset condition F in Figure 4-15. To change the EEE protection that will be loaded during the reset
sequence, the P-Flash sector containing the EEE protection byte must be unprotected, then the EEE
protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase
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containing the EEE protection byte during the reset sequence, the EPOPEN bit will be cleared and
remaining bits in the EPROT register will be set to leave the buffer RAM EEE partition fully protected.
Trying to write data to any protected area in the buffer RAM EEE partition will result in a protection
violation error and the EPVIOLIF flag will be set in the FERSTAT register. Trying to write data to any
protected area in the buffer RAM partitioned for user access will not be prevented and the EPVIOLIF flag
in the FERSTAT register will not set.
Table 4-24. EPROT Field Descriptions
Field
Description
7
EPOPEN
Enables writes to the Buffer RAM partitioned for EEE
0 The entire buffer RAM EEE partition is protected from writes
1 Unprotected buffer RAM EEE partition areas are enabled for writes
6–4
RNV[6:4]
Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements
3
EPDIS
Buffer RAM Protection Address Range Disable — The EPDIS bit determines whether there is a protected
area in a specific region of the buffer RAM EEE partition.
0 Protection enabled
1 Protection disabled
2–0
EPS[2:0]
Buffer RAM Protection Size — The EPS[2:0] bits determine the size of the protected area in the buffer RAM
EEE partition as shown inTable 4-21. The EPS bits can only be written to while the EPDIS bit is set.
Table 4-25. Buffer RAM EEE Partition Protection Address Range
4.3.2.11
EPS[2:0]
Global Address Range
Protected Size
000
0x13_FFC0 – 0x13_FFFF
64 bytes
001
0x13_FF80 – 0x13_FFFF
128 bytes
010
0x13_FF40 – 0x13_FFFF
192 bytes
011
0x13_FF00 – 0x13_FFFF
256 bytes
100
0x13_FEC0 – 0x13_FFFF
320 bytes
101
0x13_FE80 – 0x13_FFFF
384 bytes
110
0x13_FE40 – 0x13_FFFF
448 bytes
111
0x13_FE00 – 0x13_FFFF
512 bytes
Flash Common Command Object Register (FCCOB)
The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register.
Byte wide reads and writes are allowed to the FCCOB register.
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Offset Module Base + 0x000A
7
6
5
4
3
2
1
0
0
0
0
0
R
CCOB[15:8]
W
Reset
0
0
0
0
Figure 4-16. Flash Common Command Object High Register (FCCOBHI)
Offset Module Base + 0x000B
7
6
5
4
3
2
1
0
0
0
0
0
R
CCOB[7:0]
W
Reset
0
0
0
0
Figure 4-17. Flash Common Command Object Low Register (FCCOBLO)
4.3.2.11.1
FCCOB - NVM Command Mode
NVM command mode uses the indexed FCCOB register to provide a command code and its relevant
parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates
the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user
clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register
all FCCOB parameter fields are locked and cannot be changed by the user until the command completes
(as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the
FCCOB register array.
The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 4-26. The
return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by
the Memory Controller. Writes to the unimplemented parameter fields (CCOBIX = 110 and CCOBIX =
111) are ignored with reads from these fields returning 0x0000.
Table 4-26 shows the generic Flash command format. The high byte of the first word in the CCOB array
contains the command code, followed by the parameters for this specific Flash command. For details on
the FCCOB settings required by each command, see the Flash command descriptions in Section 4.4.2.
Table 4-26. FCCOB - NVM Command Mode (Typical Usage)
CCOBIX[2:0]
Byte
FCCOB Parameter Fields (NVM Command Mode)
HI
FCMD[7:0] defining Flash command
LO
0, Global address [22:16]
HI
Global address [15:8]
LO
Global address [7:0]
HI
Data 0 [15:8]
LO
Data 0 [7:0]
000
001
010
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Table 4-26. FCCOB - NVM Command Mode (Typical Usage)
CCOBIX[2:0]
Byte
FCCOB Parameter Fields (NVM Command Mode)
HI
Data 1 [15:8]
LO
Data 1 [7:0]
HI
Data 2 [15:8]
LO
Data 2 [7:0]
HI
Data 3 [15:8]
LO
Data 3 [7:0]
011
100
101
4.3.2.12
EEE Tag Counter Register (ETAG)
The ETAG register contains the number of outstanding words in the buffer RAM EEE partition that need
to be programmed into the D-Flash EEE partition. The ETAG register is decremented prior to the related
tagged word being programmed into the D-Flash EEE partition. All tagged words have been programmed
into the D-Flash EEE partition once all bits in the ETAG register read 0 and the MGBUSY flag in the
FSTAT register reads 0.
Offset Module Base + 0x000C
7
6
5
4
R
3
2
1
0
0
0
0
0
ETAG[15:8]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 4-18. EEE Tag Counter High Register (ETAGHI)
Offset Module Base + 0x000D
7
6
5
4
R
3
2
1
0
0
0
0
0
ETAG[7:0]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 4-19. EEE Tag Counter Low Register (ETAGLO)
All ETAG bits are readable but not writable and are cleared by the Memory Controller.
4.3.2.13
Flash ECC Error Results Register (FECCR)
The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.
The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits
in the FECCRIX register (see Section 4.3.2.4). Once ECC fault information has been stored, no other fault
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information will be recorded until the specific ECC fault flag has been cleared. In the event of
simultaneous ECC faults, the priority for fault recording is:
1. Double bit fault over single bit fault
2. CPU over XGATE
Offset Module Base + 0x000E
7
6
5
4
R
3
2
1
0
0
0
0
0
ECCR[15:8]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 4-20. Flash ECC Error Results High Register (FECCRHI)
Offset Module Base + 0x000F
7
6
5
4
R
3
2
1
0
0
0
0
0
ECCR[7:0]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 4-21. Flash ECC Error Results Low Register (FECCRLO)
All FECCR bits are readable but not writable.
Table 4-27. FECCR Index Settings
ECCRIX[2:0]
000
FECCR Register Content
Bits [15:8]
Bit[7]
Bits[6:0]
Parity bits read from
Flash block
CPU or XGATE
source identity
Global address
[22:16]
001
Global address [15:0]
010
Data 0 [15:0]
011
Data 1 [15:0] (P-Flash only)
100
Data 2 [15:0] (P-Flash only)
101
Data 3 [15:0] (P-Flash only)
110
Not used, returns 0x0000 when read
111
Not used, returns 0x0000 when read
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Table 4-28. FECCR Index=000 Bit Descriptions
Field
Description
15:8
PAR[7:0]
ECC Parity Bits — Contains the 8 parity bits from the 72 bit wide P-Flash data word or the 6 parity bits,
allocated to PAR[5:0], from the 22 bit wide D-Flash word with PAR[7:6]=00.
7
XBUS01
Bus Source Identifier — The XBUS01 bit determines whether the ECC error was caused by a read access
from the CPU or XGATE.
0 ECC Error happened on the CPU access
1 ECC Error happened on the XGATE access
6–0
Global Address — The GADDR[22:16] field contains the upper seven bits of the global address having
GADDR[22:16] caused the error.
The P-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The
following four words addressed by ECCRIX = 010 to 101 contain the 64-bit wide data phrase. The four
data words and the parity byte are the uncorrected data read from the P-Flash block.
The D-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The
uncorrected 16-bit data word is addressed by ECCRIX = 010.
4.3.2.14
Flash Option Register (FOPT)
The FOPT register is the Flash option register.
Offset Module Base + 0x0010
7
6
5
4
R
3
2
1
0
F
F
F
F
NV[7:0]
W
Reset
F
F
F
F
= Unimplemented or Reserved
Figure 4-22. Flash Option Register (FOPT)
All bits in the FOPT register are readable but are not writable.
During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash
configuration field at global address 0x7F_FF0E located in P-Flash memory (see Table 4-3) as indicated
by reset condition F in Figure 4-22. If a double bit fault is detected while reading the P-Flash phrase
containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set.
Table 4-29. FOPT Field Descriptions
Field
Description
7–0
NV[7:0]
Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper
use of the NV bits.
4.3.2.15
Flash Reserved0 Register (FRSV0)
This Flash register is reserved for factory testing.
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Offset Module Base + 0x0011
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 4-23. Flash Reserved0 Register (FRSV0)
All bits in the FRSV0 register read 0 and are not writable.
4.3.2.16
Flash Reserved1 Register (FRSV1)
This Flash register is reserved for factory testing.
Offset Module Base + 0x0012
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 4-24. Flash Reserved1 Register (FRSV1)
All bits in the FRSV1 register read 0 and are not writable.
4.3.2.17
Flash Reserved2 Register (FRSV2)
This Flash register is reserved for factory testing.
Offset Module Base + 0x0013
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 4-25. Flash Reserved2 Register (FRSV2)
All bits in the FRSV2 register read 0 and are not writable.
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4.4
4.4.1
Functional Description
Flash Command Operations
Flash command operations are used to modify Flash memory contents or configure module resources for
EEE operation.
The next sections describe:
• How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from
OSCCLK for Flash program and erase command operations
• The command write sequence used to set Flash command parameters and launch execution
• Valid Flash commands available for execution
4.4.1.1
Writing the FCLKDIV Register
Prior to issuing any Flash program or erase command after a reset, the user is required to write the
FCLKDIV register to divide OSCCLK down to a target FCLK of 1 MHz. Table 4-9 shows recommended
values for the FDIV field based on OSCCLK frequency.
NOTE
Programming or erasing the Flash memory cannot be performed if the bus
clock runs at less than 1 MHz. Setting FDIV too high can destroy the Flash
memory due to overstress. Setting FDIV too low can result in incomplete
programming or erasure of the Flash memory cells.
When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the
FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written,
any Flash program or erase command loaded during a command write sequence will not execute and the
ACCERR bit in the FSTAT register will set.
4.4.1.2
Command Write Sequence
The Memory Controller will launch all valid Flash commands entered using a command write sequence.
Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see
Section 4.3.2.7) and the CCIF flag should be tested to determine the status of the current command write
sequence. If CCIF is 0, the previous command write sequence is still active, a new command write
sequence cannot be started, and all writes to the FCCOB register are ignored.
CAUTION
Writes to any Flash register must be avoided while a Flash command is
active (CCIF=0) to prevent corruption of Flash register contents and
Memory Controller behavior.
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4.4.1.2.1
Define FCCOB Contents
The FCCOB parameter fields must be loaded with all required parameters for the Flash command being
executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX
register (see Section 4.3.2.3).
The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears
the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag
will remain clear until the Flash command has completed. Upon completion, the Memory Controller will
return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic
command write sequence is shown in Figure 4-26.
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Chapter 4 384 KByte Flash Module (S12XFTM384K2V1)
START
Read: FCLKDIV register
Clock Register
Written
Check
no
FDIVLD
Set?
yes
Write: FCLKDIV register
Note: FCLKDIV must be set after
each reset
Read: FSTAT register
FCCOB
Availability Check
CCIF
Set?
no
Results from previous Command
yes
Access Error and
Protection Violation
Check
ACCERR/
FPVIOL
Set?
no
yes
Write: FSTAT register
Clear ACCERR/FPVIOL 0x30
Write to FCCOBIX register
to identify specific command
parameter to load.
Write to FCCOB register
to load required command parameter.
More
Parameters?
yes
no
Write: FSTAT register (to launch command)
Clear CCIF 0x80
Read: FSTAT register
Bit Polling for
Command Completion
Check
CCIF Set?
no
yes
EXIT
Figure 4-26. Generic Flash Command Write Sequence Flowchart
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4.4.1.3
Valid Flash Module Commands
Table 4-30. Flash Commands by Mode
Unsecured
FCMD
Command
NS
NX
(1)
(2)
Secured
SS(3) ST(4)
NS
NX
(5)
(6)
SS(7) ST(8)
0x01
Erase Verify All Blocks
∗
∗
∗
∗
∗
∗
∗
∗
0x02
Erase Verify Block
∗
∗
∗
∗
∗
∗
∗
∗
0x03
Erase Verify P-Flash Section
∗
∗
∗
∗
∗
0x04
Read Once
∗
∗
∗
∗
∗
0x05
Load Data Field
∗
∗
∗
∗
∗
0x06
Program P-Flash
∗
∗
∗
∗
∗
0x07
Program Once
∗
∗
∗
∗
∗
0x08
Erase All Blocks
∗
∗
∗
∗
0x09
Erase P-Flash Block
∗
∗
∗
∗
∗
0x0A
Erase P-Flash Sector
∗
∗
∗
∗
∗
0x0B
Unsecure Flash
∗
∗
∗
∗
0x0C
Verify Backdoor Access Key
∗
0x0D
Set User Margin Level
∗
0x0E
∗
∗
∗
∗
∗
Set Field Margin Level
∗
∗
0x0F
Full Partition D-Flash
∗
∗
0x10
Erase Verify D-Flash Section
∗
∗
∗
∗
∗
0x11
Program D-Flash
∗
∗
∗
∗
∗
0x12
Erase D-Flash Sector
∗
∗
∗
∗
∗
0x13
Enable EEPROM Emulation
∗
∗
∗
∗
∗
∗
∗
∗
0x14
Disable EEPROM Emulation
∗
∗
∗
∗
∗
∗
∗
∗
0x15
EEPROM Emulation Query
∗
∗
∗
∗
∗
∗
∗
∗
0x20
Partition D-Flash
1. Unsecured Normal Single Chip mode.
2. Unsecured Normal Expanded mode.
3. Unsecured Special Single Chip mode.
4. Unsecured Special Mode.
5. Secured Normal Single Chip mode.
6. Secured Normal Expanded mode.
7. Secured Special Single Chip mode.
8. Secured Special Mode.
∗
∗
∗
∗
∗
∗
∗
∗
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4.4.1.4
P-Flash Commands
Table 4-31 summarizes the valid P-Flash commands along with the effects of the commands on the PFlash block and other resources within the Flash module.
Table 4-31. P-Flash Commands
FCMD
Command
0x01
Erase Verify All
Blocks
0x02
Erase Verify Block
0x03
Erase Verify PFlash Section
0x04
Read Once
0x05
Load Data Field
Load data for simultaneous multiple P-Flash block operations.
0x06
Program P-Flash
Program a phrase in a P-Flash block and any previously loaded phrases for any other PFlash block (see Load Data Field command).
0x07
Program Once
Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block
0 that is allowed to be programmed only once.
0x08
Erase All Blocks
Erase all P-Flash (and D-Flash) blocks.
An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN
bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are
set prior to launching the command.
0x09
Erase P-Flash
Block
Erase a single P-Flash block.
An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN
bits in the FPROT register are set prior to launching the command.
0x0A
Erase P-Flash
Sector
0x0B
Unsecure Flash
0x0C
Verify Backdoor
Access Key
Supports a method of releasing MCU security by verifying a set of security keys.
0x0D
Set User Margin
Level
Specifies a user margin read level for all P-Flash blocks.
0x0E
Set Field Margin
Level
Specifies a field margin read level for all P-Flash blocks (special modes only).
4.4.1.5
Function on P-Flash Memory
Verify that all P-Flash (and D-Flash) blocks are erased.
Verify that a P-Flash block is erased.
Verify that a given number of words starting at the address provided are erased.
Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block 0
that was previously programmed using the Program Once command.
Erase all bytes in a P-Flash sector.
Supports a method of releasing MCU security by erasing all P-Flash (and D-Flash) blocks
and verifying that all P-Flash (and D-Flash) blocks are erased.
D-Flash and EEE Commands
Table 4-32 summarizes the valid D-Flash and EEE commands along with the effects of the commands on
the D-Flash block and EEE operation.
Table 4-32. D-Flash Commands
FCMD
Command
0x01
Erase Verify All
Blocks
0x02
Erase Verify Block
Function on D-Flash Memory
Verify that all D-Flash (and P-Flash) blocks are erased.
Verify that the D-Flash block is erased.
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Table 4-32. D-Flash Commands
FCMD
Command
Function on D-Flash Memory
0x08
Erase All Blocks
Erase all D-Flash (and P-Flash) blocks.
An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN
bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are
set prior to launching the command.
0x0B
Unsecure Flash
Supports a method of releasing MCU security by erasing all D-Flash (and P-Flash) blocks
and verifying that all D-Flash (and P-Flash) blocks are erased.
0x0D
Set User Margin
Level
Specifies a user margin read level for the D-Flash block.
0x0E
Set Field Margin
Level
Specifies a field margin read level for the D-Flash block (special modes only).
0x0F
Full Partition DFlash
Erase the D-Flash block and partition an area of the D-Flash block for user access.
0x10
Erase Verify DFlash Section
Verify that a given number of words starting at the address provided are erased.
0x11
Program D-Flash
Program up to four words in the D-Flash block.
0x12
Erase D-Flash
Sector
Erase all bytes in a sector of the D-Flash block.
0x13
Enable EEPROM
Emulation
Enable EEPROM emulation where writes to the buffer RAM EEE partition will be copied
to the D-Flash EEE partition.
0x14
Disable EEPROM
Emulation
Suspend all current erase and program activity related to EEPROM emulation but leave
current EEE tags set.
0x15
EEPROM
Emulation Query
Returns EEE partition and status variables.
0x20
Partition D-Flash
Partition an area of the D-Flash block for user access.
4.4.2
Flash Command Description
This section provides details of all available Flash commands launched by a command write sequence. The
ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following
illegal steps are performed, causing the command not to be processed by the Memory Controller:
• Starting any command write sequence that programs or erases Flash memory before initializing the
FCLKDIV register
• Writing an invalid command as part of the command write sequence
• For additional possible errors, refer to the error handling table provided for each command
If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation
will return invalid data. If the SFDIF or DFDIF flags were not previously set when the invalid read
operation occurred, both the SFDIF and DFDIF flags will be set and the FECCR registers will be loaded
with the global address used in the invalid read operation with the data and parity fields set to all 0.
If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting
any command write sequence (see Section 4.3.2.7).
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CAUTION
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
4.4.2.1
Erase Verify All Blocks Command
The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased.
Table 4-33. Erase Verify All Blocks Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x01
Not required
Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify
that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks
operation has completed.
Table 4-34. Erase Verify All Blocks Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if a Load Data Field command sequence is currently active
FSTAT
FPVIOL
None
MGSTAT1
Set if any errors have been encountered during the read(1)
MGSTAT0
Set if any non-correctable errors have been encountered during the read1
FERSTAT
EPVIOLIF
None
1. As found in the memory map for FTM512K3.
4.4.2.2
Erase Verify Block Command
The Erase Verify Block command allows the user to verify that an entire P-Flash or D-Flash block has been
erased. The FCCOB upper global address bits determine which block must be verified.
Table 4-35. Erase Verify Block Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x02
Global address [22:16] of the
Flash block to be verified.
Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that
the selected P-Flash or D-Flash block is erased. The CCIF flag will set after the Erase Verify Block
operation has completed.
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Table 4-36. Erase Verify Block Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if a Load Data Field command sequence is currently active
Set if an invalid global address [22:16] is supplied(1)
FSTAT
FPVIOL
None
MGSTAT1
Set if any errors have been encountered during the read(2)
MGSTAT0
Set if any non-correctable errors have been encountered during the read2
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
2. As found in the memory map for FTM512K3.
4.4.2.3
Erase Verify P-Flash Section Command
The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is
erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and
the number of phrases. The section to be verified cannot cross a 256 Kbyte boundary in the P-Flash
memory space.
Table 4-37. Erase Verify P-Flash Section Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x03
Global address [22:16] of
a P-Flash block
001
Global address [15:0] of the first phrase to be verified
010
Number of phrases to be verified
Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will
verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash
Section operation has completed.
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Table 4-38. Erase Verify P-Flash Section Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see Table 4-30)
ACCERR
Set if an invalid global address [22:0] is supplied(1)
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
FSTAT
Set if the requested section crosses a 256 Kbyte boundary
FPVIOL
None
MGSTAT1
Set if any errors have been encountered during the read(2)
MGSTAT0
Set if any non-correctable errors have been encountered during the read2
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
2. As found in the memory map for FTM512K3.
4.4.2.4
Read Once Command
The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the
nonvolatile information register of P-Flash block 0. The Read Once field is programmed using the
Program Once command described in Section 4.4.2.7. The Read Once command must not be executed
from the Flash block containing the Program Once reserved field to avoid code runaway.
Table 4-39. Read Once Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x04
Not Required
001
Read Once phrase index (0x0000 - 0x0007)
010
Read Once word 0 value
011
Read Once word 1 value
100
Read Once word 2 value
101
Read Once word 3 value
Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the
FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid
phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the
Read Once command, any attempt to read addresses within P-Flash block 0 will return invalid data.
128
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Table 4-40. Read Once Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if command not available in current mode (see Table 4-30)
FSTAT
Set if an invalid phrase index is supplied
FPVIOL
FERSTAT
4.4.2.5
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
EPVIOLIF
None
Load Data Field Command
The Load Data Field command is executed to provide FCCOB parameters for multiple P-Flash blocks for
a future simultaneous program operation in the P-Flash memory space.
Table 4-41. Load Data Field Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x05
Global address [22:16] to
identify P-Flash block
001
Global address [15:0] of phrase location to be programmed(1)
010
Word 0
011
Word 1
100
Word 2
101
1. Global address [2:0] must be 000
Word 3
Upon clearing CCIF to launch the Load Data Field command, the FCCOB registers will be transferred to
the Memory Controller and be programmed in the block specified at the global address given with a future
Program P-Flash command launched on a P-Flash block. The CCIF flag will set after the Load Data Field
operation has completed. Note that once a Load Data Field command sequence has been initiated, the Load
Data Field command sequence will be cancelled if any command other than Load Data Field or the future
Program P-Flash is launched. Similarly, if an error occurs after launching a Load Data Field or Program
P-Flash command, the associated Load Data Field command sequence will be cancelled.
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Table 4-42. Load Data Field Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 101 at command launch
Set if command not available in current mode (see Table 4-30)
Set if an invalid global address [22:0] is supplied(1)
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
ACCERR
Set if a Load Data Field command sequence is currently active and the selected
block has previously been selected in the same command sequence
FSTAT
Set if a Load Data Field command sequence is currently active and global
address [17:0] does not match that previously supplied in the same command
sequence
FPVIOL
Set if the global address [22:0] points to a protected area
MGSTAT1
None
MGSTAT0
None
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
4.4.2.6
Program P-Flash Command
The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an
embedded algorithm.
CAUTION
A P-Flash phrase must be in the erased state before being programmed.
Cumulative programming of bits within a Flash phrase is not allowed.
Table 4-43. Program P-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x06
Global address [22:16] to
identify P-Flash block
001
Global address [15:0] of phrase location to be programmed(1)
010
Word 0 program value
011
Word 1 program value
100
Word 2 program value
101
Word 3 program value
1. Global address [2:0] must be 000
Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the
data words to the supplied global address and will then proceed to verify the data words read back as
expected. The CCIF flag will set after the Program P-Flash operation has completed.
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Table 4-44. Program P-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 101 at command launch
Set if command not available in current mode (see Table 4-30)
Set if an invalid global address [22:0] is supplied(1)
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
ACCERR
Set if a Load Data Field command sequence is currently active and the selected
block has previously been selected in the same command sequence
FSTAT
Set if a Load Data Field command sequence is currently active and global
address [17:0] does not match that previously supplied in the same command
sequence
FPVIOL
Set if the global address [22:0] points to a protected area
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
4.4.2.7
Program Once Command
The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the
nonvolatile information register located in P-Flash block 0. The Program Once reserved field can be read
using the Read Once command as described in Section 4.4.2.4. The Program Once command must only
be issued once since the nonvolatile information register in P-Flash block 0 cannot be erased. The Program
Once command must not be executed from the Flash block containing the Program Once reserved field to
avoid code runaway.
Table 4-45. Program Once Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x07
Not Required
001
Program Once phrase index (0x0000 - 0x0007)
010
Program Once word 0 value
011
Program Once word 1 value
100
Program Once word 2 value
101
Program Once word 3 value
Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the
selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with
read back. The CCIF flag will remain clear, setting only after the Program Once operation has completed.
The reserved nonvolatile information register accessed by the Program Once command cannot be erased
and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index
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values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program
Once command, any attempt to read addresses within P-Flash block 0 will return invalid data.
Table 4-46. Program Once Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 101 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if command not available in current mode (see Table 4-30)
Set if an invalid phrase index is supplied
FSTAT
Set if the requested phrase has already been programmed(1)
FPVIOL
None
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
FERSTAT
EPVIOLIF
None
1. If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will
be allowed to execute again on that same phrase.
4.4.2.8
Erase All Blocks Command
The Erase All Blocks operation will erase the entire P-Flash and D-Flash memory space including the EEE
nonvolatile information register.
Table 4-47. Erase All Blocks Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x08
Not required
Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire
Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash
memory space was properly erased, security will be released. During the execution of this command
(CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All
Blocks operation has completed.
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Table 4-48. Erase All Blocks Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see Table 4-30)
FSTAT
FPVIOL
Set if any area of the P-Flash memory is protected
MGSTAT1
Set if any errors have been encountered during the verify operation(1)
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation1
FERSTAT
EPVIOLIF
Set if any area of the buffer RAM EEE partition is protected
1. As found in the memory map for FTM512K3.
4.4.2.9
Erase P-Flash Block Command
The Erase P-Flash Block operation will erase all addresses in a P-Flash block.
Table 4-49. Erase P-Flash Block Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x09
Global address [22:16] to
identify P-Flash block
Global address [15:0] in P-Flash block to be erased
Upon clearing CCIF to launch the Erase P-Flash Block command, the Memory Controller will erase the
selected P-Flash block and verify that it is erased. The CCIF flag will set after the Erase P-Flash Block
operation has completed.
Table 4-50. Erase P-Flash Block Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if command not available in current mode (see Table 4-30)
Set if an invalid global address [22:16] is supplied(1)
FSTAT
FPVIOL
Set if an area of the selected P-Flash block is protected
MGSTAT1
Set if any errors have been encountered during the verify operation(2)
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation2
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
2. As found in the memory map for FTM512K3.
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4.4.2.10
Erase P-Flash Sector Command
The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector.
Table 4-51. Erase P-Flash Sector Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x0A
Global address [22:16] to identify
P-Flash block to be erased
Global address [15:0] anywhere within the sector to be erased.
Refer to Section 4.1.2.1 for the P-Flash sector size.
001
Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the
selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash
Sector operation has completed.
Table 4-52. Erase P-Flash Sector Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if command not available in current mode (see Table 4-30)
Set if an invalid global address [22:16] is supplied(1)
FSTAT
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
FPVIOL
Set if the selected P-Flash sector is protected
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
4.4.2.11
Unsecure Flash Command
The Unsecure Flash command will erase the entire P-Flash and D-Flash memory space and, if the erase is
successful, will release security.
Table 4-53. Unsecure Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x0B
Not required
Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire
P-Flash and D-Flash memory space and verify that it is erased. If the Memory Controller verifies that the
entire Flash memory space was properly erased, security will be released. If the erase verify is not
successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security
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state. During the execution of this command (CCIF=0) the user must not write to any Flash module
register. The CCIF flag is set after the Unsecure Flash operation has completed.
Table 4-54. Unsecure Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see Table 4-30)
FSTAT
FPVIOL
Set if any area of the P-Flash memory is protected
MGSTAT1
Set if any errors have been encountered during the verify operation(1)
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation1
FERSTAT
EPVIOLIF
Set if any area of the buffer RAM EEE partition is protected
1. As found in the memory map for FTM512K3.
4.4.2.12
Verify Backdoor Access Key Command
The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the
FSEC register (see Table 4-11). The Verify Backdoor Access Key command releases security if usersupplied keys match those stored in the Flash security bytes of the Flash configuration field (see Table 43). The Verify Backdoor Access Key command must not be executed from the Flash block containing the
backdoor comparison key to avoid code runaway.
Table 4-55. Verify Backdoor Access Key Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x0C
Not required
001
Key 0
010
Key 1
011
Key 2
100
Key 3
Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will
check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory
Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the
Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash
configuration field with Key 0 compared to 0x7F_FF00, etc. If the backdoor keys match, security will be
released. If the backdoor keys do not match, security is not released and all future attempts to execute the
Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is
set after the Verify Backdoor Access Key operation has completed.
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Table 4-56. Verify Backdoor Access Key Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 100 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if an incorrect backdoor key is supplied
Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see
Section 4.3.2.2)
FSTAT
Set if the backdoor key has mismatched since the last reset
FERSTAT
4.4.2.13
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
Set User Margin Level Command
The Set User Margin Level command causes the Memory Controller to set the margin level for future read
operations of a specific P-Flash or D-Flash block.
Table 4-57. Set User Margin Level Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x0D
001
Global address [22:16] to identify the
Flash block
Margin level setting
Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the
user margin level for the targeted block and then set the CCIF flag.
Valid margin level settings for the Set User Margin Level command are defined in Table 4-58.
Table 4-58. Valid Set User Margin Level Settings
CCOB
(CCOBIX=001)
Level Description
0x0000
Return to Normal Level
0x0001
User Margin-1 Level(1)
0x0002
User Margin-0 Level(2)
1. Read margin to the erased state
2. Read margin to the programmed state
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Table 4-59. Set User Margin Level Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if command not available in current mode (see Table 4-30)
Set if an invalid global address [22:16] is supplied(1)
FSTAT
Set if an invalid margin level setting is supplied
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
NOTE
User margin levels can be used to check that Flash memory contents have
adequate margin for normal level read operations. If unexpected results are
encountered when checking Flash memory contents at user margin levels, a
potential loss of information has been detected.
4.4.2.14
Set Field Margin Level Command
The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set
the margin level specified for future read operations of a specific P-Flash or D-Flash block.
Table 4-60. Set Field Margin Level Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x0E
001
Global address [22:16] to identify the Flash
block
Margin level setting
Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the
field margin level for the targeted block and then set the CCIF flag.
Valid margin level settings for the Set Field Margin Level command are defined in Table 4-61.
Table 4-61. Valid Set Field Margin Level Settings
CCOB
(CCOBIX=001)
Level Description
0x0000
Return to Normal Level
0x0001
User Margin-1 Level(1)
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Table 4-61. Valid Set Field Margin Level Settings
CCOB
(CCOBIX=001)
Level Description
0x0002
User Margin-0 Level(2)
0x0003
Field Margin-1 Level1
0x0004
Field Margin-0 Level2
1. Read margin to the erased state
2. Read margin to the programmed state
Table 4-62. Set Field Margin Level Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if command not available in current mode (see Table 4-30)
Set if an invalid global address [22:16] is supplied(1)
FSTAT
Set if an invalid margin level setting is supplied
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
CAUTION
Field margin levels must only be used during verify of the initial factory
programming.
NOTE
Field margin levels can be used to check that Flash memory contents have
adequate margin for data retention at the normal level setting. If unexpected
results are encountered when checking Flash memory contents at field
margin levels, the Flash memory contents should be erased and
reprogrammed.
4.4.2.15
Full Partition D-Flash Command
The Full Partition D-Flash command allows the user to allocate sectors within the D-Flash block for
applications and a partition within the buffer RAM for EEPROM access. The D-Flash block consists of
128 sectors with 256 bytes per sector.
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Table 4-63. Full Partition D-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x0F
Not required
001
Number of 256 byte sectors for the D-Flash user partition (DFPART)
010
Number of 256 byte sectors for buffer RAM EEE partition (ERPART)
Upon clearing CCIF to launch the Full Partition D-Flash command, the following actions are taken to
define a partition within the D-Flash block for direct access (DFPART) and a partition within the buffer
RAM for EEE use (ERPART):
• Validate the DFPART and ERPART values provided:
— DFPART <= 128 (maximum number of 256 byte sectors in D-Flash block)
— ERPART <= 16 (maximum number of 256 byte sectors in buffer RAM)
— If ERPART > 0, 128 - DFPART >= 12 (minimum number of 256 byte sectors in the D-Flash
block required to support EEE)
— If ERPART > 0, ((128-DFPART)/ERPART) >= 8 (minimum ratio of D-Flash EEE space to
buffer RAM EEE space to support EEE)
• Erase the D-Flash block and the EEE nonvolatile information register
• Program DFPART to the EEE nonvolatile information register at global address 0x12_0000 (see
Table 4-7)
• Program a duplicate DFPART to the EEE nonvolatile information register at global address
0x12_0002 (see Table 4-7)
• Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see
Table 4-7)
• Program a duplicate ERPART to the EEE nonvolatile information register at global address
0x12_0006 (see Table 4-7)
The D-Flash user partition will start at global address 0x10_0000. The buffer RAM EEE partition will end
at global address 0x13_FFFF. After the Full Partition D-Flash operation has completed, the CCIF flag will
set.
Running the Full Partition D-Flash command a second time will result in the previous partition values and
the entire D-Flash memory being erased. The data value written corresponds to the number of 256 byte
sectors allocated for either direct D-Flash access (DFPART) or buffer RAM EEE access (ERPART).
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Table 4-64. Full Partition D-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if command not available in current mode (see Table 4-30)
FSTAT
Set if an invalid DFPART or ERPART selection is supplied
FPVIOL
FERSTAT
4.4.2.16
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
EPVIOLIF
None
Erase Verify D-Flash Section Command
The Erase Verify D-Flash Section command will verify that a section of code in the D-Flash user partition
is erased. The Erase Verify D-Flash Section command defines the starting point of the data to be verified
and the number of words.
Table 4-65. Erase Verify D-Flash Section Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x10
Global address [22:16] to
identify the D-Flash block
001
Global address [15:0] of the first word to be verified
010
Number of words to be verified
Upon clearing CCIF to launch the Erase Verify D-Flash Section command, the Memory Controller will
verify the selected section of D-Flash memory is erased. The CCIF flag will set after the Erase Verify DFlash Section operation has completed.
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Table 4-66. Erase Verify D-Flash Section Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see Table 4-30)
Set if an invalid global address [22:0] is supplied
ACCERR
Set if a misaligned word address is supplied (global address [0] != 0)
FSTAT
Set if the global address [22:0] points to an area of the D-Flash EEE partition
Set if the requested section breaches the end of the D-Flash block or goes into
the D-Flash EEE partition
FPVIOL
FERSTAT
4.4.2.17
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
EPVIOLIF
None
Program D-Flash Command
The Program D-Flash operation programs one to four previously erased words in the D-Flash user
partition. The Program D-Flash operation will confirm that the targeted location(s) were successfully
programmed upon completion.
CAUTION
A Flash word must be in the erased state before being programmed.
Cumulative programming of bits within a Flash word is not allowed.
Table 4-67. Program D-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x11
Global address [22:16] to
identify the D-Flash block
001
Global address [15:0] of word to be programmed
010
Word 0 program value
011
Word 1 program value, if desired
100
Word 2 program value, if desired
101
Word 3 program value, if desired
Upon clearing CCIF to launch the Program D-Flash command, the user-supplied words will be transferred
to the Memory Controller and be programmed. The CCOBIX index value at Program D-Flash command
launch determines how many words will be programmed in the D-Flash block. No protection checks are
made in the Program D-Flash operation on the D-Flash block, only access error checks. The CCIF flag is
set when the operation has completed.
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Table 4-68. Program D-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] < 010 at command launch
Set if CCOBIX[2:0] > 101 at command launch
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see Table 4-30)
ACCERR
Set if an invalid global address [22:0] is supplied
Set if a misaligned word address is supplied (global address [0] != 0)
FSTAT
Set if the global address [22:0] points to an area in the D-Flash EEE partition
Set if the requested group of words breaches the end of the D-Flash block or goes
into the D-Flash EEE partition
FPVIOL
FERSTAT
4.4.2.18
None
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
EPVIOLIF
None
Erase D-Flash Sector Command
The Erase D-Flash Sector operation will erase all addresses in a sector of the D-Flash user partition.
Table 4-69. Erase D-Flash Sector Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x12
Global address [22:16] to identify
D-Flash block
Global address [15:0] anywhere within the sector to be erased.
See Section 4.1.2.2 for D-Flash sector size.
Upon clearing CCIF to launch the Erase D-Flash Sector command, the Memory Controller will erase the
selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase D-Flash Sector
operation has completed.
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Table 4-70. Erase D-Flash Sector Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see Table 4-30)
ACCERR
Set if an invalid global address [22:0] is supplied
Set if a misaligned word address is supplied (global address [0] != 0)
FSTAT
Set if the global address [22:0] points to the D-Flash EEE partition
FPVIOL
FERSTAT
4.4.2.19
None
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
EPVIOLIF
None
Enable EEPROM Emulation Command
The Enable EEPROM Emulation command causes the Memory Controller to enable EEE activity. EEE
activity is disabled after any reset.
Table 4-71. Enable EEPROM Emulation Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x13
Not required
Upon clearing CCIF to launch the Enable EEPROM Emulation command, the CCIF flag will set after the
Memory Controller enables EEE operations using the contents of the EEE tag RAM and tag counter. The
Full Partition D-Flash or the Partition D-Flash command must be run prior to launching the Enable
EEPROM Emulation command.
Table 4-72. Enable EEPROM Emulation Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if a Load Data Field command sequence is currently active
Set if Full Partition D-Flash or Partition D-Flash command not previously run
FSTAT
FERSTAT
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
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4.4.2.20
Disable EEPROM Emulation Command
The Disable EEPROM Emulation command causes the Memory Controller to suspend current EEE
activity.
Table 4-73. Disable EEPROM Emulation Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x14
Not required
Upon clearing CCIF to launch the Disable EEPROM Emulation command, the Memory Controller will
halt EEE operations at the next convenient point without clearing the EEE tag RAM or tag counter before
setting the CCIF flag.
Table 4-74. Disable EEPROM Emulation Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if a Load Data Field command sequence is currently active
Set if Full Partition D-Flash or Partition D-Flash command not previously run
FSTAT
FERSTAT
4.4.2.21
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
EEPROM Emulation Query Command
The EEPROM Emulation Query command returns EEE partition and status variables.
Table 4-75. EEPROM Emulation Query Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x15
Not required
001
Return DFPART
010
Return ERPART
011
Return ECOUNT(1)
100
Return Dead Sector Count
1. Indicates sector erase count
Return Ready Sector Count
Upon clearing CCIF to launch the EEPROM Emulation Query command, the CCIF flag will set after the
EEE partition and status variables are stored in the FCCOBIX register.If the Emulation Query command
is executed prior to partitioning (Partition D-Flash Command Section 4.4.2.15), the following reset values
are returned: DFPART = 0x_FFFF, ERPART = 0x_FFFF, ECOUNT = 0x_FFFF, Dead Sector Count =
0x_00, Ready Sector Count = 0x_00.
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Table 4-76. EEPROM Emulation Query Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see Table 4-30)
FSTAT
FERSTAT
4.4.2.22
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
Partition D-Flash Command
The Partition D-Flash command allows the user to allocate sectors within the D-Flash block for
applications and a partition within the buffer RAM for EEPROM access. The D-Flash block consists of
128 sectors with 256 bytes per sector. The Erase All Blocks command must be run prior to launching the
Partition D-Flash command.
Table 4-77. Partition D-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x20
Not required
001
Number of 256 byte sectors for the D-Flash user partition (DFPART)
010
Number of 256 byte sectors for buffer RAM EEE partition (ERPART)
Upon clearing CCIF to launch the Partition D-Flash command, the following actions are taken to define a
partition within the D-Flash block for direct access (DFPART) and a partition within the buffer RAM for
EEE use (ERPART):
• Validate the DFPART and ERPART values provided:
— DFPART <= 128 (maximum number of 256 byte sectors in D-Flash block)
— ERPART <= 16 (maximum number of 256 byte sectors in buffer RAM)
— If ERPART > 0, 128 - DFPART >= 12 (minimum number of 256 byte sectors in the D-Flash
block required to support EEE)
— If ERPART > 0, ((128-DFPART)/ERPART) >= 8 (minimum ratio of D-Flash EEE space to
buffer RAM EEE space to support EEE)
• Erase verify the D-Flash block and the EEE nonvolatile information register
• Program DFPART to the EEE nonvolatile information register at global address 0x12_0000 (see
Table 4-7)
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•
•
•
Program a duplicate DFPART to the EEE nonvolatile information register at global address
0x12_0002 (see Table 4-7)
Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see
Table 4-7)
Program a duplicate ERPART to the EEE nonvolatile information register at global address
0x12_0006 (see Table 4-7)
The D-Flash user partition will start at global address 0x10_0000. The buffer RAM EEE partition will end
at global address 0x13_FFFF. After the Partition D-Flash operation has completed, the CCIF flag will set.
Running the Partition D-Flash command a second time will result in the ACCERR bit within the FSTAT
register being set. The data value written corresponds to the number of 256 byte sectors allocated for either
direct D-Flash access (DFPART) or buffer RAM EEE access (ERPART).
Table 4-78. Partition D-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if command not available in current mode (see Table 4-30)
Set if partitions have already been defined
FSTAT
Set if an invalid DFPART or ERPART selection is supplied
FPVIOL
FERSTAT
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
EPVIOLIF
None
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4.4.3
Interrupts
The Flash module can generate an interrupt when a Flash command operation has completed or when a
Flash command operation has detected an EEE error or an ECC fault.
Table 4-79. Flash Interrupt Sources
Interrupt Source
Global (CCR)
Mask
Interrupt Flag
Local Enable
CCIF
(FSTAT register)
CCIE
(FCNFG register)
I Bit
Flash EEE Erase Error
ERSERIF
(FERSTAT register)
ERSERIE
(FERCNFG register)
I Bit
Flash EEE Program Error
PGMERIF
(FERSTAT register)
PGMERIE
(FERCNFG register)
I Bit
Flash EEE Protection Violation
EPVIOLIF
(FERSTAT register)
EPVIOLIE
(FERCNFG register)
I Bit
Flash EEE Error Type 1 Violation
ERSVIF1
(FERSTAT register)
ERSVIE1
(FERCNFG register)
I Bit
Flash EEE Error Type 0 Violation
ERSVIF0
(FERSTAT register)
ERSVIE0
(FERCNFG register)
I Bit
ECC Double Bit Fault on Flash Read
DFDIF
(FERSTAT register)
DFDIE
(FERCNFG register)
I Bit
ECC Single Bit Fault on Flash Read
SFDIF
(FERSTAT register)
SFDIE
(FERCNFG register)
I Bit
Flash Command Complete
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
4.4.3.1
Description of Flash Interrupt Operation
The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the
Flash command interrupt request. The Flash module uses the ERSEIF, PGMEIF, EPVIOLIF, ERSVIF1,
ERSVIF0, DFDIF and SFDIF flags in combination with the ERSEIE, PGMEIE, EPVIOLIE, ERSVIE1,
ERSVIE0, DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a
detailed description of the register bits involved, refer to Section 4.3.2.5, “Flash Configuration Register
(FCNFG)”, Section 4.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 4.3.2.7, “Flash
Status Register (FSTAT)”, and Section 4.3.2.8, “Flash Error Status Register (FERSTAT)”.
The logic used for generating the Flash module interrupts is shown in Figure 4-27.
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Chapter 4 384 KByte Flash Module (S12XFTM384K2V1)
Flash Command Interrupt Request
CCIE
CCIF
ERSERIE
ERSERIF
PGMERIE
PGMERIF
EPVIOLIE
EPVIOLIF
Flash Error Interrupt Request
ERSVIE1
ERSVIF1
ERSVIE0
ERSVIF0
DFDIE
DFDIF
SFDIE
SFDIF
Figure 4-27. Flash Module Interrupts Implementation
4.4.4
Wait Mode
The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU
from wait via the CCIF interrupt (see Section 4.4.3, “Interrupts”).
4.4.5
Stop Mode
If a Flash command is active (CCIF = 0) or an EE-Emulation operation is pending when the MCU requests
stop mode, the current Flash operation will be completed before the CPU is allowed to enter stop mode.
4.5
Security
The Flash module provides security information to the MCU. The Flash security state is defined by the
SEC bits of the FSEC register (see Table 4-12). During reset, the Flash module initializes the FSEC
register using data read from the security byte of the Flash configuration field at global address
0x7F_FF0F.
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Chapter 4 384 KByte Flash Module (S12XFTM384K2V1)
The security state out of reset can be permanently changed by programming the security byte of the Flash
configuration field. This assumes that you are starting from a mode where the necessary P-Flash erase and
program commands are available and that the upper region of the P-Flash is unprotected. If the Flash
security byte is successfully programmed, its new value will take affect after the next MCU reset.
The following subsections describe these security-related subjects:
• Unsecuring the MCU using Backdoor Key Access
• Unsecuring the MCU in Special Single Chip Mode using BDM
• Mode and Security Effects on Flash Command Availability
4.5.1
Unsecuring the MCU using Backdoor Key Access
The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the
contents of the backdoor keys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If
the KEYEN[1:0] bits are in the enabled state (see Section 4.3.2.2), the Verify Backdoor Access Key
command (see Section 4.4.2.12) allows the user to present four prospective keys for comparison to the
keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor
Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC
register (see Table 4-12) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not
permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash block 0
will not be available for read access and will return invalid data.
The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an
external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
If the KEYEN[1:0] bits are in the enabled state (see Section 4.3.2.2), the MCU can be unsecured by the
backdoor key access sequence described below:
1. Follow the command sequence for the Verify Backdoor Access Key command as explained in
Section 4.4.2.12
2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the
SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10
The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will
prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method
to re-enable the Verify Backdoor Access Key command.
After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is
unsecured, the sector containing the Flash security byte can be erased and the Flash security byte can be
reprogrammed to the unsecure state, if desired.
In the unsecure state, the user has full control of the contents of the backdoor keys by programming
addresses 0x7F_FF00–0x7F_FF07 in the Flash configuration field.
The security as defined in the Flash security byte (0x7F_FF0F) is not changed by using the Verify
Backdoor Access Key command sequence. The backdoor keys stored in addresses
0x7F_FF00–0x7F_FF07 are unaffected by the Verify Backdoor Access Key command sequence. After the
next reset of the MCU, the security state of the Flash module is determined by the Flash security byte
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Chapter 4 384 KByte Flash Module (S12XFTM384K2V1)
(0x7F_FF0F). The Verify Backdoor Access Key command sequence has no effect on the program and
erase protections defined in the Flash protection register, FPROT.
4.5.2
Unsecuring the MCU in Special Single Chip Mode using BDM
The MCU can be unsecured in special single chip mode by erasing the P-Flash and D-Flash memory by
one of the following methods:
• Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM,
send BDM commands to disable protection in the P-Flash and D-Flash memory, and execute the
Erase All Blocks command write sequence to erase the P-Flash and D-Flash memory.
• Reset the MCU into special expanded wide mode, disable protection in the P-Flash and D-Flash
memory and run code from external memory to execute the Erase All Blocks command write
sequence to erase the P-Flash and D-Flash memory.
After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into
special single chip mode. The BDM will execute the Erase Verify All Blocks command write sequence to
verify that the P-Flash and D-Flash memory is erased. If the P-Flash and D-Flash memory are verified as
erased the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may
be programmed to the unsecure state by the following method:
• Send BDM commands to execute a ‘Program P-Flash’ command sequence to program the Flash
security byte to the unsecured state and reset the MCU.
4.5.3
Mode and Security Effects on Flash Command Availability
The availability of Flash module commands depends on the MCU operating mode and security state as
shown in Table 4-30.
4.6
Initialization
On each system reset the Flash module executes a reset sequence which establishes initial values for the
Flash Block Configuration Parameters, the FPROT and DFPROT protection registers, and the FOPT and
FSEC registers. The Flash module reverts to built-in default values that leave the module in a fully
protected and secured state if errors are encountered during execution of the reset sequence. If a double bit
fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set. The
ACCERR bit in the FSTAT register is set if errors are encountered while initializing the EEE buffer ram
during the reset sequence.
CCIF remains clear throughout the reset sequence. The Flash module holds off all CPU access for the
initial portion of the reset sequence. While Flash reads are possible when the hold is removed, writes to
the FCCOBIX, FCCOBHI, and FCCOBLO registers are ignored to prevent command activity while the
Memory Controller remains busy. Completion of the reset sequence is marked by setting CCIF high which
enables writes to the FCCOBIX, FCCOBHI, and FCCOBLO registers to launch any available Flash
command.
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
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Chapter 5
Pierce Oscillator (S12OSCLCPV2)
Revision History
Revision
Number
Revision
Date
01.05
19-Jul-06
All xclks info was removed
02.00
04-Aug-06
incremented revision to match the design system spec revision
5.1
Author
Description of Changes
Introduction
The Pierce oscillator (XOSC) module provides a robust, low-noise and low-power clock source. The
module will be operated from the VDDPLL supply rail (1.8 V nominal) and require the minimum number
of external components. It is designed for optimal start-up margin with typical crystal oscillators.
5.1.1
Features
The XOSC will contain circuitry to dynamically control current gain in the output amplitude. This ensures
a signal with low harmonic distortion, low power and good noise immunity.
• High noise immunity due to input hysteresis
• Low RF emissions with peak-to-peak swing limited dynamically
• Transconductance (gm) sized for optimum start-up margin for typical oscillators
• Dynamic gain control eliminates the need for external current limiting resistor
• Integrated resistor eliminates the need for external bias resistor in loop controlled Pierce mode.
• Low power consumption:
— Operates from 1.8 V (nominal) supply
— Amplitude control limits power
• Clock monitor
5.1.2
Modes of Operation
Two modes of operation exist:
1. Loop controlled Pierce (LCP) oscillator
2. External square wave mode featuring also full swing Pierce (FSP) without internal bias resistor
The oscillator mode selection is described in the Device Overview section, subsection Oscillator
Configuration.
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Chapter 5 Pierce Oscillator (S12OSCLCPV2)
5.1.3
Block Diagram
Figure 5-1 shows a block diagram of the XOSC.
Monitor_Failure
Clock
Monitor
OSCCLK
Peak
Detector
Gain Control
VDDPLL = 1.8 V
Rf
XTAL
EXTAL
Figure 5-1. XOSC Block Diagram
5.2
External Signal Description
This section lists and describes the signals that connect off chip
5.2.1
VDDPLL and VSSPLL — Operating and Ground Voltage Pins
Theses pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the XOSC circuitry. This
allows the supply voltage to the XOSC to use an independent bypass capacitor.
5.2.2
EXTAL and XTAL — Input and Output Pins
These pins provide the interface for either a crystal or a 1.8V CMOS compatible clock to control the
internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator
amplifier. XTAL is the output of the crystal oscillator amplifier. The MCU internal system clock is derived
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Chapter 5 Pierce Oscillator (S12OSCLCPV2)
from the EXTAL input frequency. In full stop mode (PSTP = 0), the EXTAL pin is pulled down by an
internal resistor of typical 200 kΩ.
NOTE
Freescale recommends an evaluation of the application board and chosen
resonator or crystal by the resonator or crystal supplier.
Loop controlled circuit is not suited for overtone resonators and crystals.
EXTAL
C1
MCU
Crystal or
Ceramic Resonator
XTAL
C2
VSSPLL
Figure 5-2. Loop Controlled Pierce Oscillator Connections (LCP mode selected)
NOTE
Full swing Pierce circuit is not suited for overtone resonators and crystals
without a careful component selection.
EXTAL
C1
MCU
RB
Crystal or
Ceramic Resonator
RS*
XTAL
C2
VSSPLL
* Rs can be zero (shorted) when use with higher frequency crystals.
Refer to manufacturer’s data.
Figure 5-3. Full Swing Pierce Oscillator Connections (FSP mode selected)
EXTAL
CMOS Compatible
External Oscillator
(VDDPLL Level)
MCU
XTAL
Not Connected
Figure 5-4. External Clock Connections (FSP mode selected)
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Chapter 5 Pierce Oscillator (S12OSCLCPV2)
5.3
Memory Map and Register Definition
The CRG contains the registers and associated bits for controlling and monitoring the oscillator module.
5.4
Functional Description
The XOSC module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal
level which is determined by the amount of hysteresis being used and the maximum oscillation range.
The oscillator block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is
intended to be connected to either a crystal or an external clock source. The XTAL pin is an output signal
that provides crystal circuit feedback.
A buffered EXTAL signal becomes the internal clock. To improve noise immunity, the oscillator is
powered by the VDDPLL and VSSPLL power supply pins.
5.4.1
Gain Control
In LCP mode a closed loop control system will be utilized whereby the amplifier is modulated to keep the
output waveform sinusoidal and to limit the oscillation amplitude. The output peak to peak voltage will be
kept above twice the maximum hysteresis level of the input buffer. Electrical specification details are
provided in the Electrical Characteristics appendix.
5.4.2
Clock Monitor
The clock monitor circuit is based on an internal RC time delay so that it can operate without any MCU
clocks. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates failure
which asserts self-clock mode or generates a system reset depending on the state of SCME bit. If the clock
monitor is disabled or the presence of clocks is detected no failure is indicated.The clock monitor function
is enabled/disabled by the CME control bit, described in the CRG block description chapter.
5.4.3
Wait Mode Operation
During wait mode, XOSC is not impacted.
5.4.4
Stop Mode Operation
XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled.
During pseudo-stop mode, XOSC is not impacted.
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Chapter 6
Security (S12XFSECV2)
Revision History
Version
Number
Revision
Date
Effective
Date
01.00
26 Sep
2003
26 Sep
2003
Initial Release
02.00
27 Aug
2004
08 Sep
2004
reviewed and updated for S12XD architecture
02.01
21 Feb
2007
21 Feb
2007
added S12XE, S12XF and S12XS architectures
6.1
Author
Description of Changes
Introduction
This specification describes the function of the security mechanism in the S12XF chip family (SEC).
6.1.1
Features
The user must be reminded that part of the security must lie with the application code. An extreme example
would be application code that dumps the contents of the internal memory. This would defeat the purpose
of security. At the same time, the user may also wish to put a backdoor in the application program. An
example of this is the user downloads a security key through the SCI, which allows access to a
programming routine that updates parameters stored in another section of the Flash memory.
The security features of the S12XDF chip family (in secure mode) are:
• Protect the content of non-volatile memories (Flash, EEPROM)
• Execution of NVM commands is restricted
• Disable access to internal memory via background debug module (BDM)
• Disable access to internal Flash/EEPROM in expanded modes
• Disable debugging features for the CPU and XGATE
Table 6-1 gives an overview over availability of security relevant features in unsecure and secure modes.
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Chapter 6 Security (S12XFSECV2)
Table 6-1. Feature Availability in Unsecure and Secure Modes on S12XF
Unsecure Mode
Secure Mode
NS
SS
NX
ES
EX
ST
NS
SS
NX
ES
EX
ST
Flash Array Access
✔
✔
✔(1)
✔1
✔1
✔1
✔
✔
—
—
—
—
EEPROM Array Access
✔
✔
✔
✔
✔
✔
✔
✔
—
—
—
—
NVM Commands
✔(2)
✔
✔2
✔2
✔2
✔
✔2
✔2
✔2
✔2
✔2
✔2
BDM
✔
✔
✔
✔
✔
✔
—
✔(3)
—
—
—
—
DBG Module Trace
✔
✔
✔
✔
✔
✔
—
—
—
—
—
—
XGATE Debugging
✔
✔
✔
✔
✔
✔
—
—
—
—
—
—
External Bus Interface
—
—
✔
✔
✔
✔
—
—
✔
✔
✔
✔
Internal status visible
multiplexed on
external bus
—
—
—
✔
✔
—
—
—
—
✔
✔
—
Internal accesses visible
—
—
—
—
—
✔
—
—
—
—
—
✔
on external bus
1. Availability of Flash arrays in the memory map depends on ROMCTL/EROMCTL pins and/or the state of the
ROMON/EROMON bits in the MMCCTL1 register. Please refer to the S12X_MMC block guide for detailed
information.
2. Restricted NVM command set only. Please refer to the NVM wrapper block guides for detailed information.
3. BDM hardware commands restricted to peripheral registers only.
6.1.2
Modes of Operation
6.1.3
Securing the Microcontroller
Once the user has programmed the Flash and EEPROM, the chip can be secured by programming the
security bits located in the options/security byte in the Flash memory array. These non-volatile bits will
keep the device secured through reset and power-down.
The options/security byte is located at address 0xFF0F (= global address 0x7F_FF0F) in the Flash memory
array. This byte can be erased and programmed like any other Flash location. Two bits of this byte are used
for security (SEC[1:0]). On devices which have a memory page window, the Flash options/security byte
is also available at address 0xBF0F by selecting page 0x3F with the PPAGE register. The contents of this
byte are copied into the Flash security register (FSEC) during a reset sequence.
0xFF0F
7
6
5
4
3
2
1
0
KEYEN1
KEYEN0
NV5
NV4
NV3
NV2
SEC1
SEC0
Figure 6-1. Flash Options/Security Byte
The meaning of the bits KEYEN[1:0] is shown in Table 6-2. Please refer to Section 6.1.5.1, “Unsecuring
the MCU Using the Backdoor Key Access” for more information.
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Chapter 6 Security (S12XFSECV2)
Table 6-2. Backdoor Key Access Enable Bits
KEYEN[1:0]
Backdoor Key
Access Enabled
00
0 (disabled)
01
0 (disabled)
10
1 (enabled)
11
0 (disabled)
The meaning of the security bits SEC[1:0] is shown in Table 6-3. For security reasons, the state of device
security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to
SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put
the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’.
Table 6-3. Security Bits
SEC[1:0]
Security State
00
1 (secured)
01
1 (secured)
10
0 (unsecured)
11
1 (secured)
NOTE
Please refer to the Flash block guide for actual security configuration (in
section “Flash Module Security”).
6.1.4
Operation of the Secured Microcontroller
By securing the device, unauthorized access to the EEPROM and Flash memory contents can be prevented.
However, it must be understood that the security of the EEPROM and Flash memory contents also depends
on the design of the application program. For example, if the application has the capability of downloading
code through a serial port and then executing that code (e.g. an application containing bootloader code),
then this capability could potentially be used to read the EEPROM and Flash memory contents even when
the microcontroller is in the secure state. In this example, the security of the application could be enhanced
by requiring a challenge/response authentication before any code can be downloaded.
Secured operation has the following effects on the microcontroller:
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Chapter 6 Security (S12XFSECV2)
6.1.4.1
•
•
•
•
Background debug module (BDM) operation is completely disabled.
Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for
details.
Tracing code execution using the DBG module is disabled.
Debugging XGATE code (breakpoints, single-stepping) is disabled.
6.1.4.2
•
•
•
•
•
Normal Single Chip Mode (NS)
Special Single Chip Mode (SS)
BDM firmware commands are disabled.
BDM hardware commands are restricted to the register space.
Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for
details.
Tracing code execution using the DBG module is disabled.
Debugging XGATE code (breakpoints, single-stepping) is disabled.
Special single chip mode means BDM is active after reset. The availability of BDM firmware commands
depends on the security state of the device. The BDM secure firmware first performs a blank check of both
the Flash memory and the EEPROM. If the blank check succeeds, security will be temporarily turned off
and the state of the security bits in the appropriate Flash memory location can be changed If the blank
check fails, security will remain active, only the BDM hardware commands will be enabled, and the
accessible memory space is restricted to the peripheral register area. This will allow the BDM to be used
to erase the EEPROM and Flash memory without giving access to their contents. After erasing both Flash
memory and EEPROM, another reset into special single chip mode will cause the blank check to succeed
and the options/security byte can be programmed to “unsecured” state via BDM.
While the BDM is executing the blank check, the BDM interface is completely blocked, which means that
all BDM commands are temporarily blocked.
6.1.4.3
•
•
•
•
•
Expanded Modes (NX, ES, EX, and ST)
BDM operation is completely disabled.
Internal Flash memory and EEPROM are disabled.
Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for
details.
Tracing code execution using the DBG module is disabled.
Debugging XGATE code (breakpoints, single-stepping) is disabled
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Chapter 6 Security (S12XFSECV2)
6.1.5
Unsecuring the Microcontroller
Unsecuring the microcontroller can be done by three different methods:
1. Backdoor key access
2. Reprogramming the security bits
3. Complete memory erase (special modes)
6.1.5.1
Unsecuring the MCU Using the Backdoor Key Access
In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key
access method. This method requires that:
• The backdoor key at 0xFF00–0xFF07 (= global addresses 0x7F_FF00–0x7F_FF07) has been
programmed to a valid value.
• The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’.
• In single chip mode, the application program programmed into the microcontroller must be
designed to have the capability to write to the backdoor key locations.
The backdoor key values themselves would not normally be stored within the application data, which
means the application program would have to be designed to receive the backdoor key values from an
external source (e.g. through a serial port). It is not possible to download the backdoor keys using
background debug mode.
The backdoor key access method allows debugging of a secured microcontroller without having to erase
the Flash. This is particularly useful for failure analysis.
NOTE
No word of the backdoor key is allowed to have the value 0x0000 or
0xFFFF.
6.1.6
Reprogramming the Security Bits
In normal single chip mode (NS), security can also be disabled by erasing and reprogramming the security
bits within Flash options/security byte to the unsecured value. Because the erase operation will erase the
entire sector from 0xFE00–0xFFFF (0x7F_FE00–0x7F_FFFF), the backdoor key and the interrupt vectors
will also be erased; this method is not recommended for normal single chip mode. The application
software can only erase and program the Flash options/security byte if the Flash sector containing the Flash
options/security byte is not protected (see Flash protection). Thus Flash protection is a useful means of
preventing this method. The microcontroller will enter the unsecured state after the next reset following
the programming of the security bits to the unsecured value.
This method requires that:
• The application software previously programmed into the microcontroller has been designed to
have the capability to erase and program the Flash options/security byte, or security is first disabled
using the backdoor key method, allowing BDM to be used to issue commands to erase and program
the Flash options/security byte.
• The Flash sector containing the Flash options/security byte is not protected.
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Chapter 6 Security (S12XFSECV2)
6.1.7
Complete Memory Erase (Special Modes)
The microcontroller can be unsecured in special modes by erasing the entire EEPROM and Flash memory
contents.
When a secure microcontroller is reset into special single chip mode (SS), the BDM firmware verifies
whether the EEPROM and Flash memory are erased. If any EEPROM or Flash memory address is not
erased, only BDM hardware commands are enabled. BDM hardware commands can then be used to write
to the EEPROM and Flash registers to mass erase the EEPROM and all Flash memory blocks.
When next reset into special single chip mode, the BDM firmware will again verify whether all EEPROM
and Flash memory are erased, and this being the case, will enable all BDM commands, allowing the Flash
options/security byte to be programmed to the unsecured value. The security bits SEC[1:0] in the Flash
security register will indicate the unsecure state following the next reset.
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Chapter 7 Interrupt (S12XINTV2)
Table 7-1. Revision History
Version
Number
Revision
Date
Effective
Date
02.00
01 JUL
2005
01 JUL
2005
initial V2 release, added new features:
- XGATE threads can be interrupted
- SYS instruction vector
- access violation interrupt vectors
02.04
11 JAN
2007
11 JAN
2007
- added Notes for devices without XGATE module
02.05
20 MAR
2007
23 MAR
2007
- fixed priority definition for software exceptions in “1.4.6 Exception
Priority”
02.06
07 JAN
2008
07 JAN
2008
- added clarification of “Wake-up from STOP or WAIT by XIRQ with
X bit set” feature
7.1
Author
Description of Changes
Introduction
The INT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to either the CPU or the XGATE module. The INT module supports:
• I bit and X bit maskable interrupt requests
• One non-maskable unimplemented op-code trap
• One non-maskable software interrupt (SWI) or background debug mode request
• One non-maskable system call interrupt (SYS)
• Three non-maskable access violation interrupt
• One spurious interrupt vector request
• Three system reset vector requests
Each of the I bit maskable interrupt requests can be assigned to one of seven priority levels supporting a
flexible priority scheme. For interrupt requests that are configured to be handled by the CPU, the priority
scheme can be used to implement nested interrupt capability where interrupts from a lower level are
automatically blocked if a higher level interrupt is being processed. Interrupt requests configured to be
handled by the XGATE module can be nested one level deep.
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Chapter 7 Interrupt (S12XINTV2)
NOTE
The HPRIO register and functionality of the original S12 interrupt module
is no longer supported, since it is superseded by the 7-level interrupt request
priority scheme.
7.1.1
Glossary
The following terms and abbreviations are used in the document.
Table 7-2. Terminology
Term
CCR
DMA
INT
IPL
ISR
MCU
XGATE
IRQ
XIRQ
7.1.2
•
•
•
•
•
•
•
•
•
•
•
•
Meaning
Condition Code Register (in the S12X CPU)
Direct Memory Access
Interrupt
Interrupt Processing Level
Interrupt Service Routine
Micro-Controller Unit
refers to the XGATE co-processor; XGATE is an optional feature
refers to the interrupt request associated with the IRQ pin
refers to the interrupt request associated with the XIRQ pin
Features
Interrupt vector base register (IVBR)
One spurious interrupt vector (at address vector base1 + 0x0010).
One non-maskable system call interrupt vector request (at address vector base + 0x0012).
Three non-maskable access violation interrupt vector requests (at address vector base + 0x0014−
0x0018).
2–109 I bit maskable interrupt vector requests (at addresses vector base + 0x001A–0x00F2).
Each I bit maskable interrupt request has a configurable priority level and can be configured to be
handled by either the CPU or the XGATE module2.
I bit maskable interrupts can be nested, depending on their priority levels.
One X bit maskable interrupt vector request (at address vector base + 0x00F4).
One non-maskable software interrupt request (SWI) or background debug mode vector request (at
address vector base + 0x00F6).
One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8).
Three system reset vectors (at addresses 0xFFFA–0xFFFE).
Determines the highest priority XGATE and interrupt vector requests, drives the vector to the
XGATE module or to the bus on CPU request, respectively.
1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used
as upper byte) and 0x00 (used as lower byte).
2. The IRQ interrupt can only be handled by the CPU
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•
•
7.1.3
•
•
•
•
Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or
whenever XIRQ is asserted, even if X interrupt is masked.
XGATE can wake up and execute code, even with the CPU remaining in stop or wait mode.
Modes of Operation
Run mode
This is the basic mode of operation.
Wait mode
In wait mode, the INT module is frozen. It is however capable of either waking up the CPU if an
interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to
Section 7.5.3, “Wake Up from Stop or Wait Mode” for details.
Stop Mode
In stop mode, the INT module is frozen. It is however capable of either waking up the CPU if an
interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to
Section 7.5.3, “Wake Up from Stop or Wait Mode” for details.
Freeze mode (BDM active)
In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please
refer to Section 7.3.2.1, “Interrupt Vector Base Register (IVBR)” for details.
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7.1.4
Block Diagram
Figure 7-1 shows a block diagram of the INT module.
Peripheral
Interrupt Requests
Wake Up
CPU
Non I Bit Maskable
Channels
Interrupt
Requests
Priority
Decoder
IRQ Channel
PRIOLVL2
PRIOLVL1
PRIOLVL0
RQST
IVBR
New
IPL
To CPU
Vector
Address
Current
IPL
One Set Per Channel
(Up to 108 Channels)
INT_XGPRIO
XGATE
Requests
Priority
Decoder
Wake up
XGATE
Vector
ID
XGATE
Interrupts
To XGATE Module
RQST
XGATE Request Route,
PRIOLVLn
Priority Level
= bits from the channel configuration
in the associated configuration register
INT_XGPRIO = XGATE Interrupt Priority
IVBR
= Interrupt Vector Base
IPL
= Interrupt Processing Level
Figure 7-1. INT Block Diagram
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7.2
External Signal Description
The INT module has no external signals.
7.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the INT module.
7.3.1
Module Memory Map
Table 7-3 gives an overview over all INT module registers.
Table 7-3. INT Memory Map
Address
Use
Access
0x0120
RESERVED
—
0x0121
Interrupt Vector Base Register (IVBR)
R/W
0x0122–0x0125
RESERVED
—
0x0126
XGATE Interrupt Priority Configuration Register
(INT_XGPRIO)
R/W
0x0127
Interrupt Request Configuration Address Register
(INT_CFADDR)
R/W
0x0128
Interrupt Request Configuration Data Register 0
(INT_CFDATA0)
R/W
0x0129
Interrupt Request Configuration Data Register 1
(INT_CFDATA1)
R/W
0x012A
Interrupt Request Configuration Data Register 2
(INT_CFDATA2
R/W
0x012B
Interrupt Request Configuration Data Register 3
(INT_CFDATA3)
R/W
0x012C
Interrupt Request Configuration Data Register 4
(INT_CFDATA4)
R/W
0x012D
Interrupt Request Configuration Data Register 5
(INT_CFDATA5)
R/W
0x012E
Interrupt Request Configuration Data Register 6
(INT_CFDATA6)
R/W
0x012F
Interrupt Request Configuration Data Register 7
(INT_CFDATA7)
R/W
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7.3.2
Register Descriptions
This section describes in address order all the INT module registers and their individual bits.
Address
Register
Name
0x0121
IVBR
Bit 7
6
5
R
INT_XGPRIO
R
3
2
0
0
0
0
0
INT_CFADDR
R
R
W
0x0129 INT_CFDATA1
R
W
0x012A INT_CFDATA2
R
W
0x012B INT_CFDATA3
R
W
0x012C INT_CFDATA4
R
W
0x012D INT_CFDATA5
R
W
0x012E INT_CFDATA6
R
W
0x012F INT_CFDATA7
R
W
0
INT_CFADDR[7:4]
W
0x0128 INT_CFDATA0
Bit 0
XILVL[2:0]
W
0x0127
1
IVB_ADDR[7:0]7
W
0x0126
4
RQST
RQST
RQST
RQST
RQST
RQST
RQST
RQST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
= Unimplemented or Reserved
Figure 7-2. INT Register Summary
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7.3.2.1
Interrupt Vector Base Register (IVBR)
Address: 0x0121
7
6
5
R
3
2
1
0
1
1
1
IVB_ADDR[7:0]
W
Reset
4
1
1
1
1
1
Figure 7-3. Interrupt Vector Base Register (IVBR)
Read: Anytime
Write: Anytime
Table 7-4. IVBR Field Descriptions
Field
Description
7–0
Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of
IVB_ADDR[7:0] reset these bits are set to 0xFF (i.e., vectors are located at 0xFF10–0xFFFE) to ensure compatibility to
previous S12 microcontrollers.
Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine
the reset vector address. Therefore, changing the IVBR has no effect on the location of the three reset
vectors (0xFFFA–0xFFFE).
Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of
IVBR are ignored and the upper byte of the vector address is fixed as “0xFF”.
7.3.2.2
XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Address: 0x0126
R
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
2
0
XILVL[2:0]
W
Reset
1
0
0
1
= Unimplemented or Reserved
Figure 7-4. XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Read: Anytime
Write: Anytime
Table 7-5. INT_XGPRIO Field Descriptions
Field
Description
2–0
XILVL[2:0]
XGATE Interrupt Priority Level — The XILVL[2:0] bits configure the shared interrupt level of the XGATE
interrupts coming from the XGATE module. Out of reset the priority is set to the lowest active level (“1”).
Note: If the XGATE module is not available on the device, write accesses to this register are ignored and read
accesses to this register will return all 0.
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Table 7-6. XGATE Interrupt Priority Levels
Priority
low
high
7.3.2.3
XILVL2
XILVL1
XILVL0
Meaning
0
0
0
Interrupt request is disabled
0
0
1
Priority level 1
0
1
0
Priority level 2
0
1
1
Priority level 3
1
0
0
Priority level 4
1
0
1
Priority level 5
1
1
0
Priority level 6
1
1
1
Priority level 7
Interrupt Request Configuration Address Register (INT_CFADDR)
Address: 0x0127
7
R
5
4
INT_CFADDR[7:4]
W
Reset
6
0
0
0
1
3
2
1
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-5. Interrupt Configuration Address Register (INT_CFADDR)
Read: Anytime
Write: Anytime
Table 7-7. INT_CFADDR Field Descriptions
Field
Description
7–4
Interrupt Request Configuration Data Register Select Bits — These bits determine which of the 128
INT_CFADDR[7:4] configuration data registers are accessible in the 8 register window at INT_CFDATA0–7. The hexadecimal
value written to this register corresponds to the upper nibble of the lower byte of the address of the interrupt
vector, i.e., writing 0xE0 to this register selects the configuration data register block for the 8 interrupt vector
requests starting with vector at address (vector base + 0x00E0) to be accessible as INT_CFDATA0–7.
Note: Writing all 0s selects non-existing configuration registers. In this case write accesses to
INT_CFDATA0–7 will be ignored and read accesses will return all 0.
7.3.2.4
Interrupt Request Configuration Data Registers (INT_CFDATA0–7)
The eight register window visible at addresses INT_CFDATA0–7 contains the configuration data for the
block of eight interrupt requests (out of 128) selected by the interrupt configuration address register
(INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt configuration data register
of the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt
configuration data register of the vector with the highest address, respectively.
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Address: 0x0128
7
R
W
Reset
RQST
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
PRIOLVL[2:0]
0
0
1(1)
= Unimplemented or Reserved
Figure 7-6. Interrupt Request Configuration Data Register 0 (INT_CFDATA0)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x0129
7
R
W
Reset
RQST
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
PRIOLVL[2:0]
0
0
1(1)
= Unimplemented or Reserved
Figure 7-7. Interrupt Request Configuration Data Register 1 (INT_CFDATA1)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012A
7
R
W
Reset
RQST
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
PRIOLVL[2:0]
0
0
1(1)
= Unimplemented or Reserved
Figure 7-8. Interrupt Request Configuration Data Register 2 (INT_CFDATA2)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012B
7
R
W
Reset
RQST
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
PRIOLVL[2:0]
0
0
1(1)
= Unimplemented or Reserved
Figure 7-9. Interrupt Request Configuration Data Register 3 (INT_CFDATA3)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012C
7
R
W
Reset
RQST
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
PRIOLVL[2:0]
0
0
1(1)
= Unimplemented or Reserved
Figure 7-10. Interrupt Request Configuration Data Register 4 (INT_CFDATA4)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
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Address: 0x012D
7
R
W
Reset
RQST
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
PRIOLVL[2:0]
0
0
1(1)
= Unimplemented or Reserved
Figure 7-11. Interrupt Request Configuration Data Register 5 (INT_CFDATA5)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012E
7
R
W
Reset
RQST
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
PRIOLVL[2:0]
0
0
1(1)
= Unimplemented or Reserved
Figure 7-12. Interrupt Request Configuration Data Register 6 (INT_CFDATA6)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012F
7
R
W
Reset
RQST
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
PRIOLVL[2:0]
0
0
1(1)
= Unimplemented or Reserved
Figure 7-13. Interrupt Request Configuration Data Register 7 (INT_CFDATA7)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
Read: Anytime
Write: Anytime
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Table 7-8. INT_CFDATA0–7 Field Descriptions
Field
Description
7
RQST
XGATE Request Enable — This bit determines if the associated interrupt request is handled by the CPU or by
the XGATE module.
0 Interrupt request is handled by the CPU
1 Interrupt request is handled by the XGATE module
Note: The IRQ interrupt cannot be handled by the XGATE module. For this reason, the configuration register
for vector (vector base + 0x00F2) = IRQ vector address) does not contain a RQST bit. Writing a 1 to the
location of the RQST bit in this register will be ignored and a read access will return 0.
Note: If the XGATE module is not available on the device, writing a 1 to the location of the RQST bit in this
register will be ignored and a read access will return 0.
2–0
Interrupt Request Priority Level Bits — The PRIOLVL[2:0] bits configure the interrupt request priority level of
PRIOLVL[2:0] the associated interrupt request. Out of reset all interrupt requests are enabled at the lowest active level (“1”)
to provide backwards compatibility with previous S12 interrupt controllers. Please also refer to Table 7-9 for
available interrupt request priority levels.
Note: Write accesses to configuration data registers of unused interrupt channels will be ignored and read
accesses will return all 0. For information about what interrupt channels are used in a specific MCU,
please refer to the Device Reference Manual of that MCU.
Note: When vectors (vector base + 0x00F0–0x00FE) are selected by writing 0xF0 to INT_CFADDR, writes to
INT_CFDATA2–7 (0x00F4–0x00FE) will be ignored and read accesses will return all 0s. The
corresponding vectors do not have configuration data registers associated with them.
Note: When vectors (vector base + 0x0010–0x001E) are selected by writing 0x10 to INT_CFADDR, writes to
INT_CFDATA1–INT_CFDATA4 (0x0012–0x0018) will be ignored and read accesses will return all 0s. The
corresponding vectors do not have configuration data registers associated with them.
Note: Write accesses to the configuration register for the spurious interrupt vector request
(vector base + 0x0010) will be ignored and read accesses will return 0x07 (request is handled by the
CPU, PRIOLVL = 7).
Table 7-9. Interrupt Priority Levels
Priority
low
high
7.4
PRIOLVL2
PRIOLVL1
PRIOLVL0
Meaning
0
0
0
Interrupt request is disabled
0
0
1
Priority level 1
0
1
0
Priority level 2
0
1
1
Priority level 3
1
0
0
Priority level 4
1
0
1
Priority level 5
1
1
0
Priority level 6
1
1
1
Priority level 7
Functional Description
The INT module processes all exception requests to be serviced by the CPU module. These exceptions
include interrupt vector requests and reset vector requests. Each of these exception types and their overall
priority level is discussed in the subsections below.
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7.4.1
S12X Exception Requests
The CPU handles both reset requests and interrupt requests. The INT module contains registers to
configure the priority level of each I bit maskable interrupt request which can be used to implement an
interrupt priority scheme. This also includes the possibility to nest interrupt requests. A priority decoder
is used to evaluate the priority of a pending interrupt request.
7.4.2
Interrupt Prioritization
After system reset all interrupt requests with a vector address lower than or equal to (vector base + 0x00F2)
are enabled, are set up to be handled by the CPU and have a pre-configured priority level of 1. Exceptions
to this rule are the non-maskable interrupt requests and the spurious interrupt vector request at (vector base
+ 0x0010) which cannot be disabled, are always handled by the CPU and have a fixed priority levels. A
priority level of 0 effectively disables the associated I bit maskable interrupt request.
If more than one interrupt request is configured to the same interrupt priority level the interrupt request
with the higher vector address wins the prioritization.
The following conditions must be met for an I bit maskable interrupt request to be processed.
1. The local interrupt enabled bit in the peripheral module must be set.
2. The setup in the configuration register associated with the interrupt request channel must meet the
following conditions:
a) The XGATE request enable bit must be 0 to have the CPU handle the interrupt request.
b) The priority level must be set to non zero.
c) The priority level must be greater than the current interrupt processing level in the condition
code register (CCR) of the CPU (PRIOLVL[2:0] > IPL[2:0]).
3. The I bit in the condition code register (CCR) of the CPU must be cleared.
4. There is no access violation interrupt request pending.
5. There is no SYS, SWI, BDM, TRAP, or XIRQ request pending.
NOTE
All non I bit maskable interrupt requests always have higher priority than
I bit maskable interrupt requests. If an I bit maskable interrupt request is
interrupted by a non I bit maskable interrupt request, the currently active
interrupt processing level (IPL) remains unaffected. It is possible to nest
non I bit maskable interrupt requests, e.g., by nesting SWI or TRAP calls.
7.4.2.1
Interrupt Priority Stack
The current interrupt processing level (IPL) is stored in the condition code register (CCR) of the CPU. This
way the current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The
new IPL is copied to the CCR from the priority level of the highest priority active interrupt request channel
which is configured to be handled by the CPU. The copying takes place when the interrupt vector is
fetched. The previous IPL is automatically restored by executing the RTI instruction.
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7.4.3
XGATE Requests
If the XGATE module is implemented on the device, the INT module is also used to process all exception
requests to be serviced by the XGATE module. The overall priority level of those exceptions is discussed
in the subsections below.
7.4.3.1
XGATE Request Prioritization
An interrupt request channel is configured to be handled by the XGATE module, if the RQST bit of the
associated configuration register is set to 1 (please refer to Section 7.3.2.4, “Interrupt Request
Configuration Data Registers (INT_CFDATA0–7)”). The priority level configuration (PRIOLVL) for this
channel becomes the XGATE priority which will be used to determine the highest priority XGATE request
to be serviced next by the XGATE module. Additionally, XGATE interrupts may be raised by the XGATE
module by setting one or more of the XGATE channel interrupt flags (by using the SIF instruction). This
will result in an CPU interrupt with vector address vector base + (2 * channel ID number), where the
channel ID number corresponds to the highest set channel interrupt flag, if the XGIE and channel RQST
bits are set.
The shared interrupt priority for the XGATE interrupt requests is taken from the XGATE interrupt priority
configuration register (please refer to Section 7.3.2.2, “XGATE Interrupt Priority Configuration Register
(INT_XGPRIO)”). If more than one XGATE interrupt request channel becomes active at the same time,
the channel with the highest vector address wins the prioritization.
7.4.4
Priority Decoders
The INT module contains priority decoders to determine the priority for all interrupt requests pending for
the respective target.
There are two priority decoders, one for each interrupt request target, CPU or XGATE. The function of
both priority decoders is basically the same with one exception: the priority decoder for the XGATE
module does not take the current XGATE thread processing level into account. Instead, XGATE requests
are handed to the XGATE module including a 1-bit priority identifier. The XGATE module uses this
additional information to decide if the new request can interrupt a currently running thread. The 1-bit
priority identifier corresponds to the most significant bit of the priority level configuration of the requesting
channel. This means that XGATE requests with priority levels 4, 5, 6 or 7 can interrupt running XGATE
threads with priority levels 1, 2 and 3.
A CPU interrupt vector is not supplied until the CPU requests it. Therefore, it is possible that a higher
priority interrupt request could override the original exception which caused the CPU to request the vector.
In this case, the CPU will receive the highest priority vector and the system will process this exception
instead of the original request.
If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive
after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the
CPU will default to that of the spurious interrupt vector.
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NOTE
Care must be taken to ensure that all exception requests remain active until
the system begins execution of the applicable service routine; otherwise, the
exception request may not get processed at all or the result may be a
spurious interrupt request (vector at address (vector base + 0x0010)).
7.4.5
Reset Exception Requests
The INT module supports three system reset exception request types (for details please refer to the Clock
and Reset Generator module (CRG)):
1. Pin reset, power-on reset, low-voltage reset, or illegal address reset
2. Clock monitor reset request
3. COP watchdog reset request
7.4.6
Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the INT module upon
request by the CPU is shown in Table 7-10. Generally, all non-maskable interrupts have higher priorities
than maskable interrupts. Please note that between the three software interrupts (Unimplemented op-code
trap request, SWI/BGND request, SYS request) there is no real priority defined because they cannot occur
simultaneously (the S12XCPU executes one instruction at a time).
Table 7-10. Exception Vector Map and Priority
Vector Address(1)
Source
0xFFFE
Pin reset, power-on reset, low-voltage reset, illegal address reset
0xFFFC
Clock monitor reset
0xFFFA
COP watchdog reset
(Vector base + 0x00F8)
Unimplemented op-code trap
(Vector base + 0x00F6)
Software interrupt instruction (SWI) or BDM vector request
(Vector base + 0x0012)
System call interrupt instruction (SYS)
(Vector base + 0x0018)
(reserved for future use)
(Vector base + 0x0016)
XGATE Access violation interrupt request(2)
(Vector base + 0x0014)
CPU Access violation interrupt request(3)
(Vector base + 0x00F4)
XIRQ interrupt request
(Vector base + 0x00F2)
IRQ interrupt request
(Vector base +
0x00F0–0x001A)
Device specific I bit maskable interrupt sources (priority determined by the associated
configuration registers, in descending order)
(Vector base + 0x0010)
Spurious interrupt
1. 16 bits vector address based
2. only implemented if device features both a Memory Protection Unit (MPU) and an XGATE co-processor
3. only implemented if device features a Memory Protection Unit (MPU)
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7.5
7.5.1
Initialization/Application Information
Initialization
After system reset, software should:
• Initialize the interrupt vector base register if the interrupt vector table is not located at the default
location (0xFF10–0xFFF9).
• Initialize the interrupt processing level configuration data registers (INT_CFADDR,
INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels and the request
target (CPU or XGATE module). It might be a good idea to disable unused interrupt requests.
• If the XGATE module is used, setup the XGATE interrupt priority register (INT_XGPRIO) and
configure the XGATE module (please refer the XGATE Block Guide for details).
• Enable I maskable interrupts by clearing the I bit in the CCR.
• Enable the X maskable interrupt by clearing the X bit in the CCR (if required).
7.5.2
Interrupt Nesting
The interrupt request priority level scheme makes it possible to implement priority based interrupt request
nesting for the I bit maskable interrupt requests handled by the CPU.
• I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority,
so that there can be up to seven nested I bit maskable interrupt requests at a time (refer to Figure 714 for an example using up to three nested interrupt requests).
I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per
default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the
I bit in the CCR (CLI). After clearing the I bit, I bit maskable interrupt requests with higher priority can
interrupt the current ISR.
An ISR of an interruptible I bit maskable interrupt request could basically look like this:
• Service interrupt, e.g., clear interrupt flags, copy data, etc.
• Clear I bit in the CCR by executing the instruction CLI (thus allowing interrupt requests with
higher priority)
• Process data
• Return from interrupt by executing the instruction RTI
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Chapter 7 Interrupt (S12XINTV2)
0
Stacked IPL
IPL in CCR
0
0
4
0
0
0
4
7
4
3
1
0
7
6
RTI
L7
5
4
RTI
Processing Levels
3
L3 (Pending)
2
L4
RTI
1
L1 (Pending)
0
RTI
Reset
Figure 7-14. Interrupt Processing Example
7.5.3
7.5.3.1
Wake Up from Stop or Wait Mode
CPU Wake Up from Stop or Wait Mode
Every I bit maskable interrupt request which is configured to be handled by the CPU is capable of waking
the MCU from stop or wait mode. To determine whether an I bit maskable interrupts is qualified to wake
up the CPU or not, the same settings as in normal run mode are applied during stop or wait mode:
• If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking up the MCU.
• An I bit maskable interrupt is ignored if it is configured to a priority level below or equal to the
current IPL in CCR.
• I bit maskable interrupt requests which are configured to be handled by the XGATE module are not
capable of waking up the CPU.
The X bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if the
X bit in CCR is set.
If the X bit maskable interrupt request is used to wake-up the MCU with the X bit in the CCR set, the
associated ISR is not called. The CPU then resumes program execution with the instruction following the
WAI or STOP instruction. This features works following the same rules like any interrupt request, i.e. care
must be taken that the X interrupt request used for wake-up remains active at least until the system begins
execution of the instruction following the WAI or STOP instruction; otherwise, wake-up may not occur.
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Chapter 7 Interrupt (S12XINTV2)
7.5.3.2
XGATE Wake Up from Stop or Wait Mode
Interrupt request channels which are configured to be handled by the XGATE module are capable of
waking up the XGATE module. Interrupt request channels handled by the XGATE module do not affect
the state of the CPU.
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Chapter 7 Interrupt (S12XINTV2)
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Chapter 8
256 KByte Flash Module (S12XFTM256K2XFV1)
Table 8-1. Revision History
Revision
Number
Revision
Date
V01.00
12 Dec 2007
V01.01
19 Dec 2007
Sections
Affected
- Initial version
8.4.2/8-257
8.4.2/8-257
8.4.2/8-257
8.4.2/8-257
8.3.1/8-226
8.1.3/8-224
8.1.2.4/8-224
8.3.1/8-226
V01.02
25 Sep 2009
8.1/8-221
8.3.2.1/8-233
8.4.2.4/8-260
8.4.2.6/8-261
8.4.2.11/8-265
8.4.2.11/8-265
8.4.2.11/8-265
8.4.2.19/8-274
8.3.2/8-231
8.3.2.1/8-233
8.4.1.2/8-252
8.6/8-280
8.1
Description of Changes
- Removed Load Data Field command 0x05
- Updated Command Error Handling tables based on parent-child relationship
with FTM512K3
- Corrected Error Handling table for Full Partition D-Flash, Partition D-Flash,
and EEPROM Emulation Query commands
- Corrected maximum allowed ERPART for Full Partition D-Flash and Partition
D-Flash commands
- Corrected P-Flash IFR Accessibility table
- Corrected Tag RAM size in Block Diagram
- Corrected Buffer RAM size in Feature List
- Added EEE Resource Field table and Memory Map
- Clarify single bit fault correction for P-Flash phrase
- Expand FDIV vs OSCCLK Frequency table
- Add statement concerning code runaway when executing Read Once
command from Flash block containing associated fields
- Add statement concerning code runaway when executing Program Once
command from Flash block containing associated fields
- Add statement concerning code runaway when executing Verify Backdoor
Access Key command from Flash block containing associated fields
- Relate Key 0 to associated Backdoor Comparison Key address
- Change “power down reset” to “reset”
- Add ACCERR condition for Disable EEPROM Emulation command
The following changes were made to clarify module behavior related to Flash
register access during reset sequence and while Flash commands are active:
- Add caution concerning register writes while command is active
- Writes to FCLKDIV are allowed during reset sequence while CCIF is clear
- Add caution concerning register writes while command is active
- Writes to FCCOBIX, FCCOBHI, FCCOBLO registers are ignored during
reset sequence
Introduction
The FTM256K2XF module implements the following:
• 256 Kbytes of P-Flash (Program Flash) memory, consisting of 2 physical Flash blocks, intended
primarily for nonvolatile code storage
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•
•
32 Kbytes of D-Flash (Data Flash) memory, consisting of 1 physical Flash block, that can be used
as nonvolatile storage to support the built-in hardware scheme for emulated EEPROM, as basic
Flash memory primarily intended for nonvolatile data storage, or as a combination of both
2 Kbytes of buffer RAM, consisting of 1 physical RAM block, that can be used as emulated
EEPROM using a built-in hardware scheme, as basic RAM, or as a combination of both
The Flash memory is ideal for single-supply applications allowing for field reprogramming without
requiring external high voltage sources for program or erase operations. The Flash module includes a
memory controller that executes commands to modify Flash memory contents or configure module
resources for emulated EEPROM operation. The user interface to the memory controller consists of the
indexed Flash Common Command Object (FCCOB) register which is written to with the command, global
address, data, and any required command parameters. The memory controller must complete the execution
of a command before the FCCOB register can be written to with a new command.
CAUTION
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
The RAM and Flash memory may be read as bytes, aligned words, or misaligned words. Read access time
is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. For Flash memory,
an erased bit reads 1 and a programmed bit reads 0.
It is not possible to read from a Flash block while any command is executing on that specific Flash block.
It is possible to read from a Flash block while a command is executing on a different Flash block.
Both P-Flash and D-Flash memories are implemented with Error Correction Codes (ECC) that can resolve
single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that
programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read
by phrase, only one single bit fault in the phrase containing the byte or word accessed will be corrected.
8.1.1
Glossary
Buffer RAM — The buffer RAM constitutes the volatile memory store required for EEE. Memory space
in the buffer RAM not required for EEE can be partitioned to provide volatile memory space for
applications.
Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including
program and erase) on the Flash memory.
D-Flash Memory — The D-Flash memory constitutes the nonvolatile memory store required for EEE.
Memory space in the D-Flash memory not required for EEE can be partitioned to provide nonvolatile
memory space for applications.
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Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
D-Flash Sector — The D-Flash sector is the smallest portion of the D-Flash memory that can be erased.
The D-Flash sector consists of four 64 byte rows for a total of 256 bytes.
EEE (Emulated EEPROM) — A method to emulate the small sector size features and endurance
characteristics associated with an EEPROM.
EEE IFR — Nonvolatile information register located in the D-Flash block that contains data required to
partition the D-Flash memory and buffer RAM for EEE. The EEE IFR is visible in the global memory map
by setting the EEEIFRON bit in the MMCCTL1 register.
NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters
required for Flash command execution.
Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes eight
ECC bits for single bit fault correction and double bit fault detection within the phrase.
P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications.
P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased.
Each P-Flash sector contains 1024 bytes.
Program IFR — Nonvolatile information register located in the P-Flash block that contains the Device
ID, Version ID, and the Program Once field. The Program IFR is visible in the global memory map by
setting the PGMIFRON bit in the MMCCTL1 register.
8.1.2
Features
8.1.2.1
•
•
•
•
•
256 Kbytes of P-Flash memory composed of two 128 Kbyte Flash blocks. The 128 Kbyte Flash
blocks are each divided into 128 sectors of 1024 bytes.
Single bit fault correction and double bit fault detection within a 64-bit phrase during read
operations
Automated program and erase algorithm with verify and generation of ECC parity bits
Fast sector erase and phrase program operation
Flexible protection scheme to prevent accidental program or erase of P-Flash memory
8.1.2.2
•
•
•
•
•
•
P-Flash Features
D-Flash Features
Up to 32 Kbytes of D-Flash memory with 256 byte sectors for user access
Dedicated commands to control access to the D-Flash memory over EEE operation
Single bit fault correction and double bit fault detection within a word during read operations
Automated program and erase algorithm with verify and generation of ECC parity bits
Fast sector erase and word program operation
Ability to program up to four words in a burst sequence
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Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
8.1.2.3
•
•
•
•
•
•
•
Up to 2Kbytes of emulated EEPROM (EEE) accessible as 2 Kbytes of RAM
Flexible protection scheme to prevent accidental program or erase of data
Automatic EEE file handling using an internal Memory Controller
Automatic transfer of valid EEE data from D-Flash memory to buffer RAM on reset
Ability to monitor the number of outstanding EEE related buffer RAM words left to be
programmed into D-Flash memory
Ability to disable EEE operation and allow priority access to the D-Flash memory
Ability to cancel all pending EEE operations and allow priority access to the D-Flash memory
8.1.2.4
•
8.1.3
User Buffer RAM Features
Up to 2 Kbytes of RAM for user access
8.1.2.5
•
•
•
Emulated EEPROM Features
Other Flash Module Features
No external high-voltage power supply required for Flash memory program and erase operations
Interrupt generation on Flash command completion and Flash error detection
Security mechanism to prevent unauthorized access to the Flash memory
Block Diagram
The block diagram of the Flash module is shown in Figure 8-1.
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Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
Flash
Interface
Command
Interrupt
Request
Registers
Error
Interrupt
Request
Protection
16bit
internal
bus
P-Flash
Block 0
16Kx72
sector 0
sector 1
sector 127
Security
Oscillator
Clock (XTAL)
XGATE
CPU
P-Flash
Block 1
16Kx72
Clock
Divider FCLK
sector 0
sector 1
Memory
Controller
Scratch RAM
512x16
Buffer RAM
1Kx16
sector 127
D-Flash
16Kx22
sector 0
sector 1
sector 127
Tag RAM
64x16
Figure 8-1. FTM256K2 Block Diagram
8.2
External Signal Description
The Flash module contains no signals that connect off-chip.
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Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
8.3
Memory Map and Registers
This section describes the memory map and registers for the Flash module. Read data from unimplemented
memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space
in the Flash module will be ignored by the Flash module.
8.3.1
Module Memory Map
The S12X architecture places the P-Flash memory between global addresses 0x78_0000 and 0x7F_FFFF
as shown in Table 8-2. The P-Flash memory map is shown in Figure 8-2.
Table 8-2. P-Flash Memory Addressing
Global Address
Size
(Bytes)
0x7E_0000 – 0x7F_FFFF
128 K
P-Flash Block 0
Contains Flash Configuration Field
(see Table 8-3)
0x7A_0000 – 0x7D_FFFF
256 K
No P-Flash Memory
0x78_0000 – 0x79_FFFF
128 K
P-Flash Block 1
Description
The FPROT register, described in Section 8.3.2.9, can be set to protect regions in the Flash memory from
accidental program or erase. Three separate memory regions, one growing upward from global address
0x7F_8000 in the Flash memory (called the lower region), one growing downward from global address
0x7F_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash
memory, can be activated for protection. The Flash memory addresses covered by these protectable regions
are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader
code since it covers the vector space. Default protection settings as well as security information that allows
the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in
Table 8-3.
Table 8-3. Flash Configuration Field(1)
Global Address
Size
(Bytes)
0x7F_FF00 – 0x7F_FF07
8
0x7F_FF08 –
0x7F_FF0B(2)
4
0x7F_FF0C2
1
P-Flash Protection byte.
Refer to Section 8.3.2.9, “P-Flash Protection Register (FPROT)”
0x7F_FF0D2
1
EEE Protection byte
Refer to Section 8.3.2.10, “EEE Protection Register (EPROT)”
0x7F_FF0E2
1
Flash Nonvolatile byte
Refer to Section 8.3.2.14, “Flash Option Register (FOPT)”
Description
Backdoor Comparison Key
Refer to Section 8.4.2.11, “Verify Backdoor Access Key Command,” and
Section 8.5.1, “Unsecuring the MCU using Backdoor Key Access”
Reserved
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Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
Table 8-3. Flash Configuration Field(1)
Global Address
Size
(Bytes)
Description
Flash Security byte
Refer to Section 8.3.2.2, “Flash Security Register (FSEC)”
1. Older versions may have swapped protection byte addresses
2. 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in
the 0x7F_FF08 - 0x7F_FF0B reserved field should be programmed to 0xFF.
0x7F_FF0F2
1
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Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
P-Flash START = 0x78_0000
0x79_FFFF
Flash Protected/Unprotected Region
224 Kbytes
0x7E_0000
0x7F_8000
0x7F_8400
0x7F_8800
0x7F_9000
Flash Protected/Unprotected Lower Region
1, 2, 4, 8 Kbytes
0x7F_A000
Flash Protected/Unprotected Region
8 Kbytes (up to 29 Kbytes)
0x7F_C000
0x7F_E000
Flash Protected/Unprotected Higher Region
2, 4, 8, 16 Kbytes
0x7F_F000
0x7F_F800
P-Flash END = 0x7F_FFFF
Flash Configuration Field
16 bytes (0x7F_FF00 - 0x7F_FF0F)
Figure 8-2. P-Flash Memory Map
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Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
Table 8-4. Program IFR Fields
Global Address
(PGMIFRON)
Size
(Bytes)
0x40_0000 – 0x40_0007
8
Device ID
0x40_0008 – 0x40_00E7
224
Reserved
0x40_00E8 – 0x40_00E9
2
Version ID
0x40_00EA – 0x40_00FF
22
Reserved
0x40_0100 – 0x40_013F
64
Program Once Field
Refer to Section 8.4.2.6, “Program Once Command”
0x40_0140 – 0x40_01FF
192
Reserved
Field Description
Table 8-5. P-Flash IFR Accessibility
Global Address
(PGMIFRON)
Size
(Bytes)
0x40_0000 – 0x40_01FF
512
XBUS0 (PBLK0)(1)
0x40_0200 – 0x40_03FF
512
Unimplemented
0x40_0400 – 0x40_05FF
512
Unimplemented
0x40_0600 – 0x40_07FF
512
1. Refer to Table 8-4 for more details.
Accessed From
XBUS1 (PBLK1)
Table 8-6. EEE Resource Fields
Global Address
Size
(Bytes)
0x10_0000 – 0x10_7FFF
32,768
D-Flash Memory (User and EEE)
0x10_8000 – 0x11_FFFF
98,304
Reserved
0x12_0000 – 0x12_007F
128
0x12_0080 – 0x12_0FFF
3,968
Reserved
0x12_1000 – 0x12_1F7F
3,968
Reserved
0x12_1F80 – 0x12_1FFF
128
0x12_2000 – 0x12_3BFF
7,168
Reserved
0x12_3C00 – 0x12_3FFF
1,024
Memory Controller Scratch RAM (TMGRAMON1 = 1)
0x12_4000 – 0x12_DFFF
40,960
Reserved
0x12_E000 – 0x12_FFFF
8,192
Reserved
0x13_0000 – 0x13_F7FF
63,488
Reserved
0x13_F800 – 0x13_FFFF
1. MMCCTL1 register bit
2,048
Buffer RAM (User and EEE)
Description
EEE Nonvolatile Information Register (EEEIFRON(1) = 1)
EEE Tag RAM (TMGRAMON1 = 1)
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Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
D-Flash START = 0x10_0000
D-Flash User Partition
D-Flash Memory
32 Kbytes
D-Flash EEE Partition
D-Flash END = 0x10_7FFF
0x12_0000
0x12_1000
0x12_2000
0x12_4000
EEE Nonvolatile Information Register (EEEIFRON)
128 bytes
EEE Tag RAM (TMGRAMON)
128 bytes
Memory Controller Scratch RAM (TMGRAMON)
1024 bytes
0x12_E000
0x12_FFFF
Buffer RAM START = 0x13_F800
Buffer RAM User Partition
0x13_FE00
0x13_FE40
0x13_FE80
0x13_FEC0
0x13_FF00
0x13_FF40
0x13_FF80
0x13_FFC0
Buffer RAM END = 0x13_FFFF
Buffer RAM
2 Kbyte
Buffer RAM EEE Partition
Protectable Region (EEE only)
64, 128, 192, 256, 320, 384, 448, 512 bytes
Figure 8-3. EEE Resource Memory Map
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Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
The Full Partition D-Flash command (see Section 8.4.2.14) is used to program the EEE nonvolatile
information register fields where address 0x12_0000 defines the D-Flash partition for user access and
address 0x12_0004 defines the buffer RAM partition for EEE operations.
Table 8-7. EEE Nonvolatile Information Register Fields
Global Address
(EEEIFRON)
Size
(Bytes)
0x12_0000 – 0x12_0001
2
D-Flash User Partition (DFPART)
Refer to Section 8.4.2.14, “Full Partition D-Flash Command”
0x12_0002 – 0x12_0003
2
D-Flash User Partition (duplicate(1))
0x12_0004 – 0x12_0005
2
Buffer RAM EEE Partition (ERPART)
Refer to Section 8.4.2.14, “Full Partition D-Flash Command”
0x12_0006 – 0x12_0007
2
Buffer RAM EEE Partition (duplicate1)
Description
0x12_0008 – 0x12_007F
120
Reserved
1. Duplicate value used if primary value generates a double bit fault when read during the reset sequence.
8.3.2
Register Descriptions
The Flash module contains a set of 20 control and status registers located between Flash module base +
0x0000 and 0x0013. A summary of the Flash module registers is given in Figure 8-4 with detailed
descriptions in the following subsections.
CAUTION
Writes to any Flash register must be avoided while a Flash command is
active (CCIF=0) to prevent corruption of Flash register contents and
Memory Controller behavior.
Address
& Name
0x0000
FCLKDIV
0x0001
FSEC
0x0002
FCCOBIX
0x0003
FECCRIX
0x0004
FCNFG
7
R
6
5
4
3
2
1
0
FDIV6
FDIV5
FDIV4
FDIV3
FDIV2
FDIV1
FDIV0
KEYEN1
KEYEN0
RNV5
RNV4
RNV3
RNV2
SEC1
SEC0
0
0
0
0
0
CCOBIX2
CCOBIX1
CCOBIX0
ECCRIX2
ECCRIX1
ECCRIX0
FDFD
FSFD
FDIVLD
W
R
W
R
W
R
0
0
0
0
0
W
R
0
CCIE
0
0
IGNSF
0
W
Figure 8-4. FTM256K2XF Register Summary
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Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
Address
& Name
0x0005
FERCNFG
0x0006
FSTAT
0x0007
FERSTAT
0x0008
FPROT
0x0009
EPROT
0x000A
FCCOBHI
0x000B
FCCOBLO
0x000C
ETAGHI
0x000D
ETAGLO
0x000E
FECCRHI
0x000F
FECCRLO
0x0010
FOPT
0x0011
FRSV0
0x0012
FRSV1
7
6
ERSERIE
PGMERIE
R
5
4
3
2
1
0
EPVIOLIE
ERSVIE1
ERSVIE0
DFDIE
SFDIE
MGBUSY
RSVD
MGSTAT1
MGSTAT0
EPVIOLIF
ERSVIF1
ERSVIF0
DFDIF
SFDIF
FPHDIS
FPHS1
FPHS0
FPLDIS
FPLS1
FPLS0
RNV5
RNV4
EPDIS
EPS2
EPS1
EPS0
0
W
R
0
CCIF
ACCERR
FPVIOL
W
R
0
ERSERIF
PGMERIF
W
R
RNV6
FPOPEN
W
R
RNV6
EPOPEN
W
R
CCOB15
CCOB14
CCOB13
CCOB12
CCOB11
CCOB10
CCOB9
CCOB8
CCOB7
CCOB6
CCOB5
CCOB4
CCOB3
CCOB2
CCOB1
CCOB0
ETAG15
ETAG14
ETAG13
ETAG12
ETAG11
ETAG10
ETAG9
ETAG8
ETAG7
ETAG6
ETAG5
ETAG4
ETAG3
ETAG2
ETAG1
ETAG0
ECCR15
ECCR14
ECCR13
ECCR12
ECCR11
ECCR10
ECCR9
ECCR8
ECCR7
ECCR6
ECCR5
ECCR4
ECCR3
ECCR2
ECCR1
ECCR0
NV7
NV6
NV5
NV4
NV3
NV2
NV1
NV0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Figure 8-4. FTM256K2XF Register Summary (continued)
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Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
Address
& Name
0x0013
FRSV2
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
W
= Unimplemented or Reserved
Figure 8-4. FTM256K2XF Register Summary (continued)
8.3.2.1
Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
Offset Module Base + 0x0000
7
R
6
5
4
3
2
1
0
0
0
0
FDIVLD
FDIV[6:0]
W
Reset
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-5. Flash Clock Divider Register (FCLKDIV)
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
Table 8-8. FCLKDIV Field Descriptions
Field
7
FDIVLD
6–0
FDIV[6:0]
Description
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms. Table 8-9 shows recommended values for FDIV[6:0] based on OSCCLK frequency.
Please refer to Section 8.4.1, “Flash Command Operations,” for more information.
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
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Table 8-9. FDIV vs OSCCLK Frequency
OSCCLK Frequency
(MHz)
MIN(1)
MAX
FDIV[6:0]
(2)
OSCCLK Frequency
(MHz)
MIN
1
MAX
FDIV[6:0]
2
OSCCLK Frequency
(MHz)
MIN
1
MAX
FDIV[6:0]
2
33.60
34.65
0x20
67.20
68.25
0x40
1.60
2.10
0x01
34.65
35.70
0x21
68.25
69.30
0x41
2.40
3.15
0x02
35.70
36.75
0x22
69.30
70.35
0x42
3.20
4.20
0x03
36.75
37.80
0x23
70.35
71.40
0x43
4.20
5.25
0x04
37.80
38.85
0x24
71.40
72.45
0x44
5.25
6.30
0x05
38.85
39.90
0x25
72.45
73.50
0x45
6.30
7.35
0x06
39.90
40.95
0x26
73.50
74.55
0x46
7.35
8.40
0x07
40.95
42.00
0x27
74.55
75.60
0x47
8.40
9.45
0x08
42.00
43.05
0x28
75.60
76.65
0x48
9.45
10.50
0x09
43.05
44.10
0x29
76.65
77.70
0x49
10.50
11.55
0x0A
44.10
45.15
0x2A
77.70
78.75
0x4A
11.55
12.60
0x0B
45.15
46.20
0x2B
78.75
79.80
0x4B
12.60
13.65
0x0C
46.20
47.25
0x2C
79.80
80.85
0x4C
13.65
14.70
0x0D
47.25
48.30
0x2D
80.85
81.90
0x4D
14.70
15.75
0x0E
48.30
49.35
0x2E
81.90
82.95
0x4E
15.75
16.80
0x0F
49.35
50.40
0x2F
82.95
84.00
0x4F
16.80
17.85
0x10
50.40
51.45
0x30
84.00
85.05
0x50
17.85
18.90
0x11
51.45
52.50
0x31
85.05
86.10
0x51
18.90
19.95
0x12
52.50
53.55
0x32
86.10
87.15
0x52
19.95
21.00
0x13
53.55
54.60
0x33
87.15
88.20
0x53
21.00
22.05
0x14
54.60
55.65
0x34
88.20
89.25
0x54
22.05
23.10
0x15
55.65
56.70
0x35
89.25
90.30
0x55
23.10
24.15
0x16
56.70
57.75
0x36
90.30
91.35
0x56
24.15
25.20
0x17
57.75
58.80
0x37
91.35
92.40
0x57
25.20
26.25
0x18
58.80
59.85
0x38
92.40
93.45
0x58
26.25
27.30
0x19
59.85
60.90
0x39
93.45
94.50
0x59
27.30
28.35
0x1A
60.90
61.95
0x3A
94.50
95.55
0x5A
28.35
29.40
0x1B
61.95
63.00
0x3B
95.55
96.60
0x5B
29.40
30.45
0x1C
63.00
64.05
0x3C
96.60
97.65
0x5C
30.45
31.50
0x1D
64.05
65.10
0x3D
97.65
98.70
0x5D
31.50
32.55
0x1E
65.10
66.15
0x3E
98.70
99.75
0x5E
32.55
33.60
0x1F
66.15
67.20
1. FDIV shown generates an FCLK frequency of >0.8 MHz
0x3F
99.75
100.80
0x5F
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2. FDIV shown generates an FCLK frequency of 1.05 MHz
8.3.2.2
Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
Offset Module Base + 0x0001
7
R
6
5
4
KEYEN[1:0]
3
2
1
RNV[5:2]
0
SEC[1:0]
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 8-6. Flash Security Register (FSEC)
All bits in the FSEC register are readable but not writable.
During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the
Flash configuration field at global address 0x7F_FF0F located in P-Flash memory (see Table 8-3) as
indicated by reset condition F in Figure 8-6. If a double bit fault is detected while reading the P-Flash
phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be
set to leave the Flash module in a secured state with backdoor key access disabled.
Table 8-10. FSEC Field Descriptions
Field
Description
7–6
Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the
KEYEN[1:0] Flash module as shown in Table 8-11.
5–2
RNV[5:2}
Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements.
1–0
SEC[1:0]
Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 8-12. If the
Flash module is unsecured using backdoor key access, the SEC bits are forced to 10.
Table 8-11. Flash KEYEN States
KEYEN[1:0]
Status of Backdoor Key Access
00
DISABLED
01
DISABLED(1)
10
ENABLED
11
DISABLED
1. Preferred KEYEN state to disable backdoor key access.
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Table 8-12. Flash Security States
SEC[1:0]
Status of Security
00
SECURED
01
SECURED(1)
10
UNSECURED
11
SECURED
1. Preferred SEC state to set MCU to secured state.
The security function in the Flash module is described in Section 8.5.
8.3.2.3
Flash CCOB Index Register (FCCOBIX)
The FCCOBIX register is used to index the FCCOB register for Flash memory operations.
Offset Module Base + 0x0002
R
7
6
5
4
3
0
0
0
0
0
2
1
0
CCOBIX[2:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-7. FCCOB Index Register (FCCOBIX)
CCOBIX bits are readable and writable while remaining bits read 0 and are not writable.
Table 8-13. FCCOBIX Field Descriptions
Field
Description
2–0
CCOBIX[1:0]
Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register
array is being read or written to. See Section 8.3.2.11, “Flash Common Command Object Register (FCCOB),”
for more details.
8.3.2.4
Flash ECCR Index Register (FECCRIX)
The FECCRIX register is used to index the FECCR register for ECC fault reporting.
Offset Module Base + 0x0003
R
7
6
5
4
3
0
0
0
0
0
2
1
0
ECCRIX[2:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-8. FECCR Index Register (FECCRIX)
ECCRIX bits are readable and writable while remaining bits read 0 and are not writable.
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Table 8-14. FECCRIX Field Descriptions
Field
Description
2-0
ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is
ECCRIX[2:0] being read. See Section 8.3.2.13, “Flash ECC Error Results Register (FECCR),” for more details.
8.3.2.5
Flash Configuration Register (FCNFG)
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU or XGATE.
Offset Module Base + 0x0004
7
R
6
5
0
0
CCIE
4
3
2
0
0
IGNSF
1
0
FDFD
FSFD
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-9. Flash Configuration Register (FCNFG)
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
Table 8-15. FCNFG Field Descriptions
Field
Description
7
CCIE
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 8.3.2.7)
4
IGNSF
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section 8.3.2.8).
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
generated
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Table 8-15. FCNFG Field Descriptions (continued)
Field
Description
1
FDFD
Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array
read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The
FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual
double bit fault is detected.
0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see
Section 8.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG
register is set (see Section 8.3.2.6)
0
FSFD
Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array
read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. The
FECCR registers will not be updated during the Flash array read operation with FSFD set unless an actual single
bit fault is detected.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 8.3.2.7)
and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section 8.3.2.6)
8.3.2.6
Flash Error Configuration Register (FERCNFG)
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
Offset Module Base + 0x0005
7
6
R
5
4
3
2
1
0
EPVIOLIE
ERSVIE1
ERSVIE0
DFDIE
SFDIE
0
0
0
0
0
0
ERSERIE
PGMERIE
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 8-10. Flash Error Configuration Register (FERCNFG)
All assigned bits in the FERCNFG register are readable and writable.
Table 8-16. FERCNFG Field Descriptions
Field
Description
7
ERSERIE
EEE Erase Error Interrupt Enable — The ERSERIE bit controls interrupt generation when a failure is detected
during an EEE erase operation.
0 ERSERIF interrupt disabled
1 An interrupt will be requested whenever the ERSERIF flag is set (see Section 8.3.2.8)
6
PGMERIE
EEE Program Error Interrupt Enable — The PGMERIE bit controls interrupt generation when a failure is
detected during an EEE program operation.
0 PGMERIF interrupt disabled
1 An interrupt will be requested whenever the PGMERIF flag is set (see Section 8.3.2.8)
4
EPVIOLIE
EEE Protection Violation Interrupt Enable — The EPVIOLIE bit controls interrupt generation when a
protection violation is detected during a write to the buffer RAM EEE partition.
0 EPVIOLIF interrupt disabled
1 An interrupt will be requested whenever the EPVIOLIF flag is set (see Section 8.3.2.8)
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Table 8-16. FERCNFG Field Descriptions (continued)
Field
Description
3
ERSVIE1
EEE Error Type 1 Interrupt Enable — The ERSVIE1 bit controls interrupt generation when a change state error
is detected during an EEE operation.
0 ERSVIF1 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF1 flag is set (see Section 8.3.2.8)
2
ERSVIE0
EEE Error Type 0 Interrupt Enable — The ERSVIE0 bit controls interrupt generation when a sector format error
is detected during an EEE operation.
0 ERSVIF0 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF0 flag is set (see Section 8.3.2.8)
1
DFDIE
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see Section 8.3.2.8)
0
SFDIE
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 8.3.2.8)
1 An interrupt will be requested whenever the SFDIF flag is set (see Section 8.3.2.8)
8.3.2.7
Flash Status Register (FSTAT)
The FSTAT register reports the operational status of the Flash module.
Offset Module Base + 0x0006
7
6
R
5
4
0
CCIF
ACCERR
FPVIOL
0
0
3
2
MGBUSY
RSVD
0
0
1
0
MGSTAT[1:0]
W
Reset
1
0
0(1)
01
= Unimplemented or Reserved
Figure 8-11. Flash Status Register (FSTAT)
1. Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 8.6).
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
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Table 8-17. FSTAT Field Descriptions
Field
Description
7
CCIF
Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The
CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command
completion or command violation.
0 Flash command in progress
1 Flash command has completed
5
ACCERR
Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory
caused by either a violation of the command write sequence (see Section 8.4.1.2) or issuing an illegal Flash
command or when errors are encountered while initializing the EEE buffer ram during the reset sequence.
While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by
writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.
0 No access error detected
1 Access error detected
4
FPVIOL
Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an
address in a protected area of P-Flash memory during a command write sequence. The FPVIOL bit is cleared
by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not
possible to launch a command or start a command write sequence.
0 No protection violation detected
1 Protection violation detected
3
MGBUSY
Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller.
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0) or is handling internal EEE operations
2
RSVD
Reserved Bit — This bit is reserved and always reads 0.
1–0
Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error
MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See Section 8.4.2,
“Flash Command Description,” and Section 8.6, “Initialization” for details.
8.3.2.8
Flash Error Status Register (FERSTAT)
The FERSTAT register reflects the error status of internal Flash operations.
Offset Module Base + 0x0007
7
6
5
ERSERIF
PGMERIF
0
0
R
4
3
2
1
0
EPVIOLIF
ERSVIF1
ERSVIF0
DFDIF
SFDIF
0
0
0
0
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 8-12. Flash Error Status Register (FERSTAT)
All flags in the FERSTAT register are readable and only writable to clear the flag.
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Table 8-18. FERSTAT Field Descriptions
Field
Description
7
ERSERIF
EEE Erase Error Interrupt Flag — The setting of the ERSERIF flag occurs due to an error in a Flash erase
command that resulted in the erase operation not being successful during EEE operations. The ERSERIF flag
is cleared by writing a 1 to ERSERIF. Writing a 0 to the ERSERIF flag has no effect on ERSERIF. While
ERSERIF is set, it is possible to write to the buffer RAM EEE partition but the data written will not be transferred
to the D-Flash EEE partition.
0 Erase command successfully completed on the D-Flash EEE partition
1 Erase command failed on the D-Flash EEE partition
6
PGMERIF
EEE Program Error Interrupt Flag — The setting of the PGMERIF flag occurs due to an error in a Flash
program command that resulted in the program operation not being successful during EEE operations. The
PGMERIF flag is cleared by writing a 1 to PGMERIF. Writing a 0 to the PGMERIF flag has no effect on
PGMERIF. While PGMERIF is set, it is possible to write to the buffer RAM EEE partition but the data written will
not be transferred to the D-Flash EEE partition.
0 Program command successfully completed on the D-Flash EEE partition
1 Program command failed on the D-Flash EEE partition
4
EPVIOLIF
EEE Protection Violation Interrupt Flag —The setting of the EPVIOLIF flag indicates an attempt was made to
write to a protected area of the buffer RAM EEE partition. The EPVIOLIF flag is cleared by writing a 1 to
EPVIOLIF. Writing a 0 to the EPVIOLIF flag has no effect on EPVIOLIF. While EPVIOLIF is set, it is possible to
write to the buffer RAM EEE partition as long as the address written to is not in a protected area.
0 No EEE protection violation
1 EEE protection violation detected
3
ERSVIF1
EEE Error Interrupt 1 Flag —The setting of the ERSVIF1 flag indicates that the memory controller was unable
to change the state of a D-Flash EEE sector. The ERSVIF1 flag is cleared by writing a 1 to ERSVIF1. Writing a
0 to the ERSVIF1 flag has no effect on ERSVIF1. While ERSVIF1 is set, it is possible to write to the buffer RAM
EEE partition but the data written will not be transferred to the D-Flash EEE partition.
0 No EEE sector state change error detected
1 EEE sector state change error detected
2
ERSVIF0
EEE Error Interrupt 0 Flag —The setting of the ERSVIF0 flag indicates that the memory controller was unable
to format a D-Flash EEE sector for EEE use. The ERSVIF0 flag is cleared by writing a 1 to ERSVIF0. Writing a
0 to the ERSVIF0 flag has no effect on ERSVIF0. While ERSVIF0 is set, it is possible to write to the buffer RAM
EEE partition but the data written will not be transferred to the D-Flash EEE partition.
0 No EEE sector format error detected
1 EEE sector format error detected
1
DFDIF
Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was
detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation
was attempted on a Flash block that was under a Flash command operation. The DFDIF flag is cleared by writing
a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.
0 No double bit fault detected
1 Double bit fault detected or an invalid Flash array read operation attempted
0
SFDIF
Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag
indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation
or that a Flash array read operation was attempted on a Flash block that was under a Flash command operation.
The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF.
0 No single bit fault detected
1 Single bit fault detected and corrected or an invalid Flash array read operation attempted
8.3.2.9
P-Flash Protection Register (FPROT)
The FPROT register defines which P-Flash sectors are protected against program and erase operations.
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Offset Module Base + 0x0008
7
R
6
5
4
3
2
1
0
RNV6
FPOPEN
FPHDIS
FPHS[1:0]
FPLDIS
FPLS[1:0]
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 8-13. Flash Protection Register (FPROT)
The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected
region can only be increased (see Section 8.3.2.9.1, “P-Flash Protection Restrictions,” and Table 8-23).
During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte
in the Flash configuration field at global address 0x7F_FF0C located in P-Flash memory (see Table 8-3)
as indicated by reset condition ‘F’ in Figure 8-13. To change the P-Flash protection that will be loaded
during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash
protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase
containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and
remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected.
Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error
and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible
if any of the P-Flash sectors contained in the same P-Flash block are protected.
Table 8-19. FPROT Field Descriptions
Field
Description
7
FPOPEN
Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or
erase operations as shown in Table 8-20 for the P-Flash block.
0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the
corresponding FPHS and FPLS bits
1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the
corresponding FPHS and FPLS bits
6
RNV[6]
Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements.
5
FPHDIS
Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a
protected/unprotected area in a specific region of the P-Flash memory ending with global address 0x7F_FFFF.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
4–3
FPHS[1:0]
Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area
in P-Flash memory as shown inTable 8-21. The FPHS bits can only be written to while the FPHDIS bit is set.
2
FPLDIS
1–0
FPLS[1:0]
Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a
protected/unprotected area in a specific region of the P-Flash memory beginning with global address
0x7F_8000.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area
in P-Flash memory as shown in Table 8-22. The FPLS bits can only be written to while the FPLDIS bit is set.
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Table 8-20. P-Flash Protection Function
Function(1)
FPOPEN
FPHDIS
FPLDIS
1
1
1
No P-Flash Protection
1
1
0
Protected Low Range
1
0
1
Protected High Range
1
0
0
Protected High and Low Ranges
0
1
1
Full P-Flash Memory Protected
0
1
0
Unprotected Low Range
0
0
1
Unprotected High Range
0
0
0
Unprotected High and Low Ranges
1. For range sizes, refer to Table 8-21 and Table 8-22.
Table 8-21. P-Flash Protection Higher Address Range
FPHS[1:0]
Global Address Range
Protected Size
00
0x7F_F800–0x7F_FFFF
2 Kbytes
01
0x7F_F000–0x7F_FFFF
4 Kbytes
10
0x7F_E000–0x7F_FFFF
8 Kbytes
11
0x7F_C000–0x7F_FFFF
16 Kbytes
Table 8-22. P-Flash Protection Lower Address Range
FPLS[1:0]
Global Address Range
Protected Size
00
0x7F_8000–0x7F_83FF
1 Kbyte
01
0x7F_8000–0x7F_87FF
2 Kbytes
10
0x7F_8000–0x7F_8FFF
4 Kbytes
11
0x7F_8000–0x7F_9FFF
8 Kbytes
All possible P-Flash protection scenarios are shown in Figure 8-14. Although the protection scheme is
loaded from the Flash memory at global address 0x7F_FF0C during the reset sequence, it can be changed
by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single
chip mode while providing as much protection as possible if reprogramming is not required.
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FPHDIS = 0
FPLDIS = 1
FPHDIS = 0
FPLDIS = 0
7
6
5
4
3
2
1
0
FPLS[1:0]
FPHDIS = 1
FPLDIS = 0
0x7F_8000
0x7F_FFFF
Scenario
FPHS[1:0]
Scenario
FLASH START
FPHDIS = 1
FPLDIS = 1
FPOPEN = 1
Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
FPHS[1:0]
0x7F_8000
FPOPEN = 0
FPLS[1:0]
FLASH START
0x7F_FFFF
Unprotected region
Protected region with size
defined by FPLS
Protected region
not defined by FPLS, FPHS
Protected region with size
defined by FPHS
Figure 8-14. P-Flash Protection Scenarios
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8.3.2.9.1
P-Flash Protection Restrictions
The general guideline is that P-Flash protection can only be added and not removed. Table 8-23 specifies
all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
Table 8-23. P-Flash Protection Scenario Transitions
To Protection Scenario(1)
From
Protection
Scenario
0
1
2
3
0
X
X
X
X
X
1
X
4
X
X
X
X
X
X
X
X
6
6
7
X
3
5
5
X
X
2
4
X
X
X
X
X
X
X
X
X
X
7
1. Allowed transitions marked with X, see Figure 8-14 for a definition of the scenarios.
8.3.2.10
EEE Protection Register (EPROT)
The EPROT register defines which buffer RAM EEE partition areas are protected against writes.
Offset Module Base + 0x0009
7
6
R
5
4
3
2
1
0
RNV[6:4]
EPOPEN
EPDIS
EPS[2:0]
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 8-15. EEE Protection Register (EPROT)
All bits in the EPROT register are readable and writable except for RNV[6:4] which are only readable. The
EPOPEN and EPDIS bits can only be written to the protected state. The EPS bits can be written anytime
until the EPDIS bit is cleared. If the EPOPEN bit is cleared, the state of the EPDIS and EPS bits is
irrelevant.
During the reset sequence, the EPROT register is loaded from the EEE protection byte in the Flash
configuration field at global address 0x7F_FF0D located in P-Flash memory (see Table 8-3) as indicated
by reset condition F in Figure 8-15. To change the EEE protection that will be loaded during the reset
sequence, the P-Flash sector containing the EEE protection byte must be unprotected, then the EEE
protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase
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Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
containing the EEE protection byte during the reset sequence, the EPOPEN bit will be cleared and
remaining bits in the EPROT register will be set to leave the buffer RAM EEE partition fully protected.
Trying to write data to any protected area in the buffer RAM EEE partition will result in a protection
violation error and the EPVIOLIF flag will be set in the FERSTAT register. Trying to write data to any
protected area in the buffer RAM partitioned for user access will not be prevented and the EPVIOLIF flag
in the FERSTAT register will not set.
Table 8-24. EPROT Field Descriptions
Field
Description
7
EPOPEN
Enables writes to the Buffer RAM partitioned for EEE
0 The entire buffer RAM EEE partition is protected from writes
1 Unprotected buffer RAM EEE partition areas are enabled for writes
6–4
RNV[6:4]
Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements
3
EPDIS
Buffer RAM Protection Address Range Disable — The EPDIS bit determines whether there is a protected
area in a specific region of the buffer RAM EEE partition.
0 Protection enabled
1 Protection disabled
2–0
EPS[2:0]
Buffer RAM Protection Size — The EPS[2:0] bits determine the size of the protected area in the buffer RAM
EEE partition as shown inTable 8-21. The EPS bits can only be written to while the EPDIS bit is set.
Table 8-25. Buffer RAM EEE Partition Protection Address Range
8.3.2.11
EPS[2:0]
Global Address Range
Protected Size
000
0x13_FFC0 – 0x13_FFFF
64 bytes
001
0x13_FF80 – 0x13_FFFF
128 bytes
010
0x13_FF40 – 0x13_FFFF
192 bytes
011
0x13_FF00 – 0x13_FFFF
256 bytes
100
0x13_FEC0 – 0x13_FFFF
320 bytes
101
0x13_FE80 – 0x13_FFFF
384 bytes
110
0x13_FE40 – 0x13_FFFF
448 bytes
111
0x13_FE00 – 0x13_FFFF
512 bytes
Flash Common Command Object Register (FCCOB)
The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register.
Byte wide reads and writes are allowed to the FCCOB register.
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Offset Module Base + 0x000A
7
6
5
4
3
2
1
0
0
0
0
0
R
CCOB[15:8]
W
Reset
0
0
0
0
Figure 8-16. Flash Common Command Object High Register (FCCOBHI)
Offset Module Base + 0x000B
7
6
5
4
3
2
1
0
0
0
0
0
R
CCOB[7:0]
W
Reset
0
0
0
0
Figure 8-17. Flash Common Command Object Low Register (FCCOBLO)
8.3.2.11.1
FCCOB - NVM Command Mode
NVM command mode uses the indexed FCCOB register to provide a command code and its relevant
parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates
the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user
clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register
all FCCOB parameter fields are locked and cannot be changed by the user until the command completes
(as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the
FCCOB register array.
The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 8-26. The
return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by
the Memory Controller. Writes to the unimplemented parameter fields (CCOBIX = 110 and CCOBIX =
111) are ignored with reads from these fields returning 0x0000.
Table 8-26 shows the generic Flash command format. The high byte of the first word in the CCOB array
contains the command code, followed by the parameters for this specific Flash command. For details on
the FCCOB settings required by each command, see the Flash command descriptions in Section 8.4.2.
Table 8-26. FCCOB - NVM Command Mode (Typical Usage)
CCOBIX[2:0]
Byte
FCCOB Parameter Fields (NVM Command Mode)
HI
FCMD[7:0] defining Flash command
LO
0, Global address [22:16]
HI
Global address [15:8]
LO
Global address [7:0]
HI
Data 0 [15:8]
LO
Data 0 [7:0]
000
001
010
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Table 8-26. FCCOB - NVM Command Mode (Typical Usage)
CCOBIX[2:0]
Byte
FCCOB Parameter Fields (NVM Command Mode)
HI
Data 1 [15:8]
LO
Data 1 [7:0]
HI
Data 2 [15:8]
LO
Data 2 [7:0]
HI
Data 3 [15:8]
LO
Data 3 [7:0]
011
100
101
8.3.2.12
EEE Tag Counter Register (ETAG)
The ETAG register contains the number of outstanding words in the buffer RAM EEE partition that need
to be programmed into the D-Flash EEE partition. The ETAG register is decremented prior to the related
tagged word being programmed into the D-Flash EEE partition. All tagged words have been programmed
into the D-Flash EEE partition once all bits in the ETAG register read 0 and the MGBUSY flag in the
FSTAT register reads 0.
Offset Module Base + 0x000C
7
6
5
4
R
3
2
1
0
0
0
0
0
ETAG[15:8]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 8-18. EEE Tag Counter High Register (ETAGHI)
Offset Module Base + 0x000D
7
6
5
4
R
3
2
1
0
0
0
0
0
ETAG[7:0]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 8-19. EEE Tag Counter Low Register (ETAGLO)
All ETAG bits are readable but not writable and are cleared by the Memory Controller.
8.3.2.13
Flash ECC Error Results Register (FECCR)
The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.
The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits
in the FECCRIX register (see Section 8.3.2.4). Once ECC fault information has been stored, no other fault
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information will be recorded until the specific ECC fault flag has been cleared. In the event of
simultaneous ECC faults, the priority for fault recording is:
1. Double bit fault over single bit fault
2. CPU over XGATE
Offset Module Base + 0x000E
7
6
5
4
R
3
2
1
0
0
0
0
0
ECCR[15:8]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 8-20. Flash ECC Error Results High Register (FECCRHI)
Offset Module Base + 0x000F
7
6
5
4
R
3
2
1
0
0
0
0
0
ECCR[7:0]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 8-21. Flash ECC Error Results Low Register (FECCRLO)
All FECCR bits are readable but not writable.
Table 8-27. FECCR Index Settings
ECCRIX[2:0]
000
FECCR Register Content
Bits [15:8]
Bit[7]
Bits[6:0]
Parity bits read from
Flash block
CPU or XGATE
source identity
Global address
[22:16]
001
Global address [15:0]
010
Data 0 [15:0]
011
Data 1 [15:0] (P-Flash only)
100
Data 2 [15:0] (P-Flash only)
101
Data 3 [15:0] (P-Flash only)
110
Not used, returns 0x0000 when read
111
Not used, returns 0x0000 when read
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Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
Table 8-28. FECCR Index=000 Bit Descriptions
Field
Description
15:8
PAR[7:0]
ECC Parity Bits — Contains the 8 parity bits from the 72 bit wide P-Flash data word or the 6 parity bits,
allocated to PAR[5:0], from the 22 bit wide D-Flash word with PAR[7:6]=00.
7
XBUS01
Bus Source Identifier — The XBUS01 bit determines whether the ECC error was caused by a read access
from the CPU or XGATE.
0 ECC Error happened on the CPU access
1 ECC Error happened on the XGATE access
6–0
Global Address — The GADDR[22:16] field contains the upper seven bits of the global address having
GADDR[22:16] caused the error.
The P-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The
following four words addressed by ECCRIX = 010 to 101 contain the 64-bit wide data phrase. The four
data words and the parity byte are the uncorrected data read from the P-Flash block.
The D-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The
uncorrected 16-bit data word is addressed by ECCRIX = 010.
8.3.2.14
Flash Option Register (FOPT)
The FOPT register is the Flash option register.
Offset Module Base + 0x0010
7
6
5
4
R
3
2
1
0
F
F
F
F
NV[7:0]
W
Reset
F
F
F
F
= Unimplemented or Reserved
Figure 8-22. Flash Option Register (FOPT)
All bits in the FOPT register are readable but are not writable.
During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash
configuration field at global address 0x7F_FF0E located in P-Flash memory (see Table 8-3) as indicated
by reset condition F in Figure 8-22. If a double bit fault is detected while reading the P-Flash phrase
containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set.
Table 8-29. FOPT Field Descriptions
Field
Description
7–0
NV[7:0]
Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper
use of the NV bits.
8.3.2.15
Flash Reserved0 Register (FRSV0)
This Flash register is reserved for factory testing.
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Offset Module Base + 0x0011
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 8-23. Flash Reserved0 Register (FRSV0)
All bits in the FRSV0 register read 0 and are not writable.
8.3.2.16
Flash Reserved1 Register (FRSV1)
This Flash register is reserved for factory testing.
Offset Module Base + 0x0012
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 8-24. Flash Reserved1 Register (FRSV1)
All bits in the FRSV1 register read 0 and are not writable.
8.3.2.17
Flash Reserved2 Register (FRSV2)
This Flash register is reserved for factory testing.
Offset Module Base + 0x0013
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 8-25. Flash Reserved2 Register (FRSV2)
All bits in the FRSV2 register read 0 and are not writable.
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Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
8.4
8.4.1
Functional Description
Flash Command Operations
Flash command operations are used to modify Flash memory contents or configure module resources for
EEE operation.
The next sections describe:
• How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from
OSCCLK for Flash program and erase command operations
• The command write sequence used to set Flash command parameters and launch execution
• Valid Flash commands available for execution
8.4.1.1
Writing the FCLKDIV Register
Prior to issuing any Flash program or erase command after a reset, the user is required to write the
FCLKDIV register to divide OSCCLK down to a target FCLK of 1 MHz. Table 8-9 shows recommended
values for the FDIV field based on OSCCLK frequency.
NOTE
Programming or erasing the Flash memory cannot be performed if the bus
clock runs at less than 1 MHz. Setting FDIV too high can destroy the Flash
memory due to overstress. Setting FDIV too low can result in incomplete
programming or erasure of the Flash memory cells.
When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the
FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written,
any Flash program or erase command loaded during a command write sequence will not execute and the
ACCERR bit in the FSTAT register will set.
8.4.1.2
Command Write Sequence
The Memory Controller will launch all valid Flash commands entered using a command write sequence.
Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see
Section 8.3.2.7) and the CCIF flag should be tested to determine the status of the current command write
sequence. If CCIF is 0, the previous command write sequence is still active, a new command write
sequence cannot be started, and all writes to the FCCOB register are ignored.
CAUTION
Writes to any Flash register must be avoided while a Flash command is
active (CCIF=0) to prevent corruption of Flash register contents and
Memory Controller behavior.
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8.4.1.2.1
Define FCCOB Contents
The FCCOB parameter fields must be loaded with all required parameters for the Flash command being
executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX
register (see Section 8.3.2.3).
The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears
the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag
will remain clear until the Flash command has completed. Upon completion, the Memory Controller will
return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic
command write sequence is shown in Figure 8-26.
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Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
START
Read: FCLKDIV register
Clock Register
Written
Check
no
FDIVLD
Set?
yes
Write: FCLKDIV register
Note: FCLKDIV must be set after
each reset
Read: FSTAT register
FCCOB
Availability Check
CCIF
Set?
no
Results from previous Command
yes
Access Error and
Protection Violation
Check
ACCERR/
FPVIOL
Set?
no
yes
Write: FSTAT register
Clear ACCERR/FPVIOL 0x30
Write to FCCOBIX register
to identify specific command
parameter to load.
Write to FCCOB register
to load required command parameter.
More
Parameters?
yes
no
Write: FSTAT register (to launch command)
Clear CCIF 0x80
Read: FSTAT register
Bit Polling for
Command Completion
Check
CCIF Set?
no
yes
EXIT
Figure 8-26. Generic Flash Command Write Sequence Flowchart
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8.4.1.3
Valid Flash Module Commands
Table 8-30. Flash Commands by Mode
Unsecured
FCMD
Command
NS
NX
(1)
(2)
Secured
SS(3) ST(4)
NS
NX
(5)
(6)
SS(7) ST(8)
0x01
Erase Verify All Blocks
∗
∗
∗
∗
∗
∗
∗
∗
0x02
Erase Verify Block
∗
∗
∗
∗
∗
∗
∗
∗
0x03
Erase Verify P-Flash Section
∗
∗
∗
∗
∗
0x04
Read Once
∗
∗
∗
∗
∗
0x05
Reserved
∗
∗
∗
∗
∗
0x06
Program P-Flash
∗
∗
∗
∗
∗
0x07
Program Once
∗
∗
∗
∗
∗
0x08
Erase All Blocks
∗
∗
∗
∗
0x09
Erase P-Flash Block
∗
∗
∗
∗
∗
0x0A
Erase P-Flash Sector
∗
∗
∗
∗
∗
0x0B
Unsecure Flash
∗
∗
∗
∗
0x0C
Verify Backdoor Access Key
∗
0x0D
Set User Margin Level
∗
0x0E
∗
∗
∗
∗
∗
Set Field Margin Level
∗
∗
0x0F
Full Partition D-Flash
∗
∗
0x10
Erase Verify D-Flash Section
∗
∗
∗
∗
∗
0x11
Program D-Flash
∗
∗
∗
∗
∗
0x12
Erase D-Flash Sector
∗
∗
∗
∗
∗
0x13
Enable EEPROM Emulation
∗
∗
∗
∗
∗
∗
∗
∗
0x14
Disable EEPROM Emulation
∗
∗
∗
∗
∗
∗
∗
∗
0x15
EEPROM Emulation Query
∗
∗
∗
∗
∗
∗
∗
∗
0x20
Partition D-Flash
1. Unsecured Normal Single Chip mode.
2. Unsecured Normal Expanded mode.
3. Unsecured Special Single Chip mode.
4. Unsecured Special Mode.
5. Secured Normal Single Chip mode.
6. Secured Normal Expanded mode.
7. Secured Special Single Chip mode.
8. Secured Special Mode.
∗
∗
∗
∗
∗
∗
∗
∗
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8.4.1.4
P-Flash Commands
Table 8-31 summarizes the valid P-Flash commands along with the effects of the commands on the PFlash block and other resources within the Flash module.
Table 8-31. P-Flash Commands
FCMD
Command
0x01
Erase Verify All
Blocks
0x02
Erase Verify Block
0x03
Erase Verify PFlash Section
0x04
Read Once
0x06
Program P-Flash
Function on P-Flash Memory
Verify that all P-Flash (and D-Flash) blocks are erased.
Verify that a P-Flash block is erased.
Verify that a given number of words starting at the address provided are erased.
Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block 0
that was previously programmed using the Program Once command.
Program a phrase in a P-Flash block.
Program Once
Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block
0 that is allowed to be programmed only once.
0x08
Erase All Blocks
Erase all P-Flash (and D-Flash) blocks.
An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN
bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are
set prior to launching the command.
0x09
Erase P-Flash
Block
Erase a single P-Flash block.
An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN
bits in the FPROT register are set prior to launching the command.
0x0A
Erase P-Flash
Sector
0x0B
Unsecure Flash
0x0C
Verify Backdoor
Access Key
Supports a method of releasing MCU security by verifying a set of security keys.
0x0D
Set User Margin
Level
Specifies a user margin read level for all P-Flash blocks.
0x0E
Set Field Margin
Level
Specifies a field margin read level for all P-Flash blocks (special modes only).
0x07
8.4.1.5
Erase all bytes in a P-Flash sector.
Supports a method of releasing MCU security by erasing all P-Flash (and D-Flash) blocks
and verifying that all P-Flash (and D-Flash) blocks are erased.
D-Flash and EEE Commands
Table 8-32 summarizes the valid D-Flash and EEE commands along with the effects of the commands on
the D-Flash block and EEE operation.
Table 8-32. D-Flash Commands
FCMD
Command
0x01
Erase Verify All
Blocks
0x02
Erase Verify Block
0x08
Erase All Blocks
Function on D-Flash Memory
Verify that all D-Flash (and P-Flash) blocks are erased.
Verify that the D-Flash block is erased.
Erase all D-Flash (and P-Flash) blocks.
An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN
bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are
set prior to launching the command.
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Table 8-32. D-Flash Commands
FCMD
Command
Function on D-Flash Memory
0x0B
Unsecure Flash
Supports a method of releasing MCU security by erasing all D-Flash (and P-Flash) blocks
and verifying that all D-Flash (and P-Flash) blocks are erased.
0x0D
Set User Margin
Level
Specifies a user margin read level for the D-Flash block.
0x0E
Set Field Margin
Level
Specifies a field margin read level for the D-Flash block (special modes only).
0x0F
Full Partition DFlash
Erase the D-Flash block and partition an area of the D-Flash block for user access.
0x10
Erase Verify DFlash Section
Verify that a given number of words starting at the address provided are erased.
0x11
Program D-Flash
Program up to four words in the D-Flash block.
0x12
Erase D-Flash
Sector
Erase all bytes in a sector of the D-Flash block.
0x13
Enable EEPROM
Emulation
Enable EEPROM emulation where writes to the buffer RAM EEE partition will be copied
to the D-Flash EEE partition.
0x14
Disable EEPROM
Emulation
Suspend all current erase and program activity related to EEPROM emulation but leave
current EEE tags set.
0x15
EEPROM
Emulation Query
Returns EEE partition and status variables.
0x20
Partition D-Flash
Partition an area of the D-Flash block for user access.
8.4.2
Flash Command Description
This section provides details of all available Flash commands launched by a command write sequence. The
ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following
illegal steps are performed, causing the command not to be processed by the Memory Controller:
• Starting any command write sequence that programs or erases Flash memory before initializing the
FCLKDIV register
• Writing an invalid command as part of the command write sequence
• For additional possible errors, refer to the error handling table provided for each command
If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation
will return invalid data. If the SFDIF or DFDIF flags were not previously set when the invalid read
operation occurred, both the SFDIF and DFDIF flags will be set and the FECCR registers will be loaded
with the global address used in the invalid read operation with the data and parity fields set to all 0.
If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting
any command write sequence (see Section 8.3.2.7).
CAUTION
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
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8.4.2.1
Erase Verify All Blocks Command
The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased.
Table 8-33. Erase Verify All Blocks Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x01
Not required
Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify
that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks
operation has completed.
Table 8-34. Erase Verify All Blocks Command Error Handling
Register
Error Bit
Error Condition
ACCERR
Set if CCOBIX[2:0] != 000 at command launch
FPVIOL
None
FSTAT
MGSTAT1
Set if any errors have been encountered during the read(1)
MGSTAT0
Set if any non-correctable errors have been encountered during the read1
FERSTAT
EPVIOLIF
None
1. As found in the memory map for FTM512K3.
8.4.2.2
Erase Verify Block Command
The Erase Verify Block command allows the user to verify that an entire P-Flash or D-Flash block has been
erased. The FCCOB upper global address bits determine which block must be verified.
Table 8-35. Erase Verify Block Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x02
Global address [22:16] of the
Flash block to be verified.
Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that
the selected P-Flash or D-Flash block is erased. The CCIF flag will set after the Erase Verify Block
operation has completed.
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Table 8-36. Erase Verify Block Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if an invalid global address [22:16] is supplied(1)
FPVIOL
FSTAT
None
MGSTAT1
Set if any errors have been encountered during the read(2)
MGSTAT0
Set if any non-correctable errors have been encountered during the read2
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
2. As found in the memory map for FTM512K3.
8.4.2.3
Erase Verify P-Flash Section Command
The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is
erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and
the number of phrases.
Table 8-37. Erase Verify P-Flash Section Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x03
Global address [22:16] of
a P-Flash block
001
Global address [15:0] of the first phrase to be verified
010
Number of phrases to be verified
Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will
verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash
Section operation has completed.
Table 8-38. Erase Verify P-Flash Section Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
Set if command not available in current mode (see Table 8-30)
ACCERR
Set if an invalid global address [22:0] is supplied(1)
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
FSTAT
Set if the requested section crosses a 256 Kbyte boundary
FPVIOL
FERSTAT
None
MGSTAT1
Set if any errors have been encountered during the read(2)
MGSTAT0
Set if any non-correctable errors have been encountered during the read2
EPVIOLIF
None
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1. As defined by the memory map for FTM512K3.
2. As found in the memory map for FTM512K3.
8.4.2.4
Read Once Command
The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the
nonvolatile information register of P-Flash block 0. The Read Once field is programmed using the
Program Once command described in Section 8.4.2.6. The Read Once command must not be executed
from the Flash block containing the Program Once reserved field to avoid code runaway.
Table 8-39. Read Once Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x04
Not Required
001
Read Once phrase index (0x0000 - 0x0007)
010
Read Once word 0 value
011
Read Once word 1 value
100
Read Once word 2 value
101
Read Once word 3 value
Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the
FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid
phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the
Read Once command, any attempt to read addresses within P-Flash block 0 will return invalid data.
128
Table 8-40. Read Once Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
ACCERR
Set if command not available in current mode (see Table 8-30)
Set if an invalid phrase index is supplied
FSTAT
FPVIOL
FERSTAT
8.4.2.5
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
EPVIOLIF
None
Program P-Flash Command
The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an
embedded algorithm.
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CAUTION
A P-Flash phrase must be in the erased state before being programmed.
Cumulative programming of bits within a Flash phrase is not allowed.
Table 8-41. Program P-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x06
Global address [22:16] to
identify P-Flash block
001
Global address [15:0] of phrase location to be programmed(1)
010
Word 0 program value
011
Word 1 program value
100
Word 2 program value
101
Word 3 program value
1. Global address [2:0] must be 000
Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the
data words to the supplied global address and will then proceed to verify the data words read back as
expected. The CCIF flag will set after the Program P-Flash operation has completed.
Table 8-42. Program P-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 101 at command launch
Set if command not available in current mode (see Table 8-30)
ACCERR
Set if an invalid global address [22:0] is supplied(1)
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
FSTAT
FPVIOL
Set if the global address [22:0] points to a protected area
MGSTAT1
Set if any errors have been encountered during the verify operation(2)
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation2
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
2. As found in the memory map for FTM512K3.
8.4.2.6
Program Once Command
The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the
nonvolatile information register located in P-Flash block 0. The Program Once reserved field can be read
using the Read Once command as described in Section 8.4.2.4. The Program Once command must only
be issued once since the nonvolatile information register in P-Flash block 0 cannot be erased. The Program
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Once command must not be executed from the Flash block containing the Program Once reserved field to
avoid code runaway.
Table 8-43. Program Once Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x07
Not Required
001
Program Once phrase index (0x0000 - 0x0007)
010
Program Once word 0 value
011
Program Once word 1 value
100
Program Once word 2 value
101
Program Once word 3 value
Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the
selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with
read back. The CCIF flag will remain clear, setting only after the Program Once operation has completed.
The reserved nonvolatile information register accessed by the Program Once command cannot be erased
and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index
values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program
Once command, any attempt to read addresses within P-Flash block 0 will return invalid data.
Table 8-44. Program Once Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 101 at command launch
Set if command not available in current mode (see Table 8-30)
ACCERR
Set if an invalid phrase index is supplied
Set if the requested phrase has already been programmed(1)
FSTAT
FPVIOL
None
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
FERSTAT
EPVIOLIF
None
1. If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will
be allowed to execute again on that same phrase.
8.4.2.7
Erase All Blocks Command
The Erase All Blocks operation will erase the entire P-Flash and D-Flash memory space including the EEE
nonvolatile information register.
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Table 8-45. Erase All Blocks Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x08
Not required
Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire
Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash
memory space was properly erased, security will be released. During the execution of this command
(CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All
Blocks operation has completed.
Table 8-46. Erase All Blocks Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if command not available in current mode (see Table 8-30)
FPVIOL
FSTAT
Set if any area of the P-Flash memory is protected
MGSTAT1
Set if any errors have been encountered during the verify operation(1)
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation1
FERSTAT
EPVIOLIF
Set if any area of the buffer RAM EEE partition is protected
1. As found in the memory map for FTM512K3.
8.4.2.8
Erase P-Flash Block Command
The Erase P-Flash Block operation will erase all addresses in a P-Flash block.
Table 8-47. Erase P-Flash Block Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x09
Global address [22:16] to
identify P-Flash block
Global address [15:0] in P-Flash block to be erased
Upon clearing CCIF to launch the Erase P-Flash Block command, the Memory Controller will erase the
selected P-Flash block and verify that it is erased. The CCIF flag will set after the Erase P-Flash Block
operation has completed.
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Table 8-48. Erase P-Flash Block Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
ACCERR
Set if command not available in current mode (see Table 8-30)
Set if an invalid global address [22:16] is supplied(1)
FSTAT
FPVIOL
Set if an area of the selected P-Flash block is protected
MGSTAT1
Set if any errors have been encountered during the verify operation(2)
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation2
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
2. As found in the memory map for FTM512K3.
8.4.2.9
Erase P-Flash Sector Command
The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector.
Table 8-49. Erase P-Flash Sector Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x0A
Global address [22:16] to identify
P-Flash block to be erased
Global address [15:0] anywhere within the sector to be erased.
Refer to Section 8.1.2.1 for the P-Flash sector size.
Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the
selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash
Sector operation has completed.
Table 8-50. Erase P-Flash Sector Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if command not available in current mode (see Table 8-30)
ACCERR
Set if an invalid global address [22:16] is supplied(1)
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
FSTAT
FPVIOL
Set if the selected P-Flash sector is protected
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
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8.4.2.10
Unsecure Flash Command
The Unsecure Flash command will erase the entire P-Flash and D-Flash memory space and, if the erase is
successful, will release security.
Table 8-51. Unsecure Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x0B
Not required
Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire
P-Flash and D-Flash memory space and verify that it is erased. If the Memory Controller verifies that the
entire Flash memory space was properly erased, security will be released. If the erase verify is not
successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security
state. During the execution of this command (CCIF=0) the user must not write to any Flash module
register. The CCIF flag is set after the Unsecure Flash operation has completed.
Table 8-52. Unsecure Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if command not available in current mode (see Table 8-30)
FPVIOL
FSTAT
Set if any area of the P-Flash memory is protected
MGSTAT1
Set if any errors have been encountered during the verify operation(1)
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation1
FERSTAT
EPVIOLIF
Set if any area of the buffer RAM EEE partition is protected
1. As found in the memory map for FTM512K3.
8.4.2.11
Verify Backdoor Access Key Command
The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the
FSEC register (see Table 8-11). The Verify Backdoor Access Key command releases security if usersupplied keys match those stored in the Flash security bytes of the Flash configuration field (see Table 83). The Verify Backdoor Access Key command must not be executed from the Flash block containing the
backdoor comparison key to avoid code runaway.
Table 8-53. Verify Backdoor Access Key Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x0C
Not required
001
Key 0
010
Key 1
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Table 8-53. Verify Backdoor Access Key Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
011
Key 2
100
Key 3
Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will
check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory
Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the
Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash
configuration field with Key 0 compared to 0x7F_FF00, etc. If the backdoor keys match, security will be
released. If the backdoor keys do not match, security is not released and all future attempts to execute the
Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is
set after the Verify Backdoor Access Key operation has completed.
Table 8-54. Verify Backdoor Access Key Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 100 at command launch
Set if an incorrect backdoor key is supplied
ACCERR
FSTAT
FERSTAT
8.4.2.12
Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see
Section 8.3.2.2)
Set if the backdoor key has mismatched since the last reset
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
Set User Margin Level Command
The Set User Margin Level command causes the Memory Controller to set the margin level for future read
operations of a specific P-Flash or D-Flash block.
Table 8-55. Set User Margin Level Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x0D
Global address [22:16] to identify the
Flash block
Margin level setting
Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the
user margin level for the targeted block and then set the CCIF flag.
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Valid margin level settings for the Set User Margin Level command are defined in Table 8-56.
Table 8-56. Valid Set User Margin Level Settings
CCOB
(CCOBIX=001)
Level Description
0x0000
Return to Normal Level
0x0001
User Margin-1 Level(1)
0x0002
User Margin-0 Level(2)
1. Read margin to the erased state
2. Read margin to the programmed state
Table 8-57. Set User Margin Level Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if command not available in current mode (see Table 8-30)
ACCERR
Set if an invalid global address [22:16] is supplied(1)
Set if an invalid margin level setting is supplied
FSTAT
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
NOTE
User margin levels can be used to check that Flash memory contents have
adequate margin for normal level read operations. If unexpected results are
encountered when checking Flash memory contents at user margin levels, a
potential loss of information has been detected.
8.4.2.13
Set Field Margin Level Command
The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set
the margin level specified for future read operations of a specific P-Flash or D-Flash block.
Table 8-58. Set Field Margin Level Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x0E
Global address [22:16] to identify the Flash
block
Margin level setting
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Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the
field margin level for the targeted block and then set the CCIF flag.
Valid margin level settings for the Set Field Margin Level command are defined in Table 8-59.
Table 8-59. Valid Set Field Margin Level Settings
CCOB
(CCOBIX=001)
Level Description
0x0000
Return to Normal Level
0x0001
User Margin-1 Level(1)
0x0002
User Margin-0 Level(2)
0x0003
Field Margin-1 Level1
0x0004
Field Margin-0 Level2
1. Read margin to the erased state
2. Read margin to the programmed state
Table 8-60. Set Field Margin Level Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if command not available in current mode (see Table 8-30)
ACCERR
Set if an invalid global address [22:16] is supplied(1)
Set if an invalid margin level setting is supplied
FSTAT
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
CAUTION
Field margin levels must only be used during verify of the initial factory
programming.
NOTE
Field margin levels can be used to check that Flash memory contents have
adequate margin for data retention at the normal level setting. If unexpected
results are encountered when checking Flash memory contents at field
margin levels, the Flash memory contents should be erased and
reprogrammed.
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8.4.2.14
Full Partition D-Flash Command
The Full Partition D-Flash command allows the user to allocate sectors within the D-Flash block for
applications and a partition within the buffer RAM for EEPROM access. The D-Flash block consists of
128 sectors with 256 bytes per sector.
Table 8-61. Full Partition D-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x0F
Not required
001
Number of 256 byte sectors for the D-Flash user partition (DFPART)
010
Number of 256 byte sectors for buffer RAM EEE partition (ERPART)
Upon clearing CCIF to launch the Full Partition D-Flash command, the following actions are taken to
define a partition within the D-Flash block for direct access (DFPART) and a partition within the buffer
RAM for EEE use (ERPART):
• Validate the DFPART and ERPART values provided:
— DFPART <= 128 (maximum number of 256 byte sectors in D-Flash block)
— ERPART <= 8 (maximum number of 256 byte sectors in buffer RAM)
— If ERPART > 0, 128 - DFPART >= 12 (minimum number of 256 byte sectors in the D-Flash
block required to support EEE)
— If ERPART > 0, ((128-DFPART)/ERPART) >= 8 (minimum ratio of D-Flash EEE space to
buffer RAM EEE space to support EEE)
• Erase the D-Flash block and the EEE nonvolatile information register
• Program DFPART to the EEE nonvolatile information register at global address 0x12_0000 (see
Table 8-7)
• Program a duplicate DFPART to the EEE nonvolatile information register at global address
0x12_0002 (see Table 8-7)
• Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see
Table 8-7)
• Program a duplicate ERPART to the EEE nonvolatile information register at global address
0x12_0006 (see Table 8-7)
The D-Flash user partition will start at global address 0x10_0000. The buffer RAM EEE partition will end
at global address 0x13_FFFF. After the Full Partition D-Flash operation has completed, the CCIF flag will
set.
Running the Full Partition D-Flash command a second time will result in the previous partition values and
the entire D-Flash memory being erased. The data value written corresponds to the number of 256 byte
sectors allocated for either direct D-Flash access (DFPART) or buffer RAM EEE access (ERPART).
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Table 8-62. Full Partition D-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
ACCERR
Set if command not available in current mode (see Table 8-30)
Set if an invalid DFPART or ERPART selection is supplied(1)
FSTAT
FPVIOL
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
FERSTAT
EPVIOLIF
None
1. As defined by the maximum ERPART for FTM512K3.
8.4.2.15
Erase Verify D-Flash Section Command
The Erase Verify D-Flash Section command will verify that a section of code in the D-Flash user partition
is erased. The Erase Verify D-Flash Section command defines the starting point of the data to be verified
and the number of words.
Table 8-63. Erase Verify D-Flash Section Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x10
Global address [22:16] to
identify the D-Flash block
001
Global address [15:0] of the first word to be verified
010
Number of words to be verified
Upon clearing CCIF to launch the Erase Verify D-Flash Section command, the Memory Controller will
verify the selected section of D-Flash memory is erased. The CCIF flag will set after the Erase Verify DFlash Section operation has completed.
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Table 8-64. Erase Verify D-Flash Section Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
Set if command not available in current mode (see Table 8-30)
Set if an invalid global address [22:0] is supplied
ACCERR
Set if a misaligned word address is supplied (global address [0] != 0)
Set if the global address [22:0] points to an area of the D-Flash EEE partition
FSTAT
Set if the requested section breaches the end of the D-Flash block or goes into
the D-Flash EEE partition
FPVIOL
FERSTAT
8.4.2.16
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
EPVIOLIF
None
Program D-Flash Command
The Program D-Flash operation programs one to four previously erased words in the D-Flash user
partition. The Program D-Flash operation will confirm that the targeted location(s) were successfully
programmed upon completion.
CAUTION
A Flash word must be in the erased state before being programmed.
Cumulative programming of bits within a Flash word is not allowed.
Table 8-65. Program D-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x11
Global address [22:16] to
identify the D-Flash block
001
Global address [15:0] of word to be programmed
010
Word 0 program value
011
Word 1 program value, if desired
100
Word 2 program value, if desired
101
Word 3 program value, if desired
Upon clearing CCIF to launch the Program D-Flash command, the user-supplied words will be transferred
to the Memory Controller and be programmed. The CCOBIX index value at Program D-Flash command
launch determines how many words will be programmed in the D-Flash block. No protection checks are
made in the Program D-Flash operation on the D-Flash block, only access error checks. The CCIF flag is
set when the operation has completed.
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Table 8-66. Program D-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] < 010 at command launch
Set if CCOBIX[2:0] > 101 at command launch
Set if command not available in current mode (see Table 8-30)
ACCERR
Set if an invalid global address [22:0] is supplied
Set if a misaligned word address is supplied (global address [0] != 0)
Set if the global address [22:0] points to an area in the D-Flash EEE partition
FSTAT
Set if the requested group of words breaches the end of the D-Flash block or goes
into the D-Flash EEE partition
FPVIOL
FERSTAT
8.4.2.17
None
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
EPVIOLIF
None
Erase D-Flash Sector Command
The Erase D-Flash Sector operation will erase all addresses in a sector of the D-Flash user partition.
Table 8-67. Erase D-Flash Sector Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x12
Global address [22:16] to identify
D-Flash block
Global address [15:0] anywhere within the sector to be erased.
See Section 8.1.2.2 for D-Flash sector size.
Upon clearing CCIF to launch the Erase D-Flash Sector command, the Memory Controller will erase the
selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase D-Flash Sector
operation has completed.
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Table 8-68. Erase D-Flash Sector Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if command not available in current mode (see Table 8-30)
ACCERR
Set if an invalid global address [22:0] is supplied
Set if a misaligned word address is supplied (global address [0] != 0)
FSTAT
Set if the global address [22:0] points to the D-Flash EEE partition
FPVIOL
FERSTAT
8.4.2.18
None
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
EPVIOLIF
None
Enable EEPROM Emulation Command
The Enable EEPROM Emulation command causes the Memory Controller to enable EEE activity. EEE
activity is disabled after any reset.
Table 8-69. Enable EEPROM Emulation Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x13
Not required
Upon clearing CCIF to launch the Enable EEPROM Emulation command, the CCIF flag will set after the
Memory Controller enables EEE operations using the contents of the EEE tag RAM and tag counter. The
Full Partition D-Flash or the Partition D-Flash command must be run prior to launching the Enable
EEPROM Emulation command.
Table 8-70. Enable EEPROM Emulation Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if Full Partition D-Flash or Partition D-Flash command not previously run
FSTAT
FERSTAT
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
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8.4.2.19
Disable EEPROM Emulation Command
The Disable EEPROM Emulation command causes the Memory Controller to suspend current EEE
activity.
Table 8-71. Disable EEPROM Emulation Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x14
Not required
Upon clearing CCIF to launch the Disable EEPROM Emulation command, the Memory Controller will
halt EEE operations at the next convenient point without clearing the EEE tag RAM or tag counter before
setting the CCIF flag.
Table 8-72. Disable EEPROM Emulation Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if Full Partition D-Flash or Partition D-Flash command not previously run
FSTAT
FERSTAT
8.4.2.20
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
EEPROM Emulation Query Command
The EEPROM Emulation Query command returns EEE partition and status variables.
Table 8-73. EEPROM Emulation Query Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x15
Not required
001
Return DFPART
010
Return ERPART
011
Return ECOUNT(1)
100
Return Dead Sector Count
1. Indicates sector erase count
Return Ready Sector Count
Upon clearing CCIF to launch the EEPROM Emulation Query command, the CCIF flag will set after the
EEE partition and status variables are stored in the FCCOBIX register.If the Emulation Query command
is executed prior to partitioning (Partition D-Flash Command Section 8.4.2.14), the following reset values
are returned: DFPART = 0x_FFFF, ERPART = 0x_FFFF, ECOUNT = 0x_FFFF, Dead Sector Count =
0x_00, Ready Sector Count = 0x_00.
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Table 8-74. EEPROM Emulation Query Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if command not available in current mode (see Table 8-30)
FSTAT
FERSTAT
8.4.2.21
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
Partition D-Flash Command
The Partition D-Flash command allows the user to allocate sectors within the D-Flash block for
applications and a partition within the buffer RAM for EEPROM access. The D-Flash block consists of 64
sectors with 256 bytes per sector. The Erase All Blocks command must be run prior to launching the
Partition D-Flash command.
Table 8-75. Partition D-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x20
Not required
001
Number of 256 byte sectors for the D-Flash user partition (DFPART)
010
Number of 256 byte sectors for buffer RAM EEE partition (ERPART)
Upon clearing CCIF to launch the Partition D-Flash command, the following actions are taken to define a
partition within the D-Flash block for direct access (DFPART) and a partition within the buffer RAM for
EEE use (ERPART):
• Validate the DFPART and ERPART values provided:
— DFPART <= 128 (maximum number of 256 byte sectors in D-Flash block)
— ERPART <= 8 (maximum number of 256 byte sectors in buffer RAM)
— If ERPART > 0, 128 - DFPART >= 12 (minimum number of 256 byte sectors in the D-Flash
block required to support EEE)
— If ERPART > 0, ((128-DFPART)/ERPART) >= 8 (minimum ratio of D-Flash EEE space to
buffer RAM EEE space to support EEE)
• Erase verify the D-Flash block and the EEE nonvolatile information register
• Program DFPART to the EEE nonvolatile information register at global address 0x12_0000 (see
Table 8-7)
• Program a duplicate DFPART to the EEE nonvolatile information register at global address
0x12_0002 (see Table 8-7)
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•
•
Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see
Table 8-7)
Program a duplicate ERPART to the EEE nonvolatile information register at global address
0x12_0006 (see Table 8-7)
The D-Flash user partition will start at global address 0x10_0000. The buffer RAM EEE partition will end
at global address 0x13_FFFF. After the Partition D-Flash operation has completed, the CCIF flag will set.
Running the Partition D-Flash command a second time will result in the ACCERR bit within the FSTAT
register being set. The data value written corresponds to the number of 256 byte sectors allocated for either
direct D-Flash access (DFPART) or buffer RAM EEE access (ERPART).
Table 8-76. Partition D-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
Set if command not available in current mode (see Table 8-30)
ACCERR
Set if partitions have already been defined
Set if an invalid DFPART or ERPART selection is supplied(1)
FSTAT
FPVIOL
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
FERSTAT
EPVIOLIF
None
1. As defined by the maximum ERPART for FTM512K3.
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8.4.3
Interrupts
The Flash module can generate an interrupt when a Flash command operation has completed or when a
Flash command operation has detected an EEE error or an ECC fault.
Table 8-77. Flash Interrupt Sources
Interrupt Source
Global (CCR)
Mask
Interrupt Flag
Local Enable
CCIF
(FSTAT register)
CCIE
(FCNFG register)
I Bit
Flash EEE Erase Error
ERSERIF
(FERSTAT register)
ERSERIE
(FERCNFG register)
I Bit
Flash EEE Program Error
PGMERIF
(FERSTAT register)
PGMERIE
(FERCNFG register)
I Bit
Flash EEE Protection Violation
EPVIOLIF
(FERSTAT register)
EPVIOLIE
(FERCNFG register)
I Bit
Flash EEE Error Type 1 Violation
ERSVIF1
(FERSTAT register)
ERSVIE1
(FERCNFG register)
I Bit
Flash EEE Error Type 0 Violation
ERSVIF0
(FERSTAT register)
ERSVIE0
(FERCNFG register)
I Bit
ECC Double Bit Fault on Flash Read
DFDIF
(FERSTAT register)
DFDIE
(FERCNFG register)
I Bit
ECC Single Bit Fault on Flash Read
SFDIF
(FERSTAT register)
SFDIE
(FERCNFG register)
I Bit
Flash Command Complete
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
8.4.3.1
Description of Flash Interrupt Operation
The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the
Flash command interrupt request. The Flash module uses the ERSEIF, PGMEIF, EPVIOLIF, ERSVIF1,
ERSVIF0, DFDIF and SFDIF flags in combination with the ERSEIE, PGMEIE, EPVIOLIE, ERSVIE1,
ERSVIE0, DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a
detailed description of the register bits involved, refer to Section 8.3.2.5, “Flash Configuration Register
(FCNFG)”, Section 8.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 8.3.2.7, “Flash
Status Register (FSTAT)”, and Section 8.3.2.8, “Flash Error Status Register (FERSTAT)”.
The logic used for generating the Flash module interrupts is shown in Figure 8-27.
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Flash Command Interrupt Request
CCIE
CCIF
ERSERIE
ERSERIF
PGMERIE
PGMERIF
EPVIOLIE
EPVIOLIF
Flash Error Interrupt Request
ERSVIE1
ERSVIF1
ERSVIE0
ERSVIF0
DFDIE
DFDIF
SFDIE
SFDIF
Figure 8-27. Flash Module Interrupts Implementation
8.4.4
Wait Mode
The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU
from wait via the CCIF interrupt (see Section 8.4.3, “Interrupts”).
8.4.5
Stop Mode
If a Flash command is active (CCIF = 0) or an EE-Emulation operation is pending when the MCU requests
stop mode, the current Flash operation will be completed before the CPU is allowed to enter stop mode.
8.5
Security
The Flash module provides security information to the MCU. The Flash security state is defined by the
SEC bits of the FSEC register (see Table 8-12). During reset, the Flash module initializes the FSEC
register using data read from the security byte of the Flash configuration field at global address
0x7F_FF0F.
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The security state out of reset can be permanently changed by programming the security byte of the Flash
configuration field. This assumes that you are starting from a mode where the necessary P-Flash erase and
program commands are available and that the upper region of the P-Flash is unprotected. If the Flash
security byte is successfully programmed, its new value will take affect after the next MCU reset.
The following subsections describe these security-related subjects:
• Unsecuring the MCU using Backdoor Key Access
• Unsecuring the MCU in Special Single Chip Mode using BDM
• Mode and Security Effects on Flash Command Availability
8.5.1
Unsecuring the MCU using Backdoor Key Access
The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the
contents of the backdoor keys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If
the KEYEN[1:0] bits are in the enabled state (see Section 8.3.2.2), the Verify Backdoor Access Key
command (see Section 8.4.2.11) allows the user to present four prospective keys for comparison to the
keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor
Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC
register (see Table 8-12) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not
permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash block 0
will not be available for read access and will return invalid data.
The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an
external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
If the KEYEN[1:0] bits are in the enabled state (see Section 8.3.2.2), the MCU can be unsecured by the
backdoor key access sequence described below:
1. Follow the command sequence for the Verify Backdoor Access Key command as explained in
Section 8.4.2.11
2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the
SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10
The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will
prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method
to re-enable the Verify Backdoor Access Key command.
After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is
unsecured, the sector containing the Flash security byte can be erased and the Flash security byte can be
reprogrammed to the unsecure state, if desired.
In the unsecure state, the user has full control of the contents of the backdoor keys by programming
addresses 0x7F_FF00–0x7F_FF07 in the Flash configuration field.
The security as defined in the Flash security byte (0x7F_FF0F) is not changed by using the Verify
Backdoor Access Key command sequence. The backdoor keys stored in addresses
0x7F_FF00–0x7F_FF07 are unaffected by the Verify Backdoor Access Key command sequence. After the
next reset of the MCU, the security state of the Flash module is determined by the Flash security byte
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(0x7F_FF0F). The Verify Backdoor Access Key command sequence has no effect on the program and
erase protections defined in the Flash protection register, FPROT.
8.5.2
Unsecuring the MCU in Special Single Chip Mode using BDM
The MCU can be unsecured in special single chip mode by erasing the P-Flash and D-Flash memory by
one of the following methods:
• Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM,
send BDM commands to disable protection in the P-Flash and D-Flash memory, and execute the
Erase All Blocks command write sequence to erase the P-Flash and D-Flash memory.
• Reset the MCU into special expanded wide mode, disable protection in the P-Flash and D-Flash
memory and run code from external memory to execute the Erase All Blocks command write
sequence to erase the P-Flash and D-Flash memory.
After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into
special single chip mode. The BDM will execute the Erase Verify All Blocks command write sequence to
verify that the P-Flash and D-Flash memory is erased. If the P-Flash and D-Flash memory are verified as
erased the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may
be programmed to the unsecure state by the following method:
• Send BDM commands to execute a ‘Program P-Flash’ command sequence to program the Flash
security byte to the unsecured state and reset the MCU.
8.5.3
Mode and Security Effects on Flash Command Availability
The availability of Flash module commands depends on the MCU operating mode and security state as
shown in Table 8-30.
8.6
Initialization
On each system reset the Flash module executes a reset sequence which establishes initial values for the
Flash Block Configuration Parameters, the FPROT and DFPROT protection registers, and the FOPT and
FSEC registers. The Flash module reverts to built-in default values that leave the module in a fully
protected and secured state if errors are encountered during execution of the reset sequence. If a double bit
fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set. The
ACCERR bit in the FSTAT register is set if errors are encountered while initializing the EEE buffer ram
during the reset sequence.
CCIF remains clear throughout the reset sequence. The Flash module holds off all CPU access for the
initial portion of the reset sequence. While Flash reads are possible when the hold is removed, writes to
the FCCOBIX, FCCOBHI, and FCCOBLO registers are ignored to prevent command activity while the
Memory Controller remains busy. Completion of the reset sequence is marked by setting CCIF high which
enables writes to the FCCOBIX, FCCOBHI, and FCCOBLO registers to launch any available Flash
command.
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
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512 KByte Flash Module (S12XFTM512K3V1)
Table 9-1. Revision History
Revision
Number
Revision
Date
Sections
Affected
V01.09
14 Nov 2007
9.5.2/9-341
9.4.2/9-317
9.4.2.8/9-323
Description of Changes
- Changed terminology from ‘word program’ to “Program P-Flash’ in the BDM
unsecuring description, Section 9.5.2
- Added requirement that user not write any Flash module register during
execution of commands ‘Erase All Blocks’, Section 9.4.2.8, and ‘Unsecure
Flash’, Section 9.4.2.11
- Added statement that security is released upon successful completion of
command ‘Erase All Blocks’, Section 9.4.2.8
V01.10
19 Dec 2007
9.4.2/9-317
- Corrected Error Handling table for Full Partition D-Flash, Partition D-Flash,
and EEPROM Emulation Query commands
V01.11
25 Sep 2009
9.1/9-281
9.3.2.1/9-293
9.4.2.4/9-320
- Clarify single bit fault correction for P-Flash phrase
- Expand FDIV vs OSCCLK Frequency table
- Add statement concerning code runaway when executing Read Once
command from Flash block containing associated fields
- Add statement concerning code runaway when executing Program Once
command from Flash block containing associated fields
- Add statement concerning code runaway when executing Verify Backdoor
Access Key command from Flash block containing associated fields
- Relate Key 0 to associated Backdoor Comparison Key address
- Change “power down reset” to “reset”
- Add ACCERR condition for Disable EEPROM Emulation command
The following changes were made to clarify module behavior related to Flash
register access during reset sequence and while Flash commands are active:
- Add caution concerning register writes while command is active
- Writes to FCLKDIV are allowed during reset sequence while CCIF is clear
- Add caution concerning register writes while command is active
- Writes to FCCOBIX, FCCOBHI, FCCOBLO registers are ignored during
reset sequence
9.4.2.7/9-322
9.4.2.12/9-326
9.4.2.12/9-326
9.4.2.12/9-326
9.4.2.20/9-335
9.3.2/9-291
9.3.2.1/9-293
9.4.1.2/9-312
9.6/9-341
9.1
Introduction
The FTM512K3 module implements the following:
• 512 Kbytes of P-Flash (Program Flash) memory, consisting of 3 physical Flash blocks, intended
primarily for nonvolatile code storage
• 32 Kbytes of D-Flash (Data Flash) memory, consisting of 1 physical Flash block, that can be used
as nonvolatile storage to support the built-in hardware scheme for emulated EEPROM, as basic
Flash memory primarily intended for nonvolatile data storage, or as a combination of both
• 4 Kbytes of buffer RAM, consisting of 1 physical RAM block, that can be used as emulated
EEPROM using a built-in hardware scheme, as basic RAM, or as a combination of both
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The Flash memory is ideal for single-supply applications allowing for field reprogramming without
requiring external high voltage sources for program or erase operations. The Flash module includes a
memory controller that executes commands to modify Flash memory contents or configure module
resources for emulated EEPROM operation. The user interface to the memory controller consists of the
indexed Flash Common Command Object (FCCOB) register which is written to with the command, global
address, data, and any required command parameters. The memory controller must complete the execution
of a command before the FCCOB register can be written to with a new command.
CAUTION
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
The RAM and Flash memory may be read as bytes, aligned words, or misaligned words. Read access time
is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. For Flash memory,
an erased bit reads 1 and a programmed bit reads 0.
It is not possible to read from a Flash block while any command is executing on that specific Flash block.
It is possible to read from a Flash block while a command is executing on a different Flash block.
Both P-Flash and D-Flash memories are implemented with Error Correction Codes (ECC) that can resolve
single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that
programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read
by phrase, only one single bit fault in the phrase containing the byte or word accessed will be corrected.
9.1.1
Glossary
Buffer RAM — The buffer RAM constitutes the volatile memory store required for EEE. Memory space
in the buffer RAM not required for EEE can be partitioned to provide volatile memory space for
applications.
Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including
program and erase) on the Flash memory.
D-Flash Memory — The D-Flash memory constitutes the nonvolatile memory store required for EEE.
Memory space in the D-Flash memory not required for EEE can be partitioned to provide nonvolatile
memory space for applications.
D-Flash Sector — The D-Flash sector is the smallest portion of the D-Flash memory that can be erased.
The D-Flash sector consists of four 64 byte rows for a total of 256 bytes.
EEE (Emulated EEPROM) — A method to emulate the small sector size features and endurance
characteristics associated with an EEPROM.
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EEE IFR — Nonvolatile information register located in the D-Flash block that contains data required to
partition the D-Flash memory and buffer RAM for EEE. The EEE IFR is visible in the global memory map
by setting the EEEIFRON bit in the MMCCTL1 register.
NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters
required for Flash command execution.
Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes eight
ECC bits for single bit fault correction and double bit fault detection within the phrase.
P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications.
P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased.
Each P-Flash sector contains 1024 bytes.
Program IFR — Nonvolatile information register located in the P-Flash block that contains the Device
ID, Version ID, and the Program Once field. The Program IFR is visible in the global memory map by
setting the PGMIFRON bit in the MMCCTL1 register.
9.1.2
Features
9.1.2.1
•
•
•
•
•
•
512 Kbytes of P-Flash memory composed of one 256 Kbyte Flash block and two 128 Kbyte Flash
blocks. The 256 Kbyte Flash block consists of two 128 Kbyte sections each divided into
128 sectors of 1024 bytes. The 128 Kbyte Flash blocks are each divided into 128 sectors of 1024
bytes.
Single bit fault correction and double bit fault detection within a 64-bit phrase during read
operations
Automated program and erase algorithm with verify and generation of ECC parity bits
Fast sector erase and phrase program operation
Ability to program up to one phrase in each P-Flash block simultaneously
Flexible protection scheme to prevent accidental program or erase of P-Flash memory
9.1.2.2
•
•
•
•
•
•
D-Flash Features
Up to 32 Kbytes of D-Flash memory with 256 byte sectors for user access
Dedicated commands to control access to the D-Flash memory over EEE operation
Single bit fault correction and double bit fault detection within a word during read operations
Automated program and erase algorithm with verify and generation of ECC parity bits
Fast sector erase and word program operation
Ability to program up to four words in a burst sequence
9.1.2.3
•
P-Flash Features
Emulated EEPROM Features
Up to 4 Kbytes of emulated EEPROM (EEE) accessible as 4 Kbytes of RAM
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•
•
•
•
•
•
Flexible protection scheme to prevent accidental program or erase of data
Automatic EEE file handling using an internal Memory Controller
Automatic transfer of valid EEE data from D-Flash memory to buffer RAM on reset
Ability to monitor the number of outstanding EEE related buffer RAM words left to be
programmed into D-Flash memory
Ability to disable EEE operation and allow priority access to the D-Flash memory
Ability to cancel all pending EEE operations and allow priority access to the D-Flash memory
9.1.2.4
•
Up to 4 Kbytes of RAM for user access
9.1.2.5
•
•
•
9.1.3
User Buffer RAM Features
Other Flash Module Features
No external high-voltage power supply required for Flash memory program and erase operations
Interrupt generation on Flash command completion and Flash error detection
Security mechanism to prevent unauthorized access to the Flash memory
Block Diagram
The block diagram of the Flash module is shown in Figure 9-1.
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Chapter 9 512 KByte Flash Module (S12XFTM512K3V1)
16bit
internal
bus
Flash
Interface
P-Flash Block 0
32Kx72
16Kx72
16Kx72
sector 0
sector 1
sector 0
sector 1
sector 127
sector 127
Command
Interrupt
Request
Registers
Error
Interrupt
Request
Protection
P-Flash
Block 1N
16Kx72
Security
sector 127
Oscillator
Clock (XTAL)
sector 0
sector 1
P-Flash
Block 1S
16Kx72
Clock
Divider FCLK
XGATE
sector 0
sector 1
Memory
Controller
CPU
Scratch RAM
512x16
Buffer RAM
2Kx16
sector 127
D-Flash
16Kx22
sector 0
sector 1
sector 127
Tag RAM
128x16
Figure 9-1. FTM512K3 Block Diagram
9.2
External Signal Description
The Flash module contains no signals that connect off-chip.
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Chapter 9 512 KByte Flash Module (S12XFTM512K3V1)
9.3
Memory Map and Registers
This section describes the memory map and registers for the Flash module. Read data from unimplemented
memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space
in the Flash module will be ignored by the Flash module.
9.3.1
Module Memory Map
The S12X architecture places the P-Flash memory between global addresses 0x78_0000 and 0x7F_FFFF
as shown in Table 9-2. The P-Flash memory map is shown in Figure 9-2.
Table 9-2. P-Flash Memory Addressing
Global Address
Size
(Bytes)
0x7C_0000 – 0x7F_FFFF
256 K
P-Flash Block 0
Contains Flash Configuration Field
(see Table 9-3)
0x7A_0000 – 0x7B_FFFF
128 K
P-Flash Block 1N
0x78_0000 – 0x79_FFFF
128 K
P-Flash Block 1S
Description
The FPROT register, described in Section 9.3.2.9, can be set to protect regions in the Flash memory from
accidental program or erase. Three separate memory regions, one growing upward from global address
0x7F_8000 in the Flash memory (called the lower region), one growing downward from global address
0x7F_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash
memory, can be activated for protection. The Flash memory addresses covered by these protectable regions
are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader
code since it covers the vector space. Default protection settings as well as security information that allows
the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in
Table 9-3.
Table 9-3. Flash Configuration Field(1)
Global Address
Size
(Bytes)
0x7F_FF00 – 0x7F_FF07
8
0x7F_FF08 –
0x7F_FF0B(2)
4
0x7F_FF0C2
1
P-Flash Protection byte.
Refer to Section 9.3.2.9, “P-Flash Protection Register (FPROT)”
0x7F_FF0D2
1
EEE Protection byte
Refer to Section 9.3.2.10, “EEE Protection Register (EPROT)”
0x7F_FF0E2
1
Flash Nonvolatile byte
Refer to Section 9.3.2.14, “Flash Option Register (FOPT)”
Description
Backdoor Comparison Key
Refer to Section 9.4.2.12, “Verify Backdoor Access Key Command,” and
Section 9.5.1, “Unsecuring the MCU using Backdoor Key Access”
Reserved
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Table 9-3. Flash Configuration Field(1)
Global Address
Size
(Bytes)
Description
Flash Security byte
Refer to Section 9.3.2.2, “Flash Security Register (FSEC)”
1. Older versions may have swapped protection byte addresses
2. 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in
the 0x7F_FF08 - 0x7F_FF0B reserved field should be programmed to 0xFF.
0x7F_FF0F2
1
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Chapter 9 512 KByte Flash Module (S12XFTM512K3V1)
P-Flash START = 0x78_0000
Flash Protected/Unprotected Region
480 Kbytes
0x7F_8000
0x7F_8400
0x7F_8800
0x7F_9000
Flash Protected/Unprotected Lower Region
1, 2, 4, 8 Kbytes
0x7F_A000
Flash Protected/Unprotected Region
8 Kbytes (up to 29 Kbytes)
0x7F_C000
0x7F_E000
Flash Protected/Unprotected Higher Region
2, 4, 8, 16 Kbytes
0x7F_F000
0x7F_F800
P-Flash END = 0x7F_FFFF
Flash Configuration Field
16 bytes (0x7F_FF00 - 0x7F_FF0F)
Figure 9-2. P-Flash Memory Map
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Chapter 9 512 KByte Flash Module (S12XFTM512K3V1)
Table 9-4. Program IFR Fields
Global Address
(PGMIFRON)
Size
(Bytes)
0x40_0000 – 0x40_0007
8
Device ID
0x40_0008 – 0x40_00E7
224
Reserved
0x40_00E8 – 0x40_00E9
2
Version ID
0x40_00EA – 0x40_00FF
22
Reserved
0x40_0100 – 0x40_013F
64
Program Once Field
Refer to Section 9.4.2.7, “Program Once Command”
0x40_0140 – 0x40_01FF
192
Reserved
Field Description
Table 9-5. P-Flash IFR Accessibility
Global Address
(PGMIFRON)
Size
(Bytes)
0x40_0000 – 0x40_01FF
512
XBUS0 (PBLK0S)(1)
0x40_0200 – 0x40_03FF
512
Unimplemented
0x40_0400 – 0x40_05FF
512
XBUS0 (PBLK1N)
0x40_0600 – 0x40_07FF
512
1. Refer to Table 9-4 for more details.
XBUS1 (PBLK1S)
Accessed From
Table 9-6. EEE Resource Fields
Global Address
Size
(Bytes)
0x10_0000 – 0x10_7FFF
32,768
D-Flash Memory (User and EEE)
0x10_8000 – 0x11_FFFF
98,304
Reserved
0x12_0000 – 0x12_007F
128
0x12_0080 – 0x12_0FFF
3,968
Reserved
0x12_1000 – 0x12_1EFF
3,840
Reserved
0x12_1F00 – 0x12_1FFF
256
0x12_2000 – 0x12_3BFF
7,168
Reserved
0x12_3C00 – 0x12_3FFF
1,024
Memory Controller Scratch RAM (TMGRAMON1 = 1)
0x12_4000 – 0x12_DFFF
40,960
Reserved
0x12_E000 – 0x12_FFFF
8,192
Reserved
0x13_0000 – 0x13_EFFF
61,440
Reserved
0x13_F000 – 0x13_FFFF
1. MMCCTL1 register bit
4,096
Buffer RAM (User and EEE)
Description
EEE Nonvolatile Information Register (EEEIFRON(1) = 1)
EEE Tag RAM (TMGRAMON1 = 1)
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D-Flash START = 0x10_0000
D-Flash User Partition
D-Flash Memory
32 Kbytes
D-Flash EEE Partition
D-Flash END = 0x10_7FFF
0x12_0000
0x12_1000
0x12_2000
0x12_4000
EEE Nonvolatile Information Register (EEEIFRON)
128 bytes
EEE Tag RAM (TMGRAMON)
256 bytes
Memory Controller Scratch RAM (TMGRAMON)
1024 bytes
0x12_E000
0x12_FFFF
Buffer RAM START = 0x13_F000
Buffer RAM User Partition
0x13_FE00
0x13_FE40
0x13_FE80
0x13_FEC0
0x13_FF00
0x13_FF40
0x13_FF80
0x13_FFC0
Buffer RAM END = 0x13_FFFF
Buffer RAM
4 Kbytes
Buffer RAM EEE Partition
Protectable Region (EEE only)
64, 128, 192, 256, 320, 384, 448, 512 bytes
Figure 9-3. EEE Resource Memory Map
The Full Partition D-Flash command (see Section 9.4.2.15) is used to program the EEE nonvolatile
information register fields where address 0x12_0000 defines the D-Flash partition for user access and
address 0x12_0004 defines the buffer RAM partition for EEE operations.
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Chapter 9 512 KByte Flash Module (S12XFTM512K3V1)
Table 9-7. EEE Nonvolatile Information Register Fields
Global Address
(EEEIFRON)
Size
(Bytes)
0x12_0000 – 0x12_0001
2
D-Flash User Partition (DFPART)
Refer to Section 9.4.2.15, “Full Partition D-Flash Command”
0x12_0002 – 0x12_0003
2
D-Flash User Partition (duplicate(1))
0x12_0004 – 0x12_0005
2
Buffer RAM EEE Partition (ERPART)
Refer to Section 9.4.2.15, “Full Partition D-Flash Command”
0x12_0006 – 0x12_0007
2
Buffer RAM EEE Partition (duplicate1)
Description
0x12_0008 – 0x12_007F
120
Reserved
1. Duplicate value used if primary value generates a double bit fault when read during the reset sequence.
9.3.2
Register Descriptions
The Flash module contains a set of 20 control and status registers located between Flash module base +
0x0000 and 0x0013. A summary of the Flash module registers is given in Figure 9-4 with detailed
descriptions in the following subsections.
CAUTION
Writes to any Flash register must be avoided while a Flash command is
active (CCIF=0) to prevent corruption of Flash register contents and
Memory Controller behavior.
Address
& Name
0x0000
FCLKDIV
0x0001
FSEC
0x0002
FCCOBIX
0x0003
FECCRIX
0x0004
FCNFG
0x0005
FERCNFG
7
R
6
5
4
3
2
1
0
FDIV6
FDIV5
FDIV4
FDIV3
FDIV2
FDIV1
FDIV0
KEYEN1
KEYEN0
RNV5
RNV4
RNV3
RNV2
SEC1
SEC0
0
0
0
0
0
CCOBIX2
CCOBIX1
CCOBIX0
ECCRIX2
ECCRIX1
ECCRIX0
FDFD
FSFD
DFDIE
SFDIE
FDIVLD
W
R
W
R
W
R
0
0
0
0
0
W
R
0
0
CCIE
0
0
IGNSF
W
R
0
ERSERIE
PGMERIE
EPVIOLIE
ERSVIE1
ERSVIE0
W
Figure 9-4. FTM512K3 Register Summary
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Chapter 9 512 KByte Flash Module (S12XFTM512K3V1)
Address
& Name
0x0006
FSTAT
0x0007
FERSTAT
0x0008
FPROT
0x0009
EPROT
0x000A
FCCOBHI
0x000B
FCCOBLO
0x000C
ETAGHI
0x000D
ETAGLO
0x000E
FECCRHI
0x000F
FECCRLO
0x0010
FOPT
0x0011
FRSV0
0x0012
FRSV1
0x0013
FRSV2
7
R
6
5
4
3
2
1
0
ACCERR
FPVIOL
MGBUSY
RSVD
MGSTAT1
MGSTAT0
EPVIOLIF
ERSVIF1
ERSVIF0
DFDIF
SFDIF
FPHDIS
FPHS1
FPHS0
FPLDIS
FPLS1
FPLS0
RNV5
RNV4
EPDIS
EPS2
EPS1
EPS0
0
CCIF
W
R
0
ERSERIF
PGMERIF
W
R
RNV6
FPOPEN
W
R
RNV6
EPOPEN
W
R
CCOB15
CCOB14
CCOB13
CCOB12
CCOB11
CCOB10
CCOB9
CCOB8
CCOB7
CCOB6
CCOB5
CCOB4
CCOB3
CCOB2
CCOB1
CCOB0
ETAG15
ETAG14
ETAG13
ETAG12
ETAG11
ETAG10
ETAG9
ETAG8
ETAG7
ETAG6
ETAG5
ETAG4
ETAG3
ETAG2
ETAG1
ETAG0
ECCR15
ECCR14
ECCR13
ECCR12
ECCR11
ECCR10
ECCR9
ECCR8
ECCR7
ECCR6
ECCR5
ECCR4
ECCR3
ECCR2
ECCR1
ECCR0
NV7
NV6
NV5
NV4
NV3
NV2
NV1
NV0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Figure 9-4. FTM512K3 Register Summary (continued)
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Chapter 9 512 KByte Flash Module (S12XFTM512K3V1)
Address
& Name
7
6
5
4
3
2
1
0
= Unimplemented or Reserved
Figure 9-4. FTM512K3 Register Summary (continued)
9.3.2.1
Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
Offset Module Base + 0x0000
7
R
6
5
4
3
2
1
0
0
0
0
FDIVLD
FDIV[6:0]
W
Reset
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-5. Flash Clock Divider Register (FCLKDIV)
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
Table 9-8. FCLKDIV Field Descriptions
Field
7
FDIVLD
6–0
FDIV[6:0]
Description
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms. Table 9-9 shows recommended values for FDIV[6:0] based on OSCCLK frequency.
Please refer to Section 9.4.1, “Flash Command Operations,” for more information.
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
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Table 9-9. FDIV vs OSCCLK Frequency
OSCCLK Frequency
(MHz)
MIN(1)
MAX
FDIV[6:0]
(2)
OSCCLK Frequency
(MHz)
MIN
1
MAX
FDIV[6:0]
2
OSCCLK Frequency
(MHz)
MIN
1
MAX
FDIV[6:0]
2
33.60
34.65
0x20
67.20
68.25
0x40
1.60
2.10
0x01
34.65
35.70
0x21
68.25
69.30
0x41
2.40
3.15
0x02
35.70
36.75
0x22
69.30
70.35
0x42
3.20
4.20
0x03
36.75
37.80
0x23
70.35
71.40
0x43
4.20
5.25
0x04
37.80
38.85
0x24
71.40
72.45
0x44
5.25
6.30
0x05
38.85
39.90
0x25
72.45
73.50
0x45
6.30
7.35
0x06
39.90
40.95
0x26
73.50
74.55
0x46
7.35
8.40
0x07
40.95
42.00
0x27
74.55
75.60
0x47
8.40
9.45
0x08
42.00
43.05
0x28
75.60
76.65
0x48
9.45
10.50
0x09
43.05
44.10
0x29
76.65
77.70
0x49
10.50
11.55
0x0A
44.10
45.15
0x2A
77.70
78.75
0x4A
11.55
12.60
0x0B
45.15
46.20
0x2B
78.75
79.80
0x4B
12.60
13.65
0x0C
46.20
47.25
0x2C
79.80
80.85
0x4C
13.65
14.70
0x0D
47.25
48.30
0x2D
80.85
81.90
0x4D
14.70
15.75
0x0E
48.30
49.35
0x2E
81.90
82.95
0x4E
15.75
16.80
0x0F
49.35
50.40
0x2F
82.95
84.00
0x4F
16.80
17.85
0x10
50.40
51.45
0x30
84.00
85.05
0x50
17.85
18.90
0x11
51.45
52.50
0x31
85.05
86.10
0x51
18.90
19.95
0x12
52.50
53.55
0x32
86.10
87.15
0x52
19.95
21.00
0x13
53.55
54.60
0x33
87.15
88.20
0x53
21.00
22.05
0x14
54.60
55.65
0x34
88.20
89.25
0x54
22.05
23.10
0x15
55.65
56.70
0x35
89.25
90.30
0x55
23.10
24.15
0x16
56.70
57.75
0x36
90.30
91.35
0x56
24.15
25.20
0x17
57.75
58.80
0x37
91.35
92.40
0x57
25.20
26.25
0x18
58.80
59.85
0x38
92.40
93.45
0x58
26.25
27.30
0x19
59.85
60.90
0x39
93.45
94.50
0x59
27.30
28.35
0x1A
60.90
61.95
0x3A
94.50
95.55
0x5A
28.35
29.40
0x1B
61.95
63.00
0x3B
95.55
96.60
0x5B
29.40
30.45
0x1C
63.00
64.05
0x3C
96.60
97.65
0x5C
30.45
31.50
0x1D
64.05
65.10
0x3D
97.65
98.70
0x5D
31.50
32.55
0x1E
65.10
66.15
0x3E
98.70
99.75
0x5E
32.55
33.60
0x1F
66.15
67.20
1. FDIV shown generates an FCLK frequency of >0.8 MHz
0x3F
99.75
100.80
0x5F
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2. FDIV shown generates an FCLK frequency of 1.05 MHz
9.3.2.2
Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
Offset Module Base + 0x0001
7
R
6
5
4
KEYEN[1:0]
3
2
1
RNV[5:2]
0
SEC[1:0]
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 9-6. Flash Security Register (FSEC)
All bits in the FSEC register are readable but not writable.
During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the
Flash configuration field at global address 0x7F_FF0F located in P-Flash memory (see Table 9-3) as
indicated by reset condition F in Figure 9-6. If a double bit fault is detected while reading the P-Flash
phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be
set to leave the Flash module in a secured state with backdoor key access disabled.
Table 9-10. FSEC Field Descriptions
Field
Description
7–6
Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the
KEYEN[1:0] Flash module as shown in Table 9-11.
5–2
RNV[5:2}
Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements.
1–0
SEC[1:0]
Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 9-12. If the
Flash module is unsecured using backdoor key access, the SEC bits are forced to 10.
Table 9-11. Flash KEYEN States
KEYEN[1:0]
Status of Backdoor Key Access
00
DISABLED
01
DISABLED(1)
10
ENABLED
11
DISABLED
1. Preferred KEYEN state to disable backdoor key access.
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Table 9-12. Flash Security States
SEC[1:0]
Status of Security
00
SECURED
01
SECURED(1)
10
UNSECURED
11
SECURED
1. Preferred SEC state to set MCU to secured state.
The security function in the Flash module is described in Section 9.5.
9.3.2.3
Flash CCOB Index Register (FCCOBIX)
The FCCOBIX register is used to index the FCCOB register for Flash memory operations.
Offset Module Base + 0x0002
R
7
6
5
4
3
0
0
0
0
0
2
1
0
CCOBIX[2:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-7. FCCOB Index Register (FCCOBIX)
CCOBIX bits are readable and writable while remaining bits read 0 and are not writable.
Table 9-13. FCCOBIX Field Descriptions
Field
Description
2–0
CCOBIX[1:0]
Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register
array is being read or written to. See Section 9.3.2.11, “Flash Common Command Object Register (FCCOB),”
for more details.
9.3.2.4
Flash ECCR Index Register (FECCRIX)
The FECCRIX register is used to index the FECCR register for ECC fault reporting.
Offset Module Base + 0x0003
R
7
6
5
4
3
0
0
0
0
0
2
1
0
ECCRIX[2:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-8. FECCR Index Register (FECCRIX)
ECCRIX bits are readable and writable while remaining bits read 0 and are not writable.
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Table 9-14. FECCRIX Field Descriptions
Field
Description
2-0
ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is
ECCRIX[2:0] being read. See Section 9.3.2.13, “Flash ECC Error Results Register (FECCR),” for more details.
9.3.2.5
Flash Configuration Register (FCNFG)
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU or XGATE.
Offset Module Base + 0x0004
7
R
6
5
0
0
CCIE
4
3
2
0
0
IGNSF
1
0
FDFD
FSFD
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-9. Flash Configuration Register (FCNFG)
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
Table 9-15. FCNFG Field Descriptions
Field
Description
7
CCIE
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 9.3.2.7)
4
IGNSF
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section 9.3.2.8).
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
generated
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Table 9-15. FCNFG Field Descriptions (continued)
Field
Description
1
FDFD
Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array
read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The
FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual
double bit fault is detected.
0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see
Section 9.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG
register is set (see Section 9.3.2.6)
0
FSFD
Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array
read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. The
FECCR registers will not be updated during the Flash array read operation with FSFD set unless an actual single
bit fault is detected.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 9.3.2.7)
and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section 9.3.2.6)
9.3.2.6
Flash Error Configuration Register (FERCNFG)
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
Offset Module Base + 0x0005
7
6
R
5
4
3
2
1
0
EPVIOLIE
ERSVIE1
ERSVIE0
DFDIE
SFDIE
0
0
0
0
0
0
ERSERIE
PGMERIE
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 9-10. Flash Error Configuration Register (FERCNFG)
All assigned bits in the FERCNFG register are readable and writable.
Table 9-16. FERCNFG Field Descriptions
Field
Description
7
ERSERIE
EEE Erase Error Interrupt Enable — The ERSERIE bit controls interrupt generation when a failure is detected
during an EEE erase operation.
0 ERSERIF interrupt disabled
1 An interrupt will be requested whenever the ERSERIF flag is set (see Section 9.3.2.8)
6
PGMERIE
EEE Program Error Interrupt Enable — The PGMERIE bit controls interrupt generation when a failure is
detected during an EEE program operation.
0 PGMERIF interrupt disabled
1 An interrupt will be requested whenever the PGMERIF flag is set (see Section 9.3.2.8)
4
EPVIOLIE
EEE Protection Violation Interrupt Enable — The EPVIOLIE bit controls interrupt generation when a
protection violation is detected during a write to the buffer RAM EEE partition.
0 EPVIOLIF interrupt disabled
1 An interrupt will be requested whenever the EPVIOLIF flag is set (see Section 9.3.2.8)
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Table 9-16. FERCNFG Field Descriptions (continued)
Field
Description
3
ERSVIE1
EEE Error Type 1 Interrupt Enable — The ERSVIE1 bit controls interrupt generation when a change state error
is detected during an EEE operation.
0 ERSVIF1 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF1 flag is set (see Section 9.3.2.8)
2
ERSVIE0
EEE Error Type 0 Interrupt Enable — The ERSVIE0 bit controls interrupt generation when a sector format error
is detected during an EEE operation.
0 ERSVIF0 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF0 flag is set (see Section 9.3.2.8)
1
DFDIE
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see Section 9.3.2.8)
0
SFDIE
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 9.3.2.8)
1 An interrupt will be requested whenever the SFDIF flag is set (see Section 9.3.2.8)
9.3.2.7
Flash Status Register (FSTAT)
The FSTAT register reports the operational status of the Flash module.
Offset Module Base + 0x0006
7
6
R
5
4
0
CCIF
ACCERR
FPVIOL
0
0
3
2
MGBUSY
RSVD
0
0
1
0
MGSTAT[1:0]
W
Reset
1
0
0(1)
01
= Unimplemented or Reserved
Figure 9-11. Flash Status Register (FSTAT)
1. Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 9.6).
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
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Table 9-17. FSTAT Field Descriptions
Field
Description
7
CCIF
Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The
CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command
completion or command violation.
0 Flash command in progress
1 Flash command has completed
5
ACCERR
Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory
caused by either a violation of the command write sequence (see Section 9.4.1.2) or issuing an illegal Flash
command or when errors are encountered while initializing the EEE buffer ram during the reset sequence.
While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by
writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.
0 No access error detected
1 Access error detected
4
FPVIOL
Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an
address in a protected area of P-Flash memory during a command write sequence. The FPVIOL bit is cleared
by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not
possible to launch a command or start a command write sequence.
0 No protection violation detected
1 Protection violation detected
3
MGBUSY
Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller.
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0) or is handling internal EEE operations
2
RSVD
Reserved Bit — This bit is reserved and always reads 0.
1–0
Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error
MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See Section 9.4.2,
“Flash Command Description,” and Section 9.6, “Initialization” for details.
9.3.2.8
Flash Error Status Register (FERSTAT)
The FERSTAT register reflects the error status of internal Flash operations.
Offset Module Base + 0x0007
7
6
5
ERSERIF
PGMERIF
0
0
R
4
3
2
1
0
EPVIOLIF
ERSVIF1
ERSVIF0
DFDIF
SFDIF
0
0
0
0
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 9-12. Flash Error Status Register (FERSTAT)
All flags in the FERSTAT register are readable and only writable to clear the flag.
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Table 9-18. FERSTAT Field Descriptions
Field
Description
7
ERSERIF
EEE Erase Error Interrupt Flag — The setting of the ERSERIF flag occurs due to an error in a Flash erase
command that resulted in the erase operation not being successful during EEE operations. The ERSERIF flag
is cleared by writing a 1 to ERSERIF. Writing a 0 to the ERSERIF flag has no effect on ERSERIF. While
ERSERIF is set, it is possible to write to the buffer RAM EEE partition but the data written will not be transferred
to the D-Flash EEE partition.
0 Erase command successfully completed on the D-Flash EEE partition
1 Erase command failed on the D-Flash EEE partition
6
PGMERIF
EEE Program Error Interrupt Flag — The setting of the PGMERIF flag occurs due to an error in a Flash
program command that resulted in the program operation not being successful during EEE operations. The
PGMERIF flag is cleared by writing a 1 to PGMERIF. Writing a 0 to the PGMERIF flag has no effect on
PGMERIF. While PGMERIF is set, it is possible to write to the buffer RAM EEE partition but the data written will
not be transferred to the D-Flash EEE partition.
0 Program command successfully completed on the D-Flash EEE partition
1 Program command failed on the D-Flash EEE partition
4
EPVIOLIF
EEE Protection Violation Interrupt Flag —The setting of the EPVIOLIF flag indicates an attempt was made to
write to a protected area of the buffer RAM EEE partition. The EPVIOLIF flag is cleared by writing a 1 to
EPVIOLIF. Writing a 0 to the EPVIOLIF flag has no effect on EPVIOLIF. While EPVIOLIF is set, it is possible to
write to the buffer RAM EEE partition as long as the address written to is not in a protected area.
0 No EEE protection violation
1 EEE protection violation detected
3
ERSVIF1
EEE Error Interrupt 1 Flag —The setting of the ERSVIF1 flag indicates that the memory controller was unable
to change the state of a D-Flash EEE sector. The ERSVIF1 flag is cleared by writing a 1 to ERSVIF1. Writing a
0 to the ERSVIF1 flag has no effect on ERSVIF1. While ERSVIF1 is set, it is possible to write to the buffer RAM
EEE partition but the data written will not be transferred to the D-Flash EEE partition.
0 No EEE sector state change error detected
1 EEE sector state change error detected
2
ERSVIF0
EEE Error Interrupt 0 Flag —The setting of the ERSVIF0 flag indicates that the memory controller was unable
to format a D-Flash EEE sector for EEE use. The ERSVIF0 flag is cleared by writing a 1 to ERSVIF0. Writing a
0 to the ERSVIF0 flag has no effect on ERSVIF0. While ERSVIF0 is set, it is possible to write to the buffer RAM
EEE partition but the data written will not be transferred to the D-Flash EEE partition.
0 No EEE sector format error detected
1 EEE sector format error detected
1
DFDIF
Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was
detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation
was attempted on a Flash block that was under a Flash command operation. The DFDIF flag is cleared by writing
a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.
0 No double bit fault detected
1 Double bit fault detected or an invalid Flash array read operation attempted
0
SFDIF
Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag
indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation
or that a Flash array read operation was attempted on a Flash block that was under a Flash command operation.
The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF.
0 No single bit fault detected
1 Single bit fault detected and corrected or an invalid Flash array read operation attempted
9.3.2.9
P-Flash Protection Register (FPROT)
The FPROT register defines which P-Flash sectors are protected against program and erase operations.
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Offset Module Base + 0x0008
7
R
6
5
4
3
2
1
0
RNV6
FPOPEN
FPHDIS
FPHS[1:0]
FPLDIS
FPLS[1:0]
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 9-13. Flash Protection Register (FPROT)
The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected
region can only be increased (see Section 9.3.2.9.1, “P-Flash Protection Restrictions,” and Table 9-23).
During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte
in the Flash configuration field at global address 0x7F_FF0C located in P-Flash memory (see Table 9-3)
as indicated by reset condition ‘F’ in Figure 9-13. To change the P-Flash protection that will be loaded
during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash
protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase
containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and
remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected.
Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error
and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible
if any of the P-Flash sectors contained in the same P-Flash block are protected.
Table 9-19. FPROT Field Descriptions
Field
Description
7
FPOPEN
Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or
erase operations as shown in Table 9-20 for the P-Flash block.
0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the
corresponding FPHS and FPLS bits
1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the
corresponding FPHS and FPLS bits
6
RNV[6]
Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements.
5
FPHDIS
Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a
protected/unprotected area in a specific region of the P-Flash memory ending with global address 0x7F_FFFF.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
4–3
FPHS[1:0]
Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area
in P-Flash memory as shown inTable 9-21. The FPHS bits can only be written to while the FPHDIS bit is set.
2
FPLDIS
1–0
FPLS[1:0]
Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a
protected/unprotected area in a specific region of the P-Flash memory beginning with global address
0x7F_8000.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area
in P-Flash memory as shown in Table 9-22. The FPLS bits can only be written to while the FPLDIS bit is set.
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Table 9-20. P-Flash Protection Function
Function(1)
FPOPEN
FPHDIS
FPLDIS
1
1
1
No P-Flash Protection
1
1
0
Protected Low Range
1
0
1
Protected High Range
1
0
0
Protected High and Low Ranges
0
1
1
Full P-Flash Memory Protected
0
1
0
Unprotected Low Range
0
0
1
Unprotected High Range
0
0
0
Unprotected High and Low Ranges
1. For range sizes, refer to Table 9-21 and Table 9-22.
Table 9-21. P-Flash Protection Higher Address Range
FPHS[1:0]
Global Address Range
Protected Size
00
0x7F_F800–0x7F_FFFF
2 Kbytes
01
0x7F_F000–0x7F_FFFF
4 Kbytes
10
0x7F_E000–0x7F_FFFF
8 Kbytes
11
0x7F_C000–0x7F_FFFF
16 Kbytes
Table 9-22. P-Flash Protection Lower Address Range
FPLS[1:0]
Global Address Range
Protected Size
00
0x7F_8000–0x7F_83FF
1 Kbyte
01
0x7F_8000–0x7F_87FF
2 Kbytes
10
0x7F_8000–0x7F_8FFF
4 Kbytes
11
0x7F_8000–0x7F_9FFF
8 Kbytes
All possible P-Flash protection scenarios are shown in Figure 9-14. Although the protection scheme is
loaded from the Flash memory at global address 0x7F_FF0C during the reset sequence, it can be changed
by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single
chip mode while providing as much protection as possible if reprogramming is not required.
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FPHDIS = 0
FPLDIS = 1
FPHDIS = 0
FPLDIS = 0
7
6
5
4
3
2
1
0
FPLS[1:0]
FPHDIS = 1
FPLDIS = 0
0x7F_8000
0x7F_FFFF
Scenario
FPHS[1:0]
Scenario
FLASH START
FPHDIS = 1
FPLDIS = 1
FPOPEN = 1
Chapter 9 512 KByte Flash Module (S12XFTM512K3V1)
FPHS[1:0]
0x7F_8000
FPOPEN = 0
FPLS[1:0]
FLASH START
0x7F_FFFF
Unprotected region
Protected region with size
defined by FPLS
Protected region
not defined by FPLS, FPHS
Protected region with size
defined by FPHS
Figure 9-14. P-Flash Protection Scenarios
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9.3.2.9.1
P-Flash Protection Restrictions
The general guideline is that P-Flash protection can only be added and not removed. Table 9-23 specifies
all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
Table 9-23. P-Flash Protection Scenario Transitions
To Protection Scenario(1)
From
Protection
Scenario
0
1
2
3
0
X
X
X
X
X
1
X
4
X
X
X
X
X
X
X
X
6
6
7
X
3
5
5
X
X
2
4
X
X
X
X
X
X
X
X
X
X
7
1. Allowed transitions marked with X, see Figure 9-14 for a definition of the scenarios.
9.3.2.10
EEE Protection Register (EPROT)
The EPROT register defines which buffer RAM EEE partition areas are protected against writes.
Offset Module Base + 0x0009
7
6
R
5
4
3
2
1
0
RNV[6:4]
EPOPEN
EPDIS
EPS[2:0]
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 9-15. EEE Protection Register (EPROT)
All bits in the EPROT register are readable and writable except for RNV[6:4] which are only readable. The
EPOPEN and EPDIS bits can only be written to the protected state. The EPS bits can be written anytime
until the EPDIS bit is cleared. If the EPOPEN bit is cleared, the state of the EPDIS and EPS bits is
irrelevant.
During the reset sequence, the EPROT register is loaded from the EEE protection byte in the Flash
configuration field at global address 0x7F_FF0D located in P-Flash memory (see Table 9-3) as indicated
by reset condition F in Figure 9-15. To change the EEE protection that will be loaded during the reset
sequence, the P-Flash sector containing the EEE protection byte must be unprotected, then the EEE
protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase
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containing the EEE protection byte during the reset sequence, the EPOPEN bit will be cleared and
remaining bits in the EPROT register will be set to leave the buffer RAM EEE partition fully protected.
Trying to write data to any protected area in the buffer RAM EEE partition will result in a protection
violation error and the EPVIOLIF flag will be set in the FERSTAT register. Trying to write data to any
protected area in the buffer RAM partitioned for user access will not be prevented and the EPVIOLIF flag
in the FERSTAT register will not set.
Table 9-24. EPROT Field Descriptions
Field
Description
7
EPOPEN
Enables writes to the Buffer RAM partitioned for EEE
0 The entire buffer RAM EEE partition is protected from writes
1 Unprotected buffer RAM EEE partition areas are enabled for writes
6–4
RNV[6:4]
Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements
3
EPDIS
Buffer RAM Protection Address Range Disable — The EPDIS bit determines whether there is a protected
area in a specific region of the buffer RAM EEE partition.
0 Protection enabled
1 Protection disabled
2–0
EPS[2:0]
Buffer RAM Protection Size — The EPS[2:0] bits determine the size of the protected area in the buffer RAM
EEE partition as shown inTable 9-21. The EPS bits can only be written to while the EPDIS bit is set.
Table 9-25. Buffer RAM EEE Partition Protection Address Range
9.3.2.11
EPS[2:0]
Global Address Range
Protected Size
000
0x13_FFC0 – 0x13_FFFF
64 bytes
001
0x13_FF80 – 0x13_FFFF
128 bytes
010
0x13_FF40 – 0x13_FFFF
192 bytes
011
0x13_FF00 – 0x13_FFFF
256 bytes
100
0x13_FEC0 – 0x13_FFFF
320 bytes
101
0x13_FE80 – 0x13_FFFF
384 bytes
110
0x13_FE40 – 0x13_FFFF
448 bytes
111
0x13_FE00 – 0x13_FFFF
512 bytes
Flash Common Command Object Register (FCCOB)
The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register.
Byte wide reads and writes are allowed to the FCCOB register.
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Offset Module Base + 0x000A
7
6
5
4
3
2
1
0
0
0
0
0
R
CCOB[15:8]
W
Reset
0
0
0
0
Figure 9-16. Flash Common Command Object High Register (FCCOBHI)
Offset Module Base + 0x000B
7
6
5
4
3
2
1
0
0
0
0
0
R
CCOB[7:0]
W
Reset
0
0
0
0
Figure 9-17. Flash Common Command Object Low Register (FCCOBLO)
9.3.2.11.1
FCCOB - NVM Command Mode
NVM command mode uses the indexed FCCOB register to provide a command code and its relevant
parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates
the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user
clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register
all FCCOB parameter fields are locked and cannot be changed by the user until the command completes
(as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the
FCCOB register array.
The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 9-26. The
return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by
the Memory Controller. Writes to the unimplemented parameter fields (CCOBIX = 110 and CCOBIX =
111) are ignored with reads from these fields returning 0x0000.
Table 9-26 shows the generic Flash command format. The high byte of the first word in the CCOB array
contains the command code, followed by the parameters for this specific Flash command. For details on
the FCCOB settings required by each command, see the Flash command descriptions in Section 9.4.2.
Table 9-26. FCCOB - NVM Command Mode (Typical Usage)
CCOBIX[2:0]
Byte
FCCOB Parameter Fields (NVM Command Mode)
HI
FCMD[7:0] defining Flash command
LO
0, Global address [22:16]
HI
Global address [15:8]
LO
Global address [7:0]
HI
Data 0 [15:8]
LO
Data 0 [7:0]
000
001
010
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Table 9-26. FCCOB - NVM Command Mode (Typical Usage)
CCOBIX[2:0]
Byte
FCCOB Parameter Fields (NVM Command Mode)
HI
Data 1 [15:8]
LO
Data 1 [7:0]
HI
Data 2 [15:8]
LO
Data 2 [7:0]
HI
Data 3 [15:8]
LO
Data 3 [7:0]
011
100
101
9.3.2.12
EEE Tag Counter Register (ETAG)
The ETAG register contains the number of outstanding words in the buffer RAM EEE partition that need
to be programmed into the D-Flash EEE partition. The ETAG register is decremented prior to the related
tagged word being programmed into the D-Flash EEE partition. All tagged words have been programmed
into the D-Flash EEE partition once all bits in the ETAG register read 0 and the MGBUSY flag in the
FSTAT register reads 0.
Offset Module Base + 0x000C
7
6
5
4
R
3
2
1
0
0
0
0
0
ETAG[15:8]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 9-18. EEE Tag Counter High Register (ETAGHI)
Offset Module Base + 0x000D
7
6
5
4
R
3
2
1
0
0
0
0
0
ETAG[7:0]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 9-19. EEE Tag Counter Low Register (ETAGLO)
All ETAG bits are readable but not writable and are cleared by the Memory Controller.
9.3.2.13
Flash ECC Error Results Register (FECCR)
The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.
The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits
in the FECCRIX register (see Section 9.3.2.4). Once ECC fault information has been stored, no other fault
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information will be recorded until the specific ECC fault flag has been cleared. In the event of
simultaneous ECC faults, the priority for fault recording is:
1. Double bit fault over single bit fault
2. CPU over XGATE
Offset Module Base + 0x000E
7
6
5
4
R
3
2
1
0
0
0
0
0
ECCR[15:8]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 9-20. Flash ECC Error Results High Register (FECCRHI)
Offset Module Base + 0x000F
7
6
5
4
R
3
2
1
0
0
0
0
0
ECCR[7:0]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 9-21. Flash ECC Error Results Low Register (FECCRLO)
All FECCR bits are readable but not writable.
Table 9-27. FECCR Index Settings
ECCRIX[2:0]
000
FECCR Register Content
Bits [15:8]
Bit[7]
Bits[6:0]
Parity bits read from
Flash block
CPU or XGATE
source identity
Global address
[22:16]
001
Global address [15:0]
010
Data 0 [15:0]
011
Data 1 [15:0] (P-Flash only)
100
Data 2 [15:0] (P-Flash only)
101
Data 3 [15:0] (P-Flash only)
110
Not used, returns 0x0000 when read
111
Not used, returns 0x0000 when read
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Table 9-28. FECCR Index=000 Bit Descriptions
Field
Description
15:8
PAR[7:0]
ECC Parity Bits — Contains the 8 parity bits from the 72 bit wide P-Flash data word or the 6 parity bits,
allocated to PAR[5:0], from the 22 bit wide D-Flash word with PAR[7:6]=00.
7
XBUS01
Bus Source Identifier — The XBUS01 bit determines whether the ECC error was caused by a read access
from the CPU or XGATE.
0 ECC Error happened on the CPU access
1 ECC Error happened on the XGATE access
6–0
Global Address — The GADDR[22:16] field contains the upper seven bits of the global address having
GADDR[22:16] caused the error.
The P-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The
following four words addressed by ECCRIX = 010 to 101 contain the 64-bit wide data phrase. The four
data words and the parity byte are the uncorrected data read from the P-Flash block.
The D-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The
uncorrected 16-bit data word is addressed by ECCRIX = 010.
9.3.2.14
Flash Option Register (FOPT)
The FOPT register is the Flash option register.
Offset Module Base + 0x0010
7
6
5
4
R
3
2
1
0
F
F
F
F
NV[7:0]
W
Reset
F
F
F
F
= Unimplemented or Reserved
Figure 9-22. Flash Option Register (FOPT)
All bits in the FOPT register are readable but are not writable.
During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash
configuration field at global address 0x7F_FF0E located in P-Flash memory (see Table 9-3) as indicated
by reset condition F in Figure 9-22. If a double bit fault is detected while reading the P-Flash phrase
containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set.
Table 9-29. FOPT Field Descriptions
Field
Description
7–0
NV[7:0]
Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper
use of the NV bits.
9.3.2.15
Flash Reserved0 Register (FRSV0)
This Flash register is reserved for factory testing.
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Offset Module Base + 0x0011
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 9-23. Flash Reserved0 Register (FRSV0)
All bits in the FRSV0 register read 0 and are not writable.
9.3.2.16
Flash Reserved1 Register (FRSV1)
This Flash register is reserved for factory testing.
Offset Module Base + 0x0012
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 9-24. Flash Reserved1 Register (FRSV1)
All bits in the FRSV1 register read 0 and are not writable.
9.3.2.17
Flash Reserved2 Register (FRSV2)
This Flash register is reserved for factory testing.
Offset Module Base + 0x0013
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 9-25. Flash Reserved2 Register (FRSV2)
All bits in the FRSV2 register read 0 and are not writable.
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9.4
9.4.1
Functional Description
Flash Command Operations
Flash command operations are used to modify Flash memory contents or configure module resources for
EEE operation.
The next sections describe:
• How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from
OSCCLK for Flash program and erase command operations
• The command write sequence used to set Flash command parameters and launch execution
• Valid Flash commands available for execution
9.4.1.1
Writing the FCLKDIV Register
Prior to issuing any Flash program or erase command after a reset, the user is required to write the
FCLKDIV register to divide OSCCLK down to a target FCLK of 1 MHz. Table 9-9 shows recommended
values for the FDIV field based on OSCCLK frequency.
NOTE
Programming or erasing the Flash memory cannot be performed if the bus
clock runs at less than 1 MHz. Setting FDIV too high can destroy the Flash
memory due to overstress. Setting FDIV too low can result in incomplete
programming or erasure of the Flash memory cells.
When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the
FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written,
any Flash program or erase command loaded during a command write sequence will not execute and the
ACCERR bit in the FSTAT register will set.
9.4.1.2
Command Write Sequence
The Memory Controller will launch all valid Flash commands entered using a command write sequence.
Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see
Section 9.3.2.7) and the CCIF flag should be tested to determine the status of the current command write
sequence. If CCIF is 0, the previous command write sequence is still active, a new command write
sequence cannot be started, and all writes to the FCCOB register are ignored.
CAUTION
Writes to any Flash register must be avoided while a Flash command is
active (CCIF=0) to prevent corruption of Flash register contents and
Memory Controller behavior.
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9.4.1.2.1
Define FCCOB Contents
The FCCOB parameter fields must be loaded with all required parameters for the Flash command being
executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX
register (see Section 9.3.2.3).
The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears
the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag
will remain clear until the Flash command has completed. Upon completion, the Memory Controller will
return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic
command write sequence is shown in Figure 9-26.
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START
Read: FCLKDIV register
Clock Register
Written
Check
no
FDIVLD
Set?
yes
Write: FCLKDIV register
Note: FCLKDIV must be set after
each reset
Read: FSTAT register
FCCOB
Availability Check
CCIF
Set?
no
Results from previous Command
yes
Access Error and
Protection Violation
Check
ACCERR/
FPVIOL
Set?
no
yes
Write: FSTAT register
Clear ACCERR/FPVIOL 0x30
Write to FCCOBIX register
to identify specific command
parameter to load.
Write to FCCOB register
to load required command parameter.
More
Parameters?
yes
no
Write: FSTAT register (to launch command)
Clear CCIF 0x80
Read: FSTAT register
Bit Polling for
Command Completion
Check
CCIF Set?
no
yes
EXIT
Figure 9-26. Generic Flash Command Write Sequence Flowchart
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9.4.1.3
Valid Flash Module Commands
Table 9-30. Flash Commands by Mode
Unsecured
FCMD
Command
NS
NX
(1)
(2)
Secured
SS(3) ST(4)
NS
NX
(5)
(6)
SS(7) ST(8)
0x01
Erase Verify All Blocks
∗
∗
∗
∗
∗
∗
∗
∗
0x02
Erase Verify Block
∗
∗
∗
∗
∗
∗
∗
∗
0x03
Erase Verify P-Flash Section
∗
∗
∗
∗
∗
0x04
Read Once
∗
∗
∗
∗
∗
0x05
Load Data Field
∗
∗
∗
∗
∗
0x06
Program P-Flash
∗
∗
∗
∗
∗
0x07
Program Once
∗
∗
∗
∗
∗
0x08
Erase All Blocks
∗
∗
∗
∗
0x09
Erase P-Flash Block
∗
∗
∗
∗
∗
0x0A
Erase P-Flash Sector
∗
∗
∗
∗
∗
0x0B
Unsecure Flash
∗
∗
∗
∗
0x0C
Verify Backdoor Access Key
∗
0x0D
Set User Margin Level
∗
0x0E
∗
∗
∗
∗
∗
Set Field Margin Level
∗
∗
0x0F
Full Partition D-Flash
∗
∗
0x10
Erase Verify D-Flash Section
∗
∗
∗
∗
∗
0x11
Program D-Flash
∗
∗
∗
∗
∗
0x12
Erase D-Flash Sector
∗
∗
∗
∗
∗
0x13
Enable EEPROM Emulation
∗
∗
∗
∗
∗
∗
∗
∗
0x14
Disable EEPROM Emulation
∗
∗
∗
∗
∗
∗
∗
∗
0x15
EEPROM Emulation Query
∗
∗
∗
∗
∗
∗
∗
∗
0x20
Partition D-Flash
1. Unsecured Normal Single Chip mode.
2. Unsecured Normal Expanded mode.
3. Unsecured Special Single Chip mode.
4. Unsecured Special Mode.
5. Secured Normal Single Chip mode.
6. Secured Normal Expanded mode.
7. Secured Special Single Chip mode.
8. Secured Special Mode.
∗
∗
∗
∗
∗
∗
∗
∗
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9.4.1.4
P-Flash Commands
Table 9-31 summarizes the valid P-Flash commands along with the effects of the commands on the PFlash block and other resources within the Flash module.
Table 9-31. P-Flash Commands
FCMD
Command
0x01
Erase Verify All
Blocks
0x02
Erase Verify Block
0x03
Erase Verify PFlash Section
0x04
Read Once
0x05
Load Data Field
Load data for simultaneous multiple P-Flash block operations.
0x06
Program P-Flash
Program a phrase in a P-Flash block and any previously loaded phrases for any other PFlash block (see Load Data Field command).
0x07
Program Once
Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block
0 that is allowed to be programmed only once.
0x08
Erase All Blocks
Erase all P-Flash (and D-Flash) blocks.
An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN
bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are
set prior to launching the command.
0x09
Erase P-Flash
Block
Erase a single P-Flash block.
An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN
bits in the FPROT register are set prior to launching the command.
0x0A
Erase P-Flash
Sector
0x0B
Unsecure Flash
0x0C
Verify Backdoor
Access Key
Supports a method of releasing MCU security by verifying a set of security keys.
0x0D
Set User Margin
Level
Specifies a user margin read level for all P-Flash blocks.
0x0E
Set Field Margin
Level
Specifies a field margin read level for all P-Flash blocks (special modes only).
9.4.1.5
Function on P-Flash Memory
Verify that all P-Flash (and D-Flash) blocks are erased.
Verify that a P-Flash block is erased.
Verify that a given number of words starting at the address provided are erased.
Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block 0
that was previously programmed using the Program Once command.
Erase all bytes in a P-Flash sector.
Supports a method of releasing MCU security by erasing all P-Flash (and D-Flash) blocks
and verifying that all P-Flash (and D-Flash) blocks are erased.
D-Flash and EEE Commands
Table 9-32 summarizes the valid D-Flash and EEE commands along with the effects of the commands on
the D-Flash block and EEE operation.
Table 9-32. D-Flash Commands
FCMD
Command
0x01
Erase Verify All
Blocks
0x02
Erase Verify Block
Function on D-Flash Memory
Verify that all D-Flash (and P-Flash) blocks are erased.
Verify that the D-Flash block is erased.
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Table 9-32. D-Flash Commands
FCMD
Command
Function on D-Flash Memory
0x08
Erase All Blocks
Erase all D-Flash (and P-Flash) blocks.
An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN
bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are
set prior to launching the command.
0x0B
Unsecure Flash
Supports a method of releasing MCU security by erasing all D-Flash (and P-Flash) blocks
and verifying that all D-Flash (and P-Flash) blocks are erased.
0x0D
Set User Margin
Level
Specifies a user margin read level for the D-Flash block.
0x0E
Set Field Margin
Level
Specifies a field margin read level for the D-Flash block (special modes only).
0x0F
Full Partition DFlash
Erase the D-Flash block and partition an area of the D-Flash block for user access.
0x10
Erase Verify DFlash Section
Verify that a given number of words starting at the address provided are erased.
0x11
Program D-Flash
Program up to four words in the D-Flash block.
0x12
Erase D-Flash
Sector
Erase all bytes in a sector of the D-Flash block.
0x13
Enable EEPROM
Emulation
Enable EEPROM emulation where writes to the buffer RAM EEE partition will be copied
to the D-Flash EEE partition.
0x14
Disable EEPROM
Emulation
Suspend all current erase and program activity related to EEPROM emulation but leave
current EEE tags set.
0x15
EEPROM
Emulation Query
Returns EEE partition and status variables.
0x20
Partition D-Flash
Partition an area of the D-Flash block for user access.
9.4.2
Flash Command Description
This section provides details of all available Flash commands launched by a command write sequence. The
ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following
illegal steps are performed, causing the command not to be processed by the Memory Controller:
• Starting any command write sequence that programs or erases Flash memory before initializing the
FCLKDIV register
• Writing an invalid command as part of the command write sequence
• For additional possible errors, refer to the error handling table provided for each command
If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation
will return invalid data. If the SFDIF or DFDIF flags were not previously set when the invalid read
operation occurred, both the SFDIF and DFDIF flags will be set and the FECCR registers will be loaded
with the global address used in the invalid read operation with the data and parity fields set to all 0.
If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting
any command write sequence (see Section 9.3.2.7).
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CAUTION
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
9.4.2.1
Erase Verify All Blocks Command
The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased.
Table 9-33. Erase Verify All Blocks Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x01
Not required
Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify
that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks
operation has completed.
Table 9-34. Erase Verify All Blocks Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if a Load Data Field command sequence is currently active
FSTAT
FERSTAT
9.4.2.2
FPVIOL
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
EPVIOLIF
None
Erase Verify Block Command
The Erase Verify Block command allows the user to verify that an entire P-Flash or D-Flash block has been
erased. The FCCOB upper global address bits determine which block must be verified.
Table 9-35. Erase Verify Block Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x02
Global address [22:16] of the
Flash block to be verified.
Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that
the selected P-Flash or D-Flash block is erased. The CCIF flag will set after the Erase Verify Block
operation has completed.
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Table 9-36. Erase Verify Block Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if a Load Data Field command sequence is currently active
Set if an invalid global address [22:16] is supplied
FSTAT
FPVIOL
FERSTAT
9.4.2.3
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
EPVIOLIF
None
Erase Verify P-Flash Section Command
The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is
erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and
the number of phrases. The section to be verified cannot cross a 256 Kbyte boundary in the P-Flash
memory space.
Table 9-37. Erase Verify P-Flash Section Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x03
Global address [22:16] of
a P-Flash block
001
Global address [15:0] of the first phrase to be verified
010
Number of phrases to be verified
Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will
verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash
Section operation has completed.
Table 9-38. Erase Verify P-Flash Section Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see Table 9-30)
ACCERR
Set if an invalid global address [22:0] is supplied
FSTAT
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
Set if the requested section crosses a 256 Kbyte boundary
FPVIOL
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
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Table 9-38. Erase Verify P-Flash Section Command Error Handling
Register
Error Bit
FERSTAT
EPVIOLIF
9.4.2.4
Error Condition
None
Read Once Command
The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the
nonvolatile information register of P-Flash block 0. The Read Once field is programmed using the
Program Once command described in Section 9.4.2.7. The Read Once command must not be executed
from the Flash block containing the Program Once reserved field to avoid code runaway.
Table 9-39. Read Once Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x04
Not Required
001
Read Once phrase index (0x0000 - 0x0007)
010
Read Once word 0 value
011
Read Once word 1 value
100
Read Once word 2 value
101
Read Once word 3 value
Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the
FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid
phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the
Read Once command, any attempt to read addresses within P-Flash block 0 will return invalid data.
128
Table 9-40. Read Once Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if command not available in current mode (see Table 9-30)
FSTAT
Set if an invalid phrase index is supplied
FPVIOL
FERSTAT
9.4.2.5
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
EPVIOLIF
None
Load Data Field Command
The Load Data Field command is executed to provide FCCOB parameters for multiple P-Flash blocks for
a future simultaneous program operation in the P-Flash memory space.
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Table 9-41. Load Data Field Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x05
Global address [22:16] to
identify P-Flash block
001
Global address [15:0] of phrase location to be programmed(1)
010
Word 0
011
Word 1
100
Word 2
101
1. Global address [2:0] must be 000
Word 3
Upon clearing CCIF to launch the Load Data Field command, the FCCOB registers will be transferred to
the Memory Controller and be programmed in the block specified at the global address given with a future
Program P-Flash command launched on a P-Flash block. The CCIF flag will set after the Load Data Field
operation has completed. Note that once a Load Data Field command sequence has been initiated, the Load
Data Field command sequence will be cancelled if any command other than Load Data Field or the future
Program P-Flash is launched. Similarly, if an error occurs after launching a Load Data Field or Program
P-Flash command, the associated Load Data Field command sequence will be cancelled.
Table 9-42. Load Data Field Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 101 at command launch
Set if command not available in current mode (see Table 9-30)
Set if an invalid global address [22:0] is supplied
ACCERR
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
Set if a Load Data Field command sequence is currently active and the selected
block has previously been selected in the same command sequence
FSTAT
Set if a Load Data Field command sequence is currently active and global
address [17:0] does not match that previously supplied in the same command
sequence
FPVIOL
FERSTAT
9.4.2.6
Set if the global address [22:0] points to a protected area
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
Program P-Flash Command
The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an
embedded algorithm.
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CAUTION
A P-Flash phrase must be in the erased state before being programmed.
Cumulative programming of bits within a Flash phrase is not allowed.
Table 9-43. Program P-Flash Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x06
Global address [22:16] to
identify P-Flash block
001
Global address [15:0] of phrase location to be programmed(1)
010
Word 0 program value
011
Word 1 program value
100
Word 2 program value
101
Word 3 program value
1. Global address [2:0] must be 000
Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the
data words to the supplied global address and will then proceed to verify the data words read back as
expected. The CCIF flag will set after the Program P-Flash operation has completed.
Table 9-44. Program P-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 101 at command launch
Set if command not available in current mode (see Table 9-30)
Set if an invalid global address [22:0] is supplied
ACCERR
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
Set if a Load Data Field command sequence is currently active and the selected
block has previously been selected in the same command sequence
FSTAT
Set if a Load Data Field command sequence is currently active and global
address [17:0] does not match that previously supplied in the same command
sequence
FPVIOL
FERSTAT
9.4.2.7
Set if the global address [22:0] points to a protected area
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
EPVIOLIF
None
Program Once Command
The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the
nonvolatile information register located in P-Flash block 0. The Program Once reserved field can be read
using the Read Once command as described in Section 9.4.2.4. The Program Once command must only
be issued once since the nonvolatile information register in P-Flash block 0 cannot be erased. The Program
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Once command must not be executed from the Flash block containing the Program Once reserved field to
avoid code runaway.
Table 9-45. Program Once Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x07
Not Required
001
Program Once phrase index (0x0000 - 0x0007)
010
Program Once word 0 value
011
Program Once word 1 value
100
Program Once word 2 value
101
Program Once word 3 value
Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the
selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with
read back. The CCIF flag will remain clear, setting only after the Program Once operation has completed.
The reserved nonvolatile information register accessed by the Program Once command cannot be erased
and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index
values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program
Once command, any attempt to read addresses within P-Flash block 0 will return invalid data.
Table 9-46. Program Once Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 101 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if command not available in current mode (see Table 9-30)
Set if an invalid phrase index is supplied
FSTAT
Set if the requested phrase has already been programmed(1)
FPVIOL
None
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
FERSTAT
EPVIOLIF
None
1. If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will
be allowed to execute again on that same phrase.
9.4.2.8
Erase All Blocks Command
The Erase All Blocks operation will erase the entire P-Flash and D-Flash memory space including the EEE
nonvolatile information register.
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Table 9-47. Erase All Blocks Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x08
Not required
Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire
Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash
memory space was properly erased, security will be released. During the execution of this command
(CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All
Blocks operation has completed.
Table 9-48. Erase All Blocks Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see Table 9-30)
FSTAT
FERSTAT
9.4.2.9
FPVIOL
Set if any area of the P-Flash memory is protected
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
EPVIOLIF
Set if any area of the buffer RAM EEE partition is protected
Erase P-Flash Block Command
The Erase P-Flash Block operation will erase all addresses in a P-Flash block.
Table 9-49. Erase P-Flash Block Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x09
Global address [22:16] to
identify P-Flash block
Global address [15:0] in P-Flash block to be erased
Upon clearing CCIF to launch the Erase P-Flash Block command, the Memory Controller will erase the
selected P-Flash block and verify that it is erased. The CCIF flag will set after the Erase P-Flash Block
operation has completed.
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Table 9-50. Erase P-Flash Block Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if command not available in current mode (see Table 9-30)
Set if an invalid global address [22:16] is supplied
FSTAT
FPVIOL
FERSTAT
9.4.2.10
Set if an area of the selected P-Flash block is protected
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
EPVIOLIF
None
Erase P-Flash Sector Command
The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector.
Table 9-51. Erase P-Flash Sector Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
001
0x0A
Global address [22:16] to identify
P-Flash block to be erased
Global address [15:0] anywhere within the sector to be erased.
Refer to Section 9.1.2.1 for the P-Flash sector size.
Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the
selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash
Sector operation has completed.
Table 9-52. Erase P-Flash Sector Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if command not available in current mode (see Table 9-30)
Set if an invalid global address [22:16] is supplied
FSTAT
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
FPVIOL
FERSTAT
Set if the selected P-Flash sector is protected
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
EPVIOLIF
None
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9.4.2.11
Unsecure Flash Command
The Unsecure Flash command will erase the entire P-Flash and D-Flash memory space and, if the erase is
successful, will release security.
Table 9-53. Unsecure Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x0B
Not required
Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire
P-Flash and D-Flash memory space and verify that it is erased. If the Memory Controller verifies that the
entire Flash memory space was properly erased, security will be released. If the erase verify is not
successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security
state. During the execution of this command (CCIF=0) the user must not write to any Flash module
register. The CCIF flag is set after the Unsecure Flash operation has completed.
Table 9-54. Unsecure Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see Table 9-30)
FSTAT
FERSTAT
9.4.2.12
FPVIOL
Set if any area of the P-Flash memory is protected
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
EPVIOLIF
Set if any area of the buffer RAM EEE partition is protected
Verify Backdoor Access Key Command
The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the
FSEC register (see Table 9-11). The Verify Backdoor Access Key command releases security if usersupplied keys match those stored in the Flash security bytes of the Flash configuration field (see Table 93). The Verify Backdoor Access Key command must not be executed from the Flash block containing the
backdoor comparison key to avoid code runaway.
Table 9-55. Verify Backdoor Access Key Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x0C
Not required
001
Key 0
010
Key 1
011
Key 2
100
Key 3
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Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will
check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory
Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the
Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash
configuration field with Key 0 compared to 0x7F_FF00, etc. If the backdoor keys match, security will be
released. If the backdoor keys do not match, security is not released and all future attempts to execute the
Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is
set after the Verify Backdoor Access Key operation has completed.
Table 9-56. Verify Backdoor Access Key Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 100 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if an incorrect backdoor key is supplied
Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see
Section 9.3.2.2)
FSTAT
Set if the backdoor key has mismatched since the last reset
FERSTAT
9.4.2.13
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
Set User Margin Level Command
The Set User Margin Level command causes the Memory Controller to set the margin level for future read
operations of a specific P-Flash or D-Flash block.
Table 9-57. Set User Margin Level Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x0D
001
Global address [22:16] to identify the
Flash block
Margin level setting
Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the
user margin level for the targeted block and then set the CCIF flag.
Valid margin level settings for the Set User Margin Level command are defined in Table 9-58.
Table 9-58. Valid Set User Margin Level Settings
CCOB
(CCOBIX=001)
Level Description
0x0000
Return to Normal Level
0x0001
User Margin-1 Level(1)
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Table 9-58. Valid Set User Margin Level Settings
CCOB
(CCOBIX=001)
Level Description
0x0002
User Margin-0 Level(2)
1. Read margin to the erased state
2. Read margin to the programmed state
Table 9-59. Set User Margin Level Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if command not available in current mode (see Table 9-30)
Set if an invalid global address [22:16] is supplied
FSTAT
Set if an invalid margin level setting is supplied
FERSTAT
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
NOTE
User margin levels can be used to check that Flash memory contents have
adequate margin for normal level read operations. If unexpected results are
encountered when checking Flash memory contents at user margin levels, a
potential loss of information has been detected.
9.4.2.14
Set Field Margin Level Command
The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set
the margin level specified for future read operations of a specific P-Flash or D-Flash block.
Table 9-60. Set Field Margin Level Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x0E
Global address [22:16] to identify the Flash
block
Margin level setting
Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the
field margin level for the targeted block and then set the CCIF flag.
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Valid margin level settings for the Set Field Margin Level command are defined in Table 9-61.
Table 9-61. Valid Set Field Margin Level Settings
CCOB
(CCOBIX=001)
Level Description
0x0000
Return to Normal Level
0x0001
User Margin-1 Level(1)
0x0002
User Margin-0 Level(2)
0x0003
Field Margin-1 Level1
0x0004
Field Margin-0 Level2
1. Read margin to the erased state
2. Read margin to the programmed state
Table 9-62. Set Field Margin Level Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if command not available in current mode (see Table 9-30)
Set if an invalid global address [22:16] is supplied
FSTAT
Set if an invalid margin level setting is supplied
FERSTAT
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
CAUTION
Field margin levels must only be used during verify of the initial factory
programming.
NOTE
Field margin levels can be used to check that Flash memory contents have
adequate margin for data retention at the normal level setting. If unexpected
results are encountered when checking Flash memory contents at field
margin levels, the Flash memory contents should be erased and
reprogrammed.
9.4.2.15
Full Partition D-Flash Command
The Full Partition D-Flash command allows the user to allocate sectors within the D-Flash block for
applications and a partition within the buffer RAM for EEPROM access. The D-Flash block consists of
128 sectors with 256 bytes per sector.
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Table 9-63. Full Partition D-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x0F
Not required
001
Number of 256 byte sectors for the D-Flash user partition (DFPART)
010
Number of 256 byte sectors for buffer RAM EEE partition (ERPART)
Upon clearing CCIF to launch the Full Partition D-Flash command, the following actions are taken to
define a partition within the D-Flash block for direct access (DFPART) and a partition within the buffer
RAM for EEE use (ERPART):
• Validate the DFPART and ERPART values provided:
— DFPART <= 128 (maximum number of 256 byte sectors in D-Flash block)
— ERPART <= 16 (maximum number of 256 byte sectors in buffer RAM)
— If ERPART > 0, 128 - DFPART >= 12 (minimum number of 256 byte sectors in the D-Flash
block required to support EEE)
— If ERPART > 0, ((128-DFPART)/ERPART) >= 8 (minimum ratio of D-Flash EEE space to
buffer RAM EEE space to support EEE)
• Erase the D-Flash block and the EEE nonvolatile information register
• Program DFPART to the EEE nonvolatile information register at global address 0x12_0000 (see
Table 9-7)
• Program a duplicate DFPART to the EEE nonvolatile information register at global address
0x12_0002 (see Table 9-7)
• Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see
Table 9-7)
• Program a duplicate ERPART to the EEE nonvolatile information register at global address
0x12_0006 (see Table 9-7)
The D-Flash user partition will start at global address 0x10_0000. The buffer RAM EEE partition will end
at global address 0x13_FFFF. After the Full Partition D-Flash operation has completed, the CCIF flag will
set.
Running the Full Partition D-Flash command a second time will result in the previous partition values and
the entire D-Flash memory being erased. The data value written corresponds to the number of 256 byte
sectors allocated for either direct D-Flash access (DFPART) or buffer RAM EEE access (ERPART).
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Table 9-64. Full Partition D-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if command not available in current mode (see Table 9-30)
FSTAT
Set if an invalid DFPART or ERPART selection is supplied
FPVIOL
FERSTAT
9.4.2.16
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
EPVIOLIF
None
Erase Verify D-Flash Section Command
The Erase Verify D-Flash Section command will verify that a section of code in the D-Flash user partition
is erased. The Erase Verify D-Flash Section command defines the starting point of the data to be verified
and the number of words.
Table 9-65. Erase Verify D-Flash Section Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x10
Global address [22:16] to
identify the D-Flash block
001
Global address [15:0] of the first word to be verified
010
Number of words to be verified
Upon clearing CCIF to launch the Erase Verify D-Flash Section command, the Memory Controller will
verify the selected section of D-Flash memory is erased. The CCIF flag will set after the Erase Verify DFlash Section operation has completed.
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Table 9-66. Erase Verify D-Flash Section Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see Table 9-30)
Set if an invalid global address [22:0] is supplied
ACCERR
Set if a misaligned word address is supplied (global address [0] != 0)
FSTAT
Set if the global address [22:0] points to an area of the D-Flash EEE partition
Set if the requested section breaches the end of the D-Flash block or goes into
the D-Flash EEE partition
FPVIOL
FERSTAT
9.4.2.17
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
EPVIOLIF
None
Program D-Flash Command
The Program D-Flash operation programs one to four previously erased words in the D-Flash user
partition. The Program D-Flash operation will confirm that the targeted location(s) were successfully
programmed upon completion.
CAUTION
A Flash word must be in the erased state before being programmed.
Cumulative programming of bits within a Flash word is not allowed.
Table 9-67. Program D-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x11
Global address [22:16] to
identify the D-Flash block
001
Global address [15:0] of word to be programmed
010
Word 0 program value
011
Word 1 program value, if desired
100
Word 2 program value, if desired
101
Word 3 program value, if desired
Upon clearing CCIF to launch the Program D-Flash command, the user-supplied words will be transferred
to the Memory Controller and be programmed. The CCOBIX index value at Program D-Flash command
launch determines how many words will be programmed in the D-Flash block. No protection checks are
made in the Program D-Flash operation on the D-Flash block, only access error checks. The CCIF flag is
set when the operation has completed.
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Table 9-68. Program D-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] < 010 at command launch
Set if CCOBIX[2:0] > 101 at command launch
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see Table 9-30)
ACCERR
Set if an invalid global address [22:0] is supplied
Set if a misaligned word address is supplied (global address [0] != 0)
FSTAT
Set if the global address [22:0] points to an area in the D-Flash EEE partition
Set if the requested group of words breaches the end of the D-Flash block or goes
into the D-Flash EEE partition
FPVIOL
FERSTAT
9.4.2.18
None
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
EPVIOLIF
None
Erase D-Flash Sector Command
The Erase D-Flash Sector operation will erase all addresses in a sector of the D-Flash user partition.
Table 9-69. Erase D-Flash Sector Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x12
Global address [22:16] to identify
D-Flash block
Global address [15:0] anywhere within the sector to be erased.
See Section 9.1.2.2 for D-Flash sector size.
Upon clearing CCIF to launch the Erase D-Flash Sector command, the Memory Controller will erase the
selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase D-Flash Sector
operation has completed.
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Table 9-70. Erase D-Flash Sector Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see Table 9-30)
ACCERR
Set if an invalid global address [22:0] is supplied
Set if a misaligned word address is supplied (global address [0] != 0)
FSTAT
Set if the global address [22:0] points to the D-Flash EEE partition
FPVIOL
FERSTAT
9.4.2.19
None
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
EPVIOLIF
None
Enable EEPROM Emulation Command
The Enable EEPROM Emulation command causes the Memory Controller to enable EEE activity. EEE
activity is disabled after any reset.
Table 9-71. Enable EEPROM Emulation Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x13
Not required
Upon clearing CCIF to launch the Enable EEPROM Emulation command, the CCIF flag will set after the
Memory Controller enables EEE operations using the contents of the EEE tag RAM and tag counter. The
Full Partition D-Flash or the Partition D-Flash command must be run prior to launching the Enable
EEPROM Emulation command.
Table 9-72. Enable EEPROM Emulation Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if a Load Data Field command sequence is currently active
Set if Full Partition D-Flash or Partition D-Flash command not previously run
FSTAT
FERSTAT
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
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9.4.2.20
Disable EEPROM Emulation Command
The Disable EEPROM Emulation command causes the Memory Controller to suspend current EEE
activity.
Table 9-73. Disable EEPROM Emulation Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x14
Not required
Upon clearing CCIF to launch the Disable EEPROM Emulation command, the Memory Controller will
halt EEE operations at the next convenient point without clearing the EEE tag RAM or tag counter before
setting the CCIF flag.
Table 9-74. Disable EEPROM Emulation Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if a Load Data Field command sequence is currently active
Set if Full Partition D-Flash or Partition D-Flash command not previously run
FSTAT
FERSTAT
9.4.2.21
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
EEPROM Emulation Query Command
The EEPROM Emulation Query command returns EEE partition and status variables.
Table 9-75. EEPROM Emulation Query Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x15
Not required
001
Return DFPART
010
Return ERPART
011
Return ECOUNT(1)
100
Return Dead Sector Count
1. Indicates sector erase count
Return Ready Sector Count
Upon clearing CCIF to launch the EEPROM Emulation Query command, the CCIF flag will set after the
EEE partition and status variables are stored in the FCCOBIX register.If the Emulation Query command
is executed prior to partitioning (Partition D-Flash Command Section 9.4.2.15), the following reset values
are returned: DFPART = 0x_FFFF, ERPART = 0x_FFFF, ECOUNT = 0x_FFFF, Dead Sector Count =
0x_00, Ready Sector Count = 0x_00.
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Table 9-76. EEPROM Emulation Query Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see Table 9-30)
FSTAT
FERSTAT
9.4.2.22
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
Partition D-Flash Command
The Partition D-Flash command allows the user to allocate sectors within the D-Flash block for
applications and a partition within the buffer RAM for EEPROM access. The D-Flash block consists of
128 sectors with 256 bytes per sector. The Erase All Blocks command must be run prior to launching the
Partition D-Flash command.
Table 9-77. Partition D-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x20
Not required
001
Number of 256 byte sectors for the D-Flash user partition (DFPART)
010
Number of 256 byte sectors for buffer RAM EEE partition (ERPART)
Upon clearing CCIF to launch the Partition D-Flash command, the following actions are taken to define a
partition within the D-Flash block for direct access (DFPART) and a partition within the buffer RAM for
EEE use (ERPART):
• Validate the DFPART and ERPART values provided:
— DFPART <= 128 (maximum number of 256 byte sectors in D-Flash block)
— ERPART <= 16 (maximum number of 256 byte sectors in buffer RAM)
— If ERPART > 0, 128 - DFPART >= 12 (minimum number of 256 byte sectors in the D-Flash
block required to support EEE)
— If ERPART > 0, ((128-DFPART)/ERPART) >= 8 (minimum ratio of D-Flash EEE space to
buffer RAM EEE space to support EEE)
• Erase verify the D-Flash block and the EEE nonvolatile information register
• Program DFPART to the EEE nonvolatile information register at global address 0x12_0000 (see
Table 9-7)
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•
•
•
Program a duplicate DFPART to the EEE nonvolatile information register at global address
0x12_0002 (see Table 9-7)
Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see
Table 9-7)
Program a duplicate ERPART to the EEE nonvolatile information register at global address
0x12_0006 (see Table 9-7)
The D-Flash user partition will start at global address 0x10_0000. The buffer RAM EEE partition will end
at global address 0x13_FFFF. After the Partition D-Flash operation has completed, the CCIF flag will set.
Running the Partition D-Flash command a second time will result in the ACCERR bit within the FSTAT
register being set. The data value written corresponds to the number of 256 byte sectors allocated for either
direct D-Flash access (DFPART) or buffer RAM EEE access (ERPART).
Table 9-78. Partition D-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
Set if a Load Data Field command sequence is currently active
ACCERR
Set if command not available in current mode (see Table 9-30)
Set if partitions have already been defined
FSTAT
Set if an invalid DFPART or ERPART selection is supplied
FPVIOL
FERSTAT
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
EPVIOLIF
None
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Chapter 9 512 KByte Flash Module (S12XFTM512K3V1)
9.4.3
Interrupts
The Flash module can generate an interrupt when a Flash command operation has completed or when a
Flash command operation has detected an EEE error or an ECC fault.
Table 9-79. Flash Interrupt Sources
Interrupt Source
Global (CCR)
Mask
Interrupt Flag
Local Enable
CCIF
(FSTAT register)
CCIE
(FCNFG register)
I Bit
Flash EEE Erase Error
ERSERIF
(FERSTAT register)
ERSERIE
(FERCNFG register)
I Bit
Flash EEE Program Error
PGMERIF
(FERSTAT register)
PGMERIE
(FERCNFG register)
I Bit
Flash EEE Protection Violation
EPVIOLIF
(FERSTAT register)
EPVIOLIE
(FERCNFG register)
I Bit
Flash EEE Error Type 1 Violation
ERSVIF1
(FERSTAT register)
ERSVIE1
(FERCNFG register)
I Bit
Flash EEE Error Type 0 Violation
ERSVIF0
(FERSTAT register)
ERSVIE0
(FERCNFG register)
I Bit
ECC Double Bit Fault on Flash Read
DFDIF
(FERSTAT register)
DFDIE
(FERCNFG register)
I Bit
ECC Single Bit Fault on Flash Read
SFDIF
(FERSTAT register)
SFDIE
(FERCNFG register)
I Bit
Flash Command Complete
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
9.4.3.1
Description of Flash Interrupt Operation
The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the
Flash command interrupt request. The Flash module uses the ERSEIF, PGMEIF, EPVIOLIF, ERSVIF1,
ERSVIF0, DFDIF and SFDIF flags in combination with the ERSEIE, PGMEIE, EPVIOLIE, ERSVIE1,
ERSVIE0, DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a
detailed description of the register bits involved, refer to Section 9.3.2.5, “Flash Configuration Register
(FCNFG)”, Section 9.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 9.3.2.7, “Flash
Status Register (FSTAT)”, and Section 9.3.2.8, “Flash Error Status Register (FERSTAT)”.
The logic used for generating the Flash module interrupts is shown in Figure 9-27.
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Chapter 9 512 KByte Flash Module (S12XFTM512K3V1)
Flash Command Interrupt Request
CCIE
CCIF
ERSERIE
ERSERIF
PGMERIE
PGMERIF
EPVIOLIE
EPVIOLIF
Flash Error Interrupt Request
ERSVIE1
ERSVIF1
ERSVIE0
ERSVIF0
DFDIE
DFDIF
SFDIE
SFDIF
Figure 9-27. Flash Module Interrupts Implementation
9.4.4
Wait Mode
The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU
from wait via the CCIF interrupt (see Section 9.4.3, “Interrupts”).
9.4.5
Stop Mode
If a Flash command is active (CCIF = 0) or an EE-Emulation operation is pending when the MCU requests
stop mode, the current Flash operation will be completed before the CPU is allowed to enter stop mode.
9.5
Security
The Flash module provides security information to the MCU. The Flash security state is defined by the
SEC bits of the FSEC register (see Table 9-12). During reset, the Flash module initializes the FSEC
register using data read from the security byte of the Flash configuration field at global address
0x7F_FF0F.
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The security state out of reset can be permanently changed by programming the security byte of the Flash
configuration field. This assumes that you are starting from a mode where the necessary P-Flash erase and
program commands are available and that the upper region of the P-Flash is unprotected. If the Flash
security byte is successfully programmed, its new value will take affect after the next MCU reset.
The following subsections describe these security-related subjects:
• Unsecuring the MCU using Backdoor Key Access
• Unsecuring the MCU in Special Single Chip Mode using BDM
• Mode and Security Effects on Flash Command Availability
9.5.1
Unsecuring the MCU using Backdoor Key Access
The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the
contents of the backdoor keys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If
the KEYEN[1:0] bits are in the enabled state (see Section 9.3.2.2), the Verify Backdoor Access Key
command (see Section 9.4.2.12) allows the user to present four prospective keys for comparison to the
keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor
Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC
register (see Table 9-12) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not
permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash block 0
will not be available for read access and will return invalid data.
The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an
external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
If the KEYEN[1:0] bits are in the enabled state (see Section 9.3.2.2), the MCU can be unsecured by the
backdoor key access sequence described below:
1. Follow the command sequence for the Verify Backdoor Access Key command as explained in
Section 9.4.2.12
2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the
SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10
The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will
prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method
to re-enable the Verify Backdoor Access Key command.
After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is
unsecured, the sector containing the Flash security byte can be erased and the Flash security byte can be
reprogrammed to the unsecure state, if desired.
In the unsecure state, the user has full control of the contents of the backdoor keys by programming
addresses 0x7F_FF00–0x7F_FF07 in the Flash configuration field.
The security as defined in the Flash security byte (0x7F_FF0F) is not changed by using the Verify
Backdoor Access Key command sequence. The backdoor keys stored in addresses
0x7F_FF00–0x7F_FF07 are unaffected by the Verify Backdoor Access Key command sequence. After the
next reset of the MCU, the security state of the Flash module is determined by the Flash security byte
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Chapter 9 512 KByte Flash Module (S12XFTM512K3V1)
(0x7F_FF0F). The Verify Backdoor Access Key command sequence has no effect on the program and
erase protections defined in the Flash protection register, FPROT.
9.5.2
Unsecuring the MCU in Special Single Chip Mode using BDM
The MCU can be unsecured in special single chip mode by erasing the P-Flash and D-Flash memory by
one of the following methods:
• Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM,
send BDM commands to disable protection in the P-Flash and D-Flash memory, and execute the
Erase All Blocks command write sequence to erase the P-Flash and D-Flash memory.
• Reset the MCU into special expanded wide mode, disable protection in the P-Flash and D-Flash
memory and run code from external memory to execute the Erase All Blocks command write
sequence to erase the P-Flash and D-Flash memory.
After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into
special single chip mode. The BDM will execute the Erase Verify All Blocks command write sequence to
verify that the P-Flash and D-Flash memory is erased. If the P-Flash and D-Flash memory are verified as
erased the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may
be programmed to the unsecure state by the following method:
• Send BDM commands to execute a ‘Program P-Flash’ command sequence to program the Flash
security byte to the unsecured state and reset the MCU.
9.5.3
Mode and Security Effects on Flash Command Availability
The availability of Flash module commands depends on the MCU operating mode and security state as
shown in Table 9-30.
9.6
Initialization
On each system reset the Flash module executes a reset sequence which establishes initial values for the
Flash Block Configuration Parameters, the FPROT and DFPROT protection registers, and the FOPT and
FSEC registers. The Flash module reverts to built-in default values that leave the module in a fully
protected and secured state if errors are encountered during execution of the reset sequence. If a double bit
fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set. The
ACCERR bit in the FSTAT register is set if errors are encountered while initializing the EEE buffer ram
during the reset sequence.
CCIF remains clear throughout the reset sequence. The Flash module holds off all CPU access for the
initial portion of the reset sequence. While Flash reads are possible when the hold is removed, writes to
the FCCOBIX, FCCOBHI, and FCCOBLO registers are ignored to prevent command activity while the
Memory Controller remains busy. Completion of the reset sequence is marked by setting CCIF high which
enables writes to the FCCOBIX, FCCOBHI, and FCCOBLO registers to launch any available Flash
command.
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
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Chapter 10
128 KByte Flash Module (S12XFTM128K2XFV1)
Table 10-1. Revision History
Revision
Number
Revision
Date
V01.00
12 Dec 2007
V01.01
19 Dec 2007
Sections
Affected
- Initial version
10.4.2/10-379
10.4.2/10-379
10.4.2/10-379
10.4.2/10-379
10.3.1/10-348
10.1.3/10-346
10.3.1/10-348
10.3.1/10-348
V01.02
25 Sep 2009
Description of Changes
- Removed Load Data Field command 0x05
- Updated Command Error Handling tables based on parent-child relationship
with FTM512K3
- Corrected Error Handling table for Full Partition D-Flash, Partition D-Flash,
and EEPROM Emulation Query commands
- Corrected maximum allowed ERPART for Full Partition D-Flash and Partition
D-Flash commands
- Corrected P-Flash IFR Accessibility table
- Corrected Buffer RAM size in Feature List
- Corrected EEE Resource Memory Map
- Corrected P-Flash Memory Map
- Change references for D-Flash from 16 Kbytes to 32 Kbytes
- Clarify single bit fault correction for P-Flash phrase
10.1/10-344
10.3.2.1/10-355 - Expand FDIV vs OSCCLK Frequency table
10.4.2.4/10-382 - Add statement concerning code runaway when executing Read Once
command from Flash block containing associated fields
10.4.2.6/10-383 - Add statement concerning code runaway when executing Program Once
command from Flash block containing associated fields
10.4.2.11/10- - Add statement concerning code runaway when executing Verify Backdoor
Access Key command from Flash block containing associated fields
387
- Relate Key 0 to associated Backdoor Comparison Key address
10.4.2.11/10- - Change “power down reset” to “reset”
- Add ACCERR condition for Disable EEPROM Emulation command
387
10.4.2.11/10- The following changes were made to clarify module behavior related to Flash
register access during reset sequence and while Flash commands are active:
387
10.4.2.19/10- - Add caution concerning register writes while command is active
- Writes to FCLKDIV are allowed during reset sequence while CCIF is clear
396
- Add caution concerning register writes while command is active
- Writes to FCCOBIX, FCCOBHI, FCCOBLO registers are ignored during
10.3.2/10-353 reset sequence
10.3.2.1/10-355
10.4.1.2/10-374
10.6/10-402
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10.1
Introduction
The FTM128K2XF module implements the following:
• 128 Kbytes of P-Flash (Program Flash) memory, consisting of 2 physical Flash blocks, intended
primarily for nonvolatile code storage
• 32 Kbytes of D-Flash (Data Flash) memory, consisting of 1 physical Flash block, that can be used
as nonvolatile storage to support the built-in hardware scheme for emulated EEPROM, as basic
Flash memory primarily intended for nonvolatile data storage, or as a combination of both
• 2 Kbytes of buffer RAM, consisting of 1 physical RAM block, that can be used as emulated
EEPROM using a built-in hardware scheme, as basic RAM, or as a combination of both
The Flash memory is ideal for single-supply applications allowing for field reprogramming without
requiring external high voltage sources for program or erase operations. The Flash module includes a
memory controller that executes commands to modify Flash memory contents or configure module
resources for emulated EEPROM operation. The user interface to the memory controller consists of the
indexed Flash Common Command Object (FCCOB) register which is written to with the command, global
address, data, and any required command parameters. The memory controller must complete the execution
of a command before the FCCOB register can be written to with a new command.
CAUTION
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
The RAM and Flash memory may be read as bytes, aligned words, or misaligned words. Read access time
is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. For Flash memory,
an erased bit reads 1 and a programmed bit reads 0.
It is not possible to read from a Flash block while any command is executing on that specific Flash block.
It is possible to read from a Flash block while a command is executing on a different Flash block.
Both P-Flash and D-Flash memories are implemented with Error Correction Codes (ECC) that can resolve
single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that
programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read
by phrase, only one single bit fault in the phrase containing the byte or word accessed will be corrected.
10.1.1
Glossary
Buffer RAM — The buffer RAM constitutes the volatile memory store required for EEE. Memory space
in the buffer RAM not required for EEE can be partitioned to provide volatile memory space for
applications.
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Chapter 10 128 KByte Flash Module (S12XFTM128K2XFV1)
Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including
program and erase) on the Flash memory.
D-Flash Memory — The D-Flash memory constitutes the nonvolatile memory store required for EEE.
Memory space in the D-Flash memory not required for EEE can be partitioned to provide nonvolatile
memory space for applications.
D-Flash Sector — The D-Flash sector is the smallest portion of the D-Flash memory that can be erased.
The D-Flash sector consists of four 64 byte rows for a total of 256 bytes.
EEE (Emulated EEPROM) — A method to emulate the small sector size features and endurance
characteristics associated with an EEPROM.
EEE IFR — Nonvolatile information register located in the D-Flash block that contains data required to
partition the D-Flash memory and buffer RAM for EEE. The EEE IFR is visible in the global memory map
by setting the EEEIFRON bit in the MMCCTL1 register.
NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters
required for Flash command execution.
Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes eight
ECC bits for single bit fault correction and double bit fault detection within the phrase.
P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications.
P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased.
Each P-Flash sector contains 1024 bytes.
Program IFR — Nonvolatile information register located in the P-Flash block that contains the Device
ID, Version ID, and the Program Once field. The Program IFR is visible in the global memory map by
setting the PGMIFRON bit in the MMCCTL1 register.
10.1.2
10.1.2.1
•
•
•
•
•
•
P-Flash Features
128 Kbytes of P-Flash memory composed of two 64 Kbyte Flash blocks. The 64 Kbyte Flash
blocks are each divided into 64 sectors of 1024 bytes.
Single bit fault correction and double bit fault detection within a 64-bit phrase during read
operations
Automated program and erase algorithm with verify and generation of ECC parity bits
Fast sector erase and phrase program operation
Ability to program up to one phrase in each P-Flash block simultaneously
Flexible protection scheme to prevent accidental program or erase of P-Flash memory
10.1.2.2
•
•
Features
D-Flash Features
Up to 32 Kbytes of D-Flash memory with 256 byte sectors for user access
Dedicated commands to control access to the D-Flash memory over EEE operation
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Chapter 10 128 KByte Flash Module (S12XFTM128K2XFV1)
•
•
•
•
Single bit fault correction and double bit fault detection within a word during read operations
Automated program and erase algorithm with verify and generation of ECC parity bits
Fast sector erase and word program operation
Ability to program up to four words in a burst sequence
10.1.2.3
•
•
•
•
•
•
•
Up to 2 Kbytes of emulated EEPROM (EEE) accessible as 2 Kbytes of RAM
Flexible protection scheme to prevent accidental program or erase of data
Automatic EEE file handling using an internal Memory Controller
Automatic transfer of valid EEE data from D-Flash memory to buffer RAM on reset
Ability to monitor the number of outstanding EEE related buffer RAM words left to be
programmed into D-Flash memory
Ability to disable EEE operation and allow priority access to the D-Flash memory
Ability to cancel all pending EEE operations and allow priority access to the D-Flash memory
10.1.2.4
•
User Buffer RAM Features
Up to 2 Kbytes of RAM for user access
10.1.2.5
•
•
•
Emulated EEPROM Features
Other Flash Module Features
No external high-voltage power supply required for Flash memory program and erase operations
Interrupt generation on Flash command completion and Flash error detection
Security mechanism to prevent unauthorized access to the Flash memory
10.1.3
Block Diagram
The block diagram of the Flash module is shown in Figure 10-1.
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Chapter 10 128 KByte Flash Module (S12XFTM128K2XFV1)
Flash
Interface
Command
Interrupt
Request
Registers
Error
Interrupt
Request
Protection
16bit
internal
bus
P-Flash
Block 0
8Kx72
sector 0
sector 1
sector 63
Security
Oscillator
Clock (XTAL)
XGATE
CPU
P-Flash
Block 1
8Kx72
Clock
Divider FCLK
sector 0
sector 1
Memory
Controller
Scratch RAM
512x16
Buffer RAM
1Kx16
sector 63
D-Flash
16Kx22
sector 0
sector 1
sector 127
Tag RAM
64x16
Figure 10-1. FTM128K2 Block Diagram
10.2
External Signal Description
The Flash module contains no signals that connect off-chip.
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Chapter 10 128 KByte Flash Module (S12XFTM128K2XFV1)
10.3
Memory Map and Registers
This section describes the memory map and registers for the Flash module. Read data from unimplemented
memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space
in the Flash module will be ignored by the Flash module.
10.3.1
Module Memory Map
The S12X architecture places the P-Flash memory between global addresses 0x78_0000 and 0x7F_FFFF
as shown in Table 10-2. The P-Flash memory map is shown in Figure 10-2.
Table 10-2. P-Flash Memory Addressing
Global Address
Size
(Bytes)
0x7F_0000 – 0x7F_FFFF
64 K
P-Flash Block 0
Contains Flash Configuration Field
(see Table 10-3)
0x79_0000 – 0x7E_FFFF
384 K
No P-Flash Memory
0x78_0000 – 0x78_FFFF
64 K
P-Flash Block 1
Description
The FPROT register, described in Section 10.3.2.9, can be set to protect regions in the Flash memory from
accidental program or erase. Three separate memory regions, one growing upward from global address
0x7F_8000 in the Flash memory (called the lower region), one growing downward from global address
0x7F_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash
memory, can be activated for protection. The Flash memory addresses covered by these protectable regions
are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader
code since it covers the vector space. Default protection settings as well as security information that allows
the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in
Table 10-3.
Table 10-3. Flash Configuration Field(1)
Global Address
Size
(Bytes)
0x7F_FF00 – 0x7F_FF07
8
0x7F_FF08 –
0x7F_FF0B(2)
4
0x7F_FF0C2
1
P-Flash Protection byte.
Refer to Section 10.3.2.9, “P-Flash Protection Register (FPROT)”
0x7F_FF0D2
1
EEE Protection byte
Refer to Section 10.3.2.10, “EEE Protection Register (EPROT)”
0x7F_FF0E2
1
Flash Nonvolatile byte
Refer to Section 10.3.2.14, “Flash Option Register (FOPT)”
Description
Backdoor Comparison Key
Refer to Section 10.4.2.11, “Verify Backdoor Access Key Command,” and
Section 10.5.1, “Unsecuring the MCU using Backdoor Key Access”
Reserved
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Chapter 10 128 KByte Flash Module (S12XFTM128K2XFV1)
Table 10-3. Flash Configuration Field(1)
Global Address
Size
(Bytes)
Description
Flash Security byte
Refer to Section 10.3.2.2, “Flash Security Register (FSEC)”
1. Older versions may have swapped protection byte addresses
2. 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in
the 0x7F_FF08 - 0x7F_FF0B reserved field should be programmed to 0xFF.
0x7F_FF0F2
1
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Chapter 10 128 KByte Flash Module (S12XFTM128K2XFV1)
P-Flash START = 0x78_0000
0x78_FFFF
Flash Protected/Unprotected Region
96 Kbytes
0x7F_0000
0x7F_8000
0x7F_8400
0x7F_8800
0x7F_9000
Flash Protected/Unprotected Lower Region
1, 2, 4, 8 Kbytes
0x7F_A000
Flash Protected/Unprotected Region
8 Kbytes (up to 29 Kbytes)
0x7F_C000
0x7F_E000
Flash Protected/Unprotected Higher Region
2, 4, 8, 16 Kbytes
0x7F_F000
0x7F_F800
P-Flash END = 0x7F_FFFF
Flash Configuration Field
16 bytes (0x7F_FF00 - 0x7F_FF0F)
Figure 10-2. P-Flash Memory Map
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Table 10-4. Program IFR Fields
Global Address
(PGMIFRON)
Size
(Bytes)
0x40_0000 – 0x40_0007
8
Device ID
0x40_0008 – 0x40_00E7
224
Reserved
0x40_00E8 – 0x40_00E9
2
Version ID
0x40_00EA – 0x40_00FF
22
Reserved
0x40_0100 – 0x40_013F
64
Program Once Field
Refer to Section 10.4.2.6, “Program Once Command”
0x40_0140 – 0x40_01FF
192
Reserved
Field Description
Table 10-5. P-Flash IFR Accessibility
Global Address
(PGMIFRON)
Size
(Bytes)
0x40_0000 – 0x40_01FF
512
XBUS0 (PBLK0)(1)
0x40_0200 – 0x40_03FF
512
Unimplemented
0x40_0400 – 0x40_05FF
512
Unimplemented
0x40_0600 – 0x40_07FF
512
1. Refer to Table 10-4 for more details.
Accessed From
XBUS1 (PBLK1)
Table 10-6. EEE Resource Fields
Global Address
Size
(Bytes)
0x10_0000 – 0x10_7FFF
32,768
D-Flash Memory (User and EEE)
0x10_8000 – 0x11_FFFF
98,304
Reserved
0x12_0000 – 0x12_007F
128
0x12_0080 – 0x12_0FFF
3,968
Reserved
0x12_1000 – 0x12_1F7F
3,968
Reserved
0x12_1F80 – 0x12_1FFF
128
0x12_2000 – 0x12_3BFF
7,168
Reserved
0x12_3C00 – 0x12_3FFF
1,024
Memory Controller Scratch RAM (TMGRAMON1 = 1)
0x12_4000 – 0x12_DFFF
40,960
Reserved
0x12_E000 – 0x12_FFFF
8,192
Reserved
0x13_0000 – 0x13_F7FF
63,488
Reserved
0x13_F800 – 0x13_FFFF
1. MMCCTL1 register bit
2,048
Buffer RAM (User and EEE)
Description
EEE Nonvolatile Information Register (EEEIFRON(1) = 1)
EEE Tag RAM (TMGRAMON1 = 1)
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Chapter 10 128 KByte Flash Module (S12XFTM128K2XFV1)
D-Flash START = 0x10_0000
D-Flash User Partition
D-Flash Memory
32 Kbytes
D-Flash EEE Partition
D-Flash END = 0x10_7FFF
0x12_0000
0x12_1000
0x12_2000
0x12_4000
EEE Nonvolatile Information Register (EEEIFRON)
128 bytes
EEE Tag RAM (TMGRAMON)
128 bytes
Memory Controller Scratch RAM (TMGRAMON)
1024 bytes
0x12_E000
0x12_FFFF
Buffer RAM START = 0x13_F800
Buffer RAM User Partition
0x13_FE00
0x13_FE40
0x13_FE80
0x13_FEC0
0x13_FF00
0x13_FF40
0x13_FF80
0x13_FFC0
Buffer RAM END = 0x13_FFFF
Buffer RAM
2 Kbyte
Buffer RAM EEE Partition
Protectable Region (EEE only)
64, 128, 192, 256, 320, 384, 448, 512 bytes
Figure 10-3. EEE Resource Memory Map
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The Full Partition D-Flash command (see Section 10.4.2.14) is used to program the EEE nonvolatile
information register fields where address 0x12_0000 defines the D-Flash partition for user access and
address 0x12_0004 defines the buffer RAM partition for EEE operations.
Table 10-7. EEE Nonvolatile Information Register Fields
Global Address
(EEEIFRON)
Size
(Bytes)
0x12_0000 – 0x12_0001
2
D-Flash User Partition (DFPART)
Refer to Section 10.4.2.14, “Full Partition D-Flash Command”
0x12_0002 – 0x12_0003
2
D-Flash User Partition (duplicate(1))
0x12_0004 – 0x12_0005
2
Buffer RAM EEE Partition (ERPART)
Refer to Section 10.4.2.14, “Full Partition D-Flash Command”
0x12_0006 – 0x12_0007
2
Buffer RAM EEE Partition (duplicate1)
Description
0x12_0008 – 0x12_007F
120
Reserved
1. Duplicate value used if primary value generates a double bit fault when read during the reset sequence.
10.3.2
Register Descriptions
The Flash module contains a set of 20 control and status registers located between Flash module base +
0x0000 and 0x0013. A summary of the Flash module registers is given in Figure 10-4 with detailed
descriptions in the following subsections.
CAUTION
Writes to any Flash register must be avoided while a Flash command is
active (CCIF=0) to prevent corruption of Flash register contents and
Memory Controller behavior.
Address
& Name
0x0000
FCLKDIV
0x0001
FSEC
0x0002
FCCOBIX
0x0003
FECCRIX
0x0004
FCNFG
7
R
6
5
4
3
2
1
0
FDIV6
FDIV5
FDIV4
FDIV3
FDIV2
FDIV1
FDIV0
KEYEN1
KEYEN0
RNV5
RNV4
RNV3
RNV2
SEC1
SEC0
0
0
0
0
0
CCOBIX2
CCOBIX1
CCOBIX0
ECCRIX2
ECCRIX1
ECCRIX0
FDFD
FSFD
FDIVLD
W
R
W
R
W
R
0
0
0
0
0
W
R
0
CCIE
0
0
IGNSF
0
W
Figure 10-4. FTM128K2XF Register Summary
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Address
& Name
0x0005
FERCNFG
0x0006
FSTAT
0x0007
FERSTAT
0x0008
FPROT
0x0009
EPROT
0x000A
FCCOBHI
0x000B
FCCOBLO
0x000C
ETAGHI
0x000D
ETAGLO
0x000E
FECCRHI
0x000F
FECCRLO
0x0010
FOPT
0x0011
FRSV0
0x0012
FRSV1
7
6
ERSERIE
PGMERIE
R
5
4
3
2
1
0
EPVIOLIE
ERSVIE1
ERSVIE0
DFDIE
SFDIE
MGBUSY
RSVD
MGSTAT1
MGSTAT0
EPVIOLIF
ERSVIF1
ERSVIF0
DFDIF
SFDIF
FPHDIS
FPHS1
FPHS0
FPLDIS
FPLS1
FPLS0
RNV5
RNV4
EPDIS
EPS2
EPS1
EPS0
0
W
R
0
CCIF
ACCERR
FPVIOL
W
R
0
ERSERIF
PGMERIF
W
R
RNV6
FPOPEN
W
R
RNV6
EPOPEN
W
R
CCOB15
CCOB14
CCOB13
CCOB12
CCOB11
CCOB10
CCOB9
CCOB8
CCOB7
CCOB6
CCOB5
CCOB4
CCOB3
CCOB2
CCOB1
CCOB0
ETAG15
ETAG14
ETAG13
ETAG12
ETAG11
ETAG10
ETAG9
ETAG8
ETAG7
ETAG6
ETAG5
ETAG4
ETAG3
ETAG2
ETAG1
ETAG0
ECCR15
ECCR14
ECCR13
ECCR12
ECCR11
ECCR10
ECCR9
ECCR8
ECCR7
ECCR6
ECCR5
ECCR4
ECCR3
ECCR2
ECCR1
ECCR0
NV7
NV6
NV5
NV4
NV3
NV2
NV1
NV0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Figure 10-4. FTM128K2XF Register Summary (continued)
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Address
& Name
0x0013
FRSV2
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
W
= Unimplemented or Reserved
Figure 10-4. FTM128K2XF Register Summary (continued)
10.3.2.1
Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
Offset Module Base + 0x0000
7
R
6
5
4
3
2
1
0
0
0
0
FDIVLD
FDIV[6:0]
W
Reset
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-5. Flash Clock Divider Register (FCLKDIV)
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
Table 10-8. FCLKDIV Field Descriptions
Field
7
FDIVLD
6–0
FDIV[6:0]
Description
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms. Table 10-9 shows recommended values for FDIV[6:0] based on OSCCLK frequency.
Please refer to Section 10.4.1, “Flash Command Operations,” for more information.
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
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Table 10-9. FDIV vs OSCCLK Frequency
OSCCLK Frequency
(MHz)
MIN(1)
MAX
FDIV[6:0]
(2)
OSCCLK Frequency
(MHz)
MIN
1
MAX
FDIV[6:0]
2
OSCCLK Frequency
(MHz)
MIN
1
MAX
FDIV[6:0]
2
33.60
34.65
0x20
67.20
68.25
0x40
1.60
2.10
0x01
34.65
35.70
0x21
68.25
69.30
0x41
2.40
3.15
0x02
35.70
36.75
0x22
69.30
70.35
0x42
3.20
4.20
0x03
36.75
37.80
0x23
70.35
71.40
0x43
4.20
5.25
0x04
37.80
38.85
0x24
71.40
72.45
0x44
5.25
6.30
0x05
38.85
39.90
0x25
72.45
73.50
0x45
6.30
7.35
0x06
39.90
40.95
0x26
73.50
74.55
0x46
7.35
8.40
0x07
40.95
42.00
0x27
74.55
75.60
0x47
8.40
9.45
0x08
42.00
43.05
0x28
75.60
76.65
0x48
9.45
10.50
0x09
43.05
44.10
0x29
76.65
77.70
0x49
10.50
11.55
0x0A
44.10
45.15
0x2A
77.70
78.75
0x4A
11.55
12.60
0x0B
45.15
46.20
0x2B
78.75
79.80
0x4B
12.60
13.65
0x0C
46.20
47.25
0x2C
79.80
80.85
0x4C
13.65
14.70
0x0D
47.25
48.30
0x2D
80.85
81.90
0x4D
14.70
15.75
0x0E
48.30
49.35
0x2E
81.90
82.95
0x4E
15.75
16.80
0x0F
49.35
50.40
0x2F
82.95
84.00
0x4F
16.80
17.85
0x10
50.40
51.45
0x30
84.00
85.05
0x50
17.85
18.90
0x11
51.45
52.50
0x31
85.05
86.10
0x51
18.90
19.95
0x12
52.50
53.55
0x32
86.10
87.15
0x52
19.95
21.00
0x13
53.55
54.60
0x33
87.15
88.20
0x53
21.00
22.05
0x14
54.60
55.65
0x34
88.20
89.25
0x54
22.05
23.10
0x15
55.65
56.70
0x35
89.25
90.30
0x55
23.10
24.15
0x16
56.70
57.75
0x36
90.30
91.35
0x56
24.15
25.20
0x17
57.75
58.80
0x37
91.35
92.40
0x57
25.20
26.25
0x18
58.80
59.85
0x38
92.40
93.45
0x58
26.25
27.30
0x19
59.85
60.90
0x39
93.45
94.50
0x59
27.30
28.35
0x1A
60.90
61.95
0x3A
94.50
95.55
0x5A
28.35
29.40
0x1B
61.95
63.00
0x3B
95.55
96.60
0x5B
29.40
30.45
0x1C
63.00
64.05
0x3C
96.60
97.65
0x5C
30.45
31.50
0x1D
64.05
65.10
0x3D
97.65
98.70
0x5D
31.50
32.55
0x1E
65.10
66.15
0x3E
98.70
99.75
0x5E
32.55
33.60
0x1F
66.15
67.20
1. FDIV shown generates an FCLK frequency of >0.8 MHz
0x3F
99.75
100.80
0x5F
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2. FDIV shown generates an FCLK frequency of 1.05 MHz
10.3.2.2
Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
Offset Module Base + 0x0001
7
R
6
5
4
KEYEN[1:0]
3
2
1
RNV[5:2]
0
SEC[1:0]
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 10-6. Flash Security Register (FSEC)
All bits in the FSEC register are readable but not writable.
During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the
Flash configuration field at global address 0x7F_FF0F located in P-Flash memory (see Table 10-3) as
indicated by reset condition F in Figure 10-6. If a double bit fault is detected while reading the P-Flash
phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be
set to leave the Flash module in a secured state with backdoor key access disabled.
Table 10-10. FSEC Field Descriptions
Field
Description
7–6
Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the
KEYEN[1:0] Flash module as shown in Table 10-11.
5–2
RNV[5:2}
Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements.
1–0
SEC[1:0]
Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 10-12. If the
Flash module is unsecured using backdoor key access, the SEC bits are forced to 10.
Table 10-11. Flash KEYEN States
KEYEN[1:0]
Status of Backdoor Key Access
00
DISABLED
01
DISABLED(1)
10
ENABLED
11
DISABLED
1. Preferred KEYEN state to disable backdoor key access.
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Table 10-12. Flash Security States
SEC[1:0]
Status of Security
00
SECURED
01
SECURED(1)
10
UNSECURED
11
SECURED
1. Preferred SEC state to set MCU to secured state.
The security function in the Flash module is described in Section 10.5.
10.3.2.3
Flash CCOB Index Register (FCCOBIX)
The FCCOBIX register is used to index the FCCOB register for Flash memory operations.
Offset Module Base + 0x0002
R
7
6
5
4
3
0
0
0
0
0
2
1
0
CCOBIX[2:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-7. FCCOB Index Register (FCCOBIX)
CCOBIX bits are readable and writable while remaining bits read 0 and are not writable.
Table 10-13. FCCOBIX Field Descriptions
Field
Description
2–0
CCOBIX[1:0]
Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register
array is being read or written to. See Section 10.3.2.11, “Flash Common Command Object Register (FCCOB),”
for more details.
10.3.2.4
Flash ECCR Index Register (FECCRIX)
The FECCRIX register is used to index the FECCR register for ECC fault reporting.
Offset Module Base + 0x0003
R
7
6
5
4
3
0
0
0
0
0
2
1
0
ECCRIX[2:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-8. FECCR Index Register (FECCRIX)
ECCRIX bits are readable and writable while remaining bits read 0 and are not writable.
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Table 10-14. FECCRIX Field Descriptions
Field
Description
2-0
ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is
ECCRIX[2:0] being read. See Section 10.3.2.13, “Flash ECC Error Results Register (FECCR),” for more details.
10.3.2.5
Flash Configuration Register (FCNFG)
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU or XGATE.
Offset Module Base + 0x0004
7
R
6
5
0
0
CCIE
4
3
2
0
0
IGNSF
1
0
FDFD
FSFD
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-9. Flash Configuration Register (FCNFG)
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
Table 10-15. FCNFG Field Descriptions
Field
Description
7
CCIE
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 10.3.2.7)
4
IGNSF
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section 10.3.2.8).
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
generated
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Table 10-15. FCNFG Field Descriptions (continued)
Field
Description
1
FDFD
Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array
read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The
FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual
double bit fault is detected.
0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see
Section 10.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG
register is set (see Section 10.3.2.6)
0
FSFD
Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array
read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. The
FECCR registers will not be updated during the Flash array read operation with FSFD set unless an actual single
bit fault is detected.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 10.3.2.7)
and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section 10.3.2.6)
10.3.2.6
Flash Error Configuration Register (FERCNFG)
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
Offset Module Base + 0x0005
7
6
R
5
4
3
2
1
0
EPVIOLIE
ERSVIE1
ERSVIE0
DFDIE
SFDIE
0
0
0
0
0
0
ERSERIE
PGMERIE
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 10-10. Flash Error Configuration Register (FERCNFG)
All assigned bits in the FERCNFG register are readable and writable.
Table 10-16. FERCNFG Field Descriptions
Field
Description
7
ERSERIE
EEE Erase Error Interrupt Enable — The ERSERIE bit controls interrupt generation when a failure is detected
during an EEE erase operation.
0 ERSERIF interrupt disabled
1 An interrupt will be requested whenever the ERSERIF flag is set (see Section 10.3.2.8)
6
PGMERIE
EEE Program Error Interrupt Enable — The PGMERIE bit controls interrupt generation when a failure is
detected during an EEE program operation.
0 PGMERIF interrupt disabled
1 An interrupt will be requested whenever the PGMERIF flag is set (see Section 10.3.2.8)
4
EPVIOLIE
EEE Protection Violation Interrupt Enable — The EPVIOLIE bit controls interrupt generation when a
protection violation is detected during a write to the buffer RAM EEE partition.
0 EPVIOLIF interrupt disabled
1 An interrupt will be requested whenever the EPVIOLIF flag is set (see Section 10.3.2.8)
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Table 10-16. FERCNFG Field Descriptions (continued)
Field
Description
3
ERSVIE1
EEE Error Type 1 Interrupt Enable — The ERSVIE1 bit controls interrupt generation when a change state error
is detected during an EEE operation.
0 ERSVIF1 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF1 flag is set (see Section 10.3.2.8)
2
ERSVIE0
EEE Error Type 0 Interrupt Enable — The ERSVIE0 bit controls interrupt generation when a sector format error
is detected during an EEE operation.
0 ERSVIF0 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF0 flag is set (see Section 10.3.2.8)
1
DFDIE
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see Section 10.3.2.8)
0
SFDIE
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 10.3.2.8)
1 An interrupt will be requested whenever the SFDIF flag is set (see Section 10.3.2.8)
10.3.2.7
Flash Status Register (FSTAT)
The FSTAT register reports the operational status of the Flash module.
Offset Module Base + 0x0006
7
6
R
5
4
0
CCIF
ACCERR
FPVIOL
0
0
3
2
MGBUSY
RSVD
0
0
1
0
MGSTAT[1:0]
W
Reset
1
0
0(1)
01
= Unimplemented or Reserved
Figure 10-11. Flash Status Register (FSTAT)
1. Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 10.6).
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
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Table 10-17. FSTAT Field Descriptions
Field
Description
7
CCIF
Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The
CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command
completion or command violation.
0 Flash command in progress
1 Flash command has completed
5
ACCERR
Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory
caused by either a violation of the command write sequence (see Section 10.4.1.2) or issuing an illegal Flash
command or when errors are encountered while initializing the EEE buffer ram during the reset sequence.
While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by
writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.
0 No access error detected
1 Access error detected
4
FPVIOL
Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an
address in a protected area of P-Flash memory during a command write sequence. The FPVIOL bit is cleared
by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not
possible to launch a command or start a command write sequence.
0 No protection violation detected
1 Protection violation detected
3
MGBUSY
Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller.
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0) or is handling internal EEE operations
2
RSVD
Reserved Bit — This bit is reserved and always reads 0.
1–0
Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error
MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See Section 10.4.2,
“Flash Command Description,” and Section 10.6, “Initialization” for details.
10.3.2.8
Flash Error Status Register (FERSTAT)
The FERSTAT register reflects the error status of internal Flash operations.
Offset Module Base + 0x0007
7
6
ERSERIF
PGMERIF
0
0
R
5
4
3
2
1
0
EPVIOLIF
ERSVIF1
ERSVIF0
DFDIF
SFDIF
0
0
0
0
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 10-12. Flash Error Status Register (FERSTAT)
All flags in the FERSTAT register are readable and only writable to clear the flag.
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Table 10-18. FERSTAT Field Descriptions
Field
Description
7
ERSERIF
EEE Erase Error Interrupt Flag — The setting of the ERSERIF flag occurs due to an error in a Flash erase
command that resulted in the erase operation not being successful during EEE operations. The ERSERIF flag
is cleared by writing a 1 to ERSERIF. Writing a 0 to the ERSERIF flag has no effect on ERSERIF. While
ERSERIF is set, it is possible to write to the buffer RAM EEE partition but the data written will not be transferred
to the D-Flash EEE partition.
0 Erase command successfully completed on the D-Flash EEE partition
1 Erase command failed on the D-Flash EEE partition
6
PGMERIF
EEE Program Error Interrupt Flag — The setting of the PGMERIF flag occurs due to an error in a Flash
program command that resulted in the program operation not being successful during EEE operations. The
PGMERIF flag is cleared by writing a 1 to PGMERIF. Writing a 0 to the PGMERIF flag has no effect on
PGMERIF. While PGMERIF is set, it is possible to write to the buffer RAM EEE partition but the data written will
not be transferred to the D-Flash EEE partition.
0 Program command successfully completed on the D-Flash EEE partition
1 Program command failed on the D-Flash EEE partition
4
EPVIOLIF
EEE Protection Violation Interrupt Flag —The setting of the EPVIOLIF flag indicates an attempt was made to
write to a protected area of the buffer RAM EEE partition. The EPVIOLIF flag is cleared by writing a 1 to
EPVIOLIF. Writing a 0 to the EPVIOLIF flag has no effect on EPVIOLIF. While EPVIOLIF is set, it is possible to
write to the buffer RAM EEE partition as long as the address written to is not in a protected area.
0 No EEE protection violation
1 EEE protection violation detected
3
ERSVIF1
EEE Error Interrupt 1 Flag —The setting of the ERSVIF1 flag indicates that the memory controller was unable
to change the state of a D-Flash EEE sector. The ERSVIF1 flag is cleared by writing a 1 to ERSVIF1. Writing a
0 to the ERSVIF1 flag has no effect on ERSVIF1. While ERSVIF1 is set, it is possible to write to the buffer RAM
EEE partition but the data written will not be transferred to the D-Flash EEE partition.
0 No EEE sector state change error detected
1 EEE sector state change error detected
2
ERSVIF0
EEE Error Interrupt 0 Flag —The setting of the ERSVIF0 flag indicates that the memory controller was unable
to format a D-Flash EEE sector for EEE use. The ERSVIF0 flag is cleared by writing a 1 to ERSVIF0. Writing a
0 to the ERSVIF0 flag has no effect on ERSVIF0. While ERSVIF0 is set, it is possible to write to the buffer RAM
EEE partition but the data written will not be transferred to the D-Flash EEE partition.
0 No EEE sector format error detected
1 EEE sector format error detected
1
DFDIF
Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was
detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation
was attempted on a Flash block that was under a Flash command operation. The DFDIF flag is cleared by writing
a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.
0 No double bit fault detected
1 Double bit fault detected or an invalid Flash array read operation attempted
0
SFDIF
Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag
indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation
or that a Flash array read operation was attempted on a Flash block that was under a Flash command operation.
The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF.
0 No single bit fault detected
1 Single bit fault detected and corrected or an invalid Flash array read operation attempted
10.3.2.9
P-Flash Protection Register (FPROT)
The FPROT register defines which P-Flash sectors are protected against program and erase operations.
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Offset Module Base + 0x0008
7
R
6
5
4
3
2
1
0
RNV6
FPOPEN
FPHDIS
FPHS[1:0]
FPLDIS
FPLS[1:0]
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 10-13. Flash Protection Register (FPROT)
The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected
region can only be increased (see Section 10.3.2.9.1, “P-Flash Protection Restrictions,” and Table 10-23).
During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte
in the Flash configuration field at global address 0x7F_FF0C located in P-Flash memory (see Table 10-3)
as indicated by reset condition ‘F’ in Figure 10-13. To change the P-Flash protection that will be loaded
during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash
protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase
containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and
remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected.
Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error
and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible
if any of the P-Flash sectors contained in the same P-Flash block are protected.
Table 10-19. FPROT Field Descriptions
Field
Description
7
FPOPEN
Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or
erase operations as shown in Table 10-20 for the P-Flash block.
0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the
corresponding FPHS and FPLS bits
1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the
corresponding FPHS and FPLS bits
6
RNV[6]
Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements.
5
FPHDIS
Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a
protected/unprotected area in a specific region of the P-Flash memory ending with global address 0x7F_FFFF.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
4–3
FPHS[1:0]
Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area
in P-Flash memory as shown inTable 10-21. The FPHS bits can only be written to while the FPHDIS bit is set.
2
FPLDIS
1–0
FPLS[1:0]
Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a
protected/unprotected area in a specific region of the P-Flash memory beginning with global address
0x7F_8000.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area
in P-Flash memory as shown in Table 10-22. The FPLS bits can only be written to while the FPLDIS bit is set.
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Table 10-20. P-Flash Protection Function
Function(1)
FPOPEN
FPHDIS
FPLDIS
1
1
1
No P-Flash Protection
1
1
0
Protected Low Range
1
0
1
Protected High Range
1
0
0
Protected High and Low Ranges
0
1
1
Full P-Flash Memory Protected
0
1
0
Unprotected Low Range
0
0
1
Unprotected High Range
0
0
0
Unprotected High and Low Ranges
1. For range sizes, refer to Table 10-21 and Table 10-22.
Table 10-21. P-Flash Protection Higher Address Range
FPHS[1:0]
Global Address Range
Protected Size
00
0x7F_F800–0x7F_FFFF
2 Kbytes
01
0x7F_F000–0x7F_FFFF
4 Kbytes
10
0x7F_E000–0x7F_FFFF
8 Kbytes
11
0x7F_C000–0x7F_FFFF
16 Kbytes
Table 10-22. P-Flash Protection Lower Address Range
FPLS[1:0]
Global Address Range
Protected Size
00
0x7F_8000–0x7F_83FF
1 Kbyte
01
0x7F_8000–0x7F_87FF
2 Kbytes
10
0x7F_8000–0x7F_8FFF
4 Kbytes
11
0x7F_8000–0x7F_9FFF
8 Kbytes
All possible P-Flash protection scenarios are shown in Figure 10-14. Although the protection scheme is
loaded from the Flash memory at global address 0x7F_FF0C during the reset sequence, it can be changed
by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single
chip mode while providing as much protection as possible if reprogramming is not required.
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FPHDIS = 0
FPLDIS = 1
FPHDIS = 0
FPLDIS = 0
7
6
5
4
3
2
1
0
FPLS[1:0]
FPHDIS = 1
FPLDIS = 0
0x7F_8000
0x7F_FFFF
Scenario
FPHS[1:0]
Scenario
FLASH START
FPHDIS = 1
FPLDIS = 1
FPOPEN = 1
Chapter 10 128 KByte Flash Module (S12XFTM128K2XFV1)
FPHS[1:0]
0x7F_8000
FPOPEN = 0
FPLS[1:0]
FLASH START
0x7F_FFFF
Unprotected region
Protected region with size
defined by FPLS
Protected region
not defined by FPLS, FPHS
Protected region with size
defined by FPHS
Figure 10-14. P-Flash Protection Scenarios
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10.3.2.9.1
P-Flash Protection Restrictions
The general guideline is that P-Flash protection can only be added and not removed. Table 10-23 specifies
all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
Table 10-23. P-Flash Protection Scenario Transitions
To Protection Scenario(1)
From
Protection
Scenario
0
1
2
3
0
X
X
X
X
X
1
X
4
X
X
X
X
X
X
X
X
6
6
7
X
3
5
5
X
X
2
4
X
X
X
X
X
X
X
X
X
X
7
1. Allowed transitions marked with X, see Figure 10-14 for a definition of the scenarios.
10.3.2.10 EEE Protection Register (EPROT)
The EPROT register defines which buffer RAM EEE partition areas are protected against writes.
Offset Module Base + 0x0009
7
6
R
5
4
3
2
1
0
RNV[6:4]
EPOPEN
EPDIS
EPS[2:0]
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 10-15. EEE Protection Register (EPROT)
All bits in the EPROT register are readable and writable except for RNV[6:4] which are only readable. The
EPOPEN and EPDIS bits can only be written to the protected state. The EPS bits can be written anytime
until the EPDIS bit is cleared. If the EPOPEN bit is cleared, the state of the EPDIS and EPS bits is
irrelevant.
During the reset sequence, the EPROT register is loaded from the EEE protection byte in the Flash
configuration field at global address 0x7F_FF0D located in P-Flash memory (see Table 10-3) as indicated
by reset condition F in Figure 10-15. To change the EEE protection that will be loaded during the reset
sequence, the P-Flash sector containing the EEE protection byte must be unprotected, then the EEE
protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase
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Chapter 10 128 KByte Flash Module (S12XFTM128K2XFV1)
containing the EEE protection byte during the reset sequence, the EPOPEN bit will be cleared and
remaining bits in the EPROT register will be set to leave the buffer RAM EEE partition fully protected.
Trying to write data to any protected area in the buffer RAM EEE partition will result in a protection
violation error and the EPVIOLIF flag will be set in the FERSTAT register. Trying to write data to any
protected area in the buffer RAM partitioned for user access will not be prevented and the EPVIOLIF flag
in the FERSTAT register will not set.
Table 10-24. EPROT Field Descriptions
Field
Description
7
EPOPEN
Enables writes to the Buffer RAM partitioned for EEE
0 The entire buffer RAM EEE partition is protected from writes
1 Unprotected buffer RAM EEE partition areas are enabled for writes
6–4
RNV[6:4]
Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements
3
EPDIS
Buffer RAM Protection Address Range Disable — The EPDIS bit determines whether there is a protected
area in a specific region of the buffer RAM EEE partition.
0 Protection enabled
1 Protection disabled
2–0
EPS[2:0]
Buffer RAM Protection Size — The EPS[2:0] bits determine the size of the protected area in the buffer RAM
EEE partition as shown inTable 10-21. The EPS bits can only be written to while the EPDIS bit is set.
Table 10-25. Buffer RAM EEE Partition Protection Address Range
EPS[2:0]
Global Address Range
Protected Size
000
0x13_FFC0 – 0x13_FFFF
64 bytes
001
0x13_FF80 – 0x13_FFFF
128 bytes
010
0x13_FF40 – 0x13_FFFF
192 bytes
011
0x13_FF00 – 0x13_FFFF
256 bytes
100
0x13_FEC0 – 0x13_FFFF
320 bytes
101
0x13_FE80 – 0x13_FFFF
384 bytes
110
0x13_FE40 – 0x13_FFFF
448 bytes
111
0x13_FE00 – 0x13_FFFF
512 bytes
10.3.2.11 Flash Common Command Object Register (FCCOB)
The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register.
Byte wide reads and writes are allowed to the FCCOB register.
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Offset Module Base + 0x000A
7
6
5
4
3
2
1
0
0
0
0
0
R
CCOB[15:8]
W
Reset
0
0
0
0
Figure 10-16. Flash Common Command Object High Register (FCCOBHI)
Offset Module Base + 0x000B
7
6
5
4
3
2
1
0
0
0
0
0
R
CCOB[7:0]
W
Reset
0
0
0
0
Figure 10-17. Flash Common Command Object Low Register (FCCOBLO)
10.3.2.11.1 FCCOB - NVM Command Mode
NVM command mode uses the indexed FCCOB register to provide a command code and its relevant
parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates
the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user
clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register
all FCCOB parameter fields are locked and cannot be changed by the user until the command completes
(as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the
FCCOB register array.
The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 10-26.
The return values are available for reading after the CCIF flag in the FSTAT register has been returned to
1 by the Memory Controller. Writes to the unimplemented parameter fields (CCOBIX = 110 and CCOBIX
= 111) are ignored with reads from these fields returning 0x0000.
Table 10-26 shows the generic Flash command format. The high byte of the first word in the CCOB array
contains the command code, followed by the parameters for this specific Flash command. For details on
the FCCOB settings required by each command, see the Flash command descriptions in Section 10.4.2.
Table 10-26. FCCOB - NVM Command Mode (Typical Usage)
CCOBIX[2:0]
Byte
FCCOB Parameter Fields (NVM Command Mode)
HI
FCMD[7:0] defining Flash command
LO
0, Global address [22:16]
HI
Global address [15:8]
LO
Global address [7:0]
HI
Data 0 [15:8]
LO
Data 0 [7:0]
000
001
010
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Table 10-26. FCCOB - NVM Command Mode (Typical Usage)
CCOBIX[2:0]
Byte
FCCOB Parameter Fields (NVM Command Mode)
HI
Data 1 [15:8]
LO
Data 1 [7:0]
HI
Data 2 [15:8]
LO
Data 2 [7:0]
HI
Data 3 [15:8]
LO
Data 3 [7:0]
011
100
101
10.3.2.12 EEE Tag Counter Register (ETAG)
The ETAG register contains the number of outstanding words in the buffer RAM EEE partition that need
to be programmed into the D-Flash EEE partition. The ETAG register is decremented prior to the related
tagged word being programmed into the D-Flash EEE partition. All tagged words have been programmed
into the D-Flash EEE partition once all bits in the ETAG register read 0 and the MGBUSY flag in the
FSTAT register reads 0.
Offset Module Base + 0x000C
7
6
5
4
R
3
2
1
0
0
0
0
0
ETAG[15:8]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 10-18. EEE Tag Counter High Register (ETAGHI)
Offset Module Base + 0x000D
7
6
5
4
R
3
2
1
0
0
0
0
0
ETAG[7:0]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 10-19. EEE Tag Counter Low Register (ETAGLO)
All ETAG bits are readable but not writable and are cleared by the Memory Controller.
10.3.2.13 Flash ECC Error Results Register (FECCR)
The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.
The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits
in the FECCRIX register (see Section 10.3.2.4). Once ECC fault information has been stored, no other
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fault information will be recorded until the specific ECC fault flag has been cleared. In the event of
simultaneous ECC faults, the priority for fault recording is:
1. Double bit fault over single bit fault
2. CPU over XGATE
Offset Module Base + 0x000E
7
6
5
4
R
3
2
1
0
0
0
0
0
ECCR[15:8]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 10-20. Flash ECC Error Results High Register (FECCRHI)
Offset Module Base + 0x000F
7
6
5
4
R
3
2
1
0
0
0
0
0
ECCR[7:0]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 10-21. Flash ECC Error Results Low Register (FECCRLO)
All FECCR bits are readable but not writable.
Table 10-27. FECCR Index Settings
ECCRIX[2:0]
000
FECCR Register Content
Bits [15:8]
Bit[7]
Bits[6:0]
Parity bits read from
Flash block
CPU or XGATE
source identity
Global address
[22:16]
001
Global address [15:0]
010
Data 0 [15:0]
011
Data 1 [15:0] (P-Flash only)
100
Data 2 [15:0] (P-Flash only)
101
Data 3 [15:0] (P-Flash only)
110
Not used, returns 0x0000 when read
111
Not used, returns 0x0000 when read
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Table 10-28. FECCR Index=000 Bit Descriptions
Field
Description
15:8
PAR[7:0]
ECC Parity Bits — Contains the 8 parity bits from the 72 bit wide P-Flash data word or the 6 parity bits,
allocated to PAR[5:0], from the 22 bit wide D-Flash word with PAR[7:6]=00.
7
XBUS01
Bus Source Identifier — The XBUS01 bit determines whether the ECC error was caused by a read access
from the CPU or XGATE.
0 ECC Error happened on the CPU access
1 ECC Error happened on the XGATE access
6–0
Global Address — The GADDR[22:16] field contains the upper seven bits of the global address having
GADDR[22:16] caused the error.
The P-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The
following four words addressed by ECCRIX = 010 to 101 contain the 64-bit wide data phrase. The four
data words and the parity byte are the uncorrected data read from the P-Flash block.
The D-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The
uncorrected 16-bit data word is addressed by ECCRIX = 010.
10.3.2.14 Flash Option Register (FOPT)
The FOPT register is the Flash option register.
Offset Module Base + 0x0010
7
6
5
4
R
3
2
1
0
F
F
F
F
NV[7:0]
W
Reset
F
F
F
F
= Unimplemented or Reserved
Figure 10-22. Flash Option Register (FOPT)
All bits in the FOPT register are readable but are not writable.
During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash
configuration field at global address 0x7F_FF0E located in P-Flash memory (see Table 10-3) as indicated
by reset condition F in Figure 10-22. If a double bit fault is detected while reading the P-Flash phrase
containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set.
Table 10-29. FOPT Field Descriptions
Field
Description
7–0
NV[7:0]
Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper
use of the NV bits.
10.3.2.15 Flash Reserved0 Register (FRSV0)
This Flash register is reserved for factory testing.
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Offset Module Base + 0x0011
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 10-23. Flash Reserved0 Register (FRSV0)
All bits in the FRSV0 register read 0 and are not writable.
10.3.2.16 Flash Reserved1 Register (FRSV1)
This Flash register is reserved for factory testing.
Offset Module Base + 0x0012
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 10-24. Flash Reserved1 Register (FRSV1)
All bits in the FRSV1 register read 0 and are not writable.
10.3.2.17 Flash Reserved2 Register (FRSV2)
This Flash register is reserved for factory testing.
Offset Module Base + 0x0013
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 10-25. Flash Reserved2 Register (FRSV2)
All bits in the FRSV2 register read 0 and are not writable.
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10.4
Functional Description
10.4.1
Flash Command Operations
Flash command operations are used to modify Flash memory contents or configure module resources for
EEE operation.
The next sections describe:
• How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from
OSCCLK for Flash program and erase command operations
• The command write sequence used to set Flash command parameters and launch execution
• Valid Flash commands available for execution
10.4.1.1
Writing the FCLKDIV Register
Prior to issuing any Flash program or erase command after a reset, the user is required to write the
FCLKDIV register to divide OSCCLK down to a target FCLK of 1 MHz. Table 10-9 shows recommended
values for the FDIV field based on OSCCLK frequency.
NOTE
Programming or erasing the Flash memory cannot be performed if the bus
clock runs at less than 1 MHz. Setting FDIV too high can destroy the Flash
memory due to overstress. Setting FDIV too low can result in incomplete
programming or erasure of the Flash memory cells.
When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the
FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written,
any Flash program or erase command loaded during a command write sequence will not execute and the
ACCERR bit in the FSTAT register will set.
10.4.1.2
Command Write Sequence
The Memory Controller will launch all valid Flash commands entered using a command write sequence.
Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see
Section 10.3.2.7) and the CCIF flag should be tested to determine the status of the current command write
sequence. If CCIF is 0, the previous command write sequence is still active, a new command write
sequence cannot be started, and all writes to the FCCOB register are ignored.
CAUTION
Writes to any Flash register must be avoided while a Flash command is
active (CCIF=0) to prevent corruption of Flash register contents and
Memory Controller behavior.
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10.4.1.2.1
Define FCCOB Contents
The FCCOB parameter fields must be loaded with all required parameters for the Flash command being
executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX
register (see Section 10.3.2.3).
The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears
the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag
will remain clear until the Flash command has completed. Upon completion, the Memory Controller will
return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic
command write sequence is shown in Figure 10-26.
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START
Read: FCLKDIV register
Clock Register
Written
Check
no
FDIVLD
Set?
yes
Write: FCLKDIV register
Note: FCLKDIV must be set after
each reset
Read: FSTAT register
FCCOB
Availability Check
CCIF
Set?
no
Results from previous Command
yes
Access Error and
Protection Violation
Check
ACCERR/
FPVIOL
Set?
no
yes
Write: FSTAT register
Clear ACCERR/FPVIOL 0x30
Write to FCCOBIX register
to identify specific command
parameter to load.
Write to FCCOB register
to load required command parameter.
More
Parameters?
yes
no
Write: FSTAT register (to launch command)
Clear CCIF 0x80
Read: FSTAT register
Bit Polling for
Command Completion
Check
CCIF Set?
no
yes
EXIT
Figure 10-26. Generic Flash Command Write Sequence Flowchart
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10.4.1.3
Valid Flash Module Commands
Table 10-30. Flash Commands by Mode
Unsecured
FCMD
Command
NS
NX
(1)
(2)
Secured
SS(3) ST(4)
NS
NX
(5)
(6)
SS(7) ST(8)
0x01
Erase Verify All Blocks
∗
∗
∗
∗
∗
∗
∗
∗
0x02
Erase Verify Block
∗
∗
∗
∗
∗
∗
∗
∗
0x03
Erase Verify P-Flash Section
∗
∗
∗
∗
∗
0x04
Read Once
∗
∗
∗
∗
∗
0x05
Reserved
∗
∗
∗
∗
∗
0x06
Program P-Flash
∗
∗
∗
∗
∗
0x07
Program Once
∗
∗
∗
∗
∗
0x08
Erase All Blocks
∗
∗
∗
∗
0x09
Erase P-Flash Block
∗
∗
∗
∗
∗
0x0A
Erase P-Flash Sector
∗
∗
∗
∗
∗
0x0B
Unsecure Flash
∗
∗
∗
∗
0x0C
Verify Backdoor Access Key
∗
0x0D
Set User Margin Level
∗
0x0E
∗
∗
∗
∗
∗
Set Field Margin Level
∗
∗
0x0F
Full Partition D-Flash
∗
∗
0x10
Erase Verify D-Flash Section
∗
∗
∗
∗
∗
0x11
Program D-Flash
∗
∗
∗
∗
∗
0x12
Erase D-Flash Sector
∗
∗
∗
∗
∗
0x13
Enable EEPROM Emulation
∗
∗
∗
∗
∗
∗
∗
∗
0x14
Disable EEPROM Emulation
∗
∗
∗
∗
∗
∗
∗
∗
0x15
EEPROM Emulation Query
∗
∗
∗
∗
∗
∗
∗
∗
0x20
Partition D-Flash
1. Unsecured Normal Single Chip mode.
2. Unsecured Normal Expanded mode.
3. Unsecured Special Single Chip mode.
4. Unsecured Special Mode.
5. Secured Normal Single Chip mode.
6. Secured Normal Expanded mode.
7. Secured Special Single Chip mode.
8. Secured Special Mode.
∗
∗
∗
∗
∗
∗
∗
∗
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10.4.1.4
P-Flash Commands
Table 10-31 summarizes the valid P-Flash commands along with the effects of the commands on the PFlash block and other resources within the Flash module.
Table 10-31. P-Flash Commands
FCMD
Command
0x01
Erase Verify All
Blocks
0x02
Erase Verify Block
0x03
Erase Verify PFlash Section
0x04
Read Once
0x06
Program P-Flash
Function on P-Flash Memory
Verify that all P-Flash (and D-Flash) blocks are erased.
Verify that a P-Flash block is erased.
Verify that a given number of words starting at the address provided are erased.
Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block 0
that was previously programmed using the Program Once command.
Program a phrase in a P-Flash block.
Program Once
Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block
0 that is allowed to be programmed only once.
0x08
Erase All Blocks
Erase all P-Flash (and D-Flash) blocks.
An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN
bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are
set prior to launching the command.
0x09
Erase P-Flash
Block
Erase a single P-Flash block.
An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN
bits in the FPROT register are set prior to launching the command.
0x0A
Erase P-Flash
Sector
0x0B
Unsecure Flash
0x0C
Verify Backdoor
Access Key
Supports a method of releasing MCU security by verifying a set of security keys.
0x0D
Set User Margin
Level
Specifies a user margin read level for all P-Flash blocks.
0x0E
Set Field Margin
Level
Specifies a field margin read level for all P-Flash blocks (special modes only).
0x07
10.4.1.5
Erase all bytes in a P-Flash sector.
Supports a method of releasing MCU security by erasing all P-Flash (and D-Flash) blocks
and verifying that all P-Flash (and D-Flash) blocks are erased.
D-Flash and EEE Commands
Table 10-32 summarizes the valid D-Flash and EEE commands along with the effects of the commands
on the D-Flash block and EEE operation.
Table 10-32. D-Flash Commands
FCMD
Command
0x01
Erase Verify All
Blocks
0x02
Erase Verify Block
0x08
Erase All Blocks
Function on D-Flash Memory
Verify that all D-Flash (and P-Flash) blocks are erased.
Verify that the D-Flash block is erased.
Erase all D-Flash (and P-Flash) blocks.
An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN
bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are
set prior to launching the command.
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Table 10-32. D-Flash Commands
FCMD
Command
Function on D-Flash Memory
0x0B
Unsecure Flash
Supports a method of releasing MCU security by erasing all D-Flash (and P-Flash) blocks
and verifying that all D-Flash (and P-Flash) blocks are erased.
0x0D
Set User Margin
Level
Specifies a user margin read level for the D-Flash block.
0x0E
Set Field Margin
Level
Specifies a field margin read level for the D-Flash block (special modes only).
0x0F
Full Partition DFlash
Erase the D-Flash block and partition an area of the D-Flash block for user access.
0x10
Erase Verify DFlash Section
Verify that a given number of words starting at the address provided are erased.
0x11
Program D-Flash
Program up to four words in the D-Flash block.
0x12
Erase D-Flash
Sector
Erase all bytes in a sector of the D-Flash block.
0x13
Enable EEPROM
Emulation
Enable EEPROM emulation where writes to the buffer RAM EEE partition will be copied
to the D-Flash EEE partition.
0x14
Disable EEPROM
Emulation
Suspend all current erase and program activity related to EEPROM emulation but leave
current EEE tags set.
0x15
EEPROM
Emulation Query
Returns EEE partition and status variables.
0x20
Partition D-Flash
Partition an area of the D-Flash block for user access.
10.4.2
Flash Command Description
This section provides details of all available Flash commands launched by a command write sequence. The
ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following
illegal steps are performed, causing the command not to be processed by the Memory Controller:
• Starting any command write sequence that programs or erases Flash memory before initializing the
FCLKDIV register
• Writing an invalid command as part of the command write sequence
• For additional possible errors, refer to the error handling table provided for each command
If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation
will return invalid data. If the SFDIF or DFDIF flags were not previously set when the invalid read
operation occurred, both the SFDIF and DFDIF flags will be set and the FECCR registers will be loaded
with the global address used in the invalid read operation with the data and parity fields set to all 0.
If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting
any command write sequence (see Section 10.3.2.7).
CAUTION
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
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10.4.2.1
Erase Verify All Blocks Command
The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased.
Table 10-33. Erase Verify All Blocks Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x01
Not required
Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify
that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks
operation has completed.
Table 10-34. Erase Verify All Blocks Command Error Handling
Register
Error Bit
Error Condition
ACCERR
Set if CCOBIX[2:0] != 000 at command launch
FPVIOL
None
FSTAT
MGSTAT1
Set if any errors have been encountered during the read(1)
MGSTAT0
Set if any non-correctable errors have been encountered during the read1
FERSTAT
EPVIOLIF
None
1. As found in the memory map for FTM512K3.
10.4.2.2
Erase Verify Block Command
The Erase Verify Block command allows the user to verify that an entire P-Flash or D-Flash block has been
erased. The FCCOB upper global address bits determine which block must be verified.
Table 10-35. Erase Verify Block Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x02
Global address [22:16] of the
Flash block to be verified.
Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that
the selected P-Flash or D-Flash block is erased. The CCIF flag will set after the Erase Verify Block
operation has completed.
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Table 10-36. Erase Verify Block Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if an invalid global address [22:16] is supplied(1)
FPVIOL
FSTAT
None
MGSTAT1
Set if any errors have been encountered during the read(2)
MGSTAT0
Set if any non-correctable errors have been encountered during the read2
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
2. As found in the memory map for FTM512K3.
10.4.2.3
Erase Verify P-Flash Section Command
The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is
erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and
the number of phrases.
Table 10-37. Erase Verify P-Flash Section Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x03
Global address [22:16] of
a P-Flash block
001
Global address [15:0] of the first phrase to be verified
010
Number of phrases to be verified
Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will
verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash
Section operation has completed.
Table 10-38. Erase Verify P-Flash Section Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
Set if command not available in current mode (see Table 10-30)
ACCERR
Set if an invalid global address [22:0] is supplied(1)
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
FSTAT
Set if the requested section crosses a 256 Kbyte boundary
FPVIOL
FERSTAT
None
MGSTAT1
Set if any errors have been encountered during the read(2)
MGSTAT0
Set if any non-correctable errors have been encountered during the read2
EPVIOLIF
None
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1. As defined by the memory map for FTM512K3.
2. As found in the memory map for FTM512K3.
10.4.2.4
Read Once Command
The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the
nonvolatile information register of P-Flash block 0. The Read Once field is programmed using the
Program Once command described in Section 10.4.2.6. The Read Once command must not be executed
from the Flash block containing the Program Once reserved field to avoid code runaway.
Table 10-39. Read Once Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x04
Not Required
001
Read Once phrase index (0x0000 - 0x0007)
010
Read Once word 0 value
011
Read Once word 1 value
100
Read Once word 2 value
101
Read Once word 3 value
Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the
FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid
phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the
Read Once command, any attempt to read addresses within P-Flash block 0 will return invalid data.
128
Table 10-40. Read Once Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
ACCERR
Set if command not available in current mode (see Table 10-30)
Set if an invalid phrase index is supplied
FSTAT
FPVIOL
FERSTAT
10.4.2.5
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
EPVIOLIF
None
Program P-Flash Command
The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an
embedded algorithm.
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CAUTION
A P-Flash phrase must be in the erased state before being programmed.
Cumulative programming of bits within a Flash phrase is not allowed.
Table 10-41. Program P-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x06
Global address [22:16] to
identify P-Flash block
001
Global address [15:0] of phrase location to be programmed(1)
010
Word 0 program value
011
Word 1 program value
100
Word 2 program value
101
Word 3 program value
1. Global address [2:0] must be 000
Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the
data words to the supplied global address and will then proceed to verify the data words read back as
expected. The CCIF flag will set after the Program P-Flash operation has completed.
Table 10-42. Program P-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 101 at command launch
Set if command not available in current mode (see Table 10-30)
ACCERR
Set if an invalid global address [22:0] is supplied(1)
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
FSTAT
FPVIOL
Set if the global address [22:0] points to a protected area
MGSTAT1
Set if any errors have been encountered during the verify operation(2)
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation2
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
2. As found in the memory map for FTM512K3.
10.4.2.6
Program Once Command
The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the
nonvolatile information register located in P-Flash block 0. The Program Once reserved field can be read
using the Read Once command as described in Section 10.4.2.4. The Program Once command must only
be issued once since the nonvolatile information register in P-Flash block 0 cannot be erased. The Program
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Once command must not be executed from the Flash block containing the Program Once reserved field to
avoid code runaway.
Table 10-43. Program Once Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x07
Not Required
001
Program Once phrase index (0x0000 - 0x0007)
010
Program Once word 0 value
011
Program Once word 1 value
100
Program Once word 2 value
101
Program Once word 3 value
Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the
selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with
read back. The CCIF flag will remain clear, setting only after the Program Once operation has completed.
The reserved nonvolatile information register accessed by the Program Once command cannot be erased
and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index
values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program
Once command, any attempt to read addresses within P-Flash block 0 will return invalid data.
Table 10-44. Program Once Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 101 at command launch
Set if command not available in current mode (see Table 10-30)
ACCERR
Set if an invalid phrase index is supplied
Set if the requested phrase has already been programmed(1)
FSTAT
FPVIOL
None
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
FERSTAT
EPVIOLIF
None
1. If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will
be allowed to execute again on that same phrase.
10.4.2.7
Erase All Blocks Command
The Erase All Blocks operation will erase the entire P-Flash and D-Flash memory space including the EEE
nonvolatile information register.
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Table 10-45. Erase All Blocks Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x08
Not required
Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire
Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash
memory space was properly erased, security will be released. During the execution of this command
(CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All
Blocks operation has completed.
Table 10-46. Erase All Blocks Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if command not available in current mode (see Table 10-30)
FPVIOL
FSTAT
Set if any area of the P-Flash memory is protected
MGSTAT1
Set if any errors have been encountered during the verify operation(1)
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation1
FERSTAT
EPVIOLIF
Set if any area of the buffer RAM EEE partition is protected
1. As found in the memory map for FTM512K3.
10.4.2.8
Erase P-Flash Block Command
The Erase P-Flash Block operation will erase all addresses in a P-Flash block.
Table 10-47. Erase P-Flash Block Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x09
Global address [22:16] to
identify P-Flash block
Global address [15:0] in P-Flash block to be erased
Upon clearing CCIF to launch the Erase P-Flash Block command, the Memory Controller will erase the
selected P-Flash block and verify that it is erased. The CCIF flag will set after the Erase P-Flash Block
operation has completed.
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Table 10-48. Erase P-Flash Block Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
ACCERR
Set if command not available in current mode (see Table 10-30)
Set if an invalid global address [22:16] is supplied(1)
FSTAT
FPVIOL
Set if an area of the selected P-Flash block is protected
MGSTAT1
Set if any errors have been encountered during the verify operation(2)
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation2
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
2. As found in the memory map for FTM512K3.
10.4.2.9
Erase P-Flash Sector Command
The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector.
Table 10-49. Erase P-Flash Sector Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x0A
Global address [22:16] to identify
P-Flash block to be erased
Global address [15:0] anywhere within the sector to be erased.
Refer to Section 10.1.2.1 for the P-Flash sector size.
Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the
selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash
Sector operation has completed.
Table 10-50. Erase P-Flash Sector Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if command not available in current mode (see Table 10-30)
ACCERR
Set if an invalid global address [22:16] is supplied(1)
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
FSTAT
FPVIOL
Set if the selected P-Flash sector is protected
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
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10.4.2.10 Unsecure Flash Command
The Unsecure Flash command will erase the entire P-Flash and D-Flash memory space and, if the erase is
successful, will release security.
Table 10-51. Unsecure Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x0B
Not required
Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire
P-Flash and D-Flash memory space and verify that it is erased. If the Memory Controller verifies that the
entire Flash memory space was properly erased, security will be released. If the erase verify is not
successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security
state. During the execution of this command (CCIF=0) the user must not write to any Flash module
register. The CCIF flag is set after the Unsecure Flash operation has completed.
Table 10-52. Unsecure Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if command not available in current mode (see Table 10-30)
FPVIOL
FSTAT
Set if any area of the P-Flash memory is protected
MGSTAT1
Set if any errors have been encountered during the verify operation(1)
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation1
FERSTAT
EPVIOLIF
Set if any area of the buffer RAM EEE partition is protected
1. As found in the memory map for FTM512K3.
10.4.2.11 Verify Backdoor Access Key Command
The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the
FSEC register (see Table 10-11). The Verify Backdoor Access Key command releases security if usersupplied keys match those stored in the Flash security bytes of the Flash configuration field (see Table 103). The Verify Backdoor Access Key command must not be executed from the Flash block containing the
backdoor comparison key to avoid code runaway.
Table 10-53. Verify Backdoor Access Key Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x0C
Not required
001
Key 0
010
Key 1
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Table 10-53. Verify Backdoor Access Key Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
011
Key 2
100
Key 3
Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will
check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory
Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the
Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash
configuration field with Key 0 compared to 0x7F_FF00, etc. If the backdoor keys match, security will be
released. If the backdoor keys do not match, security is not released and all future attempts to execute the
Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is
set after the Verify Backdoor Access Key operation has completed.
Table 10-54. Verify Backdoor Access Key Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 100 at command launch
Set if an incorrect backdoor key is supplied
ACCERR
FSTAT
FERSTAT
Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see
Section 10.3.2.2)
Set if the backdoor key has mismatched since the last reset
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
10.4.2.12 Set User Margin Level Command
The Set User Margin Level command causes the Memory Controller to set the margin level for future read
operations of a specific P-Flash or D-Flash block.
Table 10-55. Set User Margin Level Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x0D
Global address [22:16] to identify the
Flash block
Margin level setting
Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the
user margin level for the targeted block and then set the CCIF flag.
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Valid margin level settings for the Set User Margin Level command are defined in Table 10-56.
Table 10-56. Valid Set User Margin Level Settings
CCOB
(CCOBIX=001)
Level Description
0x0000
Return to Normal Level
0x0001
User Margin-1 Level(1)
0x0002
User Margin-0 Level(2)
1. Read margin to the erased state
2. Read margin to the programmed state
Table 10-57. Set User Margin Level Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if command not available in current mode (see Table 10-30)
ACCERR
Set if an invalid global address [22:16] is supplied(1)
Set if an invalid margin level setting is supplied
FSTAT
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
NOTE
User margin levels can be used to check that Flash memory contents have
adequate margin for normal level read operations. If unexpected results are
encountered when checking Flash memory contents at user margin levels, a
potential loss of information has been detected.
10.4.2.13 Set Field Margin Level Command
The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set
the margin level specified for future read operations of a specific P-Flash or D-Flash block.
Table 10-58. Set Field Margin Level Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x0E
Global address [22:16] to identify the Flash
block
Margin level setting
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Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the
field margin level for the targeted block and then set the CCIF flag.
Valid margin level settings for the Set Field Margin Level command are defined in Table 10-59.
Table 10-59. Valid Set Field Margin Level Settings
CCOB
(CCOBIX=001)
Level Description
0x0000
Return to Normal Level
0x0001
User Margin-1 Level(1)
0x0002
User Margin-0 Level(2)
0x0003
Field Margin-1 Level1
0x0004
Field Margin-0 Level2
1. Read margin to the erased state
2. Read margin to the programmed state
Table 10-60. Set Field Margin Level Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if command not available in current mode (see Table 10-30)
ACCERR
Set if an invalid global address [22:16] is supplied(1)
Set if an invalid margin level setting is supplied
FSTAT
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
FERSTAT
EPVIOLIF
None
1. As defined by the memory map for FTM512K3.
CAUTION
Field margin levels must only be used during verify of the initial factory
programming.
NOTE
Field margin levels can be used to check that Flash memory contents have
adequate margin for data retention at the normal level setting. If unexpected
results are encountered when checking Flash memory contents at field
margin levels, the Flash memory contents should be erased and
reprogrammed.
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10.4.2.14 Full Partition D-Flash Command
The Full Partition D-Flash command allows the user to allocate sectors within the D-Flash block for
applications and a partition within the buffer RAM for EEPROM access. The D-Flash block consists of
128 sectors with 256 bytes per sector.
Table 10-61. Full Partition D-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x0F
Not required
001
Number of 256 byte sectors for the D-Flash user partition (DFPART)
010
Number of 256 byte sectors for buffer RAM EEE partition (ERPART)
Upon clearing CCIF to launch the Full Partition D-Flash command, the following actions are taken to
define a partition within the D-Flash block for direct access (DFPART) and a partition within the buffer
RAM for EEE use (ERPART):
• Validate the DFPART and ERPART values provided:
— DFPART <= 128 (maximum number of 256 byte sectors in D-Flash block)
— ERPART <= 8 (maximum number of 256 byte sectors in buffer RAM)
— If ERPART > 0, 128 - DFPART >= 12 (minimum number of 256 byte sectors in the D-Flash
block required to support EEE)
— If ERPART > 0, ((128-DFPART)/ERPART) >= 8 (minimum ratio of D-Flash EEE space to
buffer RAM EEE space to support EEE)
• Erase the D-Flash block and the EEE nonvolatile information register
• Program DFPART to the EEE nonvolatile information register at global address 0x12_0000 (see
Table 10-7)
• Program a duplicate DFPART to the EEE nonvolatile information register at global address
0x12_0002 (see Table 10-7)
• Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see
Table 10-7)
• Program a duplicate ERPART to the EEE nonvolatile information register at global address
0x12_0006 (see Table 10-7)
The D-Flash user partition will start at global address 0x10_0000. The buffer RAM EEE partition will end
at global address 0x13_FFFF. After the Full Partition D-Flash operation has completed, the CCIF flag will
set.
Running the Full Partition D-Flash command a second time will result in the previous partition values and
the entire D-Flash memory being erased. The data value written corresponds to the number of 256 byte
sectors allocated for either direct D-Flash access (DFPART) or buffer RAM EEE access (ERPART).
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Table 10-62. Full Partition D-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
ACCERR
Set if command not available in current mode (see Table 10-30)
Set if an invalid DFPART or ERPART selection is supplied(1)
FSTAT
FPVIOL
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
FERSTAT
EPVIOLIF
None
1. As defined by the maximum ERPART for FTM512K3.
10.4.2.15 Erase Verify D-Flash Section Command
The Erase Verify D-Flash Section command will verify that a section of code in the D-Flash user partition
is erased. The Erase Verify D-Flash Section command defines the starting point of the data to be verified
and the number of words.
Table 10-63. Erase Verify D-Flash Section Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x10
Global address [22:16] to
identify the D-Flash block
001
Global address [15:0] of the first word to be verified
010
Number of words to be verified
Upon clearing CCIF to launch the Erase Verify D-Flash Section command, the Memory Controller will
verify the selected section of D-Flash memory is erased. The CCIF flag will set after the Erase Verify DFlash Section operation has completed.
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Table 10-64. Erase Verify D-Flash Section Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
Set if command not available in current mode (see Table 10-30)
Set if an invalid global address [22:0] is supplied
ACCERR
Set if a misaligned word address is supplied (global address [0] != 0)
Set if the global address [22:0] points to an area of the D-Flash EEE partition
FSTAT
Set if the requested section breaches the end of the D-Flash block or goes into
the D-Flash EEE partition
FPVIOL
FERSTAT
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
EPVIOLIF
None
10.4.2.16 Program D-Flash Command
The Program D-Flash operation programs one to four previously erased words in the D-Flash user
partition. The Program D-Flash operation will confirm that the targeted location(s) were successfully
programmed upon completion.
CAUTION
A Flash word must be in the erased state before being programmed.
Cumulative programming of bits within a Flash word is not allowed.
Table 10-65. Program D-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x11
Global address [22:16] to
identify the D-Flash block
001
Global address [15:0] of word to be programmed
010
Word 0 program value
011
Word 1 program value, if desired
100
Word 2 program value, if desired
101
Word 3 program value, if desired
Upon clearing CCIF to launch the Program D-Flash command, the user-supplied words will be transferred
to the Memory Controller and be programmed. The CCOBIX index value at Program D-Flash command
launch determines how many words will be programmed in the D-Flash block. No protection checks are
made in the Program D-Flash operation on the D-Flash block, only access error checks. The CCIF flag is
set when the operation has completed.
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Table 10-66. Program D-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] < 010 at command launch
Set if CCOBIX[2:0] > 101 at command launch
Set if command not available in current mode (see Table 10-30)
ACCERR
Set if an invalid global address [22:0] is supplied
Set if a misaligned word address is supplied (global address [0] != 0)
Set if the global address [22:0] points to an area in the D-Flash EEE partition
FSTAT
Set if the requested group of words breaches the end of the D-Flash block or goes
into the D-Flash EEE partition
FPVIOL
FERSTAT
None
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
EPVIOLIF
None
10.4.2.17 Erase D-Flash Sector Command
The Erase D-Flash Sector operation will erase all addresses in a sector of the D-Flash user partition.
Table 10-67. Erase D-Flash Sector Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x12
Global address [22:16] to identify
D-Flash block
Global address [15:0] anywhere within the sector to be erased.
See Section 10.1.2.2 for D-Flash sector size.
Upon clearing CCIF to launch the Erase D-Flash Sector command, the Memory Controller will erase the
selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase D-Flash Sector
operation has completed.
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Table 10-68. Erase D-Flash Sector Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if command not available in current mode (see Table 10-30)
ACCERR
Set if an invalid global address [22:0] is supplied
Set if a misaligned word address is supplied (global address [0] != 0)
FSTAT
Set if the global address [22:0] points to the D-Flash EEE partition
FPVIOL
FERSTAT
None
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
EPVIOLIF
None
10.4.2.18 Enable EEPROM Emulation Command
The Enable EEPROM Emulation command causes the Memory Controller to enable EEE activity. EEE
activity is disabled after any reset.
Table 10-69. Enable EEPROM Emulation Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x13
Not required
Upon clearing CCIF to launch the Enable EEPROM Emulation command, the CCIF flag will set after the
Memory Controller enables EEE operations using the contents of the EEE tag RAM and tag counter. The
Full Partition D-Flash or the Partition D-Flash command must be run prior to launching the Enable
EEPROM Emulation command.
Table 10-70. Enable EEPROM Emulation Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if Full Partition D-Flash or Partition D-Flash command not previously run
FSTAT
FERSTAT
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
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10.4.2.19 Disable EEPROM Emulation Command
The Disable EEPROM Emulation command causes the Memory Controller to suspend current EEE
activity.
Table 10-71. Disable EEPROM Emulation Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x14
Not required
Upon clearing CCIF to launch the Disable EEPROM Emulation command, the Memory Controller will
halt EEE operations at the next convenient point without clearing the EEE tag RAM or tag counter before
setting the CCIF flag.
Table 10-72. Disable EEPROM Emulation Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if Full Partition D-Flash or Partition D-Flash command not previously run
FSTAT
FERSTAT
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
10.4.2.20 EEPROM Emulation Query Command
The EEPROM Emulation Query command returns EEE partition and status variables.
Table 10-73. EEPROM Emulation Query Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x15
Not required
001
Return DFPART
010
Return ERPART
011
Return ECOUNT(1)
100
Return Dead Sector Count
1. Indicates sector erase count
Return Ready Sector Count
Upon clearing CCIF to launch the EEPROM Emulation Query command, the CCIF flag will set after the
EEE partition and status variables are stored in the FCCOBIX register.If the Emulation Query command
is executed prior to partitioning (Partition D-Flash Command Section 10.4.2.14), the following reset
values are returned: DFPART = 0x_FFFF, ERPART = 0x_FFFF, ECOUNT = 0x_FFFF, Dead Sector
Count = 0x_00, Ready Sector Count = 0x_00.
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Table 10-74. EEPROM Emulation Query Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if command not available in current mode (see Table 10-30)
FSTAT
FERSTAT
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
EPVIOLIF
None
10.4.2.21 Partition D-Flash Command
The Partition D-Flash command allows the user to allocate sectors within the D-Flash block for
applications and a partition within the buffer RAM for EEPROM access. The D-Flash block consists of 64
sectors with 256 bytes per sector. The Erase All Blocks command must be run prior to launching the
Partition D-Flash command.
Table 10-75. Partition D-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x20
Not required
001
Number of 256 byte sectors for the D-Flash user partition (DFPART)
010
Number of 256 byte sectors for buffer RAM EEE partition (ERPART)
Upon clearing CCIF to launch the Partition D-Flash command, the following actions are taken to define a
partition within the D-Flash block for direct access (DFPART) and a partition within the buffer RAM for
EEE use (ERPART):
• Validate the DFPART and ERPART values provided:
— DFPART <= 128 (maximum number of 256 byte sectors in D-Flash block)
— ERPART <= 8 (maximum number of 256 byte sectors in buffer RAM)
— If ERPART > 0, 128 - DFPART >= 12 (minimum number of 256 byte sectors in the D-Flash
block required to support EEE)
— If ERPART > 0, ((128-DFPART)/ERPART) >= 8 (minimum ratio of D-Flash EEE space to
buffer RAM EEE space to support EEE)
• Erase verify the D-Flash block and the EEE nonvolatile information register
• Program DFPART to the EEE nonvolatile information register at global address 0x12_0000 (see
Table 10-7)
• Program a duplicate DFPART to the EEE nonvolatile information register at global address
0x12_0002 (see Table 10-7)
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•
•
Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see
Table 10-7)
Program a duplicate ERPART to the EEE nonvolatile information register at global address
0x12_0006 (see Table 10-7)
The D-Flash user partition will start at global address 0x10_0000. The buffer RAM EEE partition will end
at global address 0x13_FFFF. After the Partition D-Flash operation has completed, the CCIF flag will set.
Running the Partition D-Flash command a second time will result in the ACCERR bit within the FSTAT
register being set. The data value written corresponds to the number of 256 byte sectors allocated for either
direct D-Flash access (DFPART) or buffer RAM EEE access (ERPART).
Table 10-76. Partition D-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
Set if command not available in current mode (see Table 10-30)
ACCERR
Set if partitions have already been defined
Set if an invalid DFPART or ERPART selection is supplied(1)
FSTAT
FPVIOL
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
FERSTAT
EPVIOLIF
None
1. As defined by the maximum ERPART for FTM512K3.
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10.4.3
Interrupts
The Flash module can generate an interrupt when a Flash command operation has completed or when a
Flash command operation has detected an EEE error or an ECC fault.
Table 10-77. Flash Interrupt Sources
Interrupt Source
Global (CCR)
Mask
Interrupt Flag
Local Enable
CCIF
(FSTAT register)
CCIE
(FCNFG register)
I Bit
Flash EEE Erase Error
ERSERIF
(FERSTAT register)
ERSERIE
(FERCNFG register)
I Bit
Flash EEE Program Error
PGMERIF
(FERSTAT register)
PGMERIE
(FERCNFG register)
I Bit
Flash EEE Protection Violation
EPVIOLIF
(FERSTAT register)
EPVIOLIE
(FERCNFG register)
I Bit
Flash EEE Error Type 1 Violation
ERSVIF1
(FERSTAT register)
ERSVIE1
(FERCNFG register)
I Bit
Flash EEE Error Type 0 Violation
ERSVIF0
(FERSTAT register)
ERSVIE0
(FERCNFG register)
I Bit
ECC Double Bit Fault on Flash Read
DFDIF
(FERSTAT register)
DFDIE
(FERCNFG register)
I Bit
ECC Single Bit Fault on Flash Read
SFDIF
(FERSTAT register)
SFDIE
(FERCNFG register)
I Bit
Flash Command Complete
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
10.4.3.1
Description of Flash Interrupt Operation
The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the
Flash command interrupt request. The Flash module uses the ERSEIF, PGMEIF, EPVIOLIF, ERSVIF1,
ERSVIF0, DFDIF and SFDIF flags in combination with the ERSEIE, PGMEIE, EPVIOLIE, ERSVIE1,
ERSVIE0, DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a
detailed description of the register bits involved, refer to Section 10.3.2.5, “Flash Configuration Register
(FCNFG)”, Section 10.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 10.3.2.7, “Flash
Status Register (FSTAT)”, and Section 10.3.2.8, “Flash Error Status Register (FERSTAT)”.
The logic used for generating the Flash module interrupts is shown in Figure 10-27.
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Flash Command Interrupt Request
CCIE
CCIF
ERSERIE
ERSERIF
PGMERIE
PGMERIF
EPVIOLIE
EPVIOLIF
Flash Error Interrupt Request
ERSVIE1
ERSVIF1
ERSVIE0
ERSVIF0
DFDIE
DFDIF
SFDIE
SFDIF
Figure 10-27. Flash Module Interrupts Implementation
10.4.4
Wait Mode
The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU
from wait via the CCIF interrupt (see Section 10.4.3, “Interrupts”).
10.4.5
Stop Mode
If a Flash command is active (CCIF = 0) or an EE-Emulation operation is pending when the MCU requests
stop mode, the current Flash operation will be completed before the CPU is allowed to enter stop mode.
10.5
Security
The Flash module provides security information to the MCU. The Flash security state is defined by the
SEC bits of the FSEC register (see Table 10-12). During reset, the Flash module initializes the FSEC
register using data read from the security byte of the Flash configuration field at global address
0x7F_FF0F.
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The security state out of reset can be permanently changed by programming the security byte of the Flash
configuration field. This assumes that you are starting from a mode where the necessary P-Flash erase and
program commands are available and that the upper region of the P-Flash is unprotected. If the Flash
security byte is successfully programmed, its new value will take affect after the next MCU reset.
The following subsections describe these security-related subjects:
• Unsecuring the MCU using Backdoor Key Access
• Unsecuring the MCU in Special Single Chip Mode using BDM
• Mode and Security Effects on Flash Command Availability
10.5.1
Unsecuring the MCU using Backdoor Key Access
The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the
contents of the backdoor keys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If
the KEYEN[1:0] bits are in the enabled state (see Section 10.3.2.2), the Verify Backdoor Access Key
command (see Section 10.4.2.11) allows the user to present four prospective keys for comparison to the
keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor
Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC
register (see Table 10-12) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are
not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash block
0 will not be available for read access and will return invalid data.
The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an
external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
If the KEYEN[1:0] bits are in the enabled state (see Section 10.3.2.2), the MCU can be unsecured by the
backdoor key access sequence described below:
1. Follow the command sequence for the Verify Backdoor Access Key command as explained in
Section 10.4.2.11
2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the
SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10
The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will
prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method
to re-enable the Verify Backdoor Access Key command.
After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is
unsecured, the sector containing the Flash security byte can be erased and the Flash security byte can be
reprogrammed to the unsecure state, if desired.
In the unsecure state, the user has full control of the contents of the backdoor keys by programming
addresses 0x7F_FF00–0x7F_FF07 in the Flash configuration field.
The security as defined in the Flash security byte (0x7F_FF0F) is not changed by using the Verify
Backdoor Access Key command sequence. The backdoor keys stored in addresses
0x7F_FF00–0x7F_FF07 are unaffected by the Verify Backdoor Access Key command sequence. After the
next reset of the MCU, the security state of the Flash module is determined by the Flash security byte
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(0x7F_FF0F). The Verify Backdoor Access Key command sequence has no effect on the program and
erase protections defined in the Flash protection register, FPROT.
10.5.2
Unsecuring the MCU in Special Single Chip Mode using BDM
The MCU can be unsecured in special single chip mode by erasing the P-Flash and D-Flash memory by
one of the following methods:
• Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM,
send BDM commands to disable protection in the P-Flash and D-Flash memory, and execute the
Erase All Blocks command write sequence to erase the P-Flash and D-Flash memory.
• Reset the MCU into special expanded wide mode, disable protection in the P-Flash and D-Flash
memory and run code from external memory to execute the Erase All Blocks command write
sequence to erase the P-Flash and D-Flash memory.
After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into
special single chip mode. The BDM will execute the Erase Verify All Blocks command write sequence to
verify that the P-Flash and D-Flash memory is erased. If the P-Flash and D-Flash memory are verified as
erased the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may
be programmed to the unsecure state by the following method:
• Send BDM commands to execute a ‘Program P-Flash’ command sequence to program the Flash
security byte to the unsecured state and reset the MCU.
10.5.3
Mode and Security Effects on Flash Command Availability
The availability of Flash module commands depends on the MCU operating mode and security state as
shown in Table 10-30.
10.6
Initialization
On each system reset the Flash module executes a reset sequence which establishes initial values for the
Flash Block Configuration Parameters, the FPROT and DFPROT protection registers, and the FOPT and
FSEC registers. The Flash module reverts to built-in default values that leave the module in a fully
protected and secured state if errors are encountered during execution of the reset sequence. If a double bit
fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set. The
ACCERR bit in the FSTAT register is set if errors are encountered while initializing the EEE buffer ram
during the reset sequence.
CCIF remains clear throughout the reset sequence. The Flash module holds off all CPU access for the
initial portion of the reset sequence. While Flash reads are possible when the hold is removed, writes to
the FCCOBIX, FCCOBHI, and FCCOBLO registers are ignored to prevent command activity while the
Memory Controller remains busy. Completion of the reset sequence is marked by setting CCIF high which
enables writes to the FCCOBIX, FCCOBHI, and FCCOBLO registers to launch any available Flash
command.
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
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Memory Mapping Control (S12XMMCV4) SUPPORTING
FLEXRAY
Revision History
Rev. No.
(Item No.)
Date (Submitted
By)
v04.06
15-Nov-06
- Adding AUTOSAR Compliance concerning illegal CPU accesses
v04.07
02-Apr-07
- Adapting the MMC context to support S12XS family
v04.08
04-May-07
- Clarifying RPAGE usage for less than 12KB RAMSIZE.
- Some Cleanups
11.1
Sections
Affected
Substantial Change(s)
Introduction
This section describes the functionality of the module mapping control (MMC) sub-block of the S12X
platform. The block diagram of the MMC is shown in Figure 11-1.
The MMC module controls the multi-master priority accesses, the selection of internal resources and
external space. Internal buses, including internal memories and peripherals, are controlled in this module.
The local address space for each master is translated to a global memory space.
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11.1.1
Terminology
Table 11-1. Acronyms and Abbreviations
Logic level “1”
Logic level “0”
Voltage that corresponds to Boolean true state
Voltage that corresponds to Boolean false state
0x
Represents hexadecimal number
x
Represents logic level ’don’t care’
Byte
8-bit data
word
16-bit data
local address
based on the 64KB Memory Space (16-bit address)
global address
based on the 8MB Memory Space (23-bit address)
Aligned address
Mis-aligned address
Bus Clock
Address on even boundary
Address on odd boundary
System Clock. Refer to CRG Block Guide.
expanded modes
Normal Expanded Mode
Emulation Single-Chip Mode
Emulation Expanded Mode
Special Test Mode
single-chip modes
Normal Single-Chip Mode
Special Single-Chip Mode
emulation modes
Emulation Single-Chip Mode
Emulation Expanded Mode
normal modes
Normal Single-Chip Mode
Normal Expanded Mode
special modes
Special Single-Chip Mode
Special Test Mode
NS
Normal Single-Chip Mode
SS
Special Single-Chip Mode
NX
Normal Expanded Mode
ES
Emulation Single-Chip Mode
EX
Emulation Expanded Mode
ST
Special Test Mode
Unimplemented areas
External Space
external resource
Resources (Emulator, Application) connected to the MCU via the external bus on
expanded modes (Unimplemented areas and External Space)
PRR
Port Replacement Registers
PRU
Port Replacement Unit located on the emulator side
MCU
MicroController Unit
NVM
Non-volatile Memory; Flash, EEPROM or ROM
IFR
FLEXRAY
11.1.2
Areas which are accessible by the pages (RPAGE,PPAGE,EPAGE) and not implemented
Area which is accessible in the global address range 14_0000 to 3F_FFFF
Information Row sector located on the top of NVM. For Test purposes.
FlexRay IP Integration module
Features
The main features of this block are:
• Paging capability to support a global 8MB memory address space
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•
•
•
•
•
•
•
•
•
Bus arbitration between the masters CPU, BDM, FLEXRAY and XGATE
Simultaneous accesses to different resources1 (internal, external, and peripherals) (see Figure 111)
Resolution of target bus access collision
MCU operation mode control
MCU security control
Separate memory map schemes for each master CPU, BDM, FLEXRAY and XGATE
ROM control bits to enable the on-chip FLASH or ROM selection
Port replacement registers access control
Generation of system reset when CPU accesses an unimplemented address (i.e., an address which
does not belong to any of the on-chip modules) in single-chip modes
11.1.3
S12X Memory Mapping
The S12X architecture implements a number of memory mapping schemes including
• a CPU 8MB global map, defined using a global page (GPAGE) register and dedicated 23-bit
address load/store instructions.
• a BDM 8MB global map, defined using a global page (BDMGPR) register and dedicated 23-bit
address load/store instructions.
• a FLEXRAY 8 MByte global map.
• a (CPU or BDM) 64KB local map, defined using specific resource page (RPAGE, EPAGE and
PPAGE) registers and the default instruction set. The 64KB visible at any instant can be considered
as the local map accessed by the 16-bit (CPU or BDM) address.
• The XGATE 64 Kbyte local map.
The MMC module performs translation of the different memory mapping schemes to the specific global
(physical) memory implementation.
11.1.4
Modes of Operation
This subsection lists and briefly describes all operating modes supported by the MMC.
11.1.4.1
•
•
•
Power Saving Modes
Run mode
MMC is functional during normal run mode.
Wait mode
MMC is functional during wait mode.
Stop mode
MMC is inactive during stop mode.
1. Resources are also called targets.
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11.1.4.2
•
•
•
Single chip modes
In normal and special single chip mode the internal memory is used. External bus is not active.
Expanded modes
Address, data, and control signals are activated in normal expanded and special test modes when
accessing the external bus. Access to internal resources will not cause activity on the external bus.
Emulation modes
External bus is active to emulate, via an external tool, the normal expanded or the normal single
chip mode.
11.1.5
1
Functional Modes
Block Diagram
shows a block diagram of the MMC.
BDM
CPU
XGATE
FLEXRAY
EEEPROM
MMC
FLASH
Address Decoder & Priority
DBG
Target Bus Controller
EBI
RAM
Peripherals
Figure 11-1. MMC Block Diagram
11.2
External Signal Description
The user is advised to refer to the SoC Guide for port configuration and location of external bus signals.
Some pins may not be bonded out in all implementations.
Table 11-2 and Table 11-3 outline the pin names and functions. It also provides a brief description of their
operation.
1. Doted blocks and lines are optional. Please refer to the SoC Guide for their availlibilities.
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Table 11-2. External Input Signals Associated with the MMC
Signal
I/O
Description
Availability
MODC
I
Mode input
Latched after
RESET (active low)
MODB
I
Mode input
Latched after
RESET (active low)
MODA
I
Mode input
Latched after
RESET (active low)
EROMCTL
I
EROM control input
Latched after
RESET (active low)
ROMCTL
I
ROM control input
Latched after
RESET (active low)
Table 11-3. External Output Signals Associated with the MMC
Available in Modes
Signal
I/O
Description
NS
CS0
O
Chip select line 0
CS1
O
Chip select line 1
CS2
O
Chip select line 2
CS3
O
Chip select line 3
SS
NX
ES
EX
ST
(see Table 11-4)
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11.3
11.3.1
Memory Map and Registers
Module Memory Map
A summary of the registers associated with the MMC block is shown in Figure 11-2. Detailed descriptions
of the registers and bits are given in the subsections that follow.
Address
Register
Name
0x000A
MMCCTL0
R
W
0x000B
MODE
R
W
0x0010
GPAGE
R
Bit 7
6
5
4
3
2
1
Bit 0
CS3E1
CS3E0
CS2E1
CS2E0
CS1E1
CS1E0
CS0E1
CS0E0
MODC
MODB
MODA
0
0
0
0
0
GP6
GP5
GP4
GP3
GP2
GP1
GP0
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
0
0
0
0
0
0
0
0
ROMHM
ROMON
0
W
0x0011
DIRECT
R
W
0x0012
Reserved
R
W
0x0013
MMCCTL1
R
W
0x0014
Reserved
R
TGMRAMON
0
EEEIFRON PGMIFRON RAMHM
EROMON
0
0
0
0
0
0
0
0
PIX7
PIX6
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
RP7
RP6
RP5
RP4
RP3
RP2
RP1
RP0
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
W
0x0015
PPAGE
R
W
0x0016
RPAGE
R
W
0x0017
EPAGE
R
W
= Unimplemented or Reserved
Figure 11-2. MMC Register Summary
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11.3.2
11.3.2.1
Register Descriptions
MMC Control Register (MMCCTL0)
Address: 0x000A PRR
R
W
Reset
7
6
5
4
3
2
1
0
CS3E1
CS3E0
CS2E1
CS2E0
CS1E1
CS1E0
CS0E1
CS0E0
0
0
0
0
0
0
0
ROMON1
1. ROMON is bit[0] of the register MMCTL1 (see Figure 11-10)
= Unimplemented or Reserved
Figure 11-3. MMC Control Register (MMCCTL0)
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data is read from this register.
Write: Anytime. In emulation modes write operations will also be directed to the external bus.
Table 11-4. Chip Selects Function Activity
Chip Modes
Register Bit
NS
Disabled(1)
SS
NX
(2)
CS0E[1:0], CS1E[1:0],
Disabled
Enabled
CS2E[1:0], CS3E[1:0]
1. Disabled: feature always inactive.
2. Enabled: activity is controlled by the appropriate register bit value.
ES
EX
ST
Disabled
Enabled
Disabled
The MMCCTL0 register is used to control external bus functions, like:
• Availability of chip selects. (See Table 11-4 and Table 11-5)
• Control of different external stretch mechanism. For more detail refer to the S12X_EBI
BlockGuide.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
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Table 11-5. MMCCTL0 Field Descriptions
Field
Description
7–6
CS3E[1:0]
Chip Select 3 Enables — These bits enable the external chip select CS3 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in Table 11-6 and
Figure 11-17.
Chip select 3 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
Chip select 3 is disabled
01,10,11 Chip select 3 is enabled
5–4
CS2E[1:0]
Chip Select 2 Enables — These bits enable the external chip select CS2 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in Table 11-6 and
Figure 11-17.
Chip select 2 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
Chip select 2 is disabled
01,10,11 Chip select 2 is enabled
3–2
CS1E[1:0]
Chip Select 1 Enables — These bits enable the external chip select CS1 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in Table 11-6 and
Figure 11-17.
Chip select 1 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
Chip select 1 is disabled
01,10,11 Chip select 1 is enabled
1–0
CS0E[1:0]
Chip Select 0 Enables — These bits enable the external chip select CS0 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in Table 11-6 and
Figure 11-17.
Chip select 0 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
Chip select 0 is disabled
01,10,11 Chip select 0 is enabled
Table 11-6 shows the address boundaries of each chip select and the relationship with the implemented
resources (internal) parameters.
Table 11-6. Global Chip Selects Memory Space
Chip Selects
Bottom Address
Top Address
CS3
0x00_0800
0x0F_FFFF minus RAMSIZE(1)
CS2(2)
0x14_0000
0x1F_FFFF
CS1
0x20_0000
0x3F_FFFF
CS0(3)
0x40_0000
0x7F_FFFF minus FLASHSIZE(4)
1. External RPAGE accesses in (NX, EX)
2. When ROMHM is set (see ROMHM in Table 11-15) the CS2 is asserted in the space occupied by this onchip memory block.
3. When the internal NVM is enabled (see ROMON in Section 11.3.2.5, “MMC Control Register (MMCCTL1))
the CS0 is not asserted in the space occupied by this on-chip memory block.
4. External PPAGE accesses in (NX, EX)
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11.3.2.2
Mode Register (MODE)
Address: 0x000B PRR
R
W
Reset
7
6
5
MODC
MODB
MODA
MODC1
MODB1
MODA1
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
1. External signal (see Table 11-2).
= Unimplemented or Reserved
Figure 11-4. Mode Register (MODE)
Read: Anytime. In emulation modes read operations will return the data read from the external bus. In all
other modes the data are read from this register.
Write: Only if a transition is allowed (see Figure 11-5). In emulation modes write operations will be also
directed to the external bus.
The MODE bits of the MODE register are used to establish the MCU operating mode.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Table 11-7. MODE Field Descriptions
Field
Description
7–5
MODC,
MODB,
MODA
Mode Select Bits — These bits control the current operating mode during RESET high (inactive). The external
mode pins MODC, MODB, and MODA determine the operating mode during RESET low (active). The state of
the pins is latched into the respective register bits after the RESET signal goes inactive (see Figure 11-4).
Write restrictions exist to disallow transitions between certain modes. Figure 11-5 illustrates all allowed mode
changes. Attempting non authorized transitions will not change the MODE bits, but it will block further writes to
these register bits except in special modes.
Both transitions from normal single-chip mode to normal expanded mode and from emulation single-chip to
emulation expanded mode are only executed by writing a value of 3’b101 (write once). Writing any other value
will not change the MODE bits, but will block further writes to these register bits.
Changes of operating modes are not allowed when the device is secured, but it will block further writes to these
register bits except in special modes.
In emulation modes reading this address returns data from the external bus which has to be driven by the
emulator. It is therefore responsibility of the emulator hardware to provide the expected value (i.e. a value
corresponding to normal single chip mode while the device is in emulation single-chip mode or a value
corresponding to normal expanded mode while the device is in emulation expanded mode).
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RESET
010
Special
Test
(ST)
010
1
1
10
0
10
Normal
Expanded
(NX)
101
Emulation
Single-Chip
(ES)
001
Emulation
Expanded
(EX)
011
101
10
1
011
RESET
0
10
RESET
RESET
000
001
101
101
010
110
111
Normal
Single-Chip
(NS)
100
1
00
01
RESET
100
1
01
1
00
Special
Single-Chip
(SS)
000
000
RESET
Transition done by external pins (MODC, MODB, MODA)
RESET
Transition done by write access to the MODE register
110
111
Illegal (MODC, MODB, MODA) pin values.
Do not use. (Reserved for future use).
Figure 11-5. Mode Transition Diagram when MCU is Unsecured
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11.3.2.3
Global Page Index Register (GPAGE)
Address: 0x0010
7
R
0
W
Reset
0
6
5
4
3
2
1
0
GP6
GP5
GP4
GP3
GP2
GP1
GP0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-6. Global Page Index Register (GPAGE)
Read: Anytime
Write: Anytime
The global page index register is used to construct a 23 bit address in the global map format. It is only used
when the CPU is executing a global instruction (GLDAA, GLDAB, GLDD, GLDS, GLDX,
GLDY,GSTAA, GSTAB, GSTD, GSTS, GSTX, GSTY) (see CPU Block Guide). The generated global
address is the result of concatenation of the CPU local address [15:0] with the GPAGE register [22:16] (see
Figure 11-7).
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Global Address [22:0]
Bit22
Bit16 Bit15
GPAGE Register [6:0]
Bit 0
CPU Address [15:0]
Figure 11-7. GPAGE Address Mapping
Table 11-8. GPAGE Field Descriptions
Field
Description
6–0
GP[6:0]
Global Page Index Bits 6–0 — These page index bits are used to select which of the 128 64KB pages is to be
accessed.
Example 11-1. This example demonstrates usage of the GPAGE register
LDX
MOVB
GLDAA
#0x5000
#0x14, GPAGE
X
;Set GPAGE offset to the value of 0x5000
;Initialize GPAGE register with the value of 0x14
;Load Accu A from the global address 0x14_5000
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11.3.2.4
Direct Page Register (DIRECT)
Address: 0x0011
R
W
7
6
5
4
3
2
1
0
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
0
0
0
0
0
0
0
0
Reset
Figure 11-8. Direct Register (DIRECT)
Read: Anytime
Write: anytime in special modes, one time only in other modes.
This register determines the position of the 256B direct page within the memory map.It is valid for both
global and local mapping scheme.
Table 11-9. DIRECT Field Descriptions
Field
Description
7–0
DP[15:8]
Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct
addressing mode. The bits from this register form bits [15:8] of the address (see Figure 11-9).
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Global Address [22:0]
Bit16 Bit15
Bit22
Bit8
Bit7
Bit0
DP [15:8]
CPU Address [15:0]
Figure 11-9. DIRECT Address Mapping
Bits [22:16] of the global address will be formed by the GPAGE[6:0] bits in case the CPU executes a global
instruction in direct addressing mode or by the appropriate local address to the global address expansion
(refer to Section 11.4.2.1.1, “Expansion of the Local Address Map).
Example 11-2. This example demonstrates usage of the Direct Addressing Mode
MOVB
#0x80,DIRECT
;Set DIRECT register to 0x80. Write once only.
;Global data accesses to the range 0xXX_80XX can be direct.
;Logical data accesses to the range 0x80XX are direct.
LDY
<00
;Load the Y index register from 0x8000 (direct access).
;< operator forces direct access on some assemblers but in
;many cases assemblers are “direct page aware” and can
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;automatically select direct mode.
11.3.2.5
MMC Control Register (MMCCTL1)
Address: 0x0013 PRR
7
R
W
6
0
MGRAMON
Reset
0
0
5
4
3
EEEIFRON
PGMIFRON
RAMHM
0
0
0
2
EROMON
EROMCTL
1
0
ROMHM
ROMON
0
ROMCTL
= Unimplemented or Reserved
Figure 11-10. MMC Control Register (MMCCTL1)
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data are read from this register.
Write: Refer to each bit description. In emulation modes write operations will also be directed to the
external bus.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Table 11-10. MMCCTL1 Field Descriptions
Field
Description
7
Flash Memory Controller Tag RAM and SCRATCH RAM visible in the global memory map
MGRAMON Write: Anytime
This bit is used to made the Flash Memory Controller Tag RAM and SCRATCH RAM visible in the global memory
map.
0 Not visible in the global memory map.
1 Visible in the global memory map.
5
EEEIFRON
EEE Information Row (IFR) visible in the global memory map
Write: Anytime
This bit is used to made the IFR sector of EEE DATA FLASH visible in the global memory map.
0 Not visible in the global memory map.
1 Visible in the global memory map.
4
Program Information Row (IFR) visible in the global memory map
PGMIFRON Write: Anytime
This bit is used to made the IFR sector of the Program Flash visible in the global memory map.
0 Not visible in the global memory map.
1 Visible in the global memory map.
3
RAMHM
RAM only in higher Half of the global memory map
Write: Once in normal and emulation modes and anytime in special modes
0 Accesses to 0x4000–0x7FFF in the CPU/BDM local memory map will be mapped to 0x14_4000-0x14_7FFF
in the global memory space (external access).
1 Accesses to 0x4000–0x7FFF in the CPU/BDM local memory map will be mapped to 0x0F_C000-0x0F_FFFF
in the global memory space (RAM area).
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Table 11-10. MMCCTL1 Field Descriptions (continued)
Field
Description
2
EROMON
Enables emulated Flash or ROM memory in the global memory map
Write: Never
This bit is used in some modes to define the placement of the Emulated Flash or ROM (Refer to Table 11-11)
0 Disables the emulated Flash or ROM in the global memory map.
1 Enables the emulated Flash or ROM in the global memory map.
1
ROMHM
FLASH or ROM only in higher Half of the global memory map
Write: Once in normal and emulation modes and anytime in special modes
0 The fixed page of Flash or ROM can be accessed in the lower half of the memory map. Accesses to
0x4000–0x7FFF in the CPU/BDM local memory map will be mapped to 0x7F_4000-0x7F_7FFF in the global
memory space.
1 Disables access to the Flash or ROM in the lower half of the memory map.These physical locations of the
Flash or ROM can still be accessed through the program page window. Accesses to 0x4000–0x7FFF in the
CPU/BDM local memory map will depends on the value of the RAMHM bit (Refer to Table 11-18).
0
ROMON
Enable FLASH or ROM in the global memory map
Write: Once in normal and emulation modes and anytime in special modes.
This bit is used in some modes to define the placement of the ROM (Refer to Table 11-11)
0 Disables the Flash or ROM from the memory map.
1 Enables the Flash or ROM in the global memory map.
EROMON and ROMON control the visibility of the Flash in the global memory map for CPU or BDM
(not for XGATE). Both local and global memory maps are affected.
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Table 11-11. Data Sources when CPU or BDM is Accessing Flash Area
Chip Modes
ROMON
EROMON
DATA SOURCE(1)
Stretch(2)
Normal Single Chip
X
X
Internal Flash
N
X
0
Emulation Memory
N
X
1
Internal Flash
0
X
External Application
Y
1
X
Internal Flash
N
0
X
External Application
Y
1
0
Emulation Memory
N
1
1
Internal Flash
0
X
External Application
Special Single Chip
Emulation Single Chip
Normal Expanded
Emulation Expanded
Special Test
N
1
X
Internal Flash
1. Internal Flash means Flash resources inside the MCU are read/written.
Emulation memory means resources inside the emulator are read/written (PRU registers, flash
replacement, RAM, EEPROM and register space are always considered internal).
External application means resources residing outside the MCU are read/written.
2. The external access stretch mechanism is part of the EBI module (refer to EBI Block Guide for details).
11.3.2.6
Program Page Index Register (PPAGE)
Address: 0x0015
R
W
Reset
7
6
5
4
3
2
1
0
PIX7
PIX6
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
1
1
1
1
1
1
1
0
Figure 11-11. Program Page Index Register (PPAGE)
Read: Anytime
Write: Anytime
These eight index bits are used to page 16KB blocks into the Flash page window located in the local (CPU
or BDM) memory map from address 0x8000 to address 0xBFFF (see Figure 11-12). This supports
accessing up to 4MB of Flash (in the Global map) within the 64KB Local map. The PPAGE register is
effectively used to construct paged Flash addresses in the Local map format. The CPU has special access
to read and write this register directly during execution of CALL and RTC instructions..
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
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Global Address [22:0]
1
Bit21
Bit0
Bit14 Bit13
PPAGE Register [7:0]
Address [13:0]
Address: CPU Local Address
or BDM Local Address
Figure 11-12. PPAGE Address Mapping
NOTE
Writes to this register using the special access of the CALL and RTC
instructions will be complete before the end of the instruction execution.
Table 11-12. PPAGE Field Descriptions
Field
7–0
PIX[7:0]
Description
Program Page Index Bits 7–0 — These page index bits are used to select which of the 256 FLASH or ROM
array pages is to be accessed in the Program Page Window.
The fixed 16K page from 0x4000–0x7FFF (when ROMHM = 0) is the page number 0xFD.
The reset value of 0xFE ensures that there is linear Flash space available between addresses 0x4000 and
0xFFFF out of reset.
The fixed 16K page from 0xC000-0xFFFF is the page number 0xFF.
11.3.2.7
RAM Page Index Register (RPAGE)
Address: 0x0016
R
W
Reset
7
6
5
4
3
2
1
0
RP7
RP6
RP5
RP4
RP3
RP2
RP1
RP0
1
1
1
1
1
1
0
1
Figure 11-13. RAM Page Index Register (RPAGE)
Read: Anytime
Write: Anytime
These eight index bits are used to page 4KB blocks into the RAM page window located in the local (CPU
or BDM) memory map from address 0x1000 to address 0x1FFF (see Figure 11-14). This supports
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accessing up to 1022KB of RAM (in the Global map) within the 64KB Local map. The RAM page index
register is effectively used to construct paged RAM addresses in the Local map format.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Global Address [22:0]
0
0
0
Bit19 Bit18
Bit12 Bit11
Bit0
Address [11:0]
RPAGE Register [7:0]
Address: CPU Local Address
or BDM Local Address
Figure 11-14. RPAGE Address Mapping
NOTE
Because RAM page 0 has the same global address as the register space, it is
possible to write to registers through the RAM space when RPAGE = 0x00.
Table 11-13. RPAGE Field Descriptions
Field
Description
7–0
RP[7:0]
RAM Page Index Bits 7–0 — These page index bits are used to select which of the 256 RAM array pages is to
be accessed in the RAM Page Window.
The reset value of 0xFD ensures that there is a linear RAM space available between addresses 0x1000 and
0x3FFF out of reset.
The fixed 4K page from 0x2000–0x2FFF of RAM is equivalent to page 254 (page number 0xFE).
The fixed 4K page from 0x3000–0x3FFF of RAM is equivalent to page 255 (page number 0xFF).
NOTE
The page 0xFD (reset value) contains unimplemented area in the range not
occupied by RAM if RAMSIZE is less than 12KB (Refer to
Section 11.4.2.3, “Implemented Memory Map).
The two fixed 4KB pages (0xFE, 0xFF) contain unimplemented area in the
range not occupied by RAM if RAMSIZE is less than 8KB (Refer to
Section 11.4.2.3, “Implemented Memory Map).
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11.3.2.8
EEPROM Page Index Register (EPAGE)
Address: 0x0017
R
W
7
6
5
4
3
2
1
0
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
1
1
1
1
1
1
1
0
Reset
Figure 11-15. EEPROM Page Index Register (EPAGE)
Read: Anytime
Write: Anytime
These eight index bits are used to page 1KB blocks into the EEPROM page window located in the local
(CPU or BDM) memory map from address 0x0800 to address 0x0BFF (see Figure 11-16). This supports
accessing up to 256KB of EEPROM (in the Global map) within the 64KB Local map. The EEPROM page
index register is effectively used to construct paged EEPROM addresses in the Local map format.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Global Address [22:0]
0
0
1
0
0
Bit17 Bit16
Bit10 Bit9
Bit0
Address [9:0]
EPAGE Register [7:0]
Address: CPU Local Address
or BDM Local Address
Figure 11-16. EPAGE Address Mapping
Table 11-14. EPAGE Field Descriptions
Field
7–0
EP[7:0]
Description
EEPROM Page Index Bits 7–0 — These page index bits are used to select which of the 256 EEPROM array
pages is to be accessed in the EEPROM Page Window.
The reset value of 0xFE ensures that there is a linear EEPROM space available between addresses 0x0800
and 0x0FFF out of reset.
The fixed 1K page 0x0C00–0x0FFF of EEPROM is equivalent to page 255 (page number 0xFF).
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11.4
Functional Description
The MMC block performs several basic functions of the S12X sub-system operation: MCU operation
modes, priority control, address mapping, select signal generation and access limitations for the system.
Each aspect is described in the following subsections.
11.4.1
•
•
•
MCU Operating Mode
Normal single-chip mode
There is no external bus in this mode. The MCU program is executed from the internal memory
and no external accesses are allowed.
Special single-chip mode
This mode is generally used for debugging single-chip operation, boot-strapping or security related
operations. The active background debug mode is in control of the CPU code execution and the
BDM firmware is waiting for serial commands sent through the BKGD pin. There is no external
bus in this mode.
Emulation single-chip mode
Tool vendors use this mode for emulation systems in which the user’s target application is normal
single-chip mode. Code is executed from external or internal memory depending on the set-up of
the EROMON bit (see Section 11.3.2.5, “MMC Control Register (MMCCTL1)). The external bus
is active in both cases to allow observation of internal operations (internal visibility).
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•
•
•
Normal expanded mode
The external bus interface is configured as an up to 23-bit address bus, 8 or 16-bit data bus with
dedicated bus control and status signals. This mode allows 8 or 16-bit external memory and
peripheral devices to be interfaced to the system. The fastest external bus rate is half of the internal
bus rate. An external signal can be used in this mode to cause the external bus to wait as desired by
the external logic.
Emulation expanded mode
Tool vendors use this mode for emulation systems in which the user’s target application is normal
expanded mode.
Special test mode
This mode is an expanded mode for factory test.
11.4.2
11.4.2.1
Memory Map Scheme
CPU and BDM Memory Map Scheme
The BDM firmware lookup tables and BDM register memory locations share addresses with other
modules; however they are not visible in the global memory map during user’s code execution. The BDM
memory resources are enabled only during the READ_BD and WRITE_BD access cycles to distinguish
between accesses to the BDM memory area and accesses to the other modules. (Refer to BDM Block
Guide for further details).
When the MCU enters active BDM mode, the BDM firmware lookup tables and the BDM registers
become visible in the local memory map in the range 0xFF00-0xFFFF (global address 0x7F_FF00 0x7F_FFFF) and the CPU begins execution of firmware commands or the BDM begins execution of
hardware commands. The resources which share memory space with the BDM module will not be visible
in the global memory map during active BDM mode.
Please note that after the MCU enters active BDM mode the BDM firmware lookup tables and the BDM
registers will also be visible between addresses 0xBF00 and 0xBFFF if the PPAGE register contains value
of 0xFF.
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CPU and BDM
Local Memory Map
Global Memory Map
0x00_0000
2K REGISTERS
0x00_0800
2K RAM
RAM
253*4K paged
0x0800
0x0C00
0x1000
0x0F_E000
2K REGISTERS
8K RAM
1K EEPROM window
EPAGE
0x10_0000
1K EEPROM
EEPROM
255*1K paged
RPAGE
4K RAM window
0x2000
8K RAM
0x4000
0x13_FC00
256 Kilobytes
0x0000
1M minus 2 Kilobytes
0x00_1000
1K EEPROM
Unpaged
16K FLASH
External
Space
0x8000
16K FLASH window
2.75 Mbytes
0x14_0000
PPAGE
0x40_0000
0xC000
0xFFFF
Reset Vectors
0x7F_4000
0x7F_8000
0x7F_C000
16K FLASH
(PPAGE 0xFD)
4 Mbytes
FLASH
253 *16K paged
Unpaged
16K FLASH
16K FLASH
(PPAGE 0xFE)
16K FLASH
(PPAGE 0xFF)
0x7F_FFFF
Figure 11-17. Expansion of the Local Address Map
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11.4.2.1.1
Expansion of the Local Address Map
Expansion of the CPU Local Address Map
The program page index register in MMC allows accessing up to 4MB of FLASH or ROM in the global
memory map by using the eight page index bits to page 256 16KB blocks into the program page window
located from address 0x8000 to address 0xBFFF in the local CPU memory map.
The page value for the program page window is stored in the PPAGE register. The value of the PPAGE
register can be read or written by normal memory accesses as well as by the CALL and RTC instructions
(see Section 11.5.1, “CALL and RTC Instructions).
Control registers, vector space and parts of the on-chip memories are located in unpaged portions of the
64KB local CPU address space.
The starting address of an interrupt service routine must be located in unpaged memory unless the user is
certain that the PPAGE register will be set to the appropriate value when the service routine is called.
However an interrupt service routine can call other routines that are in paged memory. The upper 16KB
block of the local CPU memory space (0xC000–0xFFFF) is unpaged. It is recommended that all reset and
interrupt vectors point to locations in this area or to the other unpaged sections of the local CPU memory
map.
Table 11-15 summarizes mapping of the address bus in Flash/External space based on the address, the
PPAGE register value and value of the ROMHM bit in the MMCCTL1 register.
Table 11-15. Global FLASH/ROM Allocated
Local
CPU Address
ROMHM
External
Access
Global Address
0x4000–0x7FFF
0
No
0x7F_4000 –0x7F_7FFF
1
Yes
0x14_4000–0x14_7FFF
N/A
No(1)
0x40_0000–0x7F_FFFF
N/A
Yes1
0x8000–0xBFFF
0xC000–0xFFFF
N/A
No
0x7F_C000–0x7F_FFFF
1. The internal or the external bus is accessed based on the size of the memory resources
implemented on-chip. Please refer to Figure 1-23 for further details.
The RAM page index register allows accessing up to 1MB minus 2KB of RAM in the global memory map
by using the eight RPAGE index bits to page 4KB blocks into the RAM page window located in the local
CPU memory space from address 0x1000 to address 0x1FFF. The EEPROM page index register EPAGE
allows accessing up to 256KB of EEPROM in the system by using the eight EPAGE index bits to page
1KB blocks into the EEPROM page window located in the local CPU memory space from address 0x0800
to address 0x0BFF.
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Expansion of the BDM Local Address Map
PPAGE, RPAGE, and EPAGE registers are also used for the expansion of the BDM local address to the
global address. These registers can be read and written by the BDM.
The BDM expansion scheme is the same as the CPU expansion scheme.
11.4.2.2
Global Addresses Based on the Global Page
CPU Global Addresses Based on the Global Page
The seven global page index bits allow access to the full 8MB address map that can be accessed with 23
address bits. This provides an alternative way to access all of the various pages of FLASH, RAM and EEE
as well as additional external memory.
The GPAGE Register is used only when the CPU is executing a global instruction (see Section 11.3.2.3,
“Global Page Index Register (GPAGE)). The generated global address is the result of concatenation of the
CPU local address [15:0] with the GPAGE register [22:16] (see Figure 11-7).
BDM Global Addresses Based on the Global Page
The seven BDMGPR Global Page index bits allow access to the full 8MB address map that can be accessed
with 23 address bits. This provides an alternative way to access all of the various pages of FLASH, RAM
and EEE as well as additional external memory.
The BDM global page index register (BDMGPR) is used only in the case the CPU is executing a firmware
command which uses a global instruction (like GLDD, GSTD) or by a BDM hardware command (like
WRITE_W, WRITE_BYTE, READ_W, READ_BYTE). See the BDM Block Guide for further details.
The generated global address is a result of concatenation of the BDM local address with the BDMGPR
register [22:16] in the case of a hardware command or concatenation of the CPU local address and the
BDMGPR register [22:16] in the case of a firmware command (see Figure 11-18).
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BDM HARDWARE COMMAND
Global Address [22:0]
Bit22
Bit16 Bit15
BDMGPR Register [6:0]
Bit0
BDM Local Address
BDM FIRMWARE COMMAND
Global Address [22:0]
Bit22
Bit16 Bit15
BDMGPR Register [6:0]
Bit0
CPU Local Address
Figure 11-18. BDMGPR Address Mapping
11.4.2.3
Implemented Memory Map
The global memory spaces reserved for the internal resources (RAM, EEE, and FLASH) are not
determined by the MMC module. Size of the individual internal resources are however fixed in the design
of the device cannot be changed by the user. Please refer to the SoC Guide for further details. Figure and
Table 11-16 show the memory spaces occupied by the on-chip resources. Please note that the memory
spaces have fixed top addresses.
Table 11-16. Global Implemented Memory Space
Internal Resource
$Address
RAM
RAM_LOW = 0x10_0000 minus RAMSIZE(1)
FLASH
FLASH_LOW = 0x80_0000 minus FLASHSIZE(2)
1. RAMSIZE is the hexadecimal value of RAM SIZE in Bytes
2. FLASHSIZE is the hexadecimal value of FLASH SIZE in Bytes
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When the device is operating in expanded modes except emulation single-chip mode, accesses to global
addresses which are not occupied by the on-chip resources (unimplemented areas or external memory
space) result in accesses to the external bus (see Figure ).
In emulation single-chip mode, accesses to global addresses which are not occupied by the on-chip
resources (unimplemented areas) result in accesses to the external bus. CPU accesses to global addresses
which are occupied by external memory space result in an illegal access reset (system reset) in case of no
MPU error. BDM accesses to the external space are performed but the data will be undefined.
In single-chip modes accesses by the CPU (except for firmware commands) to any of the unimplemented
areas (see Figure ) will result in an illegal access reset (system reset) in case of no MPU error. BDM
accesses to the unimplemented areas are allowed but the data will be undefined.No misaligned word access
from the BDM module will occur; these accesses are blocked in the BDM module (Refer to BDM Block
Guide).
Misaligned word access to the last location of RAM is performed but the data will be undefined.
Misaligned word access to the last location of any global page (64KB) by any global instruction, is
performed by accessing the last byte of the page and the first byte of the same page, considering the above
mentioned misaligned access cases.
The non-internal resources (unimplemented areas or external space) are used to generate the chip selects
(CS0,CS1,CS2 and CS3) (see Figure ), which are only active in normal expanded, emulation expanded
(see Section 11.3.2.1, “MMC Control Register (MMCCTL0)).
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CPU and BDM
Local Memory Map
Global Memory Map
0x00_0000
0x00_07FF
2K REGISTERS
CS3
Unimplemented
RAM
0x0000
0x0800
0x0C00
0x1000
RAMSIZE
RAM_LOW
RAM
2K REGISTERS
1K EEPROM window
EPAGE
0x0F_FFFF
1K EEPROM
4K RAM window
RPAGE
0x2000
256 K EEEPROM
8K RAM
0x4000
0x13_FFFF
CS2
Unpaged
16K FLASH
0x1F_FFFF
External
Space
CS1
0x8000
PPAGE
0x3F_FFFF
0xC000
CS0
16K FLASH window
Unimplemented
FLASH
Unpaged
16K FLASH
Reset Vectors
FLASH_LOW
FLASH
FLASHSIZE
0xFFFF
0x7F_FFFF
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S12X CPU & BDM Global Address MappingThe
non-internal resources (unimplemented areas or external
space) are used to generate the chip selects (CS0,CS1,CS2 and CS3) (see Figure ), which are only active
in normal expanded, emulation expanded (see Section 11.3.2.1, “MMC Control Register (MMCCTL0)).
11.4.2.4
11.4.2.4.1
XGATE Memory Map Scheme
Expansion of the XGATE Local Address Map
The XGATE 64 Kbyte memory space allows access to internal resources only (Registers, RAM, and
FLASH). The 2 Kilobyte register address range is the same register address range as for the CPU and the
BDM module (see Table 11-17).
XGATE can access the FLASH in single chip modes, even when the MCU is secured. In expanded modes,
XGATE can not access the FLASH when MCU is secured.
The local address of the XGATE RAM access is translated to the global RAM address range. The XGATE
shares the RAM resource with the CPU and the BDM module (see Table 11-17).
XGATE RAM size (XGRAMSIZE) may be lower or equal to the MCU RAM size (RAMSIZE).
In case of XGATE RAM size less than 32 Kbytes (see Figure 11-19), the gap in the xgate local memory
map will result in an illegal RAM access (see Section 11.4.3.1, “Illegal XGATE Accesses)
The local address of the XGATE FLASH access is always translated to the global address 0x78_0800 0x78_7FFF.
Example 11-3. is a general example of the XGATE memory map implementation.
Table 11-17. XGATE Implemented Memory Space
Internal Resource
$Address
XGATE RAM
XGRAM_LOW = 0x0F_0000 plus (0x1_0000 minus XGRAMSIZE)(1)
1. XGRAMSIZE is the hexadecimal value of XGATE RAM SIZE in bytes.
Example 11-3.
The MCU FLASHSIZE is 64 Kbytes (0x10000) and MCU RAMSIZE is 32 Kbytes (0x8000).
The XGATE RAMSIZE is 16 Kbytes (0x4000).
The space occupied by the XGATE RAM in the global address space will be:
Bottom address: (0x10_0000 minus 0x4000) = 0x0F_C000
Top address: 0x0F_FFFF
XGATE accesses to local address range 0x0800–0x7FFF will result always in accesses to the
following FLASH block in the global address space:
Bottom address: 0x78_0800
Top address: 0x78_7FFF
The gap range in the local memory map 0x8000–0xBFFF will be translated in the global address
space:
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0x0F_8000 - 0x0F_BFFF (illegal xgate access to system RAM).
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XGATE
Local Memory Map
Global Memory Map
0x00_0000
Registers
0x00_07FF
XGRAM_LOW
0x0800
RAM
0x0F_FFFF
RAMSIZE
Registers
XGRAMSIZE
0x0000
FLASH
0x7FFF
XGRAMSIZE
Unimplemented
area
RAM
0x78_0800
0xFFFF
FLASHSIZE
FLASH
0x78_7FFF
0x7F_FFFF
Figure 11-19. XGATE Global Address Mapping
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11.4.2.5
11.4.2.5.1
FLEXRAY Memory Map Scheme
Expansion of the FLEXRAY Local Address Map
The FLEXRAY memory space allows access to internal resources only (RAM).
The local address of the FLEXRAY RAM access is connected to the global RAM address range. The
FLEXRAY could share the RAM resource with the CPU, XGATE and the BDM module (Refer to the
MPU Block Guide).
FLEXRAY RAM size (FLXRAMSIZE) may be lower or equal to the MCU RAM size (RAMSIZE).
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FLEXRAY
Local Memory Map
Global Memory Map
RAMSIZE
RAM
FLXRAMSIZE
0x00_0000
FLXRAMSIZE
0x0F_FFFF
RAM
Unimplemented
area
0x7F_FFFF
Figure 11-20. FLEXRAY Global Address Mapping
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11.4.2.6
Memory Configuration
Two bits in the MMCCTL1 register (ROMHM, RAMHM) configure the mapping of the local address
(0x4000-0x7FFF) in the global memory map.
ROMHM, RAMHM are write once in normal and emulation modes and anytime in special modes.
Three areas are identified (See Figure 11-21):
• Program FLASH (0x7F_4000-0x7F_7FFF) when ROMHM = 0.
• External Space (0x14_4000-0x14_7FFF) when ROMHM = 1 and RAMHM = 0.
• XSRAM Space (0x0F_C000-0x0F_FFFF) when ROMHM = 1 and RAMHM = 1.
Table 11-18 shows the translation from the local memory map to the global memory map taking in
consideration the different configurations of ROMHM and RAMHM.
Table 11-18. ROMHM and RAMHM Address Location
Local Address
0x4000 - 0x7FFF
0x2000 - 0x3FFF
0x2000 - 0x3FFF
ROMHM
RAMHM
Global Address
Location
0
X
0x7F_4000 - 0x7F_7FFF
Internal Flash
1
0
0x14_4000 - 0x14_7FFF
External Space
0x0F_C000 - 0x0F_FFFF
Bottom of the Implemented RAM
1
1
0x0F_A000 - 0x0F_BFFF
Fixed up to 8K RAM
1
0
0x0F_E000 - 0x0F_FFFF
Fixed up to 8K RAM
Table 11-19 describes the application note of the RAM configuration and its dedicated global address.
Table 11-19. RAM Configuration
phase
RPAGE
ROMHM
RAMHM
RAM AREA
Global Address
After reset
RPAGE = 0xFD
(Reset value)
0
0
12 Kilobytes
0x0F_D000 - 0x0F_FFFF
During setup
RPAGE = 0xFD
(Reset value)
1
1
24 Kilobytes
0x0F_A000 - 0x0F_FFFF
(0x00 <= RPAGE <= 0xF9)
1
1
28 Kilobytes
0x00_0000 - 0x0F_9FFF
(0xFA <= RPAGE <= 0xFF)
1
1
24 Kilobytes
0x0F_A000 - 0x0F_FFFF
Normal Operation
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CPU and BDM
Local Memory Map
Global Memory Map
0x00_0000
0x00_0800
2K REGISTERS
2K RAM
RAM
251*4K paged
0x0F_A000
8K RAM
0x0800
0x0C00
0x1000
2K REGISTERS
1K EEPROM window
16K RAM
0x10_0000
1K EEPROM
EEPROM
255*1K paged
4K RAM window
0x2000
8K RAM
0x4000
0x13_FC00
256 Kilobytes
0x0000
ROMHM RAMHM
0x0F_C000
1
1
1M minus 2 Kilobytes
0x00_1000
1K EEPROM
1
16K External
0
0x8000
External
Space
2.75 Mbytes
0x14_0000
ROMHM RAMHM 0x14_4000
16K FLASH window
0x40_0000
0xC000
0xFFFF
Reset Vectors
ROMHM RAMHM
0x7F_4000
0
16K FLASH
x
0x7F_8000
0x7F_C000
4 Mbytes
FLASH
253 *16K paged
Unpaged
16K FLASH
16K FLASH
(PPAGE 0xFE)
16K FLASH
(PPAGE 0xFF)
0x7F_FFFF
Figure 11-21. ROMHM, RAMHM Memory Configuration
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11.4.2.6.1
System XSRAM
System XSRAM has two ways to be accessed by the CPU. One is by the programming of RPAGE and the
fixed XSRAM areas configured by the values of ROMHM, RAMHM, or by the usage of the global
instruction and the usage of GPAGE.
Figure 11-22 shows the memory map for the implemented XSRAM. The size of the implemented XSRAM
is done by the device definition and denoted by RAMSIZE.
RAM Area in the global memory map
ROMHM = 1 RAMHM = 0
0x00_0000
0x00_07FF
ROMHM = 0 RAMHM = X
ROMHM = 1 RAMHM = 1
REG. Area
0x00_0800
0x00_0800
Unimplemented
RAM
RAM Area
Unimplemented
RAM
0x0F_FFFF
0x0F_A000
EEPROM Area
RAMSIZE
8K RAM
0x13_FFFF
0x0F_C000
16K RAM
0x0F_E000
External
Space Area
8K RAM
0x0F_FFFF
0x0F_FFFF
0x3F_FFFF
FLASH Area
0x7F_FFFF
Figure 11-22. S12XE System RAM in the global memory map
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11.4.3
Chip Access Restrictions
CPU, FLEXRAY and XGATE accesses are watched in the memory protection unit (See MPU Block
Guide). In case of access violation, the suspect master is acknowledged with an indication of an error; the
victim target will not be accessed.
Other violations MPU is not handling are listed below.
11.4.3.1
Illegal XGATE Accesses
A possible access error is flagged by the MMC and signalled to XGATE under the following conditions:
• XGATE performs misaligned word (in case of load-store or opcode or vector fetch accesses).
• XGATE accesses the register space (in case of opcode or vector fetch).
• XGATE performs a write to Flash in any modes (in case of load-store access).
• XGATE performs an access to a secured Flash in expanded modes (in case of load-store or opcode
or vector fetch accesses).
For further details refer to the XGATE Block Guide.
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11.4.4
Chip Bus Control
The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM,
FLEXRAY and XGATE) with the rest of the system (master buses). In addition the MMC handles all CPU
read data bus swapping operations. All internal and external resources are connected to specific target
buses (see Figure 11-231).
BDM
CPU
DBG
XGATE
XGATE
FLEXRAY
S12X1
S12X0
S12X2
MMC “Crossbar Switch”
EBI
XBUS0
XBUS1
BLKX
XBUS3
FTM
FLASH
EEE/DFLASH
XRAM
BDM
resources
XSRAM
XBUS2
IPBI
Figure 11-23. MMC Block Diagram
1. Doted blocks and lines are optional. Please refer to the SoC Guide for their availlibilities.
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11.4.4.1
Master Bus Prioritization regarding access conflicts on Target Buses
The arbitration scheme allows only one master to be connected to a target at any given time. The following
rules apply when prioritizing accesses from different masters to the same target bus:
• High priority1 FLEXRAY access to XSRAM has priority over CPU, XGATE and BDM.
• CPU always has priority over BDM, FLEXRAY and XGATE.
• XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU
for its duration.
• XGATE has priority over FLEXRAY and BDM.
• BDM has priority over CPU, FLEXRAY and XGATE when its access is stalled for more than 128
cycles. In the later case the suspect master will be stalled after finishing the current operation and
the BDM will gain access to the bus.
• In emulation modes all internal accesses are visible on the external bus as well and the external bus
is used during access to the PRU registers.
11.5
11.5.1
Initialization/Application Information
CALL and RTC Instructions
CALL and RTC instructions are uninterruptible CPU instructions that automate page switching in the
program page window. The CALL instruction is similar to the JSR instruction, but the subroutine that is
called can be located anywhere in the local address space or in any Flash or ROM page visible through the
program page window. The CALL instruction calculates and stacks a return address, stacks the current
PPAGE value and writes a new instruction-supplied value to the PPAGE register. The PPAGE value
controls which of the 256 possible pages is visible through the 16KB program page window in the 64KB
local CPU memory map. Execution then begins at the address of the called subroutine.
During the execution of the CALL instruction, the CPU performs the following steps:
1. Writes the current PPAGE value into an internal temporary register and writes the new instructionsupplied PPAGE value into the PPAGE register
2. Calculates the address of the next instruction after the CALL instruction (the return address) and
pushes this 16-bit value onto the stack
3. Pushes the temporarily stored PPAGE value onto the stack
4. Calculates the effective address of the subroutine, refills the queue and begins execution at the new
address
This sequence is uninterruptible. There is no need to inhibit interrupts during the CALL instruction
execution. A CALL instruction can be performed from any address to any other address in the local CPU
memory space.
The PPAGE value supplied by the instruction is part of the effective address of the CPU. For all addressing
mode variations (except indexed-indirect modes) the new page value is provided by an immediate operand
in the instruction. In indexed-indirect variations of the CALL instruction a pointer specifies memory
locations where the new page value and the address of the called subroutine are stored. Using indirect
1. FLEXRAY has two priority access types, one called high priority access and the other called normal access.
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addressing for both the new page value and the address within the page allows usage of values calculated
at run time rather than immediate values that must be known at the time of assembly.
The RTC instruction terminates subroutines invoked by a CALL instruction. The RTC instruction unstacks
the PPAGE value and the return address and refills the queue. Execution resumes with the next instruction
after the CALL instruction.
During the execution of an RTC instruction the CPU performs the following steps:
1. Pulls the previously stored PPAGE value from the stack
2. Pulls the 16-bit return address from the stack and loads it into the PC
3. Writes the PPAGE value into the PPAGE register
4. Refills the queue and resumes execution at the return address
This sequence is uninterruptible. The RTC can be executed from anywhere in the local CPU memory
space.
The CALL and RTC instructions behave like JSR and RTS instruction, they however require more
execution cycles. Usage of JSR/RTS instructions is therefore recommended when possible and
CALL/RTC instructions should only be used when needed. The JSR and RTS instructions can be used to
access subroutines that are already present in the local CPU memory map (i.e. in the same page in the
program memory page window for example). However calling a function located in a different page
requires usage of the CALL instruction. The function must be terminated by the RTC instruction. Because
the RTC instruction restores contents of the PPAGE register from the stack, functions terminated with the
RTC instruction must be called using the CALL instruction even when the correct page is already present
in the memory map. This is to make sure that the correct PPAGE value will be present on stack at the time
of the RTC instruction execution.
11.5.2
Port Replacement Registers (PRRs)
Registers used for emulation purposes must be rebuilt by the in-circuit emulator hardware to achieve full
emulation of single chip mode operation. These registers are called port replacement registers (PRRs) (see
Table 1-25). PRRs are accessible from CPU, BDM and XGATE using different access types (word
aligned, word-misaligned and byte).
Each access to PRRs will be extended to 2 bus cycles for write or read accesses independent of the
operating mode. In emulation modes all write operations result in simultaneous writing to the internal
registers (peripheral access) and to the emulated registers (external access) located in the PRU in the
emulator. All read operations are performed from external registers (external access) in emulation modes.
In all other modes the read operations are performed from the internal registers (peripheral access).
Due to internal visibility of CPU accesses the CPU will be halted during XGATE or BDM access to any
PRR. This rule applies also in normal modes to ensure that operation of the device is the same as in
emulation modes.
A summary of PRR accesses:
• An aligned word access to a PRR will take 2 bus cycles.
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•
•
A misaligned word access to a PRRs will take 4 cycles. If one of the two bytes accessed by the
misaligned word access is not a PRR, the access will take only 3 cycles.
A byte access to a PRR will take 2 cycles.
Table 11-20. PRR Listing
PRR Name
PRR Local Address
PRR Location
PORTA
0x0000
PIM
PORTB
0x0001
PIM
DDRA
0x0002
PIM
DDRB
0x0003
PIM
PORTC
0x0004
PIM
PORTD
0x0005
PIM
DDRC
0x0006
PIM
DDRD
0x0007
PIM
PORTE
0x0008
PIM
DDRE
0x0009
PIM
MMCCTL0
0x000A
MMC
MODE
0x000B
MMC
PUCR
0x000C
PIM
RDRIV
0x000D
PIM
EBICTL0
0x000E
EBI
EBICTL1
0x000F
EBI
Reserved
0x0012
MMC
MMCCTL1
0x0013
MMC
ECLKCTL
0x001C
PIM
Reserved
0x001D
PIM
PORTK
0x0032
PIM
DDRK
0x0033
PIM
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11.5.3
On-Chip ROM Control
The MCU offers two modes to support emulation. In the first mode (called generator) the emulator
provides the data instead of the internal FLASH and traces the CPU actions. In the other mode (called
observer) the internal FLASH provides the data and all internal actions are made visible to the emulator.
11.5.3.1
ROM Control in Single-Chip Modes
In single-chip modes the MCU has no external bus. All memory accesses and program fetches are internal
(see Figure 11-24).
No External Bus
MCU
Flash
Figure 11-24. ROM in Single Chip Modes
11.5.3.2
ROM Control in Emulation Single-Chip Mode
In emulation single-chip mode the external bus is connected to the emulator. If the EROMON bit is set,
the internal FLASH provides the data and the emulator can observe all internal CPU actions on the external
bus. If the EROMON bit is cleared, the emulator provides the data (generator) and traces the all CPU
actions (see Figure 11-25).
Observer
Emulator
MCU
Flash
EROMON = 1
Generator
MCU
Emulator
Flash
EROMON = 0
Figure 11-25. ROM in Emulation Single-Chip Mode
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11.5.3.3
ROM Control in Normal Expanded Mode
In normal expanded mode the external bus will be connected to the application. If the ROMON bit is set,
the internal FLASH provides the data. If the ROMON bit is cleared, the application memory provides the
data (see Figure 11-26).
MCU
Application
Memory
Flash
ROMON = 1
MCU
Application
Memory
ROMON = 0
Figure 11-26. ROM in Normal Expanded Mode
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11.5.3.4
ROM Control in Emulation Expanded Mode
In emulation expanded mode the external bus will be connected to the emulator and to the application. If
the ROMON bit is set, the internal FLASH provides the data. If the EROMON bit is set as well the
emulator observes all CPU internal actions, otherwise the emulator provides the data and traces all CPU
actions (see Figure 11-27). When the ROMON bit is cleared, the application memory provides the data
and the emulator will observe the CPU internal actions (see Figure 11-28).
Observer
MCU
Emulator
Flash
Application
Memory
EROMON = 1
Generator
MCU
Emulator
Flash
Application
Memory
EROMON = 0
Figure 11-27. ROMON = 1 in Emulation Expanded Mode
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Observer
MCU
Emulator
Application
Memory
Figure 11-28. ROMON = 0 in Emulation Expanded Mode
11.5.3.5
ROM Control in Special Test Mode
In special test mode the external bus is connected to the application. If the ROMON bit is set, the internal
FLASH provides the data, otherwise the application memory provides the data (see Figure 11-29).
Application
MCU
Memory
ROMON = 0
Application
MCU
Flash
Memory
ROMON = 1
Figure 11-29. ROM in Special Test Mode
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Chapter 12
Clock Generation Module using IPLL (CGMIPLL)
Block Description
Revision History
Version Revision Effective
Number
Date
Date
V01.00
12.1
4 Oct.. 06
Author
4 Oct. 06
Description of Changes
Initial release
Introduction
This specification describes the function of the Clock Generation Module using an internal PLL
(CGMIPLL).
12.1.1
Features
The main features of this block are:
• Phase Locked Loop (IPLL) frequency multiplier with internal filter
— Reference divider
— optional divide by 2 of VCO frequency
— Configurable internal filter (no external pin)
— Optional frequency modulation for defined jitter and reduced emission
— Automatic frequency lock detector
— Interrupt request on entry or exit from locked condition
12.1.2
Modes of Operation
This subsection lists and briefly describes all operating modes supported by the CGMIPLL.
• Off Mode
Default after reset, as PLLON bit is zero
• Run Mode
PLLON bit is one, CGMIPLL registers must be configured for desired target frequency.
• Stop Mode
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In Stop Model the IPLL is always off.
12.1.3
Block Diagram
Figure 12-1 shows a block diagram of the CGMIPLL.
CGMIPLL
UNLOCKF
Lock
Detector
LOCK
LOCKIF
SYNDIV
&
LOCK change
Interrupt
LOCKIE
Feedback
Divider
REFDIV
EXTAL
Oscillator
XTAL
IPLL
FBCLK
OSCCLK
Reference
Divider
REFCLK
Phase
Detector
Up
FM1, FM0
VDDPLL
VCO
VCOCLK
DIV2
CGMIPLL Clock
Down
Charge Pump
and Filter
VSSPLL
REFFRQ
VCOFRQ
Figure 12-1. Block diagram of CGMIPLL
12.2
Signal Description
This section lists and describes the signals that connect off chip.
12.2.1
VDDPLL, VSSPLL
These pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the IPLL circuitry. This allows
the supply voltage to the IPLL to be independently bypassed. Even if IPLL usage is not required VDDPLL
and VSSPLL must be connected properly.
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Chapter 12 Clock Generation Module using IPLL (CGMIPLL) Block Description
12.3
Memory Map and Registers
This section provides a detailed description of all registers accessible in the CGMIPLL.
12.3.1
Module Memory Map
Figure 12-2 gives an overview on all CGMIPLL registers.
Address
Name
Bit 7
R
6
5
4
3
2
0x0000
CGMSYN
R
W
VCOFRQ[1:0]
SYNDIV[5:0]
0x0001
CGMREF R
DV
W
REFFRQ[1:0]
REFDIV[5:0]
0x0002
RESERVE R
D
W
0x0003
CGMFLG
0x0004
CGMCTL
0x0005
0
0
0
0
0
0
0
0
CGMTES R
T02
W
0
0
0
0x0006
CGMTES R
T12
W
0
0
0x0007
CGMTES R
T22
W
0
0
R
W
R
0
LOCKIE
0
1
Bit 0
0
0
0
0
LOCK
0
0
DIV2
FM1
FM0
PLLON
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LOCKIF
W
UNLOCKF
2. CGMTEST0, CGMTEST1 and CGMTEST2 registers are intended for factory test purposes only.
= Unimplemented or Reserved
Figure 12-2. CGMIPLL Register Summary
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
12.3.2
Register Descriptions
This section describes in address order all the CGMIPLL registers and their individual bits.
12.3.2.1
CGMIPLL Synthesizer Register (CGMSYNR)
The SYNR register controls the multiplication factor of the IPLL and selects the VCO frequency range.
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Chapter 12 Clock Generation Module using IPLL (CGMIPLL) Block Description
Module Base + 0x0000
7
6
5
4
3
2
1
0
0
0
0
R
VCOFRQ[1:0]
SYNDIV[5:0]
W
Reset
0
0
0
0
0
Figure 12-3. CGMIPLL Synthesizer Register (CGMSYNR)
Read: Anytime
Write: Anytime
Writing the CGMSYNR register clears the LOCK status bit.
( SYNDIV + 1 )
f VCO = 2 × f OSC × ------------------------------------( REFDIV + 1 )
f CGMIPLL = f VCO
(IF DIV2=0)
f VCO
f CGMIPLL = --------------2
(IF DIV2=1)
NOTE
fVCO must be within the specified VCO frequency lock range. fCGMIPLL
must not exceed the specified maximum.
The VCOFRQ[1:0] bit are used to configure the VCO gain for optimal stability and lock time. For correct
IPLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in Table 12-1. Setting the VCOFRQ[1:0] bits wrong can result in a non functional
IPLL (no locking and/or insufficient stability).
Table 12-1. VCO Clock Frequency Selection
12.3.2.2
VCOCLK Frequency Ranges
VCOFRQ[1:0]
32MHz <= fVCO<= 48MHz
00
48MHz < fVCO<= 80MHz
01
Reserved
10
80MHz < fVCO <= 120MHz
11
CGMIPLL Reference Divider Register (CGMREFDV)
The REFDV register provides a finer granularity for the IPLL multiplier steps.
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Module Base + 0x0001
7
6
5
4
3
2
1
0
0
0
0
R
REFFRQ[1:0]
REFDIV[5:0]
W
Reset
0
0
0
0
0
Figure 12-4. CGMIPLL Reference Divider Register (CGMREFDV)
Read: Anytime
Write: Anytime
Writing the CGMREFDV register clears the LOCK status bit.
f OSC
f REF = -----------------------------------( REFDIV + 1 )
The REFFRQ[1:0] bit are used to configure the internal PLL filter for optimal stability and lock time. For
correct IPLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in Figure 12-2. Setting the REFFRQ[1:0] bits wrong can result in a non functional
IPLL (no locking and/or insufficient stability).
Table 12-2. Reference Clock Frequency Selection
12.3.2.3
REFCLK Frequency Ranges
REFFRQ[1:0]
1MHz <= fREF <= 2MHz
00
2MHz < fREF <= 6MHz
01
6MHz < fREF <= 12MHz
10
fREF >12MHz
11
CGMIPLL Flags Register (CGMFLG)
This register provides CGMIPLL status bits and flags.
Module Base + 0x0003
7
R
6
5
0
0
LOCKIE
4
3
2
1
LOCK
0
0
LOCKIF
0
UNLOCKF
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-5. CGMIPLL Flags Register (CGMFLG)
Read: Anytime
Write: Refer to each bit for individual write conditions
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Chapter 12 Clock Generation Module using IPLL (CGMIPLL) Block Description
Table 12-3. CGMFLG Field Descriptions
Field
Description
7
LOCKIE
Lock Interrupt Enable Bit
0 LOCK interrupt requests are disabled.
1 Interrupt will be requested whenever LOCKIF is set.
4
LOCKIF
IPLL Lock Interrupt Flag —LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect.If enabled (LOCKIE=1), LOCKIF causes an interrupt request.
0 No change in LOCK status bit.
1 LOCK status bit has changed.
3
LOCK
IPLL Lock Status Bit — LOCK reflects the current state of IPLL lock condition. Writes have no effect. Writing
registers CGMSYNR or CGMREFDV or CGMCTL clears the LOCK status bit.
0 VCOCLK is not within the desired tolerance of the target frequency.
1 VCOCLK is within the desired tolerance of the target frequency.
0
UNLOCKF
IPLL Unlock Flag —UN LOCKF flag is set to 1 when LOCK status bit changes from locked (one) to unlocked
(zero). This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 No change from locked (one) to unlocked (zero).
1 LOCK bit has changed from locked (one) to unlocked (zero).
12.3.2.4
CGMIPLL Control Register (CGMCTL)
Module Base + 0x0004
R
7
6
5
4
0
0
0
0
3
2
1
0
DIV2
FM1
FM0
PLLON
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 12-6. CGMIPLL Control Register (CGMCTL)
Read: Anytime
Write: Anytime
Writing the CGMCTL register clears the LOCK status bit.
Table 12-4. CGMCTL Field Descriptions
Field
4
DIV2
Description
VCOCLK divide by 2 Bit
0 CGMIPLL Clock equals VCOCLK.
1 CGMIPLL Clock is half the frequency of VCOCLK.
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Table 12-4. CGMCTL Field Descriptions (continued)
Field
2, 1
FM1, FM0
0
PLLON
Description
IPLL Frequency Modulation Enable Bit — FM1 and FM0 enable additional frequency modulation on the
VCOCLK. This is to reduce noise emission. The modulation frequency is fref divided by 16. See Table 12-5 for
coding.
Phase Lock Loop On Bit — PLLON turns on the IPLL circuitry.
0 IPLL is turned off.
1 IPLL is turned on.
Table 12-5. FM Amplitude selection
FM1
12.3.2.5
FM0
FM Amplitude /
fVCO Variation
0
0
FM off
0
1
±1%
1
0
±2%
1
1
±4%
Reserved Register (CGMTEST0)
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special
modes can alter the CGMIPLL’s functionality.
Module Base + 0x0005
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 12-7. Reserved Register (CGMTEST0)
Read: Always read $00 except in special modes
Write: Only in special modes
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12.3.2.6
Reserved Register (CGMTEST1)
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special test
modes can alter the CGMIPLL’s functionality.
Module Base + 0x0006
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 12-8. Reserved Register (CGMTEST1)
Read: Always read $00 except in special modes
Write: Only in special modes
12.3.2.7
Reserved Register (CGMTEST2)
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special
modes can alter the CGMIPLL’s functionality.
Module Base + 0x0007
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 12-9. Reserved Register (CGMTEST2)
Read: always read $00 except in special modes
Write: only in special modes
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12.4
Functional Description
12.4.1
Examples of IPLL divider settings
Several examples of IPLL divider settings are shown in Table 12-6. Shaded rows indicated that these
settings are not recommended. The following rules help to achieve optimum stability and shortest lock
time:
• Use lowest possible fVCO / fREF ratio (SYNDIV value).
• Use highest possible REFCLK frequency fREF.
Table 12-6. Examples of IPLL Divider Settings
fOSC
REFDIV[5:0]
fREF
fVCO
VCOFRQ[1:0]
DIV2
fCGMIPLL
4MHz
$00
4MHz
01
$09
80MHz
01
0
80MHz
8MHz
$00
8MHz
10
$04
80MHz
01
0
80MHz
4MHz
$00
4MHz
01
$03
32MHz
00
1
16MHz
4MHz
$01
2MHz
00
$18
100MHz
11
0
100MHz
4MHz
$03
1MHz
00
$18
50MHz
01
0
50MHz
4MHz
$03
1MHz
00
$32
100MHz
11
0
100MHz
12.4.2
REFFRQ[1:0] SYNDIV[5:0]
IPLL Operation
The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is
divided in a range of 1 to 64 (REFDIV+1) to output the REFCLK. The VCO output clock, (VCOCLK) is
fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2
x (SYNDIV +1)] to output the FBCLK. The VCOCLK can by divided by 2 (DIV2 bit) to output the
CGMIPLL Clock.
The phase detector then compares the FBCLK, with the REFCLK. Correction pulses are generated based
on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the
internal filter capacitor, based on the width and direction of the correction pulse.
The user must select the range of the REFCLK frequency and the range of the VCOCLK frequency to
ensure that the correct IPLL loop bandwidth is set.
The lock detector compares the frequencies of the FBCLK, and the REFCLK. Therefore, the speed of the
lock detector is directly proportional to the reference clock frequency. The circuit determines the lock
condition based on this comparison.
If IPLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and then check
the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously (during
IPLL start-up, usually) or at periodic intervals.
• The LOCK bit is a read-only indicator of the locked state of the IPLL.
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•
•
The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆Lock, and is cleared
when the VCO frequency is out of a certain tolerance, ∆unl.
Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling
the LOCK bit.
12.5
Interrupts
The interrupts/reset vectors requested by the CGMIPLL are listed in Table 12-7. Refer to MCU
specification for related vector addresses and priorities.
Table 12-7. CGMIPLL Interrupt Vectors
12.5.1
12.5.1.1
Interrupt Source
CCR
Mask
Local Enable
LOCK interrupt
I bit
CGMFLG (LOCKIE)
Description of Interrupt Operation
IPLL Lock Interrupt
The CGMIPLL generates a IPLL Lock interrupt when the LOCK condition of the IPLL has changed,
either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting
the LOCKIE bit to zero. The IPLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has
changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
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Revision History
Rev. No.
Revision
Date
Effective
Date
1.4
20 Aug
2006
31 Aug
2006
Added lower bit rate description
add pe-pll description
fixed PSR1[APTAC] description
updated calculation of message buffers that can be used
renamed PRESCALE field in MCR to BITRATE
1.5
7 Nov
2006
7 Nov
2006
Module Configuration Register (MCR)
- updated description of CLKSEL bit
Section 13.6.7, “Individual Message Buffer Search”
- split message buffer priority table into static / dynamic segment
- add statement of rx tx buffer pair in dynamic segment
Section 13.6.3.7.2, “Receive FIFO Control Data”
- removed Note on empty receive fifo update issue
- added statement, that empty fifo can not be updated
1.6
02 Feb 07
02 Feb 07
13.1
13.1.1
Author
Summary of Changes
Section 13.6.7, “Individual Message Buffer Search”
- major update
Section 13.7.6, “Message Buffer Search on Simple Message Buffer
Configuration”
- added to illustrate message buffer search
Section 13.7.2, “Shut Down Sequence”
- simplified description
Section 13.1.6.3, “Stop Mode”
- make shutdown mandatory
added w1c indication to all flag bits, added rwm to CMT bit
added flexray bus related minimum chi frequency
Section 13.1.6, “Modes of Operation”
- updated desciption
Section 13.3, “Controller Host Interface Clocking”
- added and provide minimum chi frequency
Section 13.7.1, “Initialization Sequence
-updated, changed shutdown sequence
Introduction
Reference
The following documents are referenced.
• FlexRay Communications System Protocol Specification, Version 2.1 Rev A
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
•
FlexRay Communications System Electrical Physical Layer Specification, Version 2.1 Rev A
13.1.2
Glossary
This section provides a list of terms used in the description of the FlexRay block.
Table 13-1. List of Terms
Term
Definition
BCU
Buffer Control Unit. Handles message buffer access.
BMIF
Bus Master Interface. Provides master access to FlexRay memory block.
CC
Communication Controller
CDC
Clock Domain Crosser
CHI
Controller Host Interface
Cycle length in µT
The actual length of a cycle in µT for the ideal controller (+/- 0 ppm)
EBI
External Bus Interface
FRM
FlexRay Memory. Memory to store message buffer payload, header, and status, and to store
synchronization frame related tables.
FSS
Frame Start Sequence
HIF
Host Interface. Provides host access to FlexRay block.
Host
The FlexRay CC host MCU
LUT
Look Up Table. Stores message buffer header index value.
MB
Message Buffer
MBIDX
Message Buffer Index: the position of a header field entry within the header area. If the header area
is accessed as an array, this is the same as the array index of the entry.
MBNum
Message Buffer Number: Position of message buffer configuration registers within the register map.
For example, Message Buffer Number 5 corresponds to the MBCCS5 register.
MCU
Microcontroller Unit
µT
Microtick
MT
Macrotick
MTS
Media Access Test Symbol
NIT
Network Idle Time
PE
Protocol Engine
POC
Protocol Operation Control. Each state of the POC is denoted by POC:state
Rx
Reception
SEQ
Sequencer Engine
TCU
Time Control Unit
Tx
Transmission
13.1.3
Color Coding
Throughout this chapter types of items are highlighted through the use of an italicized color font.
FlexRay protocol parameters, constants and variables are highlighted with blue italics. An example is the
parameter gdActionPointOffset.
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FlexRay protocol states are highlighted in green italics. An example is the state POC:normal active.
13.1.4
Overview
The FlexRay block is a FlexRay communication controller that implements the FlexRay Communications
System Protocol Specification, Version 2.1 Rev A.
The FlexRay block has three main components:
• Controller host interface (CHI)
• Protocol engine (PE)
• Clock domain crossing unit (CDC)
A block diagram of the FlexRay block with its surrounding modules is given in Figure 13-1.
FLEXRAY
CHI
HIF
SEARCH
LUT
System
Memory
RXD_A
PE
BCU
BMIF
config
TXD_A
SEQ
Clock Domain Crossing
Host CPU
TxA
TXE_A
RXD_B
TXD_B
TXE_B
RxA
STB0
TCU
STB1
STB2
STB3
Figure 13-1. FLEXRAY Block Diagram
The protocol engine has two transmitter units TxA and TxB and two receiver units RxA and RxB for
sending and receiving frames through the two FlexRay channels. The time control unit (TCU) is
responsible for maintaining global clock synchronization to the FlexRay network. The overall activity of
the PE is controlled by the sequencer engine (SEQ).
The controller host interface provides host access to the module’s configuration, control, and status
registers, as well as to the message buffer configuration, control, and status registers. The message buffers
themselves, which contain the frame header and payload data received or to be transmitted, and the slot
status information, are stored in the FlexRay Memory (FRM).
The clock domain crossing unit implements signal crossing from the CHI clock domain to the PE clock
domain and vice versa, to allow for asynchronous PE and CHI clock domains.
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
The FlexRay block stores the frame header and payload data of frames received or of frames to be
transmitted in the FRM. The application accesses the FRM to retrieve and provide the frames to be
processed by the FlexRay block. In addition to the frame header and payload data, the FlexRay block stores
the synchronization frame related tables in the FRM for application processing.
The FlexRay Memory is located in the system memory of the MCU. The FlexRay block has access to the
FRM via its bus master interface (BMIF). The host provides the start address of the FRM window within
the system memory by programming the System Memory Base Address High Register (SYMBADHR)
and System Memory Base Address Low Register (SYMBADLR). All FRM related offsets are stored in
offset registers. The physical address pointer into the FRM window of the MCU system memory is
calculated using the offset values the FlexRay Memory base address.
NOTE
The FlexRay block does not provide a memory protection scheme for the
FlexRay Memory.
13.1.5
Features
The FlexRay block provides the following features:
• FlexRay Communications System Protocol Specification, Version 2.1 Rev A compliant protocol
implementation
• FlexRay Communications System Electrical Physical Layer Specification, Version 2.1 Rev A
compliant bus driver interface
• single channel support
— FlexRay Port A can be configured to be connected either to physical FlexRay channel A or
physical FlexRay channel B.
• FlexRay bus data rates of 10 Mbit/s, 8 Mbit/s, 5 Mbit/s, and 2.5 Mbit/s supported
• internal oscillator or internal PLL clocking of the protocol engine
• 32 configurable message buffers with
— individual frame ID filtering
— individual channel ID filtering
— individual cycle counter filtering
• message buffer header, status and payload data stored in dedicated FlexRay Memory
— allows for flexible and efficient message buffer implementation
— consistent data access ensured by means of buffer locking scheme
— application can lock multiple buffers at the same time
• size of message buffer payload data section configurable from 0 up to 254 bytes
• two independent message buffer segments with configurable size of payload data section
— each segment can contain message buffers assigned to the static segment and message buffers
assigned to the dynamic segment at the same time
• zero padding for transmit message buffers in static segment
— applied when the frame payload length exceeds the size of the message buffer data section
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•
•
•
•
•
•
•
•
•
•
•
transmit message buffers configurable with state/event semantics
message buffers can be configured as
— receive message buffer
— single buffered transmit message buffer
— double buffered transmit message buffer (combines two single buffered message buffer)
individual message buffer reconfiguration supported
— means provided to safely disable individual message buffers
— disabled message buffers can be reconfigured
two independent receive FIFOs
— one receive FIFO per channel
— up to 255 entries for each FIFO
— global frame ID filtering, based on both value/mask filters and range filters
— global channel ID filtering
— global message ID filtering for the dynamic segment
4 configurable slot error counters
4 dedicated slot status indicators
— used to observe slots without using receive message buffers
measured value indicators for the clock synchronization
— internal synchronization frame ID and synchronization frame measurement tables can be
copied into the FlexRay Memory
fractional macroticks are supported for clock correction
maskable interrupt sources provided via individual and combined interrupt lines
1 absolute timer
1 timer that can be configured to absolute or relative
13.1.6
Modes of Operation
This section describes the basic operational power modes of the FlexRay block.
13.1.6.1
Disabled Mode
This is the mode the FlexRay block enters during hard reset. The FlexRay block indicates that it is in the
Disabled Mode by negating the module enable bit MEN in the Module Configuration Register (MCR).
No communication is performed on the FlexRay bus.
All registers with the write access conditions Any Time and Disabled Mode can be accessed for writing as
stated in Section 13.5.2, “Register Descriptions”.
The application configures the FlexRay block by accessing the configuration bits and fields in the Module
Configuration Register (MCR).
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13.1.6.1.1
Leave Disabled Mode
The FlexRay block leaves the Disabled Mode and enters the Normal Mode, when the application writes 1
to the module enable bit MEN in the Module Configuration Register (MCR)
NOTE
When the FlexRay block was enabled, it cannot be disabled the later on.
13.1.6.2
Normal Mode
In this mode the FlexRay block is fully functional. The FlexRay block indicates that it is in Normal Mode
by asserting the module enable bit MEN in the Module Configuration Register (MCR).
13.1.6.2.1
Enter Normal Mode
This mode is entered when the application requests the FlexRay block to leave the Disabled Mode or when
the MCU leaves the Stop Mode. If the Normal Mode was entered by leaving the Disabled Mode, the
application has to perform the protocol initialization described in 13.7.1.2, “Protocol Initialization” to
achieve full FlexRay functionality.
Depending on the values of the SCM, CHA, and CHB bits in the Module Configuration Register (MCR),
the corresponding FlexRay bus driver ports are driven.
13.1.6.3
Stop Mode
The FlexRay block is in Stop Mode when the MCU is either in Full Stop or Pseudo Stop Mode. In this
mode all FlexRay block clocks are stopped. No registers can be accessed. No communication is performed
on the FlexRay Bus.
13.1.6.3.1
Enter Stop Mode
Before the application requests the MCU to enter one of the Stop Modes, it has to shut down the FlexRay
block as described in Section 13.7.2, “Shut Down Sequence”.
NOTE
If the FlexRay block is stopped during transmission of data, it is not
guaranteed, that the FlexRay ports return to its inactive state before the
clocks are stopped. This can result in the lockup of the FlexRay Bus.
13.1.6.3.2
Leave Stop Mode
The FlexRay block leaves the Stop Mode when the MCU leaves its Stop Mode and all clocks are reapplied
to the FlexRay block. The FlexRay block enters the operational mode it was in before going into Stop
Mode.
If the FlexRay block enters the Normal Mode, the application has to put the protocol engine into the default
config state by the following sequence:
d) issue the DEFAULT_CONFIG command via Protocol Operation Control Register (POCR)
e) wait for POC:default config in Protocol Status Register 0 (PSR0)
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Subsequently the application can reconfigure and/or reintegrate the FlexRay node into the FlexRay cluster.
13.2
External Signal Description
This section lists and describes the FlexRay block signals, connected to external pins. These signals are
summarized in Table 13-2 and described in detail in Section 13.2.1, “Detailed Signal Descriptions”.
NOTE
The off chip signals RXD_A, TXD_A, and TXE_A are available on each
package option. The availability of the other off chip signals depends on the
package option.
Table 13-2. External Signal Properties
Name
Direction
Active
Reset
Function
RXD_A
Input
—
—
Receive Data Channel A
TXD_A
Output
—
1
Transmit Data Channel A
TXE_A
Output
Low
1
Transmit Enable Channel A
RXD_B
Input
—
—
Receive Data Channel B
TXD_B
Output
—
1
Transmit Data Channel B
TXE_B
Output
Low
1
Transmit Enable Channel B
STB0
Output
—
0
Debug Strobe Signal 0
STB1
Output
—
0
Debug Strobe Signal 1
STB2
Output
—
0
Debug Strobe Signal 2
STB3
Output
—
0
Debug Strobe Signal 3
13.2.1
Detailed Signal Descriptions
This section provides a detailed description of the FlexRay block signals, connected to external pins.
13.2.1.1
RXD_A — Receive Data Channel A
The RXD_A signal carries the receive data for channel A from the corresponding FlexRay bus driver.
13.2.1.2
TXD_A — Transmit Data Channel A
The TXD_A signal carries the transmit data for channel A to the corresponding FlexRay bus driver.
13.2.1.3
TXE_A — Transmit Enable Channel A
The TXE_A signal indicates to the FlexRay bus driver that the FlexRay block is attempting to transmit
data on channel A.
13.2.1.4
RXD_B — Receive Data Channel B
The RXD_B signal carries the receive data for channel B from the corresponding FlexRay bus driver.
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13.2.1.5
TXD_B — Transmit Data Channel B
The TXD_B signal carries the transmit data for channel B to the corresponding FlexRay bus driver
13.2.1.6
TXE_B — Transmit Enable Channel B
The TXE_B signal indicates to the FlexRay bus driver that the FlexRay block is attempting to transmit data
on channel B.
13.2.1.7
STB3, STB2, STB1, STB0 — Strobe Signals
These signals provide the selected debug strobe signals. For details on the debug strobe signal selection
refer to Section 13.6.16, “Strobe Signal Support”.
13.3
Controller Host Interface Clocking
The clock for the CHI is derived from the system bus clock and has the same phase and frequency. Since
the FlexRay protocol requires data delivery at fixed points in time, the memory read cycles from the FRM
must be finished after a fixed amount of time. To ensure this, a minimum frequency fchi of the CHI clock
is required, which is given in Equation 13-1.
f chi ≥ 16MHz
Eqn. 13-1
Additional requirements for the minimum frequency of the CHI clock result from the number of message
buffer. The requirement is provides in Section 13.7.3, “Number of Usable Message Buffers”
13.4
Protocol Engine Clocking
The clock for the protocol engine can be generated by two sources. The first source is the internal crystal
oscillator and the second source is an internal PLL. The clock source to be used is selected by the clock
source select bit CLKSEL in the Module Configuration Register (MCR).
13.4.1
Oscillator Clocking
If the protocol engine is clocked by the internal crystal oscillator, an 80 MHz crystal or 80 MHz CMOS
compatible clock must be connected to the oscillator pins. The crystal or clock must fulfill the
requirements given by the FlexRay Communications System Protocol Specification, Version 2.1 Rev A.
13.4.2
PLL Clocking
If the protocol engine is clocked by the dedicated internal PLL, which is described in Chapter 12, “Clock
Generation Module using IPLL (CGMIPLL) Block Description, the CGMIPLL must be programmed to
generate an output clock with fCGMIPLL = 80 MHz.
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13.4.3
PLL Lock Handling
For correct flexray bus functionality of the protocol engine, it is required that the PLL in the CGMIPLL
module is locked while the protocol engine is driving data onto the flexray bus. The lock state of the PLL
is indicated by the lock status bit LOCK in the CGMIPLL Flags Register (CGMFLG).
The FlexRay block drives its FlexRay transmit enable ports TXE_A and TXE_B to active state only if the
PLL unlock flag UNLOCKF in the CGMIPLL Flags Register (CGMFLG) is 0. If the unlock flag
UNLOCKF is 1, the FlexRay block drives its FlexRay transmit enable ports TXE_A and TXE_B to its
inactive state 1.
13.4.3.1
PLL Loss of Lock
If the PLL goes from the locked state to the unlock state, the CGMIPLL module sets the lock bit LOCK
to 0 and the unlock flag UNLOCKF to 1. As a result, the FlexRay block drives its FlexRay transmit enable
ports TXE_A and TXE_B to its inactive states 1 and thus stops the transmission onto the FlexRay bus
immediately. As a result of the loss of lock, the correct operation of the PE is no longer guaranteed. The
application should perform a shutdown of the FlexRay module as described in 13.7.2, “Shut Down
Sequence”.
13.4.3.2
PLL Gain of Lock
If the PLL goes from the unlocked state to the locked state, the CGMIPLL module sets the lock bit LOCK
to 1. The unlock flag UNLOCKF is not cleared by the module, this has to be done by the application. After
the clearing of the unlock flag UNLOCKF, the application can perform the FlexRay initialization as
described in 13.7.1, “Initialization Sequence”.
13.5
Memory Map and Register Description
The FlexRay block occupies 512 bytes of address space starting atthe FlexRay block’s base address
defined by the memory map of the MCU.
13.5.1
Memory Map
The complete memory map of the FlexRay block is shown in Table 13-3. The addresses presented here are
the offsets relative to the FlexRay block base address which is defined by the MCU address map.
Table 13-3. FlexRay Memory Map (Sheet 1 of 4)
Offset
Register
Access
Module Configuration and Control
0x0000
Module Version Register (MVR)
R
0x0002
Module Configuration Register (MCR)
R/W
0x0004
System Memory Base Address High Register (SYMBADHR)
R/W
0x0006
System Memory Base Address Low Register (SYMBADLR)
R/W
0x0008
Strobe Signal Control Register (STBSCR)
R/W
0x000A
Strobe Port Control Register (STBPCR)
R/W
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Table 13-3. FlexRay Memory Map (Sheet 2 of 4)
Offset
Register
Access
0x000C
Message Buffer Data Size Register (MBDSR)
R/W
0x000E
Message Buffer Segment Size and Utilization Register (MBSSUTR)
R/W
Test Registers
0x0010
Reserved
R
0x0012
Reserved
R
Interrupt and Error Handling
0x0014
Protocol Operation Control Register (POCR)
R/W
0x0016
Global Interrupt Flag and Enable Register (GIFER)
R/W
0x0018
Protocol Interrupt Flag Register 0 (PIFR0)
R/W
0x001A
Protocol Interrupt Flag Register 1 (PIFR1)
R/W
0x001C
Protocol Interrupt Enable Register 0 (PIER0)
R/W
0x001E
Protocol Interrupt Enable Register 1 (PIER1)
R/W
0x0020
CHI Error Flag Register (CHIERFR)
R/W
0x0022
Message Buffer Interrupt Vector Register (MBIVEC)
R
0x0024
Channel A Status Error Counter Register (CASERCR)
R
0x0026
Channel B Status Error Counter Register (CBSERCR)
R
Protocol Status
0x0028
Protocol Status Register 0 (PSR0)
R
0x002A
Protocol Status Register 1 (PSR1)
R
0x002C
Protocol Status Register 2 (PSR2)
R
0x002E
Protocol Status Register 3 (PSR3)
R/W
0x0030
Macrotick Counter Register (MTCTR)
R
0x0032
Cycle Counter Register (CYCTR)
R
0x0034
Slot Counter Channel A Register (SLTCTAR)
R
0x0036
Slot Counter Channel B Register (SLTCTBR)
R
0x0038
Rate Correction Value Register (RTCORVR)
R
0x003A
Offset Correction Value Register (OFCORVR)
R
0x003C
Combined Interrupt Flag Register (CIFRR)
R
0x003E
System Memory Access Time-Out Register (SYMATOR)
R/W
Sync Frame Counter and Tables
0x0040
Sync Frame Counter Register (SFCNTR)
R
0x0042
Sync Frame Table Offset Register (SFTOR)
R/W
0x0044
Sync Frame Table Configuration, Control, Status Register (SFTCCSR)
R/W
Sync Frame Filter
0x0046
Sync Frame ID Rejection Filter Register (SFIDRFR)
R/W
0x0048
Sync Frame ID Acceptance Filter Value Register (SFIDAFVR)
R/W
0x004A
Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR)
R/W
Network Management Vector
0x004C
Network Management Vector Register 0 (NMVR0)
R
0x004E
Network Management Vector Register 1 (NMVR1)
R
0x0050
Network Management Vector Register 2 (NMVR2)
R
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Table 13-3. FlexRay Memory Map (Sheet 3 of 4)
Offset
Register
Access
0x0052
Network Management Vector Register 3 (NMVR3)
R
0x0054
Network Management Vector Register 4 (NMVR4)
R
0x0056
Network Management Vector Register 5 (NMVR5)
R
0x0058
Network Management Vector Length Register (NMVLR)
R/W
Timer Configuration
0x005A
Timer Configuration and Control Register (TICCR)
R/W
0x005C
Timer 1 Cycle Set Register (TI1CYSR)
R/W
0x005E
Timer 1 Macrotick Offset Register (TI1MTOR)
R/W
0x0060
Timer 2 Configuration Register 0 (TI2CR0)
R/W
0x0062
Timer 2 Configuration Register 1 (TI2CR1)
R/W
Slot Status Configuration
0x0064
Slot Status Selection Register (SSSR)
R/W
0x0066
Slot Status Counter Condition Register (SSCCR)
R/W
Slot Status
0x0068
Slot Status Register 0 (SSR0)
R
0x006A
Slot Status Register 1 (SSR1)
R
0x006C
Slot Status Register 2 (SSR2)
R
0x006E
Slot Status Register 3 (SSR3)
R
0x0070
Slot Status Register 4 (SSR4)
R
0x0072
Slot Status Register 5 (SSR5)
R
0x0074
Slot Status Register 6 (SSR6)
R
0x0076
Slot Status Register 7 (SSR7)
R
0x0078
Slot Status Counter Register 0 (SSCR0)
R
0x007A
Slot Status Counter Register 1 (SSCR1)
R
0x007C
Slot Status Counter Register 2 (SSCR2)
R
0x007E
Slot Status Counter Register 3 (SSCR3)
R
MTS Generation
0x0080
MTS A Configuration Register (MTSACFR)
R/W
0x0082
MTS B Configuration Register (MTSBCFR)
R/W
Shadow Buffer Configuration
0x0084
Receive Shadow Buffer Index Register (RSBIR)
R/W
Receive FIFO — Configuration
0x0086
Receive FIFO Selection Register (RFSR)
R/W
0x0088
Receive FIFO Start Index Register (RFSIR)
R/W
0x008A
Receive FIFO Depth and Size Register (RFDSR)
R/W
Receive FIFO - Status
0x008C
Receive FIFO A Read Index Register (RFARIR)
R
0x008E
Receive FIFO B Read Index Register (RFBRIR)
R
Receive FIFO - Filter
0x0090
Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR)
R/W
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Table 13-3. FlexRay Memory Map (Sheet 4 of 4)
Offset
Register
Access
0x0092
Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR)
R/W
0x0094
Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR)
R/W
0x0096
Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR)
R/W
0x0098
Receive FIFO Range Filter Configuration Register (RFRFCFR)
R/W
0x009A
Receive FIFO Range Filter Control Register (RFRFCTR)
R/W
Dynamic Segment Status
0x009C
Last Dynamic Transmit Slot Channel A Register (LDTXSLAR)
R
0x009E
Last Dynamic Transmit Slot Channel B Register (LDTXSLBR)
R
Protocol Configuration
0x00A0
...
0x00DC
Protocol Configuration Register 0 (PCR0)
...
Protocol Configuration Register 30 (PCR30)
R/W
–
R/W
0x00DE
...
0x00FE
Reserved
R
Message Buffers Configuration, Control, Status
0x0100
Message Buffer Configuration, Control, Status Register 0 (MBCCSR0)
R/W
0x0102
Message Buffer Cycle Counter Filter Register 0 (MBCCFR0)
R/W
0x0104
Message Buffer Frame ID Register 0 (MBFIDR0)
R/W
0x0106
Message Buffer Index Register 0 (MBIDXR0)
R/W
...
...
...
0x01F8
Message Buffer Configuration, Control, Status Register 31 (MBCCSR31)
R/W
0x01FA
Message Buffer Cycle Counter Filter Register 31 (MBCCFR31)
R/W
0x01FC
Message Buffer Frame ID Register 31 (MBFIDR31)
R/W
0x01FE
Message Buffer Index Register 31 (MBIDXR31)
R/W
13.5.2
Register Descriptions
This section provides detailed descriptions of all registers in ascending address order, presented as 16-bit
wide entities
Table 13-4 provides a key for the register figures and register tables.
Table 13-4. Register Access Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writeable.
R*
Reserved bit or field, will not be changed. Application must not write any value different from the reset value.
FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
rwm
A read/write bit that may be modified by a hardware in some fashion other than by a reset.
w1c
Write one to clear. A flag bit that can be read, is cleared by writing a one, writing 0 has no effect.
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
Table 13-4. Register Access Conventions (continued)
Convention
Description
Reset Value
0
Resets to zero.
1
Resets to one.
–
Not defined after reset and not affected by reset.
13.5.2.1
Register Reset
All registers except the Message Buffer Cycle Counter Filter Registers (MBCCFRn), Message Buffer
Frame ID Registers (MBFIDRn), and Message Buffer Index Registers (MBIDXRn) are reset to their reset
value on system reset. The registers mentioned above are located in physical memory blocks and, thus,
they are not affected by reset. For some register fields, additional reset conditions exist. These additional
reset conditions are mentioned in the detailed description of the register. The additional reset conditions
are explained in Table 13-5.
Table 13-5. Additional Register Reset Conditions
Condition
Description
Protocol RUN Command
The register field is reset when the application writes to RUN command “0101” to the
POCCMD field in the Protocol Operation Control Register (POCR).
Message Buffer Disable
The register field is reset when the application has disabled the message buffer.
This happens when the application writes 1 to the message buffer disable trigger bit
MBCCSRn.EDT while the message buffer is enabled (MBCCSn.EDS = 1) and the FlexRay
block grants the disable to the application by clearing the MBCCSRn.EDS bit.
13.5.2.2
Register Write Access
This section describes the write access restriction terms that apply to all registers.
13.5.2.2.1
Register Write Access Restriction
For each register bit and register field, the write access conditions are specified in the detailed register
description. A description of the write access conditions is given in Table 13-6. If, for a specific register
bit or field, none of the given write access conditions is fulfilled, any write attempt to this register bit or
field is ignored without any notification. The values of the bits or fields are not changed. The condition
term [A or B] indicates that the register or field can be written to if at least one of the conditions is fulfilled.
Table 13-6. Register Write Access Restrictions
Condition
Indication
Any Time
-
Description
No write access restriction.
Disabled Mode
MCR.MEN = 0
Write access only when the FlexRay block is in Disabled Mode.
Normal Mode
MCR.MEN = 1
Write access only when the FlexRay block is in Normal Mode.
POC:config
PSR0.PROTSTATE = POC:config
Write access only when the Protocol is in the POC:config state.
MBCCSRn.EDS = 0
Write access only when the related Message Buffer is disabled.
MB_DIS
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
Table 13-6. Register Write Access Restrictions
Condition
Indication
MB_LCK
Description
MBCCSRn.LCKS = 1
13.5.2.2.2
Write access only when the related Message Buffer is locked.
Register Write Access Requirements
For some of the registers, a 16-bit wide write access is required to ensure correct operation. This write
access requirement is stated in the detailed register description for each register affected
13.5.2.2.3
Internal Register Access
The following memory mapped registers are used to access multiple internal registers.
• Strobe Signal Control Register (STBSCR)
• Slot Status Selection Register (SSSR)
• Slot Status Counter Condition Register (SSCCR)
• Receive Shadow Buffer Index Register (RSBIR)
Each of these memory mapped registers provides a SEL field and a WMD bit. The SEL field is used to
select the internal register. The WMD bit controls the write mode. If the WMD bit is set to 0 during the
write access, all fields of the internal register are updated. If the WMD bit set to 1, only the SEL field is
changed. All other fields of the internal register remain unchanged. This allows for reading back the values
of the selected internal register in a subsequent read access.
13.5.2.3
Module Version Register (MVR)
Module Base + 0x0000
15
14
13
R
12
11
10
9
8
7
6
5
CHIVER
4
3
2
1
0
1
1
0
PEVER
W
Reset
1
0
0
0
1
0
0
0
0
1
1
0
0
Figure 13-2. Module Version Register (MVR)
This register provides the FlexRay block version number. The module version number is derived from the
CHI version number and the PE version number.
Table 13-7. MVR Field Descriptions
Field
Description
15–8
CHIVER
CHI Version Number — This field provides the version number of the controller host interface.
7–0
PEVER
PE Version Number — This field provides the version number of the protocol engine.
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
13.5.2.4
Module Configuration Register (MCR)
Module Base + 0x0002
15
R
W
MEN
Reset
0
14
0
0
13
12
SCM
CHB
0
0
11
10
CHA SFFE
0
0
9
0
0
8
R*
0
7
6
5
0
0
0
4
CLKS
EL
0
0
0
0
3
2
1
BITRATE
0
0
0
0
0
0
Figure 13-3. Module Configuration Register (MCR)
Write: MEN, SCM, CHB, CHA, CLKSEL, BITRATE: Disabled Mode
SFFE: Disabled Mode or POC:config
This register defines the global configuration of the FlexRay block.
Table 13-8. MCR Field Descriptions
Field
Description
15
MEN
Module Enable — This bit indicates whether or not the FlexRay block is in the Disabled Mode. The application
requests the FlexRay block to leave the Disabled Mode by writing 1 to this bit. Before leaving the Disabled Mode,
the application must configure the SCM, CHB, CHA, TMODE, CLKSEL, BITRATE values. For details see
Section 13.1.6, “Modes of Operation”.
0 Write: ignored, FlexRay block disable not possible
Read: FlexRay block disabled
1 Write: enable FlexRay block
Read: FlexRay block enabled
Note: If the FlexRay block is enabled it can not be disabled.
13
SCM
Single Channel Device Mode — This control bit defines the channel device mode of the FlexRay block as
described in Section 13.6.10, “Channel Device Modes”.
0 FlexRay block works in dual channel device mode
1 FlexRay block works in single channel device mode
12–11
CHB
CHA
Channel Enable — protocol related parameter: pChannels
The semantic of these control bits depends on the channel device mode controlled by the SCM bit and is given
Table 13-9.
10
SFFE
Synchronization Frame Filter Enable — This bit controls the filtering for received synchronization frames. For
details see Section 13.6.15, “Sync Frame Filtering”.
0 Synchronization frame filtering disabled
1 Synchronization frame filtering enabled
8
R*
Reserved — This bit is reserved. It is read as 0. Application must not write 1 to this bit.
4
CLKSEL
Protocol Engine Clock Source Select — This bit is used to select the clock source for the protocol engine.
0 PE clock source is generated by on-chip crystal oscillator.
1 PE clock source is generated by on-chip PLL.
3–1
BITRATE
FlexRay Bus Bit Rate — This bit field defines the bit rate of the flexray channels according to Table 13-10.
Table 13-9. FlexRay Channel Selection (Sheet 1 of 2)
SCM
CHB
CHA
Description
Dual Channel Device Modes
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
Table 13-9. FlexRay Channel Selection (Sheet 2 of 2)
SCM
CHB
0
0
CHA
0
ports RXD_A, TXD_A, and TXE_A not driven by FlexRay block
ports RXD_B, TXD_B, and TXE_A not driven by FlexRay block
PE channel 0 idle
PE channel 1 idle
1
ports RXD_A, TXD_A, and TXE_A driven by FlexRay block
ports RXD_B, TXD_B, and TXE_A not driven by FlexRay block
PE channel 0 active
PE channel 1 idle
0
ports RXD_A, TXD_A, and TXE_A not driven by FlexRay block
ports RXD_B, TXD_B, and TXE_A driven by FlexRay block
PE channel 0 idle
PE channel 1 active
1
ports RXD_A, TXD_A, and TXE_A driven by FlexRay block
ports RXD_B, TXD_B, and TXE_A driven by FlexRay block
PE channel 0 active
PE channel 1 active
0
1
1
Description
Single Channel Device Mode
0
ports RXD_A, TXD_A, and TXE_A not driven by FlexRay block
ports RXD_B, TXD_B, and TXE_A not driven by FlexRay block
PE channel 0 idle
PE channel 1 idle
1
ports RXD_A, TXD_A, and TXE_A driven by FlexRay block
ports RXD_B, TXD_B, and TXE_A not driven by FlexRay block
PE channel 0 active
PE channel 1 idle
1
0
ports RXD_A, TXD_A, and TXE_A driven by FlexRay block
ports RXD_B, TXD_B, and TXE_A not driven by FlexRay block
PE channel 0 active, uses cCrcInit[B] (see Figure 13-135)
PE channel 1 idle
1
1
reserved
0
1
0
Table 13-10. FlexRay Channel Bit Rate Selection
MCR[BITRATE]
FlexRay Channel Bit Rate [Mbit/s]
000
001
010
011
100
101
110
111
10.0
5.0
2.5
8.0
reserved
reserved
reserved
reserved
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
13.5.2.5
System Memory Base Address High Register (SYMBADHR) and
System Memory Base Address Low Register (SYMBADLR)
Module Base + 0x0004
15
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
6
4
3
2
1
0
SYS_MEM_BASE_ADDR[22:16]
W
Reset
5
0
0
0
0
0
0
0
Figure 13-4. System Memory Base Address High Register (SYMBADHR)
Write: Disabled Mode
Module Base + 0x0006
15
14
13
12
R
11
10
9
8
7
6
5
4
SYS_MEM_BASE_ADDR[15:4]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
3
2
1
0
0
0
0
0
0
0
0
0
Figure 13-5. System Memory Base Address Low Register (SYMBADLR)
Write: Disabled Mode
NOTE
The system memory base address must be set before the FlexRay block is
enabled.
The system memory base address registers define the base address of the FRM within the system memory.
The base address is used by the BMIF to calculate the physical memory address for system memory
accesses.
Table 13-11. SYMBADHR and SYMBADLR Field Descriptions
Field
Description
22–4
This base address will be added to all system memory offset values stored in registers or calculated in the
SYMBADHR FlexRay block before the FlexRay block accesses the system memory via its bus master interface. The system
SYMBADLR memory base address must be aligned to an 16-byte boundary.
13.5.2.6
Strobe Signal Control Register (STBSCR)
Module Base + 0x0008
15
R
14
16-bit write access required
13
12
0
0
10
9
8
SEL
W WMD
Reset
11
0
0
0
0
0
0
0
7
6
5
0
0
0
0
0
0
4
ENB
0
3
2
0
0
0
0
1
0
STBPSEL
0
0
Figure 13-6. Strobe Signal Control Register (STBSCR)
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
Write: Anytime
This register is used to assign the individual protocol timing related strobe signals given in Table 13-13 to
the external strobe ports. Each strobe signal can be assigned to at most one strobe port. Each write access
to registers overwrites the previously written ENB and STBPSEL values for the signal indicated by SEL.
If more than one strobe signal is assigned to one strobe port, the current values of the strobe signals are
combined with a binary OR and presented at the strobe port. If no strobe signal is assigned to a strobe port,
the strobe port carries logic 0. For more detailed and timing information refer to Section 13.6.16, “Strobe
Signal Support”.
NOTE
In single channel device mode, channel B related strobe signals are
undefined and should not be assigned to the strobe ports.
Table 13-12. STBSCR Field Descriptions
Field
Description
15
WMD
Write Mode — This control bit defines the write mode of this register.
0 Write to all fields in this register on write access.
1 Write to SEL field only on write access.
14–8
SEL
Strobe Signal Select — This control field selects one of the strobe signals given in Table 13-13 to be enabled
or disabled and assigned to one of the four strobe ports given in Table 13-13.
4
ENB
Strobe Signal Enable — The control bit is used to enable and to disable the strobe signal selected by
STBSSEL.
0 Strobe signal is disabled and not assigned to any strobe port.
1 Strobe signal is enabled and assigned to the strobe port selected by STBPSEL.
1–0
STBPSEL
Strobe Port Select — This field selects the strobe port that the strobe signal selected by the SEL is assigned
to. All strobe signals that are enabled and assigned to the same strobe port are combined with a binary OR
operation.
00 assign selected signal to STB0
01 assign selected signal to STB1
10 assign selected signal to STB2
11 assign selected signal to STB3
.;
Table 13-13. Strobe Signal Mapping (Sheet 1 of 3)
SEL
Description
dec
hex
0
0x00
poc_startup_state[0] (for coding see PSR0[4])
1
0x01
poc_startup_state[1] (for coding see PSR0[5])
2
0x02
poc_startup_state[2] (for coding see PSR0[6])
3
0x03
poc_startup_state[3] (for coding see PSR0[7])
4
0x04
poc_state[0] (for coding see PSR0[8])
5
0x05
poc_state[1] (for coding see PSR0[9])
6
0x06
poc_state[2] (for coding see PSR0[10])
7
0x07
8
0x08
9
0x09
10
0x0A
channel idle indicator
receive data after glitch filtering
Channel
Type
Offset(1)
Reference
-
value
0
MT start
level
+5
A
B
A
B
value
+4
RXD_A
RXD_B
RXD_A
RXD_B
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Table 13-13. Strobe Signal Mapping (Sheet 2 of 3)
SEL
Description
dec
Channel
Type
Offset(1)
pulse
+4
pulse
+4
pulse
+5
pulse
+4
pulse
+4
pulse
+4
pulse
+4
pulse
+4
pulse
+5
level
+4
pulse
+4
pulse
-1
pulse
-1
pulse
-1
pulse
-1
Reference
hex
11
0x0B
12
0x0C
13
0x0D
14
0x0E
15
0x0F
16
0x10
17
0x11
18
0x12
19
0x13
20
0x14
21
0x15
22
0x16
23
0x17
24
0x18
25
0x19
26
0x1A
27
0x1B
28
0x1C
29
0x1D
30
0x1E
31
0x1F
32
0x20
33
0x21
34
0x22
35
0x23
36
0x24
37
0x25
38
0x26
39
0x27
40
0x28
synchronization edge strobe
A
B
A
header received
B
wakeup symbol decoded
MTS or CAS symbol decoded
A
B
A
B
A
frame decoded
B
channel idle detected
start of communication element detected
potential frame start channel
wakeup collision detected
content error detected
syntax error detected
start transmission of wakeup pattern
start transmission of MTS or CAS symbol
start of transmission
end of transmission
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
RXD_A
RXD_B
RXD_A
RXD_B
RXD_A
RXD_B
RXD_A
RXD_B
RXD_A
RXD_B
RXD_A
RXD_B
RXD_A
RXD_B
RXD_A
RXD_B
RXD_A
RXD_B
RXD_A
RXD_B
RXD_A
RXD_B
TXD_A
TXD_B
TXD_A
TXD_B
TXD_A
TXD_B
TXD_A
TXD_B
41
0x29
static segment indicator
-
level
0
MT start
42
0x2A
dynamic segment indicator
-
level
0
MT start
43
0x2B
symbol window indicator
-
level
0
MT start
44
0x2C
NIT indicator
-
level
0
MT start
45
0x2D
action point
-
pulse
-1
TXD_A
46
0x2E
sync calculation complete(2)
-
pulse
-
-
47
0x2F
start of offset correction
-
pulse
-2
MT start
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
Table 13-13. Strobe Signal Mapping (Sheet 3 of 3)
SEL
Description
dec
hex
48
0x30
cycle count[0]
49
0x31
cycle count[1]
50
0x32
cycle count[2]
51
0x33
cycle count[3]
52
0x34
cycle count[4]
53
0x35
cycle count[5]
54
0x36
slot count[0]
55
0x37
slot count[1]
56
0x38
slot count[2]
57
0x39
slot count[3]
58
0x3A
slot count[4]
59
0x3B
slot count[5]
60
0x3C
slot count[6]
61
0x3D
slot count[7]
62
0x3E
slot count[8]
63
0x3F
slot count[9]
64
0x40
slot count[10]
65
0x41
slot count[0]
66
0x42
slot count[1]
67
0x43
slot count[2]
68
0x44
slot count[3]
69
0x45
slot count[4]
70
0x46
slot count[5]
71
0x47
slot count[6]
72
0x48
slot count[7]
73
0x49
slot count[8]
74
0x4A
slot count[9]
75
0x4B
slot count[10]
76
0x4C
cycle start
77
0x4D
78
0x4E
79
0x4F
minislot start
80
0x50
arm
Channel
Type
Offset(1)
Reference
-
value
-2
MT start
A
value
0
MT start
B
value
0
MT start
-
pulse
0
MT start
pulse
0
MT start
pulse
0
MT start
A
slot start
B
-
81
0x51 mt
1. Given in PE clock cycles
2. Indicates internal PE event not directly related to FlexRay bus timing
-
value
+1
MT start
-
value
+1
MT start
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
13.5.2.7
Strobe Port Control Register (STBPCR)
Module Base + 0x000A
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
3
1
0
STB3 STB2 STB1 STB0
EN
EN
EN
EN
W
Reset
2
0
0
0
0
Figure 13-7. Strobe Port Control Register (STBPCR)
Write: Anytime
This register is used to enable and disable the strobe port signals. Each disabled port will stay disabled even
when strobe signals are assigned to it.
Table 13-14. STBPCR Field Descriptions
Field
Description
3
STB3EN
Strobe Port 3 Enable — This control bit defines whether the STB3 port is enabled or disabled.
0 Strobe port STB3 disabled
1 Strobe port STB3 enabled
2
STB2EN
Strobe Port 2 Enable — This control bit defines whether the STB2 port is enabled or disabled.
0 Strobe port STB2 disabled
1 Strobe port STB2 enabled
1
STB1EN
Strobe Port 1 Enable — This control bit defines whether the STB1 port is enabled or disabled.
0 Strobe port STB1 disabled
1 Strobe port STB1 enabled
0
STB0EN
Strobe Port 0 Enable — This control bit defines whether the STB0 port is enabled or disabled.
0 Strobe port STB0 disabled
1 Strobe port STB0 enabled
13.5.2.8
Message Buffer Data Size Register (MBDSR)
Module Base + 0x000C
15
R
14
13
12
0
0
10
9
8
0
0
0
0
7
6
5
4
0
MBSEG2DS
W
Reset
11
0
0
0
0
3
2
1
0
0
0
0
MBSEG1DS
0
0
0
0
Figure 13-8. Message Buffer Data Size Register (MBDSR)
Write: POC:config
This register defines the size of the message buffer data section for the two message buffer segments in a
number of two-byte entities.
The FlexRay block provides two independent segments for the individual message buffers. All individual
message buffers within one segment have to have the same size for the message buffer data section. This
size can be different for the two message buffer segments.
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Table 13-15. MBDSR Field Descriptions
Field
Description
14–8
Message Buffer Segment 2 Data Size — The field defines the size of the message buffer data section in twoMBSEG2DS byte entities for message buffers within the second message buffer segment.
6–0
Message Buffer Segment 1 Data Size — The field defines the size of the message buffer data section in twoMBSEG1DS byte entities for message buffers within the first message buffer segment.
13.5.2.9
Message Buffer Segment Size and Utilization Register (MBSSUTR)
Module Base + 0x000E
R
15
14
13
0
0
0
0
0
0
12
10
9
8
LAST_MB_SEG1
W
Reset
11
1
1
1
1
1
7
6
5
0
0
0
0
0
0
4
3
2
1
0
LAST_MB_UTIL
1
1
1
1
1
Figure 13-9. Message Buffer Segment Size and Utilization Register (MBSSUTR)
Write: POC:config
This register is used to define the last individual message buffer that belongs to the first message buffer
segment and the number of the last used individual message buffer.
Table 13-16. MBSSUTR Field Descriptions
Field
Description
12–8
Last Message Buffer In Segment 1 — This field defines the message buffer number of the last individual
LAST_MB_SEG1 message buffer that is assigned to the first message buffer segment. The individual message buffers in the
first segment correspond to the message buffer control registers MBCCSRn, MBCCFRn, MBFIDRn,
MBIDXRn with n <= LAST_MB_SEG1. The first message buffer segment contains LAST_MB_SEG1+1
individual message buffers.
Note: The first message buffer segment contains at least one individual message buffer.
The individual message buffers in the second message buffer segment correspond to the message buffer
control registers MBCCSRn, MBCCFRn, MBFIDRn, MBIDXRn with LAST_MB_SEG1 < n < 32.
Note: If LAST_MB_SEG1 = 31 all individual message buffers belong to the first message buffer segment
and the second message buffer segment is empty.
4–0
LAST_MB_UTIL
Last Message Buffer Utilized — This field defines the message buffer number of last utilized individual
message buffer. The message buffer search engine examines all individual message buffer with a message
buffer number n <= LAST_MB_UTIL.
Note: If LAST_MB_UTIL=LAST_MB_SEG1 all individual message buffers belong to the first message
buffer segment and the second message buffer segment is empty.
13.5.2.10 Protocol Operation Control Register (POCR)
Module Base + 0x0014
R
15
14
13
12
0
0
0
0
W WME
Reset
0
0
0
0
11
10
9
8
EOC_AP
ERC_AP
0
0
0
0
7
6
5
4
BSY
0
0
0
0
0
0
3
2
0
POCCMD
WMC
0
1
0
0
0
0
Figure 13-10. Protocol Operation Control Register (POCR)
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
Write: Normal Mode
The application uses this register to issue
• protocol control commands
• external clock correction commands
Protocol control commands are issued by writing to the POCCMD field. For more information on protocol
control commands, see Section 13.7.4, “Protocol Control Command Execution”.
External clock correction commands are issued by writing to the EOC_AP and ERC_AP fields. For more
information on external clock correction, refer to Section 13.6.11, “External Clock Synchronization”.
Table 13-17. POCR Field Descriptions (Sheet 1 of 2)
Field
15
WME
Description
Write Mode External Correction — This bit controls the write mode of the EOC_AP and ERC_AP fields.
0 Write to EOC_AP and ERC_AP fields on register write.
1 No write to EOC_AP and ERC_AP fields on register write.
11–10
EOC_AP
External Offset Correction Application — This field is used to trigger the application of the external offset
correction value defined in the Protocol Configuration Register 29 (PCR29).
00 do not apply external offset correction value
01 reserved
10 subtract external offset correction value
11 add external offset correction value
9–8
ERC_AP
External Rate Correction Application — This field is used to trigger application of the external rate correction
value defined in the Protocol Configuration Register 21 (PCR21)
00 do not apply external rate correction value
01 reserved
10 subtract external rate correction value
11 add external rate correction value
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
Table 13-17. POCR Field Descriptions (Sheet 2 of 2)
Field
Description
7
BSY
Protocol Control Command Write Busy — This status bit indicates the acceptance of the protocol control
command issued by the application via the POCCMD field. The FlexRay block sets this status bit when the
application has issued a protocol control command via the POCCMD field. The FlexRay block clears this status
bit when protocol control command was accepted by the PE.When the application issues a protocol control
command while the BSY bit is asserted, the FlexRay block ignores this command, sets the protocol command
ignored error flag PCMI_EF in the CHI Error Flag Register (CHIERFR), and will not change the value of the
POCCMD field.
0 Command write idle, command accepted and ready to receive new protocol command.
1 Command write busy, command not yet accepted, not ready to receive new protocol command.
Write Mode Command — This bit controls the write mode of the POCCMD field.
0 Write to POCCMD field on register write.
1 Do not write to POCCMD field on register write.
WMC
3–0
POCCMD
Protocol Control Command — The application writes to this field to issue a protocol control command to the
PE. The FlexRay block sends the protocol command to the PE immediately. While the transfer is running, the
BSY bit is set.
0000 ALLOW_COLDSTART — Immediately activate capability of node to cold start cluster.
0001 ALL_SLOTS — Delayed(1) transition to the all slots transmission mode.
0010 CONFIG — Immediately transition to the POC:config state.
0011 FREEZE — Immediately transition to the POC:halt state.
0100 READY, CONFIG_COMPLETE — Immediately transition to the POC:ready state.
0101 RUN — Immediately transition to the POC:startup start state.
0110 DEFAULT_CONFIG — Immediately transition to the POC:default config state.
0111 HALT — Delayed transition to the POC:halt state
1000 WAKEUP — Immediately initiate the wakeup procedure.
1001 reserved
1010 reserved
1011 reserved
1100 RESET(2) — Immediately reset the Protocol Engine.
1101 reserved
1110 reserved
1111 reserved
1. Delayed means on completion of current communication cycle.
2. Additional to FlexRay Communications System Protocol Specification, Version 2.1 Rev A
After sending the RESET command, it is mandatory to execute the
command sequence described in Section 13.7.5, “Protocol Reset
Command” immediately, to reach the DEFAULT CONFIG state correctly.
13.5.2.11 Global Interrupt Flag and Enable Register (GIFER)
Module Base + 0x0016
15
R
MIF
14
13
W
Reset
0
12
11
10
9
WUP FNEB FNEA
PRIF CHIF
RBIF
IF
IF
IF
0
0
w1c
w1c
w1c
0
0
0
0
8
TBIF
0
7
MIE
0
6
5
PRIE CHIE
0
0
4
3
2
1
WUP FNEB FNEA
RBIE
IE
IE
IE
0
0
0
0
0
TBIE
0
Figure 13-11. Global Interrupt Flag and Enable Register (GIFER)
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
Write: Normal Mode
This register provides the means to control some of the interrupt request lines and provides the
corresponding interrupt flags. The interrupt flags MIF, PRIF, CHIF, RBIF, and TBIF are the outcome of a
binary OR of the related individual interrupt flags and interrupt enables. The generation scheme for these
flags is depicted in Figure 13-144. For more details on interrupt generation, see Section 13.6.19, “Interrupt
Support. These flags are cleared automatically when all of the corresponding interrupt flags or interrupt
enables in the related interrupt flag and enable registers are cleared by the application.
Table 13-18. GIFER Field Descriptions (Sheet 1 of 2)
Field
Description
15
MIF
Module Interrupt Flag — This flag is set if at least one of the other interrupt flags is in this register is asserted
and the related interrupt enable is asserted, too. The FlexRay block generates the module interrupt request if
MIE is asserted.
0 No interrupt flag is asserted or no interrupt enable is set
1 At least one of the other interrupt flags in this register is asserted and the related interrupt bit is asserted, too
13
PRIF
Protocol Interrupt Flag — This flag is set if at least one of the individual protocol interrupt flags in the Protocol
Interrupt Flag Register 0 (PIFR0) and Protocol Interrupt Flag Register 1 (PIFR1) is asserted and the related
interrupt enable flag is asserted, too. The FlexRay block generates the combined protocol interrupt request if the
PRIE flag is asserted.
0 All individual protocol interrupt flags are equal to 0 or no interrupt enable bit is set.
1 At least one of the individual protocol interrupt flags and the related interrupt enable is equal to 1.
13
CHIF
CHI Interrupt Flag — This flag is set if at least one of the individual CHI error flags in the CHI Error Flag Register
(CHIERFR) is asserted and the chi error interrupt enable GIFER.CHIE is asserted. The FlexRay block generates
the combined CHI error interrupt if the CHIE flag is asserted, too.
0 All CHI error flags are equal to 0 or the chi error interrupt is disabled
1 At least one CHI error flag is asserted and chi error interrupt is enabled
12
WUPIF
Wakeup Interrupt Flag — This flag is set when the FlexRay block has received a wakeup symbol on the
FlexRay bus. The application can determine on which channel the wakeup symbol was received by reading the
related wakeup flags WUB and WUA in the Protocol Status Register 3 (PSR3). The FlexRay block generates
the wakeup interrupt request if the WUPIE flag is asserted.
0 No wakeup condition or interrupt disabled
1 Wakeup symbol received on FlexRay bus and interrupt enabled
11
FNEBIF
Receive FIFO channel B Not Empty Interrupt Flag — This flag is set when the receive FIFO for channel B is
not empty. If the application writes 1 to this bit, the FlexRay block updates the FIFO status, increments or wraps
the FIFO read index in the Receive FIFO B Read Index Register (RFBRIR) and clears the interrupt flag if the
FIFO B is now empty. If the FIFO is still not empty, the FlexRay block sets this flag again. The FlexRay block
generates the Receive FIFO B Not empty interrupt if the FNEBIE flag is asserted.
0 Receive FIFO B is empty or interrupt is disabled
1 Receive FIFO B is not empty and interrupt enabled
10
FNEAIF
Receive FIFO channel A Not Empty Interrupt Flag — This flag is set when the receive FIFO for channel A is
not empty. If the application writes 1 to this bit, the FlexRay block updates the FIFO status, increments or wraps
the FIFO read index in the Receive FIFO A Read Index Register (RFARIR) and clears the interrupt flag if the
FIFO A is now empty. If the FIFO is still not empty, the FlexRay block sets this flag again. The FlexRay block
generates the Receive FIFO A Not empty interrupt if the FNEAIE flag is asserted.
0 Receive FIFO A is empty or interrupt is disabled
1 Receive FIFO A is not empty and interrupt enabled
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
Table 13-18. GIFER Field Descriptions (Sheet 2 of 2)
Field
Description
9
RBIF
Receive Message Buffer Interrupt Flag — This flag is set if for at least one of the individual receive message
buffers (MBCCSn.MTD = 0) both the interrupt flag MBIF and the interrupt enable bit MBIE in the corresponding
Message Buffer Configuration, Control, Status Registers (MBCCSRn) are asserted. The application can not
clear this RBIF flag directly. This flag is cleared by the FlexRay block when all of the interrupt flags MBIF of the
individual receive message buffers are cleared by the application or if the application has cleared the interrupt
enables bit MBIE.
0 None of the individual receive message buffers has the MBIF and MBIE flag asserted.
1 At least one individual receive message buffer has the MBIF and MBIE flag asserted.
8
TBIF
Transmit Buffer Interrupt Flag — This flag is set if for at least one of the individual single or double transmit
message buffers (MBCCSn.MTD = 0) both the interrupt flag MBIF and the interrupt enable bit MBIE in the
corresponding Message Buffer Configuration, Control, Status Registers (MBCCSRn) are equal to 1. The
application can not clear this TBIF flag directly. This flag is cleared by the FlexRay block when either all of the
individual interrupt flags MBIF of the individual transmit message buffers are cleared by the application or the
host has cleared the interrupt enables bit MBIE.
0 None of the individual transmit message buffers has the MBIF and MBIE flag asserted.
1 At least one individual transmit message buffer has the MBIF and MBIE flag asserted.
7
MIE
Module Interrupt Enable — This flag controls if the module interrupt line is asserted when the MIF flag is set.
0 Disable interrupt line
1 Enable interrupt line
6
PRIE
Protocol Interrupt Enable — This flag controls if the protocol interrupt line is asserted when the PRIF flag is set.
0 Disable interrupt line
1 Enable interrupt line
5
CHIE
CHI Interrupt Enable — This flag controls if the CHI interrupt line is asserted when the CHIF flag is set.
0 Disable interrupt line
1 Enable interrupt line
4
WUPIE
Wakeup Interrupt Enable — This flag controls if the wakeup interrupt line is asserted when the WUPIF flag is
set.
0 Disable interrupt line
1 Enable interrupt line
3
FNEBIE
Receive FIFO channel B Not Empty Interrupt Enable — This flag controls if the receive FIFO B interrupt line
is asserted when the FNEBIF flag is set.
0 Disable interrupt line
1 Enable interrupt line
2
FNEAIE
Receive FIFO channel A Not Empty Interrupt Enable — This flag controls if the receive FIFO A interrupt line
is asserted when the FNEAIF flag is set.
0 Disable interrupt line
1 Enable interrupt line
1
RBIE
Receive Buffer Interrupt Enable — This flag controls if the receive buffer interrupt line is asserted when the
RBIF flag is set.
0 Disable interrupt line
1 Enable interrupt line
0
TBIE
Transmit Interrupt Enable — This flag controls if the transmit buffer interrupt line is asserted when the TBIF
flag is set.
0 Disable interrupt line
1 Enable interrupt line
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13.5.2.12 Protocol Interrupt Flag Register 0 (PIFR0)
Module Base + 0x0018
14
13
12
9
8
7
R FATL
_IF
15
INTL
_IF
ILCF
_IF
CSA
_IF
MRC MOC
_IF
_IF
CCL
_IF
MXS
_IF
MTX
_IF
W w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
Reset
0
11
10
6
5
4
3
2
1
0
TI2
_IF
TI1
_IF
CYS
_IF
w1c
w1c
w1c
w1c
0
0
0
0
LTXB LTXA TBVB TBVA
_IF
_IF
_IF
_IF
Figure 13-12. Protocol Interrupt Flag Register 0 (PIFR0)
Write: Normal Mode
The register holds one set of the protocol-related individual interrupt flags.
Table 13-19. PIFR0 Field Descriptions (Sheet 1 of 2)
Field
Description
15
FATL_IF
Fatal Protocol Error Interrupt Flag — This flag is set when the protocol engine has detected a fatal protocol
error. In this case, the protocol engine goes into the POC:halt state immediately. The fatal protocol errors are:
1) pLatestTx violation, as described in the MAC process of the FlexRay protocol
2) transmission across slot boundary violation, as described in the FSP process of the FlexRay protocol
0 No such event.
1 Fatal protocol error detected.
14
INTL_IF
Internal Protocol Error Interrupt Flag — This flag is set when the protocol engine has detected an internal
protocol error. In this case, the protocol engine goes into the POC:halt state immediately. An internal protocol
error occurs when the protocol engine has not finished a calculation and a new calculation is requested. This
can be caused by a hardware error.
0 No such event.
1 Internal protocol error detected.
13
ILCF_IF
Illegal Protocol Configuration Interrupt Flag — This flag is set when the protocol engine has detected an
illegal protocol configuration parameter setting. In this case, the protocol engine goes into the POC:halt state
immediately.
The protocol engine checks the listen_timeout value programmed into the Protocol Configuration Register 14
(PCR14) and Protocol Configuration Register 15 (PCR15) when the CONFIG_COMPLETE command was sent
by the application via the Protocol Operation Control Register (POCR). If the value of listen_timeout is equal to
zero, the protocol configuration setting is considered as illegal.
0 No such event.
1 Illegal protocol configuration detected.
12
CSA_IF
Cold Start Abort Interrupt Flag — This flag is set when the configured number of allowed cold start attempts
is reached and none of these attempts was successful. The number of allowed cold start attempts is configured
by the coldstart_attempts field in the Protocol Configuration Register 3 (PCR3).
0 No such event.
1 Cold start aborted and no more coldstart attempts allowed.
11
MRC_IF
Missing Rate Correction Interrupt Flag — This flag is set when an insufficient number of measurements is
available for rate correction at the end of the communication cycle.
0 No such event
1 Insufficient number of measurements for rate correction detected
10
MOC_IF
Missing Offset Correction Interrupt Flag — This flag is set when an insufficient number of measurements is
available for offset correction. This is related to the MISSING_TERM event in the CSP process for offset
correction in the FlexRay protocol.
0 No such event.
1 Insufficient number of measurements for offset correction detected.
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
Table 13-19. PIFR0 Field Descriptions (Sheet 2 of 2)
Field
Description
9
CCL_IF
Clock Correction Limit Reached Interrupt Flag — This flag is set when the internal calculated offset or rate
calculation values have reached or exceeded its configured thresholds as given by the offset_coorection_out
field in the Protocol Configuration Register 9 (PCR9) and the rate_correction_out field in the Protocol
Configuration Register 14 (PCR14).
0 No such event.
1 Offset or rate correction limit reached.
8
MXS_IF
Max Sync Frames Detected Interrupt Flag — This flag is set when the number of synchronization frames
detected in the current communication cycle exceeds the value of the node_sync_max field in the Protocol
Configuration Register 30 (PCR30).
0 No such event.
1 More than node_sync_max sync frames detected.
Note: Only synchronization frames that have passed the synchronization frame acceptance and rejection filters
are taken into account.
7
MTX_IF
Media Access Test Symbol Received Interrupt Flag — This flag is set when the MTS symbol was received
on channel A or channel B.
0 No such event.
1 MTS symbol received.
6
LTXB_IF
pLatestTx Violation on Channel B Interrupt Flag — This flag is set when the frame transmission on channel B
in the dynamic segment exceeds the dynamic segment boundary. This is related to the pLatestTx violation, as
described in the MAC process of the FlexRay protocol.
0 No such event.
1 pLatestTx violation occurred on channel B.
5
LTXA_IF
pLatestTx Violation on Channel A Interrupt Flag — This flag is set when the frame transmission on channel A
in the dynamic segment exceeds the dynamic segment boundary. This is related to the pLatestTx violation as
described in the MAC process of the FlexRay protocol.
0 No such event.
1 pLatestTx violation occurred on channel A.
4
TBVB_IF
Transmission across boundary on channel B Interrupt Flag — This flag is set when the frame transmission
on channel B crosses the slot boundary. This is related to the transmission across slot boundary violation as
described in the FSP process of the FlexRay protocol.
0 No such event.
1 Transmission across boundary violation occurred on channel B.
3
TBVA_IF
Transmission across boundary on channel A Interrupt Flag — This flag is set when the frame transmission
on channel A crosses the slot boundary. This is related to the transmission across slot boundary violation as
described in the FSP process of the FlexRay protocol.
0 No such event.
1 Transmission across boundary violation occurred on channel A.
2
TI2_IF
Timer 2 Expired Interrupt Flag — This flag is set whenever timer 2 expires.
0 No such event.
1 Timer 2 has reached its time limit.
1
TI1_IF
Timer 1 Expired Interrupt Flag — This flag is set whenever timer 1 expires.
0 No such event
1 Timer 1 has reached its time limit
0
CYS_IF
Cycle Start Interrupt Flag — This flag is set when a communication cycle starts.
0 No such event
1 Communication cycle started.
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13.5.2.13 Protocol Interrupt Flag Register 1 (PIFR1)
Module Base + 0x001A
15
14
13
R EMC
_IF
IPC
_IF
W w1c
w1c
w1c
0
0
Reset
0
12
11
10
9
8
SSI3
_IF
SSI2
_IF
SSI1
_IF
SSI0
_IF
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
PECF PSC
_IF
_IF
7
6
5
4
3
2
1
0
0
0
EVT
_IF
ODT
_IF
0
0
0
0
w1c
w1c
0
0
0
0
0
0
0
0
Figure 13-13. Protocol Interrupt Flag Register 1 (PIFR1)
Write: Normal Mode
The register holds one set of the protocol-related individual interrupt flags.
Table 13-20. PIFR1 Field Descriptions
Field
Description
15
EMC_IF
Error Mode Changed Interrupt Flag — This flag is set when the value of the ERRMODE bit field in the Protocol
Status Register 0 (PSR0) is changed by the FlexRay block.
0 No such event.
1 ERRMODE field changed.
14
IPC_IF
Illegal Protocol Control Command Interrupt Flag — This flag is set when the PE tries to execute a protocol
control command, which was issued via the POCCMD field of the Protocol Operation Control Register (POCR),
and detects that this protocol control command is not allowed in the current protocol state. In this case the
command is not executed. For more details, see Section 13.7.4, “Protocol Control Command Execution”.
0 No such event.
1 Illegal protocol control command detected.
13
PECF_IF
Protocol Engine Communication Failure Interrupt Flag — This flag is set if the FlexRay block has detected
a communication failure between the protocol engine and the controller host interface
0 No such event.
1 Protocol Engine Communication Failure detected.
12
PSC_IF
Protocol State Changed Interrupt Flag — This flag is set when the protocol state in the PROTSTATE field in
the Protocol Status Register 0 (PSR0) has changed.
0 No such event.
1 Protocol state changed.
11–8
SSI[3:0]_IF
Slot Status Counter Incremented Interrupt Flag — Each of these flags is set when the SLOTSTATUSCNT
field in the corresponding Slot Status Counter Registers (SSCR0–SSCR3) is incremented.
0 No such event.
1 The corresponding slot status counter has incremented.
5
EVT_IF
Even Cycle Table Written Interrupt Flag — This flag is set if the FlexRay block has written the sync frame
measurement / ID tables into the FlexRay Memory for the even cycle.
0 No such event.
1 Sync frame measurement table written
4
ODT_IF
Odd Cycle Table Written Interrupt Flag — This flag is set if the FlexRay block has written the sync frame
measurement / ID tables into the FlexRay Memory for the odd cycle.
0 No such event.
1 Sync frame measurement table written
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
13.5.2.14 Protocol Interrupt Enable Register 0 (PIER0)
Module Base + 0x001C
15
R FATL
W _IE
Reset
0
14
13
12
INTL
_IE
ILCF
_IE
CSA
_IE
0
0
0
11
10
MRC MOC
_IE
_IE
0
0
9
8
7
CCL
_IE
MXS
_IE
MTX
_IE
0
0
0
6
5
4
3
LTXB LTXA TBVB TBVA
_IE
_IE
_IE
_IE
0
0
0
0
2
1
0
TI2
_IE
TI1
_IE
CYS
_IE
0
0
0
Figure 13-14. Protocol Interrupt Enable Register 0 (PIER0)
Write: Anytime
This register defines whether or not the individual interrupt flags defined in the Protocol Interrupt Flag
Register 0 (PIFR0) can generate a protocol interrupt request.
Table 13-21. PIER0 Field Descriptions
Field
Description
15
FATL_IE
Fatal Protocol Error Interrupt Enable — This bit controls FATL_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
14
INTL_IE
Internal Protocol Error Interrupt Enable — This bit controls INTL_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
13
ILCF_IE
Illegal Protocol Configuration Interrupt Enable — This bit controls ILCF_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
12
CSA_IE
Cold Start Abort Interrupt Enable — This bit controls CSA_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
11
MRC_IE
Missing Rate Correction Interrupt Enable — This bit controls MRC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
10
MOC_IE
Missing Offset Correction Interrupt Enable — This bit controls MOC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
9
CCL_IE
Clock Correction Limit Reached Interrupt Enable — This bit controls CCL_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
8
MXS_IE
Max Sync Frames Detected Interrupt Enable — This bit controls MXS_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
7
MTX_IE
Media Access Test Symbol Received Interrupt Enable — This bit controls MTX_IF interrupt request
generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
6
LTXB_IE
pLatestTx Violation on Channel B Interrupt Enable — This bit controls LTXB_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
5
LTXA_IE
pLatestTx Violation on Channel A Interrupt Enable — This bit controls LTXA_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
Table 13-21. PIER0 Field Descriptions (continued)
Field
Description
4
TBVB_IE
Transmission across boundary on channel B Interrupt Enable — This bit controls TBVB_IF interrupt
request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
3
TBVA_IE
Transmission across boundary on channel A Interrupt Enable — This bit controls TBVA_IF interrupt request
generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
2
TI2_IE
Timer 2 Expired Interrupt Enable — This bit controls TI1_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
1
TI1_IE
Timer 1 Expired Interrupt Enable — This bit controls TI1_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
0
CYS_IE
Cycle Start Interrupt Enable — This bit controls CYC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
13.5.2.15 Protocol Interrupt Enable Register 1 (PIER1)
Module Base + 0x001E
15
R EMC
W _IE
Reset
0
14
IPC
_IE
0
13
12
PECF PSC
_IE
_IE
0
0
11
10
9
8
7
6
5
4
3
2
1
0
SSI3
_IE
SSI2
_IE
SSI1
_IE
SSI0
_IE
0
0
EVT
_IE
ODT
_IE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-15. Protocol Interrupt Enable Register 1 (PIER1)
Write: Anytime
This register defines whether or not the individual interrupt flags defined in Protocol Interrupt Flag
Register 1 (PIFR1) can generate a protocol interrupt request.
Table 13-22. PIER1 Field Descriptions
Field
Description
15
EMC_IE
Error Mode Changed Interrupt Enable — This bit controls EMC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
14
IPC_IE
Illegal Protocol Control Command Interrupt Enable — This bit controls IPC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
13
PECF_IE
12
PSC_IE
Protocol Engine Communication Failure Interrupt Enable — This bit controls PECF_IF interrupt request
generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Protocol State Changed Interrupt Enable — This bit controls PSC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
Table 13-22. PIER1 Field Descriptions (continued)
Field
Description
11–8
SSI[3:0]_IE
Slot Status Counter Incremented Interrupt Enable — This bit controls SSI[3:0]_IF interrupt request
generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
5
EVT_IE
Even Cycle Table Written Interrupt Enable — This bit controls EVT_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
4
ODT_IE
Odd Cycle Table Written Interrupt Enable — This bit controls ODT_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
13.5.2.16 CHI Error Flag Register (CHIERFR)
Module Base + 0x0020
9
8
5
4
3
2
1
0
R FRLB FRLA PCMI FOVB FOVA MBS
_EF _EF _EF _EF _EF _EF
15
MBU
_EF
LCK
_EF
DBL SBCF
_EF _EF
FID
_EF
DPL
_EF
SPL
_EF
NML
_EF
NMF
_EF
ILSA
_EF
W w1c
Reset
0
14
13
12
11
10
7
6
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-16. CHI Error Flag Register (CHIERFR)
Write: Normal Mode
This register holds the CHI related error flags. The interrupt generation for each of these error flags is
controlled by the CHI interrupt enable bit CHIE in the Global Interrupt Flag and Enable Register (GIFER).
Table 13-23. CHIERFR Field Descriptions (Sheet 1 of 3)
Field
Description
15
FRLB_EF
Frame Lost Channel B Error Flag — This flag is set if a complete frame was received on channel B but could
not be stored in the selected individual message buffer because this message buffer is currently locked by the
application. In this case, the frame and the related slot status information are lost.
0 No such event
1 Frame lost on channel B detected
14
FRLA_EF
Frame Lost Channel A Error Flag — This flag is set if a complete frame was received on channel A but could
not be stored in the selected individual message buffer because this message buffer is currently locked by the
application. In this case, the frame and the related slot status information are lost.
0 No such error
1 Frame lost on channel A detected
13
PCMI_EF
Protocol Command Ignored Error Flag — This flag is set if the application has issued a POC command by
writing to the POCCMD field in the Protocol Operation Control Register (POCR) while the BSY flag is equal to
1. In this case the command is ignored by the FlexRay block and is lost.
0 No such error
1 POC command ignored
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Table 13-23. CHIERFR Field Descriptions (Sheet 2 of 3)
Field
Description
12
FOVB_EF
Receive FIFO Overrun Channel B Error Flag — This flag is set when an overrun of the Receive FIFO for
channel B occurred. This error occurs if a semantically valid frame was received on channel B and matches the
all criteria to be appended to the FIFO for channel B but the FIFO is full. In this case, the received frame and its
related slot status information is lost.
0 No such error
1 Receive FIFO overrun on channel B has been detected
11
FOVA_EF
Receive FIFO Overrun Channel A Error Flag — This flag is set when an overrun of the Receive FIFO for
channel A occurred. This error occurs if a semantically valid frame was received on channel A and matches the
all criteria to be appended to the FIFO for channel A but the FIFO is full. In this case, the received frame and its
related slot status information is lost.
0 No such error
1 Receive FIFO overrun on channel B has been detected
10
MSB_EF
Message Buffer Search Error Flag — This flag is set if the message buffer search engine is still running while
the next search cycle must be started due to the FlexRay protocol timing. In this case, not all message buffers
are considered while searching.
0 No such event
1 Search engine active while search start appears
9
MBU_EF
Message Buffer Utilization Error Flag — This flag is asserted if the application writes to a message buffer
control field that is beyond the number of utilized message buffers programmed in the Message Buffer
Segment Size and Utilization Register (MBSSUTR).
If the application writes to a MBCCSRn register with n > LAST_MB_UTIL, the FlexRay block ignores the write
attempt and asserts the message buffer utilization error flag MBU_EF in the CHI Error Flag Register (CHIERFR).
0 No such event
1 Non-utilized message buffer enabled
8
LCK_EF
Lock Error Flag — This flag is set if the application tries to lock a message buffer that is already locked by the
FlexRay block due to internal operations. In that case, the FlexRay block does not grant the lock to the
application. The application must issue the lock request again.
0 No such error
1 Lock error detected
7
DBL_EF
Double Transmit Message Buffer Lock Error Flag — This flag is set if the application tries to lock the transmit
side of a double transmit message buffer. In this case, the FlexRay block does not grant the lock to the transmit
side of a double transmit message buffer.
0 No such event
1 Double transmit buffer lock error occurred
6
SBCF_EF
System Bus Communication Failure Error Flag — This flag is set if the FlexRay block was not able to transmit
or receive data via the system bus in time. In the case of writing, data is lost; in the case of reading, the
transmission onto the FlexRay bus is stopped for the current slot and resumed in the next slot.
0 No such event
1 System bus communication failure occurred
5
FID_EF
Frame ID Error Flag — This flag is set if the frame ID stored in the message buffer header area differs from the
frame ID stored in the message buffer control register.
0 No such error occurred
1 Frame ID error occurred
4
DPL_EF
Dynamic Payload Length Error Flag — This flag is set if the payload length written into the message buffer
header field of a single or double transmit message buffer assigned to the dynamic segment is greater than the
maximum payload length for the dynamic segment as it is configured in the corresponding protocol configuration
register field max_payload_length_dynamic in the Protocol Configuration Register 24 (PCR24).
0 No such error occurred
1 Dynamic payload length error occurred
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Table 13-23. CHIERFR Field Descriptions (Sheet 3 of 3)
Field
Description
3
SPL_EF
Static Payload Length Error Flag — This flag is set if the payload length written into the message buffer header
field of a single or double transmit message buffer assigned to the static segment is different from the payload
length for the static segment as it is configured in the corresponding protocol configuration register field
payload_length_static in the Protocol Configuration Register 19 (PCR19).
0 No such error occurred
1 Static payload length error occurred
2
NML_EF
Network Management Length Error Flag — This flag is set if the payload length written into the header
structure of a receive message buffer assigned to the static segment is less than the configured length of the
Network Management Vector as configured in the Network Management Vector Length Register (NMVLR). In
this case the received part of the Network Management Vector will be used to update the Network Management
Vector.
0 No such error occurred
1 Network management length error occurred
1
NMF_EF
Network Management Frame Error Flag — This flag is set if a received message in the static segment with a
Preamble Indicator flag PP asserted has its Null Frame indicator flag NF asserted as well. In this case, the
Global Network Management Registers (see Network Management Vector Registers (NMVR0–NMVR5)) are
not updated.
0 No such error occurred
1 Network management frame error occurred
0
ILSA_EF
Illegal System Memory Access Error Flag — This flag is set if the external system memory subsystem has
detected and indicated an illegal system memory access from the FlexRay block. The exact meaning of an illegal
system memory access is defined by the current implementation of the memory subsystem.
0 No such event.
1 Illegal system memory access occurred.
13.5.2.17 Message Buffer Interrupt Vector Register (MBIVEC)
Module Base + 0x0022
15
14
13
0
0
0
0
0
0
R
12
11
10
9
8
TBIVEC
7
6
5
0
0
0
0
0
0
4
3
2
1
0
0
0
RBIVEC
W
Reset
0
0
0
0
0
0
0
0
Figure 13-17. Message Buffer Interrupt Vector Register (MBIVEC)
This register indicates the lowest numbered receive message buffer and the lowest numbered transmit
message buffer that have their interrupt status flag MBIF and interrupt enable MBIE bits asserted. This
means that message buffers with lower message buffer numbers have higher priority.
Table 13-24. MBIVEC Field Descriptions
Field
Description
12–8
TBIVEC
Transmit Buffer Interrupt Vector — This field provides the number of the lowest numbered enabled transmit
message buffer that has its interrupt status flag MBIF and its interrupt enable bit MBIE set. If there is no transmit
message buffer with the interrupt status flag MBIF and the interrupt enable MBIE bits asserted, the value in this
field is set to 0.
4–0
RBIVEC
Receive Buffer Interrupt Vector — This field provides the message buffer number of the lowest numbered
receive message buffer which has its interrupt flag MBIF and its interrupt enable bit MBIE asserted. If there is
no receive message buffer with the interrupt status flag MBIF and the interrupt enable MBIE bits asserted, the
value in this field is set to 0.
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13.5.2.18 Channel A Status Error Counter Register (CASERCR)
Module Base + 0x0024
15
14
Additional Reset: RUN Command
13
12
11
10
9
R
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
STATUS_ERR_CNT
W
Reset
0
0
0
0
0
0
0
0
0
Figure 13-18. Channel A Status Error Counter Register (CASERCR)
This register provides the channel status error counter for channel A. The protocol engine generates a slot
status vector for each static slot, each dynamic slot, the symbol window, and the NIT. The slot status vector
contains the four protocol related error indicator bits vSS!SyntaxError, vSS!ContentError, vSS!BViolation,
and vSS!TxConflict. The FlexRay block increments the status error counter by 1 if, for a slot or segment,
at least one error indicator bit is set to 1. The counter wraps around after it has reached the maximum value.
For more information on slot status monitoring, see Section 13.6.18, “Slot Status Monitoring”.
Table 13-25. CASERCR Field Descriptions
Field
Description
15–0
Channel Status Error Counter — This field provides the current value channel status error counter. The
STATUS_ERR_CNT counter value is updated within the first macrotick of the following slot or segment.
13.5.2.19 Channel B Status Error Counter Register (CBSERCR)
Module Base + 0x0026
15
14
Additional Reset: RUN Command
13
12
11
10
9
R
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
STATUS_ERR_CNT
W
Reset
0
0
0
0
0
0
0
0
0
Figure 13-19. Channel B Status Error Counter Register (CBSERCR)
This register provides the channel status error counter for channel B. The protocol engine generates a slot
status vector for each static slot, each dynamic slot, the symbol window, and the NIT. The slot status vector
contains the four protocol related error indicator bits vSS!SyntaxError, vSS!ContentError, vSS!BViolation,
and vSS!TxConflict. The FlexRay block increments the status error counter by 1 if, for a slot or segment,
at least one error indicator bit is set to 1. The counter wraps around after it has reached the maximum value.
For more information on slot status monitoring see Section 13.6.18, “Slot Status Monitoring”.
Table 13-26. CBSERCR Field Descriptions
Field
Description
15–0
Channel Status Error Counter — This field provides the current channel status error count. The counter
STATUS_ERR_CNT value is updated within the first macrotick of the following slot or segment.
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13.5.2.20 Protocol Status Register 0 (PSR0)
Module Base + 0x0028
15
14
R ERRMODE
13
12
11
SLOTMODE
10
0
9
8
7
PROTSTATE
6
5
4
STARTUPSTATE
3
2
0
1
0
WAKEUPSTATUS
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-20. Protocol Status Register 0 (PSR0)
This register provides information about the current protocol status.
Table 13-27. PSR0 Field Descriptions (Sheet 1 of 2)
Field
Description
15–14
ERRMODE
Error Mode — protocol related variable: vPOC!ErrorMode. This field indicates the error mode of the protocol.
00 ACTIVE
01 PASSIVE
10 COMM_HALT
11 reserved
13–12
Slot Mode — protocol related variable: vPOC!SlotMode. This field indicates the slot mode of the protocol.
SLOTMODE 00 SINGLE
01 ALL_PENDING
10 ALL
11 reserved
10–8
Protocol State — protocol related variable: vPOC!State. This field indicates the state of the protocol.
PROTSTATE 000 POC:default config
001 POC:config
010 POC:wakeup
011 POC:ready
100 POC:normal passive
101 POC:normal active
110 POC:halt
111 POC:startup
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Table 13-27. PSR0 Field Descriptions (Sheet 2 of 2)
Field
Description
7–4
STARTUP
STATE
Startup State — protocol related variable: vPOC!StartupState. This field indicates the current sub-state of the
startup procedure.
0000 reserved
0001 reserved
0010 POC:coldstart collision resolution
0011 POC:coldstart listen
0100 POC:integration consistency check
0101 POC:integrationi listen
0110 reserved
0111 POC:initialize schedule
1000 reserved
1001 reserved
1010 POC:coldstart consistency check
1011 reserved
1100 reserved
1101 POC:integration coldstart check
1110 POC:coldstart gap
1111 POC:coldstart join
2–0
WAKEUP
STATUS
Wakeup Status — protocol related variable: vPOC!WakeupStatus. This field provides the outcome of the
execution of the wakeup mechanism.
000 UNDEFINED
001 RECEIVED_HEADER
010 RECEIVED_WUP
011 COLLISION_HEADER
100 COLLISION_WUP
101 COLLISION_UNKNOWN
110 TRANSMITTED
111 reserved
13.5.2.21 Protocol Status Register 1 (PSR1)
Module Base + 0x002A
15
14
R CSAA CSP
Additional Reset: CSAA, CSP, CPN: RUN Command
13
12
11
0
10
9
8
REMCSAT
7
6
5
CPN
HHR
FRZ
0
0
0
4
3
2
1
0
0
0
APTAC
W w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
Figure 13-21. Protocol Status Register 1 (PSR1)
Write: Normal Mode
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Table 13-28. PSR1 Field Descriptions
Field
Description
15
CSAA
14
CSP
Cold Start Attempt Aborted Flag — protocol related event: ‘set coldstart abort indicator in CHI’
This flag is set when the FlexRay block has aborted a cold start attempt.
0 No such event
1 Cold start attempt aborted
Leading Cold Start Path — This status bit is set when the FlexRay block has reached the POC:normal active
state via the leading cold start path. This indicates that this node has started the network
0 No such event
1 POC:normal active reached from POC:startup state via leading cold start path
12–8
REMCSAT
Remaining Coldstart Attempts — protocol related variable: vRemainingColdstartAttempts
This field provides the number of remaining cold start attempts that the FlexRay block will execute.
7
CPN
Leading Cold Start Path Noise — protocol related variable: vPOC!ColdstartNoise
This status bit is set if the FlexRay block has reached the POC:normal active state via the leading cold start path
under noise conditions. This indicates there was some activity on the FlexRay bus while the FlexRay block was
starting up the cluster.
0 No such event
1 POC:normal active state was reached from POC:startup state via noisy leading cold start path
6
HHR
Host Halt Request Pending — protocol related variable: vPOC!CHIHaltRequest
This status bit is set when FlexRay block receives the HALT command from the application via the Protocol
Operation Control Register (POCR). The FlexRay block clears this status bit after a hard reset condition or when
the protocol is in the POC:default config state.
0 No such event
1 HALT command received
5
FRZ
Freeze Occurred — protocol related variable: vPOC!Freeze
This status bit is set when the FlexRay block has reached the POC:halt state due to the host FREEZE command
or due to an internal error condition requiring immediate halt. The FlexRay block clears this status bit after a hard
reset condition or when the protocol is in the POC:default config state.
0 No such event
1 Immediate halt due to FREEZE or internal error condition
4–0
APTAC
Allow Passive to Active Counter — protocol related variable: vPOC!vAllowPassivetoActive
This field provides the number of consecutive even/odd communication cycle pairs that have passed with valid
rate and offset correction terms, but the protocol is still in the POC:normal passive state due to an application
configured delay to enter POC:normal active state. This delay is defined by the allow_passive_to_active field in
the Protocol Configuration Register 12 (PCR12).
13.5.2.22 Protocol Status Register 2 (PSR2)
Module Base + 0x002C
15
14
Additional Reset: RUN Command
13
12
11
10
9
8
7
6
5
4
3
2
R NBVB NSEB STCB SBVB SSEB MTB NBVA NSEA STCA SBVA SSEA MTA
1
0
CLKCORRFAILCNT
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-22. Protocol Status Register 2 (PSR2)
This register provides a snapshot of status information about the Network Idle Time NIT, the Symbol
Window and the clock synchronization. The NIT related status bits NBVB, NSEB, NBVA, and NSEA are
updated by the FlexRay block after the end of the NIT and before the end of the first slot of the next
communication cycle. The Symbol Window related status bits STCB, SBVB, SSEB, MTB, STCA, SBVA,
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SSEB, and MTA are updated by the FlexRay block after the end of the symbol window and before the end
of the current communication cycle. If no symbol window is configured, the symbol window related status
bits remain in their reset state. The clock synchronization related CLKCORRFAILCNT is updated by the
FlexRay block after the end of the static segment and before the end of the current communication cycle.
Table 13-29. PSR2 Field Descriptions (Sheet 1 of 2)
Field
Description
15
NBVB
NIT Boundary Violation on Channel B — protocol related variable: vSS!BViolation for NIT on channel B
This status bit is set when there was some media activity on the FlexRay bus channel B at the end of the NIT.
0 No such event
1 Media activity at boundaries detected
14
NSEB
NIT Syntax Error on Channel B — protocol related variable: vSS!SyntaxError for NIT on channel B
This status bit is set when a syntax error was detected during NIT on channel B.
0 No such event
1 Syntax error detected
13
STCB
Symbol Window Transmit Conflict on Channel B — protocol related variable: vSS!TxConflict for symbol
window on channel B
This status bit is set if there was a transmission conflict during the symbol window on channel B.
0 No such event
1 Transmission conflict detected
12
SBVB
Symbol Window Boundary Violation on Channel B — protocol related variable: vSS!BViolation for symbol
window on channel B
This status bit is set if there was some media activity on the FlexRay bus channel B at the start or at the end of
the symbol window.
0 No such event
1 Media activity at boundaries detected
11
SSEB
Symbol Window Syntax Error on Channel B — protocol related variable: vSS!SyntaxError for symbol window
on channel B
This status bit is set when a syntax error was detected during the symbol window on channel B.
0 No such event
1 Syntax error detected
10
MTB
Media Access Test Symbol MTS Received on Channel B — protocol related variable: vSS!ValidMTS for
Symbol Window on channel B
This status bit is set if the Media Access Test Symbol MTS was received in the symbol window on channel B.
0 No such event
1 MTS symbol received
9
NBVA
NIT Boundary Violation on Channel A — protocol related variable: vSS!BViolation for NIT on channel A
This status bit is set when there was some media activity on the FlexRay bus channel A at the end of the NIT.
0 No such event
1 Media activity at boundaries detected
8
NSEA
NIT Syntax Error on Channel A — protocol related variable: vSS!SyntaxError for NIT on channel A
This status bit is set when a syntax error was detected during NIT on channel A.
0 No such event
1 Syntax error detected
7
STCA
Symbol Window Transmit Conflict on Channel A — protocol related variable: vSS!TxConflict for symbol
window on channel A
This status bit is set if there was a transmission conflicts during the symbol window on channel A.
0 No such event
1 Transmission conflict detected
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Table 13-29. PSR2 Field Descriptions (Sheet 2 of 2)
Field
Description
6
SBVA
Symbol Window Boundary Violation on Channel A — protocol related variable: vSS!BViolation for symbol
window on channel A
This status bit is set if there was some media activity on the FlexRay bus channel A at the start or at the end of
the symbol window.
0 No such event
1 Media activity at boundaries detected
5
SSEA
Symbol Window Syntax Error on Channel A — protocol related variable: vSS!SyntaxError for symbol window
on channel A
This status bit is set when a syntax error was detected during the symbol window on channel A.
0 No such event
1 Syntax error detected
4
MTA
Media Access Test Symbol MTS Received on Channel A — protocol related variable: vSS!ValidMTS for
symbol window on channel A
This status bit is set if the Media Access Test Symbol MTS was received in the symbol window on channel A.
1 MTS symbol received
0 No such event
3–0
CLKCORRFAILCNT
Clock Correction Failed Counter — protocol related variable: vClockCorrectionFailed
This field provides the number of consecutive even/odd communication cycle pairs that have passed without
clock synchronization having performed an offset or a rate correction due to lack of synchronization frames. It is
not incremented when it has reached the configured value of either max_without_clock_correction_fatal or
max_without_clock_correction_passive as defined in the Protocol Configuration Register 8 (PCR8). The
FlexRay block resets this counter on a hard reset condition, when the protocol enters the POC:normal active
state, or when both the rate and offset correction terms have been calculated successfully.
13.5.2.23 Protocol Status Register 3 (PSR3)
Module Base + 0x002E
R
15
14
0
0
W
Reset
0
0
Additional Reset: RUN Command
13
12
11
10
9
8
WUB ABVB AACB ACEB ASEB AVFB
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
7
6
0
0
0
0
5
4
3
2
1
0
WUA ABVA AACA ACEA ASEA AVFA
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
Figure 13-23. Protocol Status Register 3 (PSR3)
Write: Normal Mode
This register provides aggregated channel status information as an accrued status of channel activity for
all communication slots, regardless of whether they are assigned for transmission or subscribed for
reception. It provides accrued information for the symbol window, the NIT, and the wakeup status.
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Table 13-30. PSR3 Field Descriptions (Sheet 1 of 2)
Field
Description
13
WUB
Wakeup Symbol Received on Channel B — This flag is set when a wakeup symbol was received on
channel B.
0 No wakeup symbol received
1 Wakeup symbol received
12
ABVB
Aggregated Boundary Violation on Channel B — This flag is set when a boundary violation has been
detected on channel B. Boundary violations are detected in the communication slots, the symbol window, and
the NIT.
0 No boundary violation detected
1 Boundary violation detected
11
AACB
Aggregated Additional Communication on Channel B — This flag is set when at least one valid frame was
received on channel B in a slot that also contained an additional communication with either syntax error, content
error, or boundary violations.
0 No additional communication detected
1 Additional communication detected
10
ACEB
Aggregated Content Error on Channel B — This flag is set when a content error has been detected on
channel B. Content errors are detected in the communication slots, the symbol window, and the NIT.
0 No content error detected
1 Content error detected
9
ASEB
Aggregated Syntax Error on Channel B — This flag is set when a syntax error has been detected on
channel B. Syntax errors are detected in the communication slots, the symbol window and the NIT.
0 No syntax error detected
1 Syntax errors detected
8
AVFB
Aggregated Valid Frame on Channel B — This flag is set when a syntactically correct valid frame has been
received in any static or dynamic slot through channel B.
1 At least one syntactically valid frame received
0 No syntactically valid frames received
5
WUA
Wakeup Symbol Received on Channel A — This flag is set when a wakeup symbol was received on
channel A.
0 No wakeup symbol received
1 Wakeup symbol received
4
ABVA
Aggregated Boundary Violation on Channel A — This flag is set when a boundary violation has been
detected on channel A. Boundary violations are detected in the communication slots, the symbol window, and
the NIT.
0 No boundary violation detected
1 Boundary violation detected
3
AACA
Aggregated Additional Communication on Channel A — This flag is set when a valid frame was received in
a slot on channel A that also contained an additional communication with either syntax error, content error, or
boundary violations.
0 No additional communication detected
1 Additional communication detected
2
ACEA
Aggregated Content Error on Channel A — This flag is set when a content error has been detected on
channel A. Content errors are detected in the communication slots, the symbol window, and the NIT.
0 No content error detected
1 Content error detected
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Table 13-30. PSR3 Field Descriptions (Sheet 2 of 2)
Field
Description
1
ASEA
Aggregated Syntax Error on Channel A — This flag is set when a syntax error has been detected on channel
A. Syntax errors are detected in the communication slots, the symbol window, and the NIT.
0 No syntax error detected
1 Syntax errors detected
0
AVFA
Aggregated Valid Frame on Channel A — This flag is set when a syntactically correct valid frame has been
received in any static or dynamic slot through channel A.
0 No syntactically valid frames received
1 At least one syntactically valid frame received
13.5.2.24 Macrotick Counter Register (MTCTR)
Module Base + 0x0030
15
14
0
0
0
0
R
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
3
2
1
0
0
0
MTCT
W
Reset
0
0
0
0
0
0
0
Figure 13-24. Macrotick Counter Register (MTCTR)
This register provides the macrotick count of the current communication cycle.
Table 13-31. MTCTR Field Descriptions
Field
Description
13–0
MTCT
Macrotick Counter — protocol related variable: vMacrotick
This field provides the macrotick count of the current communication cycle.
13.5.2.25 Cycle Counter Register (CYCTR)
Module Base + 0x0032
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
5
4
CYCCNT
W
Reset
0
0
0
0
Figure 13-25. Cycle Counter Register (CYCTR)
This register provides the number of the current communication cycle.
Table 13-32. CYCTR Field Descriptions
Field
Description
5–0
CYCCNT
Cycle Counter — protocol related variable: vCycleCounter
This field provides the number of the current communication cycle. If the counter reaches the maximum value
of 63, the counter wraps and starts from zero again.
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13.5.2.26 Slot Counter Channel A Register (SLTCTAR)
Module Base + 0x0034
15
14
13
12
11
0
0
0
0
0
0
0
0
0
0
R
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
SLOTCNTA
W
Reset
0
0
0
0
0
0
Figure 13-26. Slot Counter Channel A Register (SLTCTAR)
This register provides the number of the current slot in the current communication cycle for channel A.
Table 13-33. SLTCTAR Field Descriptions
Field
Description
10–0
SLOTCNTA
Slot Counter Value for Channel A — protocol related variable: vSlotCounter for channel A
This field provides the number of the current slot in the current communication cycle.
13.5.2.27 Slot Counter Channel B Register (SLTCTBR)
Module Base + 0x0036
15
14
13
12
11
0
0
0
0
0
0
0
0
0
0
R
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
SLOTCNTB
W
Reset
0
0
0
0
0
0
Figure 13-27. Slot Counter Channel B Register (SLTCTBR)
This register provides the number of the current slot in the current communication cycle for channel B.
Table 13-34. SLTCTBR Field Descriptions
Field
Description
10–0
SLOTCNTA
Slot Counter Value for Channel B — protocol related variable: vSlotCounter for channel B
This field provides the number of the current slot in the current communication cycle.
13.5.2.28 Rate Correction Value Register (RTCORVR)
Module Base + 0x0038
15
14
Additional Reset: RUN Command
13
12
11
10
9
R
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
RATECORR
W
Reset
0
0
0
0
0
0
0
0
0
Figure 13-28. Rate Correction Value Register (RTCORVR)
This register provides the sign extended rate correction value in microticks as it was calculated by the clock
synchronization algorithm. The FlexRay block updates this register during the NIT of each odd numbered
communication cycle.
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Table 13-35. RTCORVR Field Descriptions
Field
Description
15–0
Rate Correction Value — protocol related variable: vRateCorrection (before value limitation and external rate
RATECORR correction)
This field provides the sign extended rate correction value in microticks as it was calculated by the clock
synchronization algorithm. The value is represented in 2’s complement format. This value does not include the
value limitation and the application of the external rate correction. If the magnitude of the internally calculated
rate correction value exceeds the limit given by rate_correction_out in the Protocol Configuration Register 13
(PCR13), the clock correction reached limit interrupt flag CCL_IF is set in the Protocol Interrupt Flag Register 0
(PIFR0).
Note: If the FlexRay block was not able to calculate a new rate correction term due to a lack of synchronization
frames, the RATECORR value is not updated.
13.5.2.29 Offset Correction Value Register (OFCORVR)
Module Base + 0x003A
15
14
Additional Reset: RUN Command
13
12
11
10
9
R
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
OFFSETCORR
W
Reset
0
0
0
0
0
0
0
0
0
Figure 13-29. Offset Correction Value Register (OFCORVR)
This register provides the sign extended offset correction value in microticks as it was calculated by the
clock synchronization algorithm. The FlexRay block updates this register during the NIT.
Table 13-36. OFCORVR Field Descriptions
Field
Description
15–0
OFFSETCORR
Offset Correction Value — protocol related variable: vOffsetCorrection (before value limitation and external
offset correction)
This field provides the sign extended offset correction value in microticks as it was calculated by the clock
synchronization algorithm. The value is represented in 2’s complement format. This value does not include the
value limitation and the application of the external offset correction. If the magnitude of the internally calculated
rate correction value exceeds the limit given by offset_correction_out field in the Protocol Configuration Register
29 (PCR29), the clock correction reached limit interrupt flag CCL_IF is set in the Protocol Interrupt Flag Register
0 (PIFR0).
Note: If the FlexRay block was not able to calculate an new offset correction term due to a lack of
synchronization frames, the OFFSETCORR value is not updated.
13.5.2.30 Combined Interrupt Flag Register (CIFRR)
Module Base + 0x003C
15
R
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
MIF
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
WUP FNEB FNEA
PRIF CHIF
RBIF
IF
IF
IF
0
TBIF
W
Reset
0
0
0
0
0
0
0
Figure 13-30. Combined Interrupt Flag Register (CIFRR)
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This register provides five combined interrupt flags and a copy of three individual interrupt flags. The
combined interrupt flags are the result of a binary OR of the values of other interrupt flags regardless of
the state of the interrupt enable bits. The generation scheme for the combined interrupt flags is depicted in
Figure 13-146. The individual interrupt flags WUPIF, FNEBIF, and FNEAIF are copies of corresponding
flags in the Global Interrupt Flag and Enable Register (GIFER) and are provided here to simplify the
application interrupt flag check. To clear the individual interrupt flags, the application must use the Global
Interrupt Flag and Enable Register (GIFER).
NOTE
The meanings of the combined status bits MIF, PRIF, CHIF, RBIF, and
TBIF are different from those mentioned in the Global Interrupt Flag and
Enable Register (GIFER).
Table 13-37. CIFRR Field Descriptions
Field
Description
7
MIF
Module Interrupt Flag — This flag is set if there is at least one interrupt source that has its interrupt flag
asserted.
0 No interrupt source has its interrupt flag asserted
1 At least one interrupt source has its interrupt flag asserted
6
PRIF
Protocol Interrupt Flag — This flag is set if at least one of the individual protocol interrupt flags in the Protocol
Interrupt Flag Register 0 (PIFR0) or Protocol Interrupt Flag Register 1 (PIFR1) is equal to 1.
0 All individual protocol interrupt flags are equal to 0
1 At least one of the individual protocol interrupt flags is equal to 1
5
CHIF
CHI Interrupt Flag — This flag is set if at least one of the individual CHI error flags in the CHI Error Flag Register
(CHIERFR) is equal to 1.
0 All CHI error flags are equal to 0
1 At least one CHI error flag is equal to 1
4
WUPIF
Wakeup Interrupt Flag — Provides the same value as GIFER[WUPIF]
3
FNEBIF
Receive FIFO channel B Not Empty Interrupt Flag — Provides the same value as GIFER[FNEBI]
2
FNEAIF
Receive FIFO channel A Not Empty Interrupt Flag — Provides the same value as GIFER[FNEAIF]
1
RBIF
Receive Message Buffer Interrupt Flag — This flag is set if for at least one of the individual receive message
buffers (MBCCSRn[MTD] = 0) the interrupt flag MBIF in the corresponding Message Buffer Configuration,
Control, Status Registers (MBCCSRn) is equal to 1.
0 None of the individual receive message buffers has the MBIF flag asserted.
1 At least one individual receive message buffers has the MBIF flag asserted.
0
TBIF
Transmit Message Buffer Interrupt Flag — This flag is set if for at least one of the individual single or double
transmit message buffers (MBCCSRn[MTD] = 1) the interrupt flag MBIF in the corresponding Message Buffer
Configuration, Control, Status Registers (MBCCSRn) is equal to 1.
0 None of the individual transmit message buffers has the MBIF flag asserted.
1 At least one individual transmit message buffers has the MBIF flag asserted.
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13.5.2.31 System Memory Access Time-Out Register (SYMATOR)
Module Base + 0x003E
15
14
13
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
4
3
2
0
0
0
TIMEOUT
W
Reset
1
0
0
1
Figure 13-31. System Memory Access Time-Out Register (SYMATOR)
Write: Disabled Mode
Table 13-38. SYMATOR Field Descriptions
Field
Description
4–0
TIMEOUT
Time-Out — This value defines the maximum number of wait states on the system memory bus interface. This
value must never exceeded in order to ensure no data are lost even under internal worst case conditions.
If the number of wait states is greater than the TIMEOUT value, but is less than twice the TIMEOUT value, and
internal worst case conditions occur, than data might be lost. If data are lost, the System Bus Communication
Failure Error Flag SBCF_EF is set in the CHI Error Flag Register (CHIERFR).
If the number of wait states is greater than twice the TIMEOUT value, data will be lost, and the System Bus
Communication Failure Error Flag SBCF_EF is set in the CHI Error Flag Register (CHIERFR).
13.5.2.32 Sync Frame Counter Register (SFCNTR)
Module Base + 0x0040
15
R
14
Additional Reset: RUN Command
13
12
11
SFEVB
10
9
8
7
SFEVA
6
5
4
3
2
SFODB
1
0
SFODA
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-32. Sync Frame Counter Register (SFCNTR)
This register provides the number of synchronization frames that are used for clock synchronization in the
last even and in the last odd numbered communication cycle. This register is updated after the start of the
NIT and before 10 MT after offset correction start.
NOTE
If the application has locked the even synchronization table at the end of the
static segment of an even communication cycle, the FlexRay block will not
update the fields SFEVB and SFEVA.
If the application has locked the odd synchronization table at the end of the
static segment of an odd communication cycle, the FlexRay block will not
update the values SFODB and SFODA.
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Table 13-39. SFCNTR Field Descriptions
Field
Description
15–12
SFEVB
Sync Frames Channel B, even cycle — protocol related variable: size of (vsSyncIdListB for even cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
11–8
SFEVB
Sync Frames Channel A, even cycle — protocol related variable: size of (vsSyncIdListA for even cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
7–4
SFODB
Sync Frames Channel B, odd cycle — protocol related variable: size of (vsSyncIdListB for odd cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
3–0
SFODA
Sync Frames Channel A, odd cycle — protocol related variable: size of (vsSyncIdListA for odd cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for clock
synchronization.
13.5.2.33 Sync Frame Table Offset Register (SFTOR)
Module Base + 0x0042
15
14
13
12
11
10
R
9
8
7
6
5
4
3
2
1
SFT_OFFSET[15:1]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-33. Sync Frame Table Offset Register (SFTOR)
Write: POC:config
This register defines the Flexray Memory related offset for sync frame tables. For more details, see
Section 13.6.12, “Sync Frame ID and Sync Frame Deviation Tables”.
Table 13-40. SFTOR Field Description
Field
Description
15–1
SFTOR
Sync Frame Table Offset — The offset of the Sync Frame Tables in the Flexray Memory. This offset is required
to be 16-bit aligned. Thus STF_OFFSET[0] is always 0.
13.5.2.34 Sync Frame Table Configuration, Control, Status Register (SFTCCSR)
Module Base + 0x0044
R
15
14
0
0
13
12
11
10
9
8
CYCNUM
7
6
5
4
ELKS OLKS EVAL OVAL
3
2
1
0
0
0
OPT
SDV
EN
SID
EN
0
0
0
W ELKT OLKT
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-34. Sync Frame Table Configuration, Control, Status Register (SFTCCSR)
Write: Normal Mode
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This register provides configuration, control, and status information related to the generation and access
of the clock sync ID tables and clock sync measurement tables. For a detailed description, see
Section 13.6.12, “Sync Frame ID and Sync Frame Deviation Tables”.
Table 13-41. SFTCCSR Field Descriptions
Field
Description
15
ELKT
Even Cycle Tables Lock/Unlock Trigger — This trigger bit is used to lock and unlock the even cycle tables.
0 No effect
1 Triggers lock/unlock of the even cycle tables.
14
OLKT
Odd Cycle Tables Lock/Unlock Trigger — This trigger bit is used to lock and unlock the odd cycle tables.
0 No effect
1 Triggers lock/unlock of the odd cycle tables.
13–8
CYCNUM
Cycle Number — This field provides the number of the cycle in which the currently locked table was
recorded. If none or both tables are locked, this value is related to the even cycle table.
7
ELKS
Even Cycle Tables Lock Status — This status bit indicates whether the application has locked the even
cycle tables.
0 Application has not locked the even cycle tables.
1 Application has locked the even cycle tables.
6
OLKS
Odd Cycle Tables Lock Status — This status bit indicates whether the application has locked the odd cycle
tables.
0 Application has not locked the odd cycle tables.
1 Application has locked the odd cycle tables.
5
EVAL
Even Cycle Tables Valid — This status bit indicates whether the Sync Frame ID and Sync Frame Deviation
Tables for the even cycle are valid. The FlexRay block clears this status bit when it starts updating the tables,
and sets this bit when it has finished the table update.
0 Tables are not valid (update is ongoing)
1 Tables are valid (consistent).
4
OVAL
Odd Cycle Tables Valid — This status bit indicates whether the Sync Frame ID and Sync Frame Deviation
Tables for the odd cycle are valid. The FlexRay block clears this status bit when it starts updating the tables,
and sets this bit when it has finished the table update.
0 Tables are not valid (update is ongoing)
1 Tables are valid (consistent).
2
OPT
One Pair Trigger — This trigger bit controls whether the FlexRay block writes continuously or only one pair
of Sync Frame Tables into the FRM.
If this trigger is set to 1 while SDVEN or SIDEN is set to 1, the FlexRay block writes only one pair of the
enabled Sync Frame Tables corresponding to the next even-odd-cycle pair into the FRM. In this case, the
FlexRay block clears the SDVEN or SIDEN bits immediately.
If this trigger is set to 0 while SDVEN or SIDEN is set to 1, the FlexRay block writes continuously the enabled
Sync Frame Tables into the FRM.
0 Write continuously pairs of enabled Sync Frame Tables into FRM.
1 Write only one pair of enabled Sync Frame Tables into FRM.
1
SDVEN
Sync Frame Deviation Table Enable — This bit controls the generation of the Sync Frame Deviation Tables.
The application must set this bit to request the FlexRay block to write the Sync Frame Deviation Tables into
the FRM.
0 Do not write Sync Frame Deviation Tables
1 Write Sync Frame Deviation Tables into FRM
Note: If SDVEN is set to 1, then SIDEN must also be set to 1.
0
SIDEN
Sync Frame ID Table Enable — This bit controls the generation of the Sync Frame ID Tables. The
application must set this bit to 1 to request the FlexRay block to write the Sync Frame ID Tables into the FRM.
0 Do not write Sync Frame ID Tables
1 Write Sync Frame ID Tables into FRM
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13.5.2.35 Sync Frame ID Rejection Filter Register (SFIDRFR)
Module Base + 0x0046
16-bit write access required
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
0
0
R
9
8
7
6
4
3
2
1
0
0
0
0
0
SYNFRID
W
Reset
5
0
0
0
0
0
0
Figure 13-35. Sync Frame ID Rejection Filter Register (SFIDRFR)
Write: Normal Mode
This register defines the Sync Frame Rejection Filter ID. The application must update this register outside
of the static segment. If the application updates this register in the static segment, it can appear that the
FlexRay block accepts the sync frame in the current cycle.
Table 13-42. SFIDRFR Field Descriptions
Field
Description
9–0
SYNFRID
Sync Frame Rejection ID — This field defines the frame ID of a frame that must not be used for clock
synchronization. For details see Section 13.6.15.2, “Sync Frame Rejection Filtering”.
13.5.2.36 Sync Frame ID Acceptance Filter Value Register (SFIDAFVR)
Module Base + 0x0048
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
0
0
R
9
8
7
6
5
3
2
1
0
0
0
0
0
0
FVAL
W
Reset
4
0
0
0
0
0
Figure 13-36. Sync Frame ID Acceptance Filter Value Register (SFIDAFVR)
Write: POC:config
This register defines the sync frame acceptance filter value. For details on filtering, see Section 13.6.15,
“Sync Frame Filtering”.
Table 13-43. SFIDAFVR Field Descriptions
Field
Description
9–0
FVAL
Filter Value — This field defines the value for the sync frame acceptance filtering.
13.5.2.37 Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR)
Module Base + 0x004A
R
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
0
0
9
8
7
6
4
3
2
1
0
0
0
0
0
0
FMSK
W
Reset
5
0
0
0
0
0
Figure 13-37. Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR)
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Write: POC:config
This register defines the sync frame acceptance filter mask. For details on filtering see Section 13.6.15.1,
“Sync Frame Acceptance Filtering”.
Table 13-44. SFIDAFMR Field Descriptions
Field
Description
9–0
FMSK
Filter Mask — This field defines the mask for the sync frame acceptance filtering.
13.5.2.38 Network Management Vector Registers (NMVR0–NMVR5)
Module Base + 0x004C (NMVR0)
Module Base + 0x004E (NMVR1)
Module Base + 0x0050 (NMVR2)
Module Base + 0x0052 (NMVR3)
Module Base + 0x0054 (NMVR4)
Module Base + 0x0056 (NMVR5)
15
14
13
R
12
11
10
9
8
7
6
5
NMVP[15:8]
4
3
2
1
0
0
0
0
NMVP[7:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-38. Network Management Vector Registers (NMVR0–NMVR5)
Each of these six registers holds one part of the Network Management Vector. The length of the Network
Management Vector is configured in the Network Management Vector Length Register (NMVLR). If
NMVLR is programmed with a value that is less than 12 bytes, the remaining bytes of the Network
Management Vector Registers (NMVR0–NMVR5), which are not used for the Network Management
Vector accumulating, will remain 0.
The NMVR provides accrued information over all received NMVs in the last communication cycle. All
NMVs received in one cycle are ORed into the NMVR. The NMVR is updated at the end of the
communication cycle.
Table 13-45. NMVR[0:5] Field Descriptions
Field
15–0
NMVP
Description
Network Management Vector Part — The mapping between the Network Management Vector Registers
(NMVR0–NMVR5) and the receive message buffer payload bytes in NMV[0:11] is depicted in Table 13-46.
Table 13-46. Mapping of NMVRn to the Received Payload Bytes NMVn
NMVRn Register
NMVn Received Payload
NMVR0[NMVP[15:8]]
NMV0
NMVR0[NMVP[7:0]]
NMV1
NMVR1[NMVP[15:8]]
NMV2
NMVR1[NMVP[7:0]]
NMV3
...
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Table 13-46. Mapping of NMVRn to the Received Payload Bytes NMVn
NMVRn Register
NMVn Received Payload
NMVR5[NMVP[15:8]]
NMV10
NMVR5[NMVP[7:0]]
NMV11
13.5.2.39 Network Management Vector Length Register (NMVLR)
Module Base + 0x0058
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
3
2
0
0
0
NMVL
W
Reset
1
0
0
Figure 13-39. Network Management Vector Length Register (NMVLR)
Write: POC:config
This register defines the length of the network management vector in bytes.
Table 13-47. NMVLR Field Descriptions
Field
Description
3–0
NMVL
Network Management Vector Length — protocol related variable: gNetworkManagementVectorLength
This field defines the length of the Network Management Vector in bytes. Legal values are between 0 and 12.
13.5.2.40 Timer Configuration and Control Register (TICCR)
Module Base + 0x005A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
T2_
CFG
T2_
REP
0
0
0
T2ST
0
0
0
T1_
REP
0
0
0
T1ST
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
T2SP T2TR
0
0
T1SP T1TR
0
0
0
Figure 13-40. Timer Configuration and Control Register (TICCR)
Write: T2_CFG: POC:config
T2_REP, T1_REP, T1SP, T2SP, T1TR, T2TR: Normal Mode
This register is used to configure and control the two timers T1 and T2. For timer details, see
Section 13.6.17, “Timer Support”. The Timer T1 is an absolute timer. The Timer T2 can be configured as
an absolute or relative timer.
Table 13-48. TICCR Field Descriptions (Sheet 1 of 2)
Field
Description
13
T2_CFG
Timer T2 Configuration — This bit configures the timebase mode of Timer T2.
0 T2 is absolute timer.
1 T2 is relative timer.
12
T2_REP
Timer T2 Repetitive Mode — This bit configures the repetition mode of Timer T2.
0 T2 is non repetitive
1 T2 is repetitive
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Table 13-48. TICCR Field Descriptions (Sheet 2 of 2)
Field
Description
10
T2SP
Timer T2 Stop — This trigger bit is used to stop timer T2.
0 no effect
1 stop timer T2
9
T2TR
Timer T2 Trigger — This trigger bit is used to start timer T2.
0 no effect
1 start timer T2
8
T2ST
Timer T2 State — This status bit provides the current state of timer T2.
0 timer T2 is idle
1 timer T2 is running
4
T1_REP
Timer T1 Repetitive Mode — This bit configures the repetition mode of timer T1.
0 T1 is non repetitive
1 T1 is repetitive
2
T1SP
Timer T1 Stop — This trigger bit is used to stop timer T1.
0 no effect
1 stop timer T1
1
T1TR
Timer T1 Trigger — This trigger bit is used to start timer T1.
0 no effect
1 start timer T1
0
T1ST
Timer T1 State — This status bit provides the current state of timer T1.
0 timer T1 is idle
1 timer T1 is running
NOTE
Both timers are deactivated immediately when the protocol enters a state
different from POC:normal active or POC:normal passive.
13.5.2.41 Timer 1 Cycle Set Register (TI1CYSR)
Module Base + 0x005C
R
15
14
0
0
0
0
13
12
10
9
8
T1_CYC_VAL
W
Reset
11
0
0
0
0
0
0
7
6
0
0
0
0
5
4
3
2
1
0
0
0
T1_CYC_MSK
0
0
0
0
Figure 13-41. Timer 1 Cycle Set Register (TI1CYSR)
Write: Anytime
This register defines the cycle filter value and the cycle filter mask for timer T1. For a detailed description
of timer T1, refer to Section 13.6.17.1, “Absolute Timer T1”.
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Table 13-49. TI1CYSR Field Descriptions
Field
13–8
T1_CYC_VAL
Description
Timer T1 Cycle Filter Value — This field defines the cycle filter value for timer T1.
5–0
Timer T1 Cycle Filter Mask — This field defines the cycle filter mask for timer T1.
T1_CYC_MSK
NOTE
If the application modifies the value in this register while the timer is
running, the change becomes effective immediately and timer T1 will expire
according to the changed value.
13.5.2.42 Timer 1 Macrotick Offset Register (TI1MTOR)
Module Base + 0x005E
R
15
14
0
0
0
0
13
12
11
10
9
8
6
5
4
3
2
1
0
0
0
0
0
0
0
T1_MTOFFSET
W
Reset
7
0
0
0
0
0
0
0
0
Figure 13-42. Timer 1 Macrotick Offset Register (TI1MTOR)
Write: Anytime
This register holds the macrotick offset value for timer T1. For a detailed description of timer T1, refer to
Section 13.6.17.1, “Absolute Timer T1”.
Table 13-50. TI1MTOR Field Descriptions
Field
Description
13–0
Timer 1 Macrotick Offset — This field defines the macrotick offset value for timer 1.
T1_MTOFFSET
NOTE
If the application modifies the value in this register while the timer is
running, the change becomes effective immediately and timer T1 will expire
according to the changed value.
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13.5.2.43 Timer 2 Configuration Register 0 (TI2CR0)
Module Base + 0x0060
R
15
14
0
0
13
12
11
10
9
T2_CYC_VAL
W
R
7
6
0
0
5
4
3
2
1
0
0
0
T2_CYC_MSK
T2_MTCNT[31:16]
W
Reset
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-43. Timer 2 Configuration Register 0 (TI2CR0)
Write: Anytime
The content of this register depends on the value of the T2_CFG bit in the Timer Configuration and Control
Register (TICCR). For a detailed description of timer T2, refer to Section 13.6.17.2, “Absolute / Relative
Timer T2”.
Table 13-51. TI2CR0 Field Descriptions
Field
Description
Fields for absolute timer T2 (TICCR[T2_CFG] = 0)
13–8
T2_CYC_VAL
Timer T2 Cycle Filter Value — This field defines the cycle filter value for timer T2.
5–0
T2_CYC_MSK
Timer T2 Cycle Filter Mask — This field defines the cycle filter mask for timer T2.
Fields for relative timer T2 (TICCR[T2_CFG = 1)
15–0
Timer T2 Macrotick High Word — This field defines the high word of the macrotick count for timer T2.
T2_MTCNT[31:16]
NOTE
If timer T2 is configured as an absolute timer and the application modifies
the values in this register while the timer is running, the change becomes
effective immediately and timer T2 will expire according to the changed
values.
If timer T2 is configured as a relative timer and the application changes the
values in this register while the timer is running, the change becomes
effective when the timer has expired according to the old values.
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13.5.2.44 Timer 2 Configuration Register 1 (TI2CR1)
Module Base + 0x0062
R
15
14
0
0
13
12
11
10
9
8
6
5
4
3
2
1
0
0
0
0
0
0
0
T2_MTOFFSET
W
R
T2_MTCNT[15:0]
W
Reset
7
0
0
0
0
0
0
0
0
0
0
Figure 13-44. Timer 2 Configuration Register 1 (TI2CR1)
Write: Anytime
The content of this register depends on the value of the T2_CFG bit in the Timer Configuration and Control
Register (TICCR). For a detailed description of timer T2, refer to Section 13.6.17.2, “Absolute / Relative
Timer T2”.
Table 13-52. TI2CR1 Field Descriptions
Field
Description
Fields for absolute timer T2 (TICCR[T2_CFG] = 0)
13–0
T2_MTOFFSET
Timer T2 Macrotick Offset — This field holds the macrotick offset value for timer T2.
Fields for relative timer T2 (TICCR[T2_CFG] = 1)
15–0
T2_MTCNT[15:0]
Timer T2 Macrotick Low Word — This field defines the low word of the macrotick value for timer T2.
NOTE
If timer T2 is configured as an absolute timer and the application modifies
the values in this register while the timer is running, the change becomes
effective immediately and the timer T2 will expire according to the changed
values.
If timer T2 is configured as a relative timer and the application changes the
values in this register while the timer is running, the change becomes
effective when the timer has expired according to the old values.
13.5.2.45 Slot Status Selection Register (SSSR)
Module Base + 0x0064
R
15
14
0
0
16-bit write access required
13
0
0
0
11
10
9
8
7
0
SEL
W WMD
Reset
12
0
0
6
5
4
3
2
1
0
0
0
0
0
SLOTNUMBER
0
0
0
0
0
0
0
Figure 13-45. Slot Status Selection Register (SSSR)
Write: Anytime
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This register is used to access the four internal non memory-mapped slot status selection registers SSSR0
to SSSR3. Each internal registers selects a slot, or symbol window/NIT, whose status vector will be saved
in the corresponding Slot Status Registers (SSR0–SSR7) according to Table 13-54. For a detailed
description of slot status monitoring, refer to Section 13.6.18, “Slot Status Monitoring”.
Table 13-53. SSSR Field Descriptions
Field
Description
15
WMD
Write Mode — This control bit defines the write mode of this register.
0 Write to all fields in this register on write access.
1 Write to SEL field only on write access.
13–12
SEL
Selector — This field selects one of the four internal slot status selection registers for access.
00 select SSSR0.
01 select SSSR1.
10 select SSSR2.
11 select SSSR3.
10–0
Slot Number — This field specifies the number of the slot whose status will be saved in the corresponding
SLOTNUMBER slot status registers.
Note: If this value is set to 0, the related slot status register provides the status of the symbol window after
the NIT start, and provides the status of the NIT after the cycle start.
Table 13-54. Mapping Between SSSRn and SSRn
Write the Slot Status of the Slot Selected by SSSRn for each
Internal Slot
Status Selection
Register
Even Communication Cycle
Odd Communication Cycle
For Channel B
to
For Channel A
to
For Channel B
to
For Channel A
to
SSSR0
SSR0[15:8]
SSR0[7:0]
SSR1[15:8]
SSR1[7:0]
SSSR1
SSR2[15:8]
SSR2[7:0]
SSR3[15:8]
SSR3[7:0]
SSSR2
SSR4[15:8]
SSR4[7:0]
SSR5[15:8]
SSR5[7:0]
SSSR3
SSR6[15:8]
SSR6[7:0]
SSR7[15:8]
SSR7[7:0]
13.5.2.46 Slot Status Counter Condition Register (SSCCR)
Module Base + 0x0066
R
15
14
0
0
16-bit write access required
13
0
0
0
11
0
SEL
W WMD
Reset
12
0
0
10
9
CNTCFG
0
0
8
7
6
5
4
MCY
VFR
SYF
NUF
SUF
0
0
0
0
0
3
2
1
0
STATUSMASK
0
0
0
0
Figure 13-46. Slot Status Counter Condition Register (SSCCR)
Write: Anytime
This register is used to access and program the four internal non-memory mapped Slot Status Counter
Condition Registers SSCCR0 to SSCCR3. Each of these four internal slot status counter condition
registers defines the mode and the conditions for incrementing the counter in the corresponding Slot Status
Counter Registers (SSCR0–SSCR3). The correspondence is given in Table 13-56. For a detailed
description of slot status counters, refer to Section 13.6.18.4, “Slot Status Counter Registers”.
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Table 13-55. SSCCR Field Descriptions
Field
Description
15
WMD
Write Mode — This control bit defines the write mode of this register.
0 Write to all fields in this register on write access.
1 Write to SEL field only on write access.
13–12
SEL
Selector — This field selects one of the four internal slot counter condition registers for access.
00 select SSCCR0.
01 select SSCCR1.
10 select SSCCR2.
11 select SSCCR3.
10–9
CNTCFG
Counter Configuration — These bit field controls the channel related incrementing of the slot status counter.
00 increment by 1 if condition is fulfilled on channel A.
01 increment by 1 if condition is fulfilled on channel B.
10 increment by 1 if condition is fulfilled on at least one channel.
11 increment by 2 if condition is fulfilled on both channels channel.
increment by 1 if condition is fulfilled on only one channel.
8
MCY
Multi Cycle Selection — This bit defines whether the slot status counter accumulates over multiple
communication cycles or provides information for the previous communication cycle only.
0 The Slot Status Counter provides information for the previous communication cycle only.
1 The Slot Status Counter accumulates over multiple communication cycles.
7
VFR
Valid Frame Restriction — This bit is used to restrict the counter to received valid frames.
0 The counter is not restricted to valid frames only.
1 The counter is restricted to valid frames only.
6
SYF
Sync Frame Restriction — This bit is used to restrict the counter to received frames with the sync frame
indicator bit set to 1.
0 The counter is not restricted with respect to the sync frame indicator bit.
1 The counter is restricted to frames with the sync frame indicator bit set to 1.
5
NUF
Null Frame Restriction — This bit is used to restrict the counter to received frames with the null frame
indicator bit set to 0.
0 The counter is not restricted with respect to the null frame indicator bit.
1 The counter is restricted to frames with the null frame indicator bit set to 0.
4
SUF
Startup Frame Restriction — This bit is used to restrict the counter to received frames with the startup frame
indicator bit set to 1.
0 The counter is not restricted with respect to the startup frame indicator bit.
1 The counter is restricted to received frames with the startup frame indicator bit set to 1.
3–0
Slot Status Mask — This bit field is used to enable the counter with respect to the four slot status error
STATUSMASK indicator bits.
STATUSMASK[3] – This bit enables the counting for slots with the syntax error indicator bit set to 1.
STATUSMASK[2] – This bit enables the counting for slots with the content error indicator bit set to 1.
STATUSMASK[1] – This bit enables the counting for slots with the boundary violation indicator bit set to 1.
STATUSMASK[0] – This bit enables the counting for slots with the transmission conflict indicator bit set to 1.
Table 13-56. Mapping between internal SSCCRn and SSCRn
Condition Register
Condition Defined for Register
SSCCR0
SSCR0
SSCCR1
SSCR1
SSCCR2
SSCR2
SSCCR3
SSCR3
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13.5.2.47 Slot Status Registers (SSR0–SSR7)
Module Base + 0x0068 (SSR0)
Module Base + 0x006A (SSR1)
Module Base + 0x006C (SSR2)
Module Base + 0x006E (SSR3)
Module Base + 0x0070 (SSR4)
Module Base + 0x0072 (SSR5)
Module Base + 0x0074 (SSR6)
Module Base + 0x0076 (SSR7)
15
R VFB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SYB
NFB
SUB
SEB
CEB
BVB
TCB
VFA
SYA
NFA
SUA
SEA
CEA
BVA
TCA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
Figure 13-47. Slot Status Registers (SSR0–SSR7)
Each of these eight registers holds the status vector of the slot specified in the corresponding internal slot
status selection register, which can be programmed using the Slot Status Selection Register (SSSR). Each
register is updated after the end of the corresponding slot as shown in Figure 13-142. The register bits are
directly related to the protocol variables and described in more detail in Section 13.6.18, “Slot Status
Monitoring”.
Table 13-57. SSR0–SSR7 Field Descriptions
Field
Description
15
VFB
Valid Frame on Channel B — protocol related variable: vSS!ValidFrame channel B
0 vSS!ValidFrame = 0
1 vSS!ValidFrame = 1
14
SYB
Sync Frame Indicator Channel B — protocol related variable: vRF!Header!SyFIndicator channel B
0 vRF!Header!SyFIndicator = 0
1 vRF!Header!SyFIndicator = 1
13
NFB
Null Frame Indicator Channel B — protocol related variable: vRF!Header!NFIndicator channel B
0 vRF!Header!NFIndicator = 0
1 vRF!Header!NFIndicator = 1
12
SUB
Startup Frame Indicator Channel B — protocol related variable: vRF!Header!SuFIndicator channel B
0 vRF!Header!SuFIndicator = 0
1 vRF!Header!SuFIndicator = 1
11
SEB
Syntax Error on Channel B — protocol related variable: vSS!SyntaxError channel B
0 vSS!SyntaxError = 0
1 vSS!SyntaxError = 1
10
CEB
Content Error on Channel B — protocol related variable: vSS!ContentError channel B
0 vSS!ContentError = 0
1 vSS!ContentError = 1
9
BVB
Boundary Violation on Channel B — protocol related variable: vSS!BViolation channel B
0 vSS!BViolation = 0
1 vSS!BViolation = 1
8
TCB
Transmission Conflict on Channel B — protocol related variable: vSS!TxConflict channel B
0 vSS!TxConflict = 0
1 vSS!TxConflict = 1
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Table 13-57. SSR0–SSR7 Field Descriptions (continued)
Field
Description
7
VFA
Valid Frame on Channel A — protocol related variable: vSS!ValidFrame channel A
0 vSS!ValidFrame = 0
1 vSS!ValidFrame = 1
6
SYA
Sync Frame Indicator Channel A — protocol related variable: vRF!Header!SyFIndicator channel A
0 vRF!Header!SyFIndicator = 0
1 vRF!Header!SyFIndicator = 1
5
NFA
Null Frame Indicator Channel A — protocol related variable: vRF!Header!NFIndicator channel A
0 vRF!Header!NFIndicator = 0
1 vRF!Header!NFIndicator = 1
4
SUA
Startup Frame Indicator Channel A — protocol related variable: vRF!Header!SuFIndicator channel A
0 vRF!Header!SuFIndicator = 0
1 vRF!Header!SuFIndicator = 1
3
SEA
Syntax Error on Channel A — protocol related variable: vSS!SyntaxError channel A
0 vSS!SyntaxError = 0
1 vSS!SyntaxError = 1
2
CEA
Content Error on Channel A — protocol related variable: vSS!ContentError channel A
0 vSS!ContentError = 0
1 vSS!ContentError = 1
1
BVA
Boundary Violation on Channel A — protocol related variable: vSS!BViolation channel A
0 vSS!BViolation = 0
1 vSS!BViolation = 1
0
TCA
Transmission Conflict on Channel A — protocol related variable: vSS!TxConflict channel A
0 vSS!TxConflict = 0
1 vSS!TxConflict = 1
13.5.2.48 Slot Status Counter Registers (SSCR0–SSCR3)
Module Base + 0x0078
(SSCR0)
Module Base + 0x007A
(SSCR1)
Module Base + 0x007C
(SSCR2)
Module Base + 0x007E
(SSCR3)
15
14
Additional Reset: RUN Command
13
12
11
10
9
R
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
SLOTSTATUSCNT
W
Reset
0
0
0
0
0
0
0
0
0
Figure 13-48. Slow Status Counter Registers (SSCR0–SSCR3)
Each of these four registers provides the slot status counter value for the previous communication cycle(s)
and is updated at the cycle start. The provided value depends on the control bits and fields in the related
internal slot status counter condition register SSCCRn, which can be programmed by using the Slot Status
Counter Condition Register (SSCCR). For more details, see Section 13.6.18.4, “Slot Status Counter
Registers”.
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NOTE
If the counter has reached its maximum value 0xFFFF and is in the
multicycle mode, i.e. SSCCRn[MCY] = 1, the counter is not reset to
0x0000. The application can reset the counter by clearing the
SSCCRn[MCY] bit and waiting for the next cycle start, when the FlexRay
block clears the counter. Subsequently, the counter can be set into the
multicycle mode again.
Table 13-58. SSCR0–SSCR3 Field Descriptions
Field
Description
15–0
Slot Status Counter — This field provides the current value of the Slot Status Counter.
SLOTSTATUSCNT
13.5.2.49 MTS A Configuration Register (MTSACFR)
Module Base + 0x0080
15
R
W
Reset
MTE
0
14
13
12
0
0
11
10
9
8
CYCCNTMSK
0
0
0
0
0
0
7
6
0
0
0
0
5
4
3
2
1
0
0
0
CYCCNTVAL
0
0
0
0
Figure 13-49. MTS A Configuration Register (MTSACFR)
Write: MTE: Anytime; CYCCNTMSK,CYCCNTVAL: POC:config
This register controls the transmission of the Media Access Test Symbol MTS on channel A. For more
details, see Section 13.6.13, “MTS Generation”.
Table 13-59. MTSACFR Field Descriptions
Field
15
MTE
Description
Media Access Test Symbol Transmission Enable — This control bit is used to enable and disable the
transmission of the Media Access Test Symbol in the selected set of cycles.
0 MTS transmission disabled
1 MTS transmission enabled
13–8
Cycle Counter Mask — This field provides the filter mask for the MTS cycle count filter.
CYCCNTMSK
5–0
Cycle Counter Value — This field provides the filter value for the MTS cycle count filter.
CYCCNTVAL
13.5.2.50 MTS B Configuration Register (MTSBCFR)
Module Base + 0x0082
15
R
W
Reset
MTE
0
14
13
12
0
0
11
10
9
8
CYCCNTMSK
0
0
0
0
0
0
7
6
0
0
0
0
5
4
3
2
1
0
0
0
CYCCNTVAL
0
0
0
0
Figure 13-50. MTS B Configuration Register (MTSBCFR)
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Write: MTE: Anytime; CYCCNTMSK,CYCCNTVAL: POC:config
This register controls the transmission of the Media Access Test Symbol MTS on channel B. For more
details, see Section 13.6.13, “MTS Generation”.
Table 13-60. MTSBCFR Field Descriptions
Field
15
MTE
Description
Media Access Test Symbol Transmission Enable — This control bit is used to enable and disable the
transmission of the Media Access Test Symbol in the selected set of cycles.
0 MTS transmission disabled
1 MTS transmission enabled
13–8
Cycle Counter Mask — This field provides the filter mask for the MTS cycle count filter.
CYCCNTMSK
Cycle Counter Value — This field provides the filter value for the MTS cycle count filter.
5–0
CYCCNTVAL
13.5.2.51 Receive Shadow Buffer Index Register (RSBIR)
Module Base + 0x0084
15
14
0
0
R
16-bit write access required
13
SEL
W WMD
Reset
0
0
12
0
0
11
10
9
8
7
6
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
0
0
RSBIDX
0
0
0
0
Figure 13-51. Receive Shadow Buffer Index Register (RSBIR)
Write: WMD, SEL: Any Time; RSBIDX: POC:config
This register is used to provide and retrieve the indices of the message buffer header fields currently
associated with the receive shadow buffers. For more details on the receive shadow buffer concept, refer
to Section 13.6.6.3.5, “Receive Shadow Buffers Concept”.
Table 13-61. RSBIR Field Descriptions
Field
Description
15
WMD
Write Mode — This bit controls the write mode for this register.
0 update SEL and RSBIDX field on register write
1 update only SEL field on register write
13–12
SEL
Selector — This field is used to select the internal receive shadow buffer index register for access.
00 RSBIR_A1 — receive shadow buffer index register for channel A, segment 1
01 RSBIR_A2 — receive shadow buffer index register for channel A, segment 2
10 RSBIR_B1 — receive shadow buffer index register for channel B, segment 1
11 RSBIR_B2 — receive shadow buffer index register for channel B, segment 2
5–0
RSBIDX
Receive Shadow Buffer Index — This field contains the current index of the message buffer header field of the
receive shadow message buffer selected by the SEL field. The FlexRay block uses this index to determine the
physical location of the shadow buffer header field in the FlexRay memory. The FlexRay block will update this
field during receive operation.The application provides initial message buffer header index value in the
configuration phase.
FlexRay block: Updates the message buffer header index after successful reception.
Application: Provides initial message buffer header index.
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13.5.2.52 Receive FIFO Selection Register (RFSR)
Module Base + 0x0086
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
0
SEL
Figure 13-52. Receive FIFO Selection Register (RFSR)
Write: Anytime
This register is used to select a receiver FIFO for subsequent access through the receiver FIFO
configuration registers summarized in Table 13-62.
Table 13-62. SEL Controlled Receiver FIFO Registers
Register
Receive FIFO Start Index Register (RFSIR)
Receive FIFO Depth and Size Register (RFDSR)
Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR)
Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR)
Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR)
Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR)
Receive FIFO Range Filter Configuration Register (RFRFCFR)
Receive FIFO Range Filter Control Register (RFRFCTR)
Table 13-63. RFSR Field Descriptions
Field
Description
0
SEL
Select — This control bit selects the receiver FIFO for subsequent programming.
0 Receiver FIFO for channel A selected
1 Receiver FIFO for channel B selected
13.5.2.53 Receive FIFO Start Index Register (RFSIR)
Module Base + 0x0088
R
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
0
0
9
8
7
6
5
3
2
1
0
0
0
0
0
0
SIDX
W
Reset
4
0
0
0
0
0
Figure 13-53. Receive FIFO Start Index Register (RFSIR)
Write: POC:config
This register defines the message buffer header index of the first message buffer of the selected FIFO.
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Table 13-64. RFSIR Field Descriptions
Field
Description
9–0
SIDX
Start Index — This field defines the number of the message buffer header field of the first message buffer of the
selected receive FIFO. The FlexRay block uses the value of the SIDX field to determine the physical location of
the receiver FIFO’s first message buffer header field.
13.5.2.54 Receive FIFO Depth and Size Register (RFDSR)
Module Base + 0x008A
15
14
13
R
12
11
10
9
8
Reset
0
0
0
0
0
6
5
4
0
FIFO_DEPTH
W
7
0
0
0
0
3
2
1
0
0
0
ENTRY_SIZE
0
0
0
0
0
Figure 13-54. Receive FIFO Depth and Size Register (RFDSR)
Write: POC:config
This register defines the structure of the selected FIFO, i.e. the number of entries and the size of each entry.
Table 13-65. RFDSR Field Descriptions
Field
Description
15–8
FIFO Depth — This field defines the depth of the selected receive FIFO, i.e. the number of entries.
FIFO_DEPTH
6–0
Entry Size — This field defines the size of the frame data sections for the selected receive FIFO in 2 byte
ENTRY_SIZE entities.
13.5.2.55 Receive FIFO A Read Index Register (RFARIR)
Module Base + 0x008C
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
0
0
R
9
8
7
6
5
4
3
2
1
0
0
0
0
0
RDIDX
W
Reset
0
0
0
0
0
0
Figure 13-55. Receive FIFO A Read Index Register (RFARIR)
This register provides the message buffer header index of the next available receive FIFO A entry that the
application can read.
Table 13-66. RFARIR Field Descriptions
Field
Description
9–0
RDIDX
Read Index — This field provides the message buffer header index of the next available receive FIFO message
buffer that the application can read. The FlexRay block increments this index when the application writes to the
FNEAIF flag in the Global Interrupt Flag and Enable Register (GIFER). The index wraps back to the first
message buffer header index if the end of the FIFO was reached.
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NOTE
If the receive FIFO not empty flag FNEAIF is not set, the RDIDX field
points to an physical message buffer which content is not valid. Only when
FNEAIF is set, the message buffer indicated by RDIDX contains valid data.
13.5.2.56 Receive FIFO B Read Index Register (RFBRIR)
Module Base + 0x008E
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
0
0
R
9
8
7
6
5
4
3
2
1
0
0
0
0
0
RDIDX
W
Reset
0
0
0
0
0
0
Figure 13-56. Receive FIFO B Read Index Register (RFBRIR)
This register provides the message buffer header index of the next available receive FIFO B entry that the
application can read.
Table 13-67. RFBRIR Field Descriptions
Field
Description
9–0
RDIDX
Read Index — This field provides the message buffer header index of the next available receive FIFO entry that
the application can read. The FlexRay block increments this index when the application writes to the FNEBIF
flag in the Global Interrupt Flag and Enable Register (GIFER).The index wraps back to the first message buffer
header index if the end of the FIFO was reached.
NOTE
If the receive FIFO not empty flag FNEBIF is not set, the RDIDX field
points to an physical message buffer which content is not valid. Only when
FNEBIF is set, the message buffer indicated by RDIDX contains valid data.
13.5.2.57 Receive FIFO Message ID Acceptance Filter Value Register
(RFMIDAFVR)
Module Base + 0x0090
15
14
13
12
11
10
9
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
MIDAFVAL
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-57. Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR)
Write: POC:config
This register defines the filter value for the message ID acceptance filter of the selected receive FIFO. For
details on message ID filtering see Section 13.6.9.5, “Receive FIFO filtering”.
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Table 13-68. RFMIDAFVR Field Descriptions
Field
Description
15–0
MIDAFVAL
Message ID Acceptance Filter Value — Filter value for the message ID acceptance filter.
13.5.2.58 Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR)
Module Base + 0x0092
15
14
13
12
11
10
9
R
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
MIDAFMSK
W
Reset
0
0
0
0
0
0
0
0
0
Figure 13-58. Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR)
Write: POC:config
This register defines the filter mask for the message ID acceptance filter of the selected receive FIFO. For
details on message ID filtering see Section 13.6.9.5, “Receive FIFO filtering”.
Table 13-69. RFMIAFMR Field Descriptions
Field
Description
15–0
MIDAFMSK
Message ID Acceptance Filter Mask — Filter mask for the message ID acceptance filter.
13.5.2.59 Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR)
Module Base + 0x0094
15
14
13
12
11
0
0
0
0
0
0
0
0
0
0
R
10
9
8
7
6
4
3
2
1
0
0
0
0
0
0
FIDRFVAL
W
Reset
5
0
0
0
0
0
0
Figure 13-59. Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR)
Write: POC:config
This register defines the filter value for the frame ID rejection filter of the selected receive FIFO. For details
on frame ID filtering see Section 13.6.9.5, “Receive FIFO filtering”.
Table 13-70. RFFIDRFVR Field Descriptions
Field
10–0
FIDRFVAL
Description
Frame ID Rejection Filter Value — Filter value for the frame ID rejection filter.
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
13.5.2.60 Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR)
Module Base + 0x0096
15
14
13
12
11
0
0
0
0
0
0
0
0
0
0
R
10
9
8
7
6
4
3
2
1
0
0
0
0
0
0
FIDRFMSK
W
Reset
5
0
0
0
0
0
0
Figure 13-60. Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR)
Write: POC:config
This register defines the filter mask for the frame ID rejection filter of the selected receive FIFO. For details
on frame ID filtering see Section 13.6.9.5, “Receive FIFO filtering”.
Table 13-71. RFFIDRFMR Field Descriptions
Field
Description
10–0
FIDRFMSK
Frame ID Rejection Filter Mask — Filter mask for the frame ID rejection filter.
13.5.2.61 Receive FIFO Range Filter Configuration Register (RFRFCFR)
Module Base + 0x0098
15
R
0
W WMD
Reset
0
14
16-bit write access required
13
IBD
0
12
10
9
8
7
6
0
SEL
0
11
0
0
5
4
3
2
1
0
0
0
0
0
0
SID
0
0
0
0
0
0
Figure 13-61. Receive FIFO Range Filter Configuration Register (RFRFCFR)
Write: WMD, IBD, SEL: Any Time; SID: POC:config
This register provides access to the four internal frame ID range filter boundary registers of the selected
receive FIFO. For details on frame ID range filter see Section 13.6.9.5, “Receive FIFO filtering”.
Table 13-72. RFRFCFR Field Descriptions
Field
15
WMD
14
IBD
Description
Write Mode — This control bit defines the write mode of this register.
0 Write to all fields in this register on write access.
1 Write to SEL and IBD field only on write access.
Interval Boundary — This control bit selects the interval boundary to be programmed with the SID value.
0 program lower interval boundary
1 program upper interval boundary
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Table 13-72. RFRFCFR Field Descriptions (continued)
Field
Description
13–12
SEL
Filter Selector — This control field selects the frame ID range filter to be accessed.
00 select frame ID range filter 0.
01 select frame ID range filter 1.
10 select frame ID range filter 2.
11 select frame ID range filter 3.
10–0
SID
Slot ID — Defines the IBD-selected frame ID boundary value for the SEL-selected range filter.
13.5.2.62 Receive FIFO Range Filter Control Register (RFRFCTR)
Module Base + 0x009A
15
14
13
12
0
0
0
0
0
0
0
0
R
W
Reset
11
10
9
8
F3MD F2MD F1MD F0MD
0
0
0
0
7
6
5
4
0
0
0
0
0
0
0
0
3
2
1
0
F3EN F2EN F1EN F0EN
0
0
0
0
Figure 13-62. Receive FIFO Range Filter Control Register (RFRFCTR)
Write: Anytime
This register is used to enable and disable each frame ID range filter and to define whether it is running as
acceptance or rejection filter.
Table 13-73. RFRFCTR Field Descriptions (Sheet 1 of 2)
Field
Description
11
F3MD
Range Filter 3 Mode — This control bit defines the filter mode of the frame ID range filter 3.
0 range filter 3 runs as acceptance filter
1 range filter 3 runs as rejection filter
10
F2MD
Range Filter 2 Mode — This control bit defines the filter mode of the frame ID range filter 2.
0 range filter 2 runs as acceptance filter
1 range filter 2 runs as rejection filter
9
F1MD
Range Filter 1 Mode — This control bit defines the filter mode of the frame ID range filter 1.
0 range filter 1 runs as acceptance filter
1 range filter 1 runs as rejection filter
8
F0MD
Range Filter 0 Mode — This control bit defines the filter mode of the frame ID range filter 0.
0 range filter 0 runs as acceptance filter
1 range filter 0 runs as rejection filter
3
F3EN
Range Filter 3 Enable — This control bit is used to enable and disable the frame ID range filter 3.
0 range filter 3 disabled
1 range filter 3 enabled
2
F2EN
Range Filter 2 Enable — This control bit is used to enable and disable the frame ID range filter 2.
0 range filter 2 disabled
1 range filter 2 enabled
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Table 13-73. RFRFCTR Field Descriptions (Sheet 2 of 2)
Field
Description
1
F1EN
Range Filter 1 Enable — This control bit is used to enable and disable the frame ID range filter 1.
0 range filter 1 disabled
1 range filter 1 enabled
0
F0EN
Range Filter 0 Enable — This control bit is used to enable and disable the frame ID range filter 0.
0 range filter 0 disabled
1 range filter 0 enabled
13.5.2.63 Last Dynamic Transmit Slot Channel A Register (LDTXSLAR)
Module Base + 0x009C
15
14
13
12
11
0
0
0
0
0
0
0
0
0
0
R
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
LASTDYNTXSLOTA
W
Reset
0
0
0
0
0
0
0
Figure 13-63. Last Dynamic Slot Channel A Register (LDTXSLAR)
This register provides the number of the last transmission slot in the dynamic segment for channel A. This
register is updated after the end of the dynamic segment and before the start of the next communication
cycle.
Table 13-74. LDTXSLAR Field Descriptions
Field
Description
10–0
Last Dynamic Transmission Slot Channel A — protocol related variable: zLastDynTxSlot channel A
LASTDYNTX Number of the last transmission slot in the dynamic segment for channel A. If no frame was transmitted during
SLOTA
the dynamic segment on channel A, the value of this field is set to 0.
13.5.2.64 Last Dynamic Transmit Slot Channel B Register (LDTXSLBR)
Module Base + 0x009E
15
14
13
12
11
0
0
0
0
0
0
0
0
0
0
R
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
LASTDYNTXSLOTB
W
Reset
0
0
0
0
0
0
0
Figure 13-64. Last Dynamic Slot Channel B Register (LDTXSLBR)
This register provides the number of the last transmission slot in the dynamic segment for channel B. This
register is updated after the end of the dynamic segment and before the start of the next communication
cycle.
Table 13-75. LDTXSLBR Field Descriptions
Field
Description
10–0
Last Dynamic Transmission Slot Channel B — protocol related variable: zLastDynTxSlot channel B
LASTDYNTX Number of the last transmission slot in the dynamic segment for channel B. If no frame was transmitted during
SLOTB
the dynamic segment on channel B the value of this field is set to 0.
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
13.5.2.65 Protocol Configuration Registers
The following configuration registers provide the necessary configuration information to the protocol
engine. The individual values in the registers are described in Table 13-76. For more details about the
FlexRay related configuration parameters and the allowed parameter ranges, see FlexRay Communications
System Protocol Specification, Version 2.1 Rev A.
Table 13-76. Protocol Configuration Register Fields (Sheet 1 of 2)
Description(1)
Name
coldstart_attempts
gColdstartAttempts
action_point_offset
gdActionPointOffset - 1
cas_rx_low_max
gdCASRxLowMax - 1
Min
Max
Unit
PCR
number
3
MT
0
gdBit
4
dynamic_slot_idle_phase
gdDynamicSlotIdlePhase
minislot
28
minislot_action_point_offset
gdMinislotActionPointOffset - 1
MT
3
minislot_after_action_point
gdMinislot - gdMinislotActionPointOffset - 1
MT
2
static_slot_length
gdStaticSlot
MT
0
static_slot_after_action_point
gdStaticSlot - gdActionPointOffset - 1
symbol_window_exists
gdSymbolWindow!=0
symbol_window_after_action_point
gdSymbolWindow - gdActionPointOffset - 1
tss_transmitter
MT
13
bool
9
MT
6
gdTSSTransmitter
gdBit
5
wakeup_symbol_rx_idle
gdWakeupSymbolRxIdle
gdBit
5
wakeup_symbol_rx_low
gdWakeupSymbolRxLow
gdBit
3
wakeup_symbol_rx_window
gdWakeupSymbolRxWindow
gdBit
4
wakeup_symbol_tx_idle
gdWakeupSymbolTxIdle
gdBit
8
wakeup_symbol_tx_low
gdWakeupSymbolTxLow
gdBit
5
noise_listen_timeout
(gListenNoise * pdListenTimeout) - 1
µT
16/17
macro_initial_offset_a
pMacroInitialOffset[A]
MT
6
macro_initial_offset_b
pMacroInitialOffset[B]
MT
16
macro_per_cycle
gMacroPerCycle
MT
10
macro_after_first_static_slot
gMacroPerCycle - gdStaticSlot
MT
1
macro_after_offset_correction
gMacroPerCycle - gOffsetCorrectionStart
MT
28
max_without_clock_correction_fatal
gMaxWithoutClockCorrectionFatal
cyclepairs
8
0
1
cyclepairs
8
bool
9
minislot
29
static slot
2
gOffsetCorrectionStart
MT
11
gPayloadLengthStatic
2-bytes
19
max_payload_length_dynamic
pPayloadLengthDynMax
2-bytes
24
first_minislot_action_point_offset
max(gdActionPointOffset,
gdMinislotActionPointOffset) - 1
MT
13
allow_halt_due_to_clock
pAllowHaltDueToClock
bool
26
allow_passive_to_active
pAllowPassiveToActive
cyclepairs
12
max_without_clock_correction_passive gMaxWithoutClockCorrectionPassive
minislot_exists
gNumberOfMinislots!=0
minislots_max
gNumberOfMinislots - 1
number_of_static_slots
gNumberOfStaticSlots
offset_correction_start
payload_length_static
0
1
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Chapter 13 FlexRay Communication Controller (FLEXRAY)
Table 13-76. Protocol Configuration Register Fields (Sheet 2 of 2)
Description(1)
Name
Min
Max
Unit
PCR
cluster_drift_damping
pClusterDriftDamping
µT
24
comp_accepted_startup_range_a
pdAcceptedStartupRange pDelayCompensationChA
µT
22
comp_accepted_startup_range_b
pdAcceptedStartupRange pDelayCompensationChB
µT
26
listen_timeout
pdListenTimeout - 1
µT
14/15
key_slot_id
pKeySlotId
number
18
key_slot_used_for_startup
pKeySlotUsedForStartup
bool
11
key_slot_used_for_sync
pKeySlotUsedForSync
bool
11
latest_tx
gNumberOfMinislots - pLatestTx
minislot
21
sync_node_max
gSyncNodeMax
number
30
micro_initial_offset_a
pMicroInitialOffset[A]
µT
20
micro_initial_offset_b
pMicroInitialOffset[B]
µT
20
micro_per_cycle
pMicroPerCycle
µT
22/23
micro_per_cycle_min
pMicroPerCycle - pdMaxDrift
µT
24/25
micro_per_cycle_max
pMicroPerCycle + pdMaxDrift
µT
26/27
micro_per_macro_nom_half
round(pMicroPerMacroNom / 2)
µT
7
offset_correction_out
pOffsetCorrectionOut
µT
9
rate_correction_out
pRateCorrectionOut
µT
14
single_slot_enabled
pSingleSlotEnabled
wakeup_channel
pWakeupChannel
wakeup_pattern
pWakeupPattern
decoding_correction_a
bool
see Table 13-77
10
10
number
18
pDecodingCorrection +
pDelayCompensation[A] + 2
µT
19
decoding_correction_b
pDecodingCorrection +
pDelayCompensation[B] + 2
µT
7
key_slot_header_crc
header CRC for key slot
number
12
extern_offset_correction
pExternOffsetCorrection
µT
29
0x000
0x7FF
µT
21
extern_rate_correction
pExternRateCorrection
1. See FlexRay Communications System Protocol Specification, Version 2.1 Rev A for detailed protocol parameter definitions
Table 13-77. Wakeup Channel Selection
wakeup_channel
Wakeup Channel
0
A
1
B
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13.5.2.65.1 Protocol Configuration Register 0 (PCR0)
Module Base + 0x00A0
15
14
R
12
11
10
9
8
7
6
action_point_offset
W
Reset
13
0
0
0
0
5
4
3
2
1
0
0
0
0
0
4
3
2
1
0
0
0
0
0
0
3
2
1
0
0
0
0
0
3
2
1
0
static_slot_length
0
0
0
0
0
0
0
0
Figure 13-65. Protocol Configuration Register 0 (PCR0)
Write: POC:config
13.5.2.65.2 Protocol Configuration Register 1 (PCR1)
Module Base + 0x00A2
R
15
14
0
0
0
0
13
12
11
10
9
7
6
5
macro_after_first_static_slot
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-66. Protocol Configuration Register 1 (PCR1)
Write: POC:config
13.5.2.65.3 Protocol Configuration Register 2 (PCR2)
Module Base + 0x00A4
15
R
13
12
11
10
9
8
7
minislot_after_action_point
W
Reset
14
0
0
0
0
0
6
5
4
number_of_static_slots
0
0
0
0
0
0
0
Figure 13-67. Protocol Configuration Register 2 (PCR2)
Write: POC:config
13.5.2.65.4 Protocol Configuration Register 3 (PCR3)
Module Base + 0x00A6
15
R
13
12
11
10
wakeup_symbol_rx_low
W
Reset
14
0
0
0
0
0
9
8
7
6
5
4
minislot_action_point_offset[4:0]
0
0
0
0
0
0
coldstart_attempts
0
0
0
0
0
Figure 13-68. Protocol Configuration Register 3 (PCR3)
Write: POC:config
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13.5.2.65.5 Protocol Configuration Register 4 (PCR4)
Module Base + 0x00A8
15
14
R
12
11
10
9
8
7
6
cas_rx_low_max
W
Reset
13
0
0
0
0
0
5
4
3
2
1
0
0
0
0
0
3
2
1
0
wakeup_symbol_rx_window
0
0
0
0
0
0
0
Figure 13-69. Protocol Configuration Register 4 (PCR4)
Write: POC:config
13.5.2.65.6 Protocol Configuration Register 5 (PCR5)
Module Base + 0x00AA
15
R
13
12
11
tss_transmitter
W
Reset
14
0
0
0
10
9
8
7
6
5
4
wakeup_symbol_tx_low
0
0
0
0
0
0
wakeup_symbol_rx_idle
0
0
0
0
0
0
0
3
2
1
0
Figure 13-70. Protocol Configuration Register 5 (PCR5)
Write: POC:config
13.5.2.65.7 Protocol Configuration Register 6 (PCR6)
Module Base + 0x00AC
15
R
14
13
0
0
11
10
9
8
7
6
5
4
symbol_window_after_action_point
W
Reset
12
0
0
0
0
0
0
macro_initial_offset_a
0
0
0
0
0
0
0
0
0
3
2
1
0
0
0
Figure 13-71. Protocol Configuration Register 6 (PCR6)
Write: POC:config
13.5.2.65.8 Protocol Configuration Register 7 (PCR7)
Module Base + 0x00AE
15
14
13
R
11
10
9
8
7
6
5
decoding_correction_b
W
Reset
12
0
0
0
0
0
0
4
micro_per_macro_nom_half
0
0
0
0
0
0
0
0
Figure 13-72. Protocol Configuration Register 7 (PCR7)
Write: POC:config
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13.5.2.65.9 Protocol Configuration Register 8 (PCR8)
Module Base + 0x00B0
15
R
W
Reset
14
13
12
11
max_without_clock_
correction_fatal
0
0
0
10
9
8
7
6
max_without_clock_
correction_passive
0
0
0
0
5
4
3
2
1
0
wakeup_symbol_tx_idle
0
0
0
0
0
0
0
0
0
Figure 13-73. Protocol Configuration Register 8 (PCR8)
Write: POC:config
13.5.2.65.10 Protocol Configuration Register 9 (PCR9)
Module Base + 0x00B2
15
14
13
12
11
10
9
8
sym
mini bol_
slot_ win
dow_
exists
W
exists
7
6
5
4
3
2
1
0
0
0
0
0
0
0
R
Reset
0
0
offset_correction_out
0
0
0
0
0
0
0
0
Figure 13-74. Protocol Configuration Register 9 (PCR9)
Write: POC:config
13.5.2.65.11 Protocol Configuration Register 10 (PCR10)
Module Base + 0x00B4
15
14
13
12
11
10
9
8
R single wake
_slot up_
W _en chan
abled nel
Reset
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
macro_per_cycle
0
0
0
0
0
0
0
0
Figure 13-75. Protocol Configuration Register 10 (PCR10)
Write: POC:config
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13.5.2.65.12 Protocol Configuration Register 11 (PCR11)
Module Base + 0x00B6
15
14
R key_
slot_
used_
W for_
start
up
Reset
0
13
12
11
10
9
key_
slot_
used_
for_
sync
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
3
2
1
0
0
0
0
0
3
2
1
0
0
0
0
0
3
2
1
0
offset_correction_start
0
0
0
0
0
0
0
0
0
Figure 13-76. Protocol Configuration Register 11 (PCR11)
Write: POC:config
13.5.2.65.13 Protocol Configuration Register 12 (PCR12)
Module Base + 0x00B8
15
R
13
12
11
10
9
8
7
allow_passive_to_active
W
Reset
14
0
0
0
0
6
5
4
key_slot_header_crc
0
0
0
0
0
0
0
0
Figure 13-77. Protocol Configuration Register 12 (PCR12)
Write: POC:config
13.5.2.65.14 Protocol Configuration Register 13 (PCR13)
Module Base + 0x00BA
15
R
13
12
11
10
9
8
7
first_minislot_action_point_offset
W
Reset
14
0
0
0
0
0
6
5
4
static_slot_after_action_point
0
0
0
0
0
0
0
Figure 13-78. Protocol Configuration Register 13 (PCR13)
Write: POC:config
13.5.2.65.15 Protocol Configuration Register 14 (PCR14)
Module Base + 0x00BC
15
14
13
12
R
10
9
8
7
6
5
4
rate_correction_out
W
Reset
11
0
0
0
0
0
0
0
listen_timeout[20:16]
0
0
0
0
0
0
0
0
0
Figure 13-79. Protocol Configuration Register 14 (PCR14)
Write: POC:config
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13.5.2.65.16 Protocol Configuration Register 15 (PCR15)
Module Base + 0x00BE
15
14
13
12
11
10
9
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
3
2
1
0
0
0
0
0
listen_timeout[15:0]
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-80. Protocol Configuration Register 15 (PCR15)
Write: POC:config
13.5.2.65.17 Protocol Configuration Register 16 (PCR16)
Module Base + 0x00C0
15
14
R
12
11
10
9
8
7
6
macro_initial_offset_b
W
Reset
13
0
0
0
0
0
5
4
noise_listen_timeout[24:16]
0
0
0
0
0
0
0
Figure 13-81. Protocol Configuration Register 16 (PCR16)
Write: POC:config
13.5.2.65.18 Protocol Configuration Register 17 (PCR17)
Module Base + 0x00C2
15
14
13
12
11
10
R
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
3
2
1
0
0
0
0
0
noise_listen_timeout[15:0]
W
Reset
9
0
0
0
0
0
0
0
0
0
0
Figure 13-82. Protocol Configuration Register 17 (PCR17)
Write: POC:config
13.5.2.65.19 Protocol Configuration Register 18 (PCR18)
Module Base + 0x00C4
15
14
R
12
11
10
9
8
7
6
wakeup_pattern
W
Reset
13
0
0
0
0
5
4
key_slot_id
0
0
0
0
0
0
0
0
Figure 13-83. Protocol Configuration Register 18 (PCR18)
Write: POC:config
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13.5.2.65.20 Protocol Configuration Register 19 (PCR19)
Module Base + 0x00C6
15
14
13
R
11
10
9
8
7
6
5
4
decoding_correction_a
W
Reset
12
0
0
0
0
0
0
3
2
1
0
payload_length_static
0
0
0
0
0
0
0
0
0
0
3
2
1
0
0
0
0
0
Figure 13-84. Protocol Configuration Register 19 (PCR19)
Write: POC:config
13.5.2.65.21 Protocol Configuration Register 20 (PCR20)
Module Base + 0x00C8
15
14
R
12
11
10
9
8
7
6
5
micro_initial_offset_b
W
Reset
13
0
0
0
0
0
0
4
micro_initial_offset_a
0
0
0
0
0
0
Figure 13-85. Protocol Configuration Register 20 (PCR20)
Write: POC:config
13.5.2.65.22 Protocol Configuration Register 21 (PCR21)
Module Base + 0x00CA
15
R
W
Reset
14
13
12
11
10
9
8
7
extern_rate_
correction
0
0
6
5
4
3
2
1
0
0
0
0
0
0
0
3
2
1
0
latest_tx
0
0
0
0
0
0
0
0
Figure 13-86. Protocol Configuration Register 21 (PCR21)
Write: POC:config
13.5.2.65.23 Protocol Configuration Register 22 (PCR22)
Module Base + 0x00CC
15
R
W
Reset
14
13
12
R*
0
11
10
9
8
7
6
5
4
comp_accepted_startup_range_a
0
0
0
0
0
0
0
0
micro_per_cycle[19:16
0
0
0
0
0
0
0
Figure 13-87. Protocol Configuration Register 22 (PCR22)
Write: POC:config
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13.5.2.65.24 Protocol Configuration Register 23 (PCR23)
Module Base + 0x00CE
15
14
13
12
11
10
R
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
3
2
1
0
micro_per_cycle[15:0]
W
Reset
9
0
0
0
0
0
0
0
0
0
0
Figure 13-88. Protocol Configuration Register 23 (PCR23)
Write: POC:config
13.5.2.65.25 Protocol Configuration Register 24 (PCR24)
Module Base + 0x00D0
15
R
13
12
11
10
cluster_drift_damping
W
Reset
14
0
0
0
0
9
8
7
6
5
4
micro_per_cycle_min
[19:16]
max_payload_length_dynamic
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-89. Protocol Configuration Register 24 (PCR24)
Write: POC:config
13.5.2.65.26 Protocol Configuration Register 25 (PCR25)
Module Base + 0x00D2
15
14
13
12
11
10
R
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
3
2
1
0
micro_per_cycle_min[15:0]
W
Reset
9
0
0
0
0
0
0
0
0
0
0
Figure 13-90. Protocol Configuration Register 25 (PCR25)
Write: POC:config
13.5.2.65.27 Protocol Configuration Register 26 (PCR26)
Module Base + 0x00D4
15
14
13
12
R allow
_halt_
W due
_to_
clock
Reset
0
11
10
9
8
7
6
5
4
micro_per_cycle_max
[19:16]
comp_accepted_startup_range_b
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-91. Protocol Configuration Register 26 (PCR26)
Write: POC:config
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13.5.2.65.28 Protocol Configuration Register 27 (PCR27)
Module Base + 0x00D6
15
14
13
12
11
10
R
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
4
3
2
1
0
0
0
0
0
0
4
3
2
1
0
0
0
0
0
0
3
2
1
0
micro_per_cycle_max[15:0]
W
Reset
9
0
0
0
0
0
0
0
0
0
0
Figure 13-92. Protocol Configuration Register 27 (PCR27)
Write: POC:config
13.5.2.65.29 Protocol Configuration Register 28 (PCR28)
Module Base + 0x00D8
15
14
13
12
11
10
9
R dynamic_slot
W _idle_phase
Reset
0
0
8
7
6
5
macro_after_offset_correction
0
0
0
0
0
0
0
0
0
Figure 13-93. Protocol Configuration Register 28 (PCR28)
Write: POC:config
13.5.2.65.30 Protocol Configuration Register 29 (PCR29)
Module Base + 0x00DA
15
R
W
Reset
14
13
12
11
10
9
8
extern_offset_
correction
0
0
0
7
6
5
minislots_max
0
0
0
0
0
0
0
0
Figure 13-94. Protocol Configuration Register 29 (PCR29)
Write: POC:config
13.5.2.65.31 Protocol Configuration Register 30 (PCR30)
Module Base + 0x00DC
R
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
sync_node_max
W
Reset
0
0
0
0
Figure 13-95. Protocol Configuration Register 30 (PCR30)
Write: POC:config
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13.5.2.66 Message Buffer Configuration, Control, Status Registers (MBCCSRn)
Module Base + 0x0100 (MBCCSR0)
Module Base + 0x0108 (MBCCSR1)
...
Module Base + 0x01F8 (MBCCSR31)
Additional Reset: CMT, DUP, DVAL, MBIF: Message Buffer Disable
15
R
0
W
Reset
0
14
13
12
MCM
MBT
MTD
0
0
0
11
10
9
CMT
0
0
rwm
EDT
LCKT
0
0
0
8
MBIE
0
7
6
5
4
3
0
0
0
DUP
DVAL
0
0
0
0
0
2
1
0
EDS LCKS MBIF
w1c
0
0
0
Figure 13-96. Message Buffer Configuration, Control, Status Registers (MBCCSRn)
Write: MCM, MBT, MTD: POC:config or MB_DIS
CMT: MB_LCK
EDT, LCKT, MBIE, MBIF: Normal Mode
The content of these registers comprises message buffer configuration data, message buffer control data,
message buffer status information, and message buffer interrupt flags.
Table 13-78. MBCCSRn Field Descriptions (Sheet 1 of 3)
Field
Description
Message Buffer Configuration
14
MCM
Message Buffer Commit Mode — This bit applies only to double buffered transmit message buffers and defines
the commit mode.
0 Streaming commit mode
1 Immediate commit mode
13
MBT
Message Buffer Type — This bit applies only to transmit message buffers and defines the buffering type.
0 Single buffered transmit message buffer
1 Double buffered transmit message buffer
12
MTD
Message Buffer Transfer Direction — This bit defines the transfer direction of the message buffer.
0 Receive message buffer
1 Transmit message buffer
Message Buffer Control
11
CMT
Commit for Transmission — This bit applies only to transmit message buffers and indicates whether the
message buffer contains valid data that are ready for transmission. Both the application and the FlexRay block
can modify this bit.
• Application: The application sets this bit to indicate that the transmit message buffer contains valid data ready
for transmission. The application clears this bit to indicate that the message buffer data are no longer valid for
transmission.
• FlexRay block: The FlexRay block clears this bit when the message buffer data are no longer valid for
transmission.
0 Message buffer does not contain valid data.
1 Message buffer contains valid data.
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Table 13-78. MBCCSRn Field Descriptions (Sheet 2 of 3)
Field
Description
10
EDT
Enable/Disable Trigger — This trigger bit is used to enable and disable a message buffer. The message buffer
enable is triggered when the application writes 1 to this bit and the message buffer is disabled, i.e. the EDS status
bit is 0. The message buffer disable is triggered when the application writes 1 to this bit and the message buffer
is enabled, i.e. the EDS status bit is 1.
0 No effect
1 message buffer enable/disable triggered
Note: If the application writes 1 to this bit, the write access to all other bits is ignored.
9
LCKT
Lock/Unlock Trigger — This trigger bit is used to lock and unlock a message buffer. The message buffer lock
is triggered when the application writes 1 to this bit and the message buffer is not locked, i.e. the LCKS status
bit is 0. The message buffer unlock is triggered when the application writes 1 to this bit and the message buffer
is locked, i.e. the LCKS status bit is 1.
0 No effect
1 Trigger message buffer lock/unlock
Note: If the application writes 1 to this bit and 0 to the EDT bit, the write access to all other bits is ignored.
8
MBIE
Message Buffer Interrupt Enable — This control bit defines whether the message buffer will generate an
interrupt request when its MBIF flag is set.
0 Interrupt request generation disabled
1 Interrupt request generation enabled
Message Buffer Status
4
DUP
Data Updated — This status bit applies only to receive message buffers. It is always 0 for transmit message
buffers. This bit provides information whether the frame header in the message buffer header field and the
message buffer data field were updated. See Section 13.6.6.3.3, “Message Buffer Status Update” for a detailed
description of the update condtions.
0 Frame Header and Message buffer data field not updated.
1 Frame Header and Message buffer data field updated.
3
DVAL
Data Valid — The semantic of this status bit depends on the message buffer type and transfer direction.
• Receive Message Buffer: Indicates whether the message buffer data field contains valid frame data. See
Section 13.6.6.3.3, “Message Buffer Status Update” for a detailed update description of the update conditions.
0 message buffer data field contains no valid frame data
1 message buffer data field contains valid frame data
• Single Transmit Message Buffer: Indicates whether the message is transferred again due to the state
transmission mode of the message buffer.
0 Message transferred for the first time.
1 Message will be transferred again.
• Double Transmit Message Buffer: For the commit side it is always 0. For the transmit side it indicates whether
the message is transferred again due to the state transmission mode of the message buffer.
0 Message transferred for the first time.
1 Message will be transferred again.
2
EDS
Enable/Disable Status — This status bit indicates whether the message buffer is enabled or disabled.
0 Message buffer is disabled.
1 Message buffer is enabled.
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Table 13-78. MBCCSRn Field Descriptions (Sheet 3 of 3)
Field
Description
1
LCKS
Lock Status — This status bit indicates the current lock status of the message buffer.
0 Message buffer is not locked by the application.
1 Message buffer is locked by the application.
0
MBIF
Message Buffer Interrupt Flag — The semantic of this flag depends on the message buffer transfer direction.
• Receive Message Buffer: This flag is set when the slot status in the message buffer header field was updated
and this slot was not an empty dynamic slot. See Section 13.6.6.3.3, “Message Buffer Status Update” for a
detailed description of the update conditions.
0 slot status not updated
1 slot status updated and slot was not an empty dynamic slot
• Transmit Message Buffer: This flag is set when the slot status in the message buffer header field was updated.
Additionally this flag is set immediately when a transmit message buffer was enabled.
0 slot status not updated
1 slot status updated / message buffer just enabled
13.5.2.67 Message Buffer Cycle Counter Filter Registers (MBCCFRn)
Module Base + 0x0102 (MBCCFR0)
Module Base + 0x010A (MBCCFR1)
...
Module Base + 0x01FA (MBCCFR31)
R
W
15
14
MTM
CHA
-
-
Reset
13
12
11
10
CHB CCFE
-
9
8
7
6
5
4
CCFMSK
-
-
-
-
-
3
2
1
0
-
-
CCFVAL
-
-
-
-
-
-
Figure 13-97. Message Buffer Cycle Counter Filter Registers (MBCCFRn)
Write: POC:config or MB_DIS
This register contains message buffer configuration data for the transmission mode, the channel
assignment, and for the cycle counter filtering. For detailed information on cycle counter filtering, refer to
Section 13.6.7.1, “Message Buffer Cycle Counter Filtering”.
Table 13-79. MBCCFRn Field Descriptions
Field
Description
15
MTM
Message Buffer Transmission Mode — This control bit applies only to transmit message buffers and defines
the transmission mode.
0 Event transmission mode
1 State transmission mode
14–13
CHA
CHB
Channel Assignment — These control bits define the channel assignment and control the receive and transmit
behavior of the message buffer according to Table 13-80.
12
CCFE
Cycle Counter Filtering Enable — This control bit is used to enable and disable the cycle counter filtering.
0 Cycle counter filtering disabled
1 Cycle counter filtering enabled
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Table 13-79. MBCCFRn Field Descriptions
Field
Description
11–6
CCFMSK
Cycle Counter Filtering Mask — This field defines the filter mask for the cycle counter filtering.
5–0
CCFVAL
Cycle Counter Filtering Value — This field defines the filter value for the cycle counter filtering.
.
Table 13-80. Channel Assignment Description
Transmit Message Buffer
CHA
Receive Message Buffer
CHB
static segment
dynamic segment
static segment
dynamic segment
1
1
transmit on both channel A transmit on channel A only store first valid frame
and channel B
received on either
channel A or channel B
store first valid frame
received on channel A,
ignore channel B
0
1
transmit on channel B
transmit on channel B
store first valid frame
received on channel B
store first valid frame
received on channel B
1
0
transmit on channel A
transmit on channel A
store first valid frame
received on channel A
store first valid frame
received on channel A
0
0
no frame transmission
no frame transmission
no frame stored
no frame stored
NOTE
If at least one message buffer assigned to a certain slot is assigned to both
channels, then all message buffers assigned to this slot have to be assigned
to both channels. Otherwise, the message buffer configuration is illegal and
the result of the message buffer search is not defined.
13.5.2.68 Message Buffer Frame ID Registers (MBFIDRn)
Module Base + 0x0104 (MBFIDR0)
Module Base + 0x010C (MBFIDR1)
...
Module Base + 0x01FC (MBFIDR31)
R
15
14
13
12
11
0
0
0
0
0
0
0
0
0
0
10
9
8
7
6
4
3
2
1
0
-
-
-
-
-
FID
W
Reset
5
-
-
-
-
-
-
Figure 13-98. Message Buffer Frame ID Registers (MBFIDRn)
Write: POC:config or MB_DIS
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Table 13-81. MBFIDRn Field Descriptions
Field
Description
10–0
FID
Frame ID — The semantic of this field depends on the message buffer transfer type.
• Receive Message Buffer: This field is used as a filter value to determine if the message buffer is used for
reception of a message received in a slot with the slot ID equal to FID.
• Transmit Message Buffer: This field is used to determine the slot in which the message in this message buffer
should be transmitted.
13.5.2.69 Message Buffer Index Registers (MBIDXRn)
Module Base + 0x0106 (MBIDXR0)
Module Base + 0x010E (MBIDXR1)
...
Module Base + 0x01FE (MBIDXR31)
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
5
4
2
1
0
-
-
MBIDX
W
Reset
3
-
-
-
-
Figure 13-99. Message Buffer Index Registers (MBIDXRn)
Write: POC:config or MB_DIS
Table 13-82. MBIDXRn Field Descriptions
Field
5–0
MBIDX
Description
Message Buffer Index — This field provides the index of the message buffer header field of the physical
message buffer that is currently associated with this message buffer.
The application writes the index of the initially associated message buffer header field into this register. The
FlexRay block updates this register after frame reception or transmission.
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13.6
Functional Description
This section provides a detailed description of the functionality implemented in the FlexRay block.
13.6.1
Message Buffer Concept
The FlexRay block uses a data structure called message buffer to store frame data, configuration, control,
and status data. Each message buffer consists of two parts, the message buffer control data and the physical
message buffer. The message buffer control data are located in dedicated registers. The structure of the
message buffer control data depends on the message buffer type and is described in Section 13.6.3,
“Message Buffer Types”. The physical message buffer is located in the FRM and is described in
Section 13.6.2, “Physical Message Buffer”.
13.6.2
Physical Message Buffer
All FlexRay messages and related frame and slot status information of received frames and of frames to
be transmitted to the FlexRay bus are stored in data structures called physical message buffers. The
physical message buffers are located in the FRM.The structure of a physical message buffer is depicted in
Figure 13-100.
A physical message buffer consists of two fields, the message buffer header field and the message buffer
data field. The message buffer header field contains the frame header, the data field offset, and the slot
status.The message buffer data field contains the frame data.
The connection between the two fields is established by the data field offset.
System Memory
SADR_MBDF
Frame Data
Message Buffer Data Field
SADR_MBHF
Frame Header
Data Field Offset
Slot Status
Message Buffer Header Field
Figure 13-100. Physical Message Buffer Structure
13.6.2.1
Message Buffer Header Field
The message buffer header field is a contiguous region in the FRM and occupies ten bytes. It contains the
frame header, the data field offset, and the slot status. Its structure is shown in Figure 13-100. The physical
start address SADR_MBHF of the message buffer header field must be 16-bit aligned.
13.6.2.1.1
Frame Header
The frame header occupies the first six bytes in the message buffer header field. It contains all FlexRay
frame header related information according to the FlexRay Communications System Protocol
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Specification, Version 2.1 Rev A. A detailed description of the usage and the content of the frame header
is provided in Section 13.6.5.2.1, “Frame Header Section Description”.
13.6.2.1.2
Data Field Offset
The data field offset follows the frame header in the message buffer data field and occupies two bytes. It
contains the offset of the corresponding message buffer data field with respect to the FlexRay block FRM
base address as provided by SYS_MEM_BASE_ADDR field in the System Memory Base Address High
Register (SYMBADHR) and System Memory Base Address Low Register (SYMBADLR)”. The data field
offset is used to determine the start address SADR_MBDF of the corresponding message buffer data field in
the FRM according to Equation 13-2.
SADR_MBDF = [Data Field Offset] + SYS_MEM_BASE_ADDR
13.6.2.1.3
Eqn. 13-2
Slot Status
The slot status occupies the last two bytes of the message buffer header field. It provides the slot and frame
status related information according to the FlexRay Communications System Protocol Specification,
Version 2.1 Rev A. A detailed description of the content and usage of the slot status is provided in
Section 13.6.5.2.3, “Slot Status Description”.
13.6.2.2
Message Buffer Data Field
The message buffer data field is a contiguous area of 2-byte entities. This field contains the frame payload
data, or a part of it, of the frame to be transmitted to or received from the FlexRay bus. The minimum length
of this field depends on the specific message buffer configuration and is specified in the message buffer
descriptions given in Section 13.6.3, “Message Buffer Types”.
13.6.3
Message Buffer Types
The FlexRay block provides three different types of message buffers.
• Individual Message Buffers
• Receive Shadow Buffers
• Receive FIFO Buffers
For each message buffer type the structure of the physical message buffer is identical. The message buffer
types differ only in the structure and content of message buffer control data, which control the related
physical message buffer. The message buffer control data are described in the following sections.
13.6.3.1
Individual Message Buffers
The individual message buffers are used for all types of frame transmission and for dedicated frame
reception based on individual filter settings for each message buffer. The FlexRay block supports three
types of individual message buffers, which are described in Section 13.6.6, “Individual Message Buffer
Functional Description”.
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Each individual message buffer consists of two parts, the physical message buffer, which is located in the
FRM, and the message buffer control data, which are located in dedicated registers. The structure of an
individual message buffer is given in Figure 13-101.
Each individual message buffer has a message buffer number n assigned, which determines the set of
message buffer control registers associated to this individual message buffer. The individual message
buffer with message buffer number n is controlled by the registers MBCCSRn, MBCCFRn, MBFIDRn,
and MBIDXRn.
The connection between the message buffer control registers and the physical message buffer is
established by the message buffer index field MBIDX in the Message Buffer Index Registers (MBIDXRn).
The start address SADR_MBHF of the related message buffer header field in the FRM is determined
according to Equation 13-3.
SADR_MBHF = (MBIDXRn[MBIDX] * 10) + SYS_MEM_BASE_ADDR
Eqn. 13-3
(min) MBDSR[MBSEG1DS] * 2 bytes / MBDSR[MBSEG2DS] * 2 bytes
System Memory
SADR_MBDF
Frame Data
Message Buffer Data Field
SADR_MBHF
Frame Header
Data Field Offset
Slot Status
Message Buffer Header Field
MBCCSRn
MBCCFRn
MBFIDRn
MBIDXRn
Message Buffer Control Registers
Figure 13-101. Individual Message Buffer Structure
13.6.3.1.1
Individual Message Buffer Segments
The set of the individual message buffers can be split up into two message buffer segments using the
Message Buffer Segment Size and Utilization Register (MBSSUTR). All individual message buffers with
a message buffer number n <= MBSSUTR.LAST_MB_SEG1 belong to the first message buffer segment.
All individual message buffers with a message buffer number n > MBSSUTR.LAST_MB_SEG1 belong
to the second message buffer segment. The following rules apply to the length of the message buffer data
field:
• all physical message buffers associated to individual message buffers that belong to the same
message buffer segment must have message buffer data fields of the same length
• the minimum length of the message buffer data field for individual message buffers in the first
message buffer segment is 2 * MBDSR.MBSEG1DS bytes
• the minimum length of the message buffer data field for individual message buffers assigned to the
second segment is 2 * MBDSR.MBSEG2DS bytes.
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13.6.3.2
Receive Shadow Buffers
The receive shadow buffers are required for the frame reception process for individual message buffers.
The FlexRay block provides four receive shadow buffers, one receive shadow buffer per channel and per
message buffer segment.
Each receive shadow buffer consists of two parts, the physical message buffer located in the FRM and the
receive shadow buffer control registers located in dedicated registers. The structure of a receive shadow
buffer is shown in Figure 13-102. The four internal shadow buffer control registers can be accessed by the
Receive Shadow Buffer Index Register (RSBIR).
The connection between the receive shadow buffer control register and the physical message buffer for the
selected receive shadow buffer is established by the receive shadow buffer index field RSBIDX in the
Receive Shadow Buffer Index Register (RSBIR). The start address SADR_MBHF of the related message
buffer header field in the FRM is determined according to Equation 13-4.
SADR_MBHF = (RSBIR[RSBIDX] * 10) + SYS_MEM_BASE_ADDR
Eqn. 13-4
The length required for the message buffer data field depends on the message buffer segment that the
receive shadow buffer is assigned to. For the receive shadow buffers assigned to the first message buffer
segment, the length must be the same as for the individual message buffers assigned to the first message
buffer segment. For the receive shadow buffers assigned to the second message buffer segment, the length
must be the same as for the individual message buffers assigned to the second message buffer segment.
The receive shadow buffer assignment is described in Receive Shadow Buffer Index Register (RSBIR).
(min) MBDSR[MBSEG1DS] * 2 bytes / MBDSR[MBSEG2DS] * 2 bytes
System Memory
SADR_MBDF
Frame Data
Message Buffer Data Field
SADR_MBHF
Frame Header
Data Field Offset
Slot Status
Message Buffer Header Field
RSBIDX[0]
RSBIDX[1]
RSBIDX[2]
RSBIDX[3]
Receive Shadow Buffer Control Register
Figure 13-102. Receive Shadow Buffer Structure
13.6.3.3
Receive FIFO
The receive FIFO implements a frame reception system based on the FIFO concept. The FlexRay block
provides two independent receive FIFOs, one per channel.
A receive FIFO consists of a set of physical message buffers in the FRM and a set of receive FIFO control
registers located in dedicated registers. The structure of a receive FIFO is given in Figure 13-103.
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The connection between the receive FIFO control registers and the set of physical message buffers is
established by the start index field SIDX in the Receive FIFO Start Index Register (RFSIR), the FIFO
depth field FIFO_DEPTH in the Receive FIFO Depth and Size Register (RFDSR), and the read index field
RDIDX Receive FIFO A Read Index Register (RFARIR) / Receive FIFO B Read Index Register
(RFBRIR). The start address SADR_MBHF_1 of the first message buffer header field that belongs to the
receive FIFO in the FRM is determined according to Equation 13-5.
SADR_MBHF[1] = (RFSIR[SIDX] * 10) + SYS_MEM_BASE_ADDR
Eqn. 13-5
The start address SADR_MBHF[n] of the last message buffer header field that belongs to the receive FIFO
in the FRM is determined according to Equation 13-6.
SADR_MBHF[n] = ((RFSIR[SIDX] + RFDSR[FIFO_DEPTH]) * 10) + SYS_MEM_BASE_ADDR
Eqn. 13-6
NOTE
All message buffer header fields assigned to a receive FIFO must be a
contiguous region.
(min) RFDSR[ENTRY_SIZE] * 2 bytes
RFDSR[FIFO_DEPTH]
SADR_MBDF[n]
Frame Data[n]
SADR_MBDF[i]
Frame Data[i]
Frame Data[1]
Message Buffer Data Fields
SADR_MBHF[n]
+
Frame Header[n]
Data Field Offset[n]
Slot Status[n]
Frame Header[i]
Data Field Offset[i]
Slot Status[i]
Frame Header[1]
Data Field Offset[1]
Slot Status[1]
SADR_MBHF[i]
SADR_MBHF[1]
RFDSR[FIFO_DEPTH]
System Memory
SADR_MBDF[1]
Message Buffer Header Fields
RFDSR[A]
RFDSR[B]
RFSIR[A]
RFSIR[B]
RFARIR
RFBRIR
Receive FIFO Control Register
Figure 13-103. Receive FIFO Structure
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13.6.3.4
Message Buffer Configuration and Control Data
This section describes the configuration and control data for each message buffer type.
13.6.3.4.1
Individual Message Buffer Configuration Data
Before an individual message buffer can be used for transmission or reception, it must be configured. There
is a set of common configuration parameters that applies to all individual message buffers and a set of
configuration parameters that applies to each message buffer individually.
Common Configuration Data
The set of common configuration data for individual message buffers is located in the following registers.
• Message Buffer Data Size Register (MBDSR)
The MBSEG2DS and MBSEG1DS fields define the minimum length of the message buffer data
field with respect to the message buffer segment.
• Message Buffer Segment Size and Utilization Register (MBSSUTR)
The LAST_MB_SEG1 and LAST_MB_UTIL fields define the segmentation of the individual
message buffers and the number of individual message buffers that are used. For more details, see
Section 13.6.3.1.1, “Individual Message Buffer Segments”
Specific Configuration Data
The set of message buffer specific configuration data for individual message buffers is located in the
following registers.
• Message Buffer Configuration, Control, Status Registers (MBCCSRn)
The MCM, MBT, MTD bits configure the message buffer type.
• Message Buffer Cycle Counter Filter Registers (MBCCFRn)
The MTM, CHA, CHB bits configure the transmission mode and the channel assignment. The
CCFE, CCFMSK, and CCFVAL bits and fields configure the cycle counter filter.
• Message Buffer Frame ID Registers (MBFIDRn)
For a transmit message buffer, the FID field is used to determine the slot in which the message in
this message buffer will be transmitted.
• Message Buffer Index Registers (MBIDXRn)
This MBIDX field provides the index of the message buffer header field of the physic