ICST ICS671-15 Zero delay, low skew buffer Datasheet

ICS671-15
ZERO DELAY, LOW SKEW BUFFER
Description
Features
The ICS671-15 is a low-jitter, low-skew,
high-performance zero delay buffer (ZDB) for
high-speed applications. The device is designed using
ICS’ proprietary low-jitter PLL (Phase-Locked Loop)
techniques. The ICS671-15 includes a ZDB bank of
four outputs running at 33 MHz, and two outputs at 66
MHz from the CPU PLL. This device also provides two
66 MHz zero delay clocks derived from the AGP PLL. In
the zero delay mode, the rising edge of the input clock
is aligned with the rising edges of the feedback clock.
The ICS671-15 provides feedback clocks internally for
the CPU PLL and the AGP PLL, and with the lowest
jitter.
• Packaged in 24-pin TSSOP
• Input-output delay (±300 ps)
• Two ZDB 66 MHz outputs from a 66 MHz input AGP
clock
• Two ZDB 66 MHz outputs, plus four 33 MHz outputs
from a 33 MHz input CPU clock
• Output-to-output skew is less than 250 ps
• Full CMOS outputs with 18 mA output drive
capability at TTL levels (at 3.3 V)
• Spread SmartTM technology works with spread
spectrum clock generators
• Advanced, low-power, sub-micron CMOS process
• Operating voltage of 3.3 V
• Separate hardware output enable pins: OE1, OE2,
OE3, OE4, OE5 and OE6
Block Diagram
VDD
4
OE6
66M_AGPOUT2
AGP PLL
66M_IN
66M_AGPOUT1
33M_IN
OE5
66M_CPUOUT2
CPU PLL
66M_CPUOUT1
OE4
OE3
/2
33M_PCIOUT4
OE2
33M_PCIOUT3
33M_PCIOUT2
33M_PCIOUT1
OE1
4
GND
1
MDS 671-15 B
I n t e gra te d C i r c u i t S y s t e m s
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ICS671-15
ZERO DELAY, LOW SKEW BUFFER
Pin Assignment
33M_IN
1
24
66M_IN
VDD
2
23
OE6
OE5
3
22
VDD
GND
4
21
66M_AGPOUT2
66M_CPUOUT1
5
20
66M_AGPOUT1
66M_CPUOUT2
6
19
GND
VDD
7
18
GND
VDD
8
17
OE4
OE3
9
16
OE1
33M_PCIOUT4
10
15
GND
33M_PCIOUT3
11
14
33M_PCIOUT1
OE2
12
13
33M_PCIOUT2
24-pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
33M_IN
Input
Connect this pin to a 33 MHz input clock.
2
VDD
Power
Connect to +3.3 V.
3
OE5
Input
Output Enable control pin for outputs 66M_CPUOUT2. This pin is active
high and tri-states the outputs when low.
4
GND
Power
Connect to ground.
5
66M_CPUOUT1
Output
66 MHz output clock.
6
66M_CPUOUT2
Output
66 MHz output clock.
7
VDD
Power
Connect to +3.3 V.
8
VDD
Power
Connect to +3.3 V.
9
OE3
Input
Output Enable control pin for output 33M_PCIOUT4. This pin is active
high and tri-states the outputs when low.
10
33M_PCIOUT4
Output
33 MHz output clock.
11
33M_PCIOUT3
Output
33 MHz output clock.
12
OE2
Input
13
33M_PCIOUT2
Output
Output Enable control pin for output 33M_PCIOUT3. This pin is active
high and tri-states the outputs when low.
33 MHz output clock.
2
MDS 671-15 B
In te grated Circuit Systems
Pin Description
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ICS671-15
ZERO DELAY, LOW SKEW BUFFER
Pin
Number
Pin
Name
Pin
Type
Pin Description
14
33M_PCIOUT1
Output
33 MHz output clock.
15
GND
Power
Connect to ground.
16
OE1
Input
Output Enable control pin for output 33M_PCIOUT1 and
33M_PCIOUT2. This pin is active high and tri-states the outputs when
low.
17
OE4
Input
Output Enable control pin for outputs 66M_CPUOUT1. This pin is active
high and tri-states the outputs when low.
18
GND
Power
Connect to ground.
19
GND
Power
Connect to ground.
20
66M_AGPOUT1
Output
66 MHz output clock.
21
66M_AGPOUT2
Output
66 MHz output clock.
22
VDD
Power
Connect to +3.3 V.
23
OE6
Input
Output Enable control pin for outputs 66M_AGPOUT1 and
66M_AGPOUT2. This pin is active high and tri-states the outputs when
low.
24
66M_IN
Input
COnnect this pin to a 66 MHz input clock.
External Components
The ICS671-15 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1µF should be connected between VDD and GND, as close to the part as possible. A 33 Ω
series terminating resistor should be used on each clock output to reduce reflections.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS671-15. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
0 to +70 °C
Storage Temperature
-65 to +150 °C
Junction Temperature
125 °C
Soldering Temperature
260 °C
3
MDS 671-15 B
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
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ICS671-15
ZERO DELAY, LOW SKEW BUFFER
Recommended Operation Conditions
Parameter
Min.
Ambient Operating Temperature
Typ.
0
Power Supply Voltage (measured in respect to GND)
+3.135
3.3
Max.
Units
+70
°C
+3.465
V
DC Electrical Characteristics
VDD=3.3 V ±5%, Ambient temperature 0 to +70°C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
3.135
3.3
3.465
V
Operating Voltage
VDD
Input High Voltage
VIH
66M, 33M,
OE1:OE6
Input Low Voltage
VIL
66M, 33M
OE1:OE6
Output High Voltage
VOH
IOH = -12 mA
Output Low Voltage
VOL
IOL = 12 mA
Output High Voltage
VOH
IOH = -4 mA
Operating Supply Current
66M, 33M Input
IDD
No Load. both
inputs active
32
mA
Short Circuit Current
IOS
Each output
±50
mA
Input Capacitance
CIN
5
pF
2.0
V
0.8
2.4
V
V
0.4
VDD-0.4
V
V
AC Electrical Characteristics
VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C, CL=15 pF (Total)
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ.
Max. Units
FIN
33
66
MHz
Output Frequency
FOUT
33
66
MHz
Output Rise Time
tOR
0.8 to 2.0 V
1.5
ns
Output Fall Time
tOF
2.0 to 0.8 V
1.5
ns
50
55
%
Output Clock Duty Cycle
at VDD/2
Device-to-Device Skew
Rising edges at VDD/2
for similar outputs,
Note 1
500
700
ps
Rising edges at VDD/2
66M AGP outputs,
Note 1
250
500
ps
Output-to-Output Skew
4
MDS 671-15 B
In te grated Circuit Systems
tS
45
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525 Ra ce Street, San Jose, CA 9512 6
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ICS671-15
ZERO DELAY, LOW SKEW BUFFER
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Output-to-Output Skew
tS
Rising edges at VDD/2
66M CPU outputs,
Note 1
250
500
ps
Output-to-Output Skew
tS
Rising edges at VDD/2
33M PCI outputs,
Note 1
300
500
ps
Skew from output of 66M CPU to
33M PCI, equally loaded
tS
Rising edges at VDD/2
33M PCI outputs
300
500
ps
Short-term Jitter
tJA
pealk-to-peak
300
Input-to-Output Delay
tD
measured at VDD/2
ps
+500
ps
Stable power supply,
valid clocks on 66M and
33M
1
ms
Output Enable Time
(for OE1 to E6)
OE going from low to
high with stable output
1.0
ns
Output Disable Time
(for OE1 to E6)
OE going high to low
tri-state output
1.0
ns
PLL Lock Time
tLOCK
-500
Note 1: All outputs are equally loaded.
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Conditions
Min.
Typ.
●
Max. Units
θJA
Still air
77
°C/W
θJA
1 m/s air flow
68
°C/W
θJA
2 m/s air flow
66
°C/W
25
°C/W
θJC
5
MDS 671-15 B
In te grated Circuit Systems
Symbol
525 Ra ce Street, San Jose, CA 9512 6
Revision 021904
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ICS671-15
ZERO DELAY, LOW SKEW BUFFER
Package Outline and Package Dimensions (24-pin TSSOP, 4.4mm Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
24
Symbol
E1
Min
A
A1
A2
b
C
D
E
E1
e
L
α
aaa
E
INDEX
AREA
1 2
D
Inches
Max
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
7.70
7.90
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
-0.10
Min
Max
-0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.303
0.311
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0°
8°
-0.004
A
A2
A1
c
-Ce
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
Marking
Shipping
Packaging
Package
Temperature
ICS671G-15
ICS671G-15
Tubes
24-pin TSSOP
0 to 70° C
ICS671G-15T
ICS671G-15
Tape and Reel
24-pin TSSOP
0 to 70° C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit
Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of
third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended
temperature range, high reliability, or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice.
ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
6
MDS 671-15 B
I n t e gra te d C i r c u i t S y s t e m s
●
525 Race Stre et, San Jo se, CA 9 5126
Revision 021904
●
te l (40 8) 2 97-12 01
●
w w w. i c st . c o m
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