Features
• Incorporates the ARM926EJ-S™ ARM® Thumb® Processor
•
•
•
•
•
•
•
•
•
•
– DSP Instruction Extensions, ARM Jazelle® Technology for Java® Acceleration
– 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
– 220 MIPS at 200 MHz
– Memory Management Unit
– EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
Additional Embedded Memories
– One 32 Kbyte Internal ROM, Two-cycle Access at Maximum Matrix Speed
– One 32 Kbyte Internal SRAM, Single-cycle Access at Maximum Matrix Speed
External Bus Interface (EBI)
– EBI Supports Mobile DDR, SDRAM, Low Power SDRAM, Static Memory,
Synchronous CellularRAM, ECC-enabled NAND Flash and CompactFlash™
Metal Programmable (MP) Block
– 500,000 Gates/250,000 Gates Metal Programmable Logic (through 5 Metal Layers)
for AT91CAP9S500A/AT91CAP9S250A Respectively
– Ten 512 x 36-bit Dual Port RAMs
– Eight 512 x 72-bit Single Port RAMs
– High Connectivity for Up to Three AHB Masters and Four AHB Slaves
– Up to Seven AIC Interrupt Inputs
– Up to Four DMA Hardware Handshake Interfaces
– Delay Lines for Double Data Rate Interface
– UTMI+ Full Connection
– Up to 77 Dedicated I/Os
LCD Controller
– Supports Passive or Active Displays
– Up to 24 Bits per Pixel in TFT Mode, Up to 16 Bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Wider
Screen Buffers
Image Sensor Interface
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
USB 2.0 Full Speed (12 Mbits per second) OHCI Host Double Port
– Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
USB 2.0 High Speed (480 Mbits per second) Device Port
– On-chip Transceiver, 4 Kbyte Configurable Integrated DPRAM
– Integrated FIFOs and Dedicated DMA Channels
– Integrated UTMI+ Physical Interface
Ethernet MAC 10/100 Base T
– Media Independent Interface (MII) or Reduced Media Independent Interface (RMII)
– 128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
Multi-Layer Bus Matrix
– Twelve 32-bit-layer Matrix, Allowing a Maximum of 38.4 Gbps of On-chip Bus
Bandwidth at Maximum 100 MHz System Clock Speed
– Boot Mode Select Option, Remap Command
Fully-featured System Controller, Including
– Reset Controller, Shutdown Controller
Customizable
Microcontroller
Processor
AT91CAP9S500A
AT91CAP9S250A
Preliminary
6264C–CAP–24-Mar-09
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-Time Timer
Reset Controller (RSTC)
– Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control
Shutdown Controller (SHDC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
Clock Generator (CKGR)
– Selectable 32768 Hz Low-power Oscillator or Internal Low-power RC Oscillator on Battery Backup Power Supply,
Providing a Permanent Slow Clock
– 8 to 16 MHz On-chip Oscillator
– Two PLLs up to 240 MHz
– One USB 480 MHz PLL
Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Four Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention
Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
Real-Time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
Four 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC and PIOD)
– 128 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
DMA Controller (DMAC)
– Acts as one Bus Matrix Master
– Embeds 4 Unidirectional Channels with Programmable Priority, Address Generation, Channel Buffering and Control
– Supports Four External DMA Requests and Four Internal DMA Requests from the Metal Programmable Block (MPBlock)
Twenty-two Peripheral DMA Controller Channels (PDC)
One 2.0A and 2.0B Compliant CAN Controller
– 16 Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter
Two Multimedia Card Interfaces (MCI)
– SDCard/SDIO and MultiMedia™ Card 3.31 Compliant
– Supports SDHC Devices
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
Two Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
One AC97 Controller (AC97C)
– 6-channel Single AC97 Analog Front End Interface, Slot Assigner
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
•
•
•
•
•
•
•
•
•
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester
Encoding/Decoding
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
Two Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– Synchronous Communications at Up to 90 Mbits/sec
One Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
One Four-channel 20-bit PWM Controller (PWMC)
One Two-wire Interface (TWI)
– Master and Slave Mode Support, All Two-wire Atmel EEPROMs Supported
One 8-channel, 10-bit Analog-to-Digital Converter (ADC)
– Eight Channels Multiplexed with Digital I/Os
IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
Required Power Supplies:
– 1.08V to 1.32V for VDDCORE and VDDBU, VDDUPLL and VDDUTMIC
– 3.0V to 3.6V for VDDOSC, VDDPLL and VDDIOP0 (Peripheral I/Os) and VDDANA (ADC)
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOP1 (Peripheral I/Os), VDDIOM (Memory
I/Os) and VDDMPIOA/VDDMPIOB (MP Block I/Os)
Available in 400-ball LFBGA RoHS-compliant Package
Can also be Delivered in a 324-ball TFBGA RoHS-compliant Package According to User Needs
1. Description
The AT91CAP9S500A/AT91CAP9S250A family is based on the integration of an ARM926EJ-S
processor with fast ROM and SRAM memories, and a wide range of peripherals. By providing up
to 500K gates of metal programmable logic, AT91CAP9S500A/AT91CAP9S250A is the ideal
platform for creating custom designs.
The AT91CAP9S500A/AT91CAP9S250A embeds a USB High-speed Device, a 2-port USB
OHCI Host, an LCD Controller, a 4-channel DMA Controller, and one Image Sensor Interface. It
also integrates several standard peripherals, such as USART, SPI, TWI, Timer Counters, PWM
generators, Multimedia Card interface, and one CAN Controller.
The AT91CAP9S500A/AT91CAP9S250A is architectured on a 12-layer matrix, allowing a maximum internal bandwidth of twelve 32-bit buses. It also features one external memory bus (EBI)
capable of interfacing with a wide range of memory devices.
The AT91CAP9S500A/AT91CAP9S250A is packaged in a 400-ball LFBGA RoHS-compliant
package. It can also be delivered in a 324-ball TFBGA RoHS-compliant package according to
the customer’s requirements.
3
6264C–CAP–24-Mar-09
NRST
VDDCORE
VDDBU
SHDN
WKUP
XIN32
XOUT32
OSC
XIN
XOUT
MCI0
MCI1
PDC
POR
POR
OSC
PIT
RSTC
SHDC
RTT
4 GPREG
PLLB
PLLRCB
WDT
PLLA
PLLRCA
PMC
PDC
DBGU
MCI0_, MCI1_
TWI
PDC
PIOD
PIOC
PIOB
PIOA
USART0
USART1
USART2
PDC
DMA
FIFO
USB
High-Speed
Device
CAN
ROM
32Kbytes
DMA
USB
OHCI
SPI0
SPI1
PDC
SRAM
32Kbytes
DMA
Image
Sensor
Interface
PWMC
Peripheral
Bridge
TC0
TC1
TC2
FIFO
DMA
LUT
LCD
Controller
DMA
FIFO
AC97C
PDC
24-channel
Peripheral
DMA
PDC
8-channel
10-bit
ADC
4-channel
DMA
SSC0
SSC1
PDC
APB
12-layer Matrix
FIFO
10/100 Ethernet
MAC
V
B
PL G
HSLR
C
HSDP
D
F M
S
FSDP
DM
HD
HDPA
M
HD A
HDPB
M
IS B
I
IS _P
C
I
IS _DOK
I_
IS HS -IS
I
I
IS _V YN _D
I
_MSY C 11
LC CKNC
L D
D
C
0
LCDV -LC
S
LCDH YN DD
S
LCDD YNC 23
O
LCDD TCC
DCEN K
C
ER
ET XC
ECXE K-E
N T
ERRS -E XC
T
ERXE -EC XE K/E
R O
ET X0 -E L R REF
- R
CK
EMX0 ER XD
- X
EMDCETX 3 V
3
E DI
F
10 O
BM 0
S
SPI0_, SPI1_
In-Circuit Emulator
ICache
16K bytes
D
L
L
I
DCache
16K bytes
DDRSDR
Controller
CompactFlash
NAND Flash
& ECC
EBI
8x
SPR
512x72
10x
DPR
512x36
Static
Memory
Controller
Burst Cellular
Memory
Controller
Metal Programable Block
500K Gates (CAP9500)
250K Gates (CAP9250)
D
Bus Interface
MMU
ARM926EJ-S Processor
T
TWWD
CK
CT
R S0
SCTS0-CT
RD K0 -R S2
T
TXX0 -SCS2
- K
R
D
0- DX2
TX 2
D2
CA
CA NT
NRX
NP X
NPCS
NPCS3
NPCS2
C 1
SP S0
M CK
O
M SI
PW
IS
O
M
0PW
M
TC
3
L
TI K0
O TI A0 TC
O -T LK
B0 IO 2
-T A
IO 2
AC B2
AC97
AC 97CK
AC97 FS
9 RX
TK 7TX
T 0-T
TDF0- K1
RD 0-TTF1
DM
R 0-RD1
A
F
R
Q RK 0-RD1
0- 0 F
DM -R 1
A K1
R
AD Q3
0AD
AD 7
TR
IG
AD
VDVR
E
G DA F
ND N
ANA
A
DRXD
DTXD
PCK0-PCK3
AIC
O
A0
FIQ
IRQ0-IRQ1
D0
JTAG Boundary Scan
O
A3
1
Transc. Transc.
PI
UTMI+
Transc.
-M
System
Controller
M
PI
B
TST
O
PI
-D
3
CD
CK
TD
TDI
TMO
TC S
RTK
C
NT K
R
JT ST
AG
SE
L
M
SLAVE
4
B4
4
O
Note:
PI
NWAIT
A23-A24
NCS2
NCS3/NANDCS
NCS4/CFCS0
NCS5/CFCS1
A25/CFRNW
CFCE1-CFCE2
D16-D31
D0-D15
A0/NBS0
A1/NBS2/NWR2
A2-A15, A18-A22
A16/BA0
A17/BA1
NCS0
NCS1/BCCS
NRD
NWR0/NWE
NWR1/NBS1
NWR3/NBS3
SDCK, SDCKN
SDCS
DQS0, DQS1
SDCKE/BCCRE
RAS/BCADV, CAS/BCOE
SDWE/BCWE, SDA10
NANDOE, NANDWE
BCOWAIT
Figure 2-1.
0M
MASTER
2. AT91CAP9S500A/AT91CAP9S250A Block Diagram
AT91CAP9S500A/AT91CAP9S250A Block Diagram
1. For information on signal multiplexing refer to Table 22-3, “EBI Pins and External Device Connections”.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
3. Signal Description
Table 3-1 gives details on the signal name classified by peripheral.
Table 3-1.
Signal Description List
Signal Name
Function
Type
Active
Level
Comments
Power Supplies
VDDIOM
EBI I/O Lines Power Supply
Power
1.65V to 3.6V
VDDIOP0
Peripherals I/O Lines Power Supply
Power
3.0V to 3.6V
VDDIOP1
Peripherals I/O Lines Power Supply
Power
1.65V to 3.6V
VDDIOMPA
MP Block I/O A Lines Power Supply
Power
1.65V to 3.6V
VDDIOMPB
MP Block I/O B Lines Power Supply
Power
1.65V to 3.6V
VDDBU
Backup I/O Lines Power Supply
Power
1.08V to 1.32V
VDDPLL
PLL Power Supply
Power
3.0V to 3.6V
VDDUTMII
USB UTMI+ Interface Power Supply
Power
3.0V to 3.6V
VDDUTMIC
USB UTMI+ Core Power Supply
Power
1.08V to 1.32V
VDDUPLL
USB UTMI+ PLL Power Supply
Power
1.08V to 1.32V
VDDANA
ADC Analog Power Supply
Power
3.0V to 3.6V
VDDCORE
Core Chip Power Supply
Power
1.08V to 1.32V
GND
Ground
Ground
GNDPLL
PLL Ground
Ground
GNDUTMII
USB UTMI+ Interface Ground
Ground
GNDUTMIC
USB UTMI+ Core Ground
Ground
GNDUPLL
USB UTMI+ PLL Ground
Ground
GNDANA
ADC Analog Ground
Ground
GNDBU
Backup Ground
Ground
GNDTHERMAL
Thermal Ground Ball
Ground
Thermally coupled with
package substrate
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
Input
XOUT
Main Oscillator Output
XIN32
Slow Clock Oscillator Input
XOUT32
Slow Clock Oscillator Output
PLLRCA
PLL A Filter
Input
PLLRCB
PLL B Filter
Input
PCK0 - PCK3
Programmable Clock Output
Output
Input
Output
Output
Shutdown, Wakeup Logic
SHDN
Shutdown Control
WKUP
Wake-Up Input
Output
Do not tie over VDDBU
Input
Accept between 0V and
VDDBU
5
6264C–CAP–24-Mar-09
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Low
Comments
ICE and JTAG
NTRST
Test Reset Signal
Input
No pull-up resistor
TCK
Test Clock
Input
No pull-up resistor
TDI
Test Data In
Input
No pull-up resistor
TDO
Test Data Out
TMS
Test Mode Select
Input
No pull-up resistor
JTAGSEL
JTAG Selection
Input
Pull-down resistor
RTCK
Return Test Clock
Output
Output
Reset/Test
NRST
Microcontroller Reset
I/O
Low
Pull-up resistor
TST
Test Mode Select
Input
Pull-down resistor
BMS
Boot Mode Select
Input
Pull-up resistor
Debug Unit - DBGU
DRXD
Debug Receive Data
Input
DTXD
Debug Transmit Data
Output
Advanced Interrupt Controller - AIC
IRQ0 - IRQ1
External Interrupt Inputs
Input
FIQ
Fast Interrupt Input
Input
PIO Controller - PIOA - PIOB - PIOC - PIOD
PA0 - PA31
Parallel IO Controller A
I/O
Pulled-up input at reset
PB0 - PB31
Parallel IO Controller B
I/O
Pulled-up input at reset
PC0 - PC31
Parallel IO Controller C
I/O
Pulled-up input at reset
PD0 - PD31
Parallel IO Controller D
I/O
Pulled-up input at reset
Direct Memory Access Controller - DMA
DMARQ0-DMARQ3
DMA Requests
Input
External Bus Interface - EBI
D0 - D31
Data Bus
I/O
A0 - A25
Address Bus
NWAIT
External Wait Signal
Pulled-up input at reset
Output
Input
0 at reset
Low
Static Memory Controller - SMC
NCS0 - NCS5
Chip Select Lines
Output
Low
NWR0 - NWR3
Write Signal
Output
Low
NRD
Read Signal
Output
Low
NWE
Write Enable
Output
Low
NBS0 - NBS3
Byte Mask Signal
Output
Low
6
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Comments
CompactFlash Support
CFCE1 - CFCE2
CompactFlash Chip Enable
Output
Low
CFOE
CompactFlash Output Enable
Output
Low
CFWE
CompactFlash Write Enable
Output
Low
CFIOR
CompactFlash IO Read
Output
Low
CFIOW
CompactFlash IO Write
Output
Low
CFRNW
CompactFlash Read Not Write
Output
CFCS0 - CFCS1
CompactFlash Chip Select Lines
Output
Low
NAND Flash Support
NANDCS
NAND Flash Chip Select
Output
Low
NANDOE
NAND Flash Output Enable
Output
Low
NANDWE
NAND Flash Write Enable
Output
Low
DDR/SDRAM Controller
SDCK
DDR/SDRAM Clock
Output
SDCKN
DDR Inverted Clock
Output
DQS0 - DQS1
DDR Data Qualifier Strobes
DQM0 - DQM1
DDR/SDRAM Data Masks
Output
DQM2 - DQM3
DDR/SDRAM Data Masks
Output
SDCKE
DDR/SDRAM Clock Enable
Output
High
SDCS
DDR/SDRAM Controller Chip Select
Output
Low
BA0 - BA1
DDR/SDRAM Bank Select
Output
SDWE
DDR/SDRAM Write Enable
Output
Low
RAS - CAS
DDR/SDRAMRow and Column Signal
Output
Low
SDA10
DDR/SDRAM Address 10 Line
Output
I/O
Burst CellularRAM Controller
BCCK
Burst CellularRAM Clock
Output
BCCRE
Burst CellularRAM Enable
Output
BCADV
Burst CellularRAM Burst Advance Signal
Output
BCWE
Burst CellularRAM Write Enable
Output
BCOE
Burst CellularRAM Output Enable
Output
BCOWAIT
Burst CellularRAM Output Wait
Input
Multimedia Card Interface MCI
MCIx_CK
Multimedia Card Clock
Output
MCIx_CD
Multimedia Card Command
I/O
MCIx_D0 - D3
Multimedia Card Data
I/O
7
6264C–CAP–24-Mar-09
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Comments
Universal Synchronous Asynchronous Receiver Transmitter USART
SCKx
USARTx Serial Clock
I/O
TXDx
USARTx Transmit Data
I/O
RXDx
USARTx Receive Data
Input
RTSx
USARTx Request To Send
CTSx
USARTx Clear To Send
Output
Input
Synchronous Serial Controller - SSC
TDx
SSCx Transmit Data
Output
RDx
SSCx Receive Data
Input
TKx
SSCx Transmit Clock
I/O
RKx
SSCx Receive Clock
I/O
TFx
SSCx Transmit Frame Sync
I/O
RFx
SSCx Receive Frame Sync
I/O
AC97 Controller - AC97C
AC97RX
AC97 Receive Signal
Input
AC97TX
AC97 Transmit Signal
Output
AC97FS
AC97 Frame Synchronization Signal
Output
AC97CK
AC97 Clock signal
Input
Timer/Counter - TC
TCLKx
TC Channel x External Clock Input
Input
TIOAx
TC Channel x I/O Line A
I/O
TIOBx
TC Channel x I/O Line B
I/O
Pulse Width Modulation Controller- PWMC
PMWx
Pulse Width Modulation Output
Output
Serial Peripheral Interface - SPI
SPIx_MISO
Master In Slave Out
I/O
SPIx_MOSI
Master Out Slave In
I/O
SPIx_SPCK
SPI Serial Clock
I/O
SPIx_NPCS0
SPI Peripheral Chip Select 0
I/O
Low
SPIx_NPCS1 - SPIx_NPCS3
SPI Peripheral Chip Select
Output
Low
Two-Wire Interface - TWI
TWD
Two-wire Serial Data
I/O
TWCK
Two-wire Serial Clock
I/O
8
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Comments
CAN Controller
CANRX
CAN input
CANTX
CAN output
Input
Output
LCD Controller - LCDC
LCDD0 - LCDD23
LCD Data Bus
Input
LCDVSYNC
LCD Vertical Synchronization
Output
LCDHSYNC
LCD Horizontal Synchronization
Output
LCDDOTCK
LCD Dot Clock
Output
LCDDEN
LCD Data Enable
Output
LCDCC
LCD Contrast Control
Output
Ethernet 10/100 EMAC
ETXCK/EREFCK
Transmit Clock or Reference Clock
Input
MII only, REFCK in RMII
ERXCK
Receive Clock
Input
MII only
ETXEN
Transmit Enable
Output
ETX0-ETX3
Transmit Data
Output
ETX0-ETX1 only in RMII
ETXER
Transmit Coding Error
Output
MII only
ERXDV
Receive Data Valid
Input
RXDV in MII, CRSDV in
RMII
ERX0-ERX3
Receive Data
Input
ERX0-ERX1 only in RMII
ERXER
Receive Error
Input
ECRS
Carrier Sense and Data Valid
Input
MII only
ECOL
Collision Detect
Input
MII only
EMDC
Management Data Clock
EMDIO
Management Data Input/Output
EF100
Force 100Mbit/sec.
Output
I/O
Output
High
RMII only
USB High Speed Device
FSDM
USB Full Speed Data -
Analog
FSDP
USB Full Speed Data +
Analog
HSDM
USB High Speed Data -
Analog
HSDP
USB High Speed Data +
Analog
VBG
Bias Voltage Reference
Analog
PLLRCU
USB PLL Test Pad
Analog
9
6264C–CAP–24-Mar-09
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Comments
OHCI USB Host Port
HDPA
USB Host Port A Data +
Analog
HDMA
USB Host Port A Data -
Analog
HDPB
USB Host Port B Data +
Analog
HDMB
USB Host Port B Data -
Analog
ADC
AD0-AD7
Analog Inputs
Analog
ADVREF
ADC Voltage Reference
Analog
ADTRIG
ADC Trigger
Input
Image Sensor Interface - ISI
ISI_D0-ISI_D11
Image Sensor Data
Input
ISI_MCK
Image Sensor Reference Clock
ISI_HSYNC
Image Sensor Horizontal Synchro
Input
ISI_VSYNC
Image Sensor Vertical Synchro
Input
ISI_PCK
Image Sensor Data Clock
Input
Output
MPBLOCK - MPB
MPIOA0-MPIOA31
MPBlock I/Os A
I/O
MPIOB0-MPIOB44
MPBlock I/Os B
I/O
10
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
4. Package and Pinout
The AT91CAP9S500A/AT91CAP9S250A is available in two packages:
• a 400-ball RoHS-compliant LFBGA package, 17 x 17 mm, 0.8 mm ball pitch
• a 324-ball RoHS-compliant TFBGA package, 15 x 15 mm, 0.8 mm ball pitch
4.1
400-ball LFBGA Package Outline
Figure 4-1 shows the orientation of the 400-ball BGA Package.
A detailed mechanical description is given in the section “AT91CAP9S500A/AT91CAP9S250A
Mechanical Characteristics” of the product datasheet.
Figure 4-1.
400-ball LFBGA Package Outline and Marking (Top View)
Top View
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CAP9
A B C D E F G H J K L M N P R T U V W
A1 Corner
Y
A1 Corner
11
6264C–CAP–24-Mar-09
4.2
400-ball LFBGA Package Pinout
Table 4-1.
AT91CAP9S500A/AT91CAP9S250A Pinout for 400-ball BGA Package
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
A1
PC5
F1
PA3
L1
PA22
T1
PD22
A2
PC3
F2
PA4
L2
PA25
T2
PD23
A3
PC2
F3
PA8
L3
PA29
T3
PD30
A4
PC1
F4
PA5
L4
PA31
T4
VDDCORE
A5
PC0
F5
PA6
L5
PD6
T5
SDCS
A6
BMS
F6
VDDIOM
L6
GNDIO
T6
DQS0
A7
NRST
F7
VDDIOP0
L7
GNDCORE
T7
D4
A8
GNDCORE
F8
PC24
L8
PA18
T8
D11
A9
PB18
F9
NC
L9
GNDTHERMAL
T9
D14
A10
PB17
F10
VDDCORE
L10
GNDTHERMAL
T10
SDA10
A11
PB14
F11
GNDIO
L11
GNDTHERMAL
T11
VDDCORE
A12
PB15
F12
PB23
L12
GNDTHERMAL
T12
MPIOA0
A13
GNDANA
F13
PB6
L13
GNDCORE
T13
MPIOA9
A14
PB26
F14
NC
L14
GNDIO
T14
GNDIO
A15
VDDIOP0
F15
NC
L15
VDDCORE
T15
MPIOA25
A16
GNDIO
F16
NC
L16
MPIOB28
T16
MPIOA24
A17
FSDP
F17
GNDPLL
L17
MPIOB32
T17
MPIOA29
A18
FSDM
F18
WKUP0
L18
MPIOB34
T18
MPIOB3
A19
HSDP
F19
SHDW
L19
MPIOB31
T19
MPIOB17
A20
HSDM
F20
PLLRCA
L20
MPIOB29
T20
MPIOB18
B1
PC17
G1
PA7
M1
PA26
U1
PD25
B2
PC16
G2
PA10
M2
PA30
U2
PD31
B3
PC14
G3
PA11
M3
PD11
U3
BCCLK
B4
PC11
G4
PA9
M4
PD12
U4
A0
B5
PC10
G5
PA12
M5
PD13
U5
D0
B6
PC9
G6
PD10
M6
PD15
U6
D1
B7
TDO
G7
GNDIO
M7
GNDCORE
U7
NWR1
B8
TCK
G8
GNDCORE
M8
PA28
U8
DQS1
B9
PB20
G9
VDDIOP0
M9
GNDTHERMAL
U9
A7
B10
PB19
G10
PC8
M10
GNDTHERMAL
U10
A13
B11
PB13
G11
PB25
M11
GNDTHERMAL
U11
A20
B12
ADVREF
G12
PB21
M12
GNDTHERMAL
U12
GNDIO
B13
PB16
G13
PB8
M13
NRD
U13
MPIOA4
B14
PB27
G14
PB0
M14
MPIOB26
U14
MPIOA11
B15
PB24
G15
PB2
M15
GNDIO
U15
MPIOA16
B16
HDMA
G16
NC
M16
MPIOB16
U16
VDDMPIOA
B17
VDDIOP0
G17
VDDPLL
M17
GNDCORE
U17
MPIOA23
12
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Table 4-1.
AT91CAP9S500A/AT91CAP9S250A Pinout for 400-ball BGA Package (Continued)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
B18
GNDIO
G18
GNDCORE
M18
MPIOB27
U18
MPIOA28
B19
VDDUTMII
G19
TST
M19
MPIOB25
U19
MPIOB6
B20
GNDUTMII
G20
PLLRCB
M20
MPIOB24
U20
MPIOB9
C1
PC23
H1
PA13
N1
PD7
V1
PD26
C2
PC22
H2
PA14
N2
PD8
V2
RAS
C3
PC21
H3
PD0
N3
PD16
V3
SDCKE
C4
PC20
H4
PA15
N4
PD19
V4
D3
C5
PC18
H5
PD1
N5
PD20
V5
VDDIOM
C6
PC15
H6
VDDIOP1
N6
PD29
V6
D5
C7
PC12
H7
VDDCORE
N7
GNDIO
V7
D9
C8
PC6
H8
GNDIO
N8
VDDIOM
V8
D15
C9
NTRST
H9
GNDIO
N9
NCS1
V9
A11
C10
TDI
H10
PB10
N10
VDDCORE
V10
GNDCORE
C11
VDDANA
H11
PB4
N11
A3
V11
A22
C12
PB12
H12
VDDMPIOB
N12
A6
V12
MPIOA1
C13
PB29
H13
JTAGSEL
N13
VDDCORE
V13
MPIOA6
C14
PB9
H14
GNDCORE
N14
MPIOB11
V14
MPIOA10
C15
PB7
H15
GNDPLL
N15
MPIOB13
V15
MPIOA13
C16
HDPA
H16
NC
N16
MPIOB12
V16
MPIOA17
C17
HDPB
H17
VDDCORE
N17
MPIOB14
V17
MPIOA20
C18
VDDUPLL
H18
MPIOB44
N18
MPIOB15
V18
MPIOA27
C19
VDDUTMIC
H19
XOUT32
N19
MPIOB22
V19
MPIOB5
C20
VBG
H20
XIN32
N20
MPIOB23
V20
VDDMPIOB
D1
PC29
J1
PD3
P1
PD9
W1
SDWE
D2
PC28
J2
PD2
P2
PD14
W2
BCOWAIT
D3
PC27
J3
PD5
P3
PD18
W3
NANDWE
D4
PC26
J4
PA17
P4
PD27
W4
GNDIO
D5
PC25
J5
PA19
P5
PD28
W5
D6
D6
PC19
J6
VDDIOP0
P6
VDDIOM
W6
A2
D7
NANDOE
J7
PA16
P7
NWR3
W7
A5
D8
PC7
J8
GNDCORE
P8
D8
W8
A14
D9
GNDIO
J9
GNDTHERMAL
P9
D10
W9
A17
D10
TMS
J10
GNDTHERMAL
P10
GNDIO
W10
A19
D11
NC
J11
GNDTHERMAL
P11
A9
W11
NWR0
D12
PB31
J12
GNDTHERMAL
P12
A12
W12
MPIOA2
D13
PB22
J13
GNDIO
P13
NC
W13
MPIOA5
D14
VDDCORE
J14
GNDBU
P14
MPIOB8
W14
MPIOA8
D15
PB3
J15
GNDBU
P15
MPIOB0
W15
MPIOA12
13
6264C–CAP–24-Mar-09
Table 4-1.
AT91CAP9S500A/AT91CAP9S250A Pinout for 400-ball BGA Package (Continued)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
D16
PB1
J16
MPIOB42
P16
MPIOB1
W16
MPIOA15
D17
HDMB
J17
MPIOB39
P17
MPIOB7
W17
MPIOA21
D18
PLLRCU
J18
MPIOB43
P18
MPIOB10
W18
MPIOA22
D19
GNDUTMIC
J19
MPIOB41
P19
MPIOB21
W19
GNDIO
D20
GNDUPLL
J20
GNDIO
P20
VDDMPIOB
W20
VDDCORE
E1
PC30
K1
PD4
R1
PD21
Y1
SDCK
E2
PA2
K2
PA21
R2
PD17
Y2
SDCKN
E3
PA1
K3
PA24
R3
PD24
Y3
A1
E4
PA0
K4
PA27
R4
CAS
Y4
GNDCORE
E5
PC31
K5
PA23
R5
VDDCORE
Y5
A4
E6
GNDIO
K6
GNDIO
R6
D2
Y6
A8
E7
VDDCORE
K7
PA20
R7
D7
Y7
A10
E8
PC13
K8
VDDCORE
R8
VDDIOM
Y8
A15
E9
PC4
K9
GNDTHERMAL
R9
D13
Y9
A18
E10
RTCK
K10
GNDTHERMAL
R10
D12
Y10
A21
E11
VDDIOP0
K11
GNDTHERMAL
R11
VDDIOM
Y11
NCS0
E12
PB30
K12
GNDTHERMAL
R12
A16
Y12
MPIOA3
E13
PB28
K13
GNDCORE
R13
VDDIOM
Y13
MPIOA7
E14
PB11
K14
MPIOB33
R14
NC
Y14
VDDMPIOA
E15
PB5
K15
MPIOB30
R15
NC
Y15
MPIOA14
E16
NC
K16
MPIOB35
R16
NC
Y16
MPIOA18
E17
VDDPLL
K17
MPIOB38
R17
MPIOB2
Y17
MPIOA19
E18
VDDBU
K18
MPIOB40
R18
MPIOB4
Y18
MPIOA26
E19
XIN
K19
MPIOB37
R19
MPIOB19
Y19
MPIOA30
E20
XOUT
K20
MPIOB36
R20
MPIOB20
Y20
MPIOA31
14
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
4.3
324-ball TFBGA Package Outline
Figure 4-2 shows the orientation of the 324-ball TFBGA green package.
A detailed mechanical description is given in the section “AT91CAP9S500A/AT91CAP9S250A
Mechanical Characteristics” of the product datasheet.
Figure 4-2.
324-ball TFBGA Package Outline and Marking (Top View)
Top View
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CAP9
A B C D E F G H J K L M N P R T U V
A1 Corner
4.4
A1 Corner
324-ball TFBGA Package Pinout
The pin assignment for the 324-ball TFBGA package is customizable and dependent upon the
needs of the user.
Important: It is possible to partially or totally remove the connections to dedicated Metal Programmable I/0s: MPIOAO-MPIOA31 and MPIOB0-MPIOB44. Likewise, PA16-PA31, PB21PB31, PDC0-PC27, PD0-PD10 can be partially or totally disconnected. However, it is incumbent
upon the user to ensure that the associated functionality removed is not needed for the intended
application. Refer to Section 10.3.1 on page 42, Section 10.3.2 on page 43, Section 10.3.3 on
page 44, Section 10.3.4 on page 45 for information on PIO multiplexing and to verify functionality before disconnecting signals.
15
6264C–CAP–24-Mar-09
5. Power Considerations
5.1
Power Supplies
The AT91CAP9S500A/AT91CAP9S250A has several types of power supply pins:
• VDDCORE pins: Power the core, including the processor, the embedded memories and the
peripherals; voltage range between1.08V and 1.32V, 1.2V nominal.
• VDDIOM pins: Power the External Bus Interface; voltage ranges between 1.65V and 1.95V
(1.8V nominal) or between 3.0V and 3.6V (3.3V nominal).
• VDDIOP0 pins: Power the Peripherals I/O lines and the USB transceivers; voltage range
between 3.0V and 3.6V, 3.3V nominal.
• VDDIOP1 pins: Power the Peripherals I/O lines involving the Image Sensor Interface; voltage
ranges from 1.65V to 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal.
• VDDIOMPA pins: Power the MP Block I/O A lines; voltage ranges from 1.65V to 3.6V, 1.8V,
2.5V, 3V or 3.3V nominal.
• VDDIOMPB pins: Power the dedicated MP Block I/O B lines; voltage ranges from 1.65V to
3.6V, 1.8V, 2.5V, 3V or 3.3V nominal.
• VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage
range between1.08V and 1.32V, 1.2V nominal.
• VDDPLL pin: Powers the PLL cells; voltage ranges between 3.0V to 3.6V, 3.3V nominal.
• VDDUTMII pin: Powers the UTMI+ interface; voltage ranges from 3.0V to 3.6V, 3.3V nominal.
• VDDUTMIC pin: Powers the UTMI+ core; voltage ranges between 1.08V and 1.32V, 1.2V
nominal.
• VDDUPLL pin: Powers the USB PLL cell; voltage ranges between 1.08V and 1.32V, 1.2V
nominal.
• VDDANA pin: Powers the ADC cell; voltage ranges between 3.0V and 3.6V, 3.3V nominal.
The power supplies VDDIOM, VDDIOP0 and VDDIOP1 are identified in the pinout table and the
multiplexing tables. These supplies enable the user to power the device differently for interfacing
with memories and for interfacing with peripherals.
Ground pins GNDIO are common to VDDIOM, VDDIOP0, VDDIOP1, VDDIOMPA and VDDIOMPB pin power supplies. Separated ground pins are provided for VDDCORE, VDDBU,
VDDPLL, VDDUTMII, VDDUTMIC, VDDUPLL and VDDANA. These ground pins are, respectively, GNDBU, GNDOSC, GNDPLL, GNDUTMII, GNDUTMIC, GNDUPLL and GNDANA.
Special GNDTHERMAL ground balls are thermally coupled with package substrate.
5.2
Power Consumption
The AT91CAP9S500A/AT91CAP9S250A consumes about 190 µA of static current on
VDDCORE at 25°C.
On VDDBU, the current does not exceed 4 µA @25°C.
For dynamic power consumption and more details, refer to the Power Consumption section and
tables in the Electrical Characteristics section of the product datasheet.
16
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
5.3
Programmable I/O Lines Power Supplies
The power supply pins VDDIOM, VDDMPIOA and VDDMPIOB accept two voltage ranges. This
allows the device to reach its maximum speed either out of 1.8V or 3.3V external memories.
The target maximum speed is 100 MHz on the pin DDR/SDR and MPIOA or MPIOB pins loaded
with 30 pF for power supply at 1.8V and 50 pF for power supply at 3.3V. The other signals (control, address and data signals) do not go over 50 MHz.
The voltage ranges are determined by programming registers in the Chip Configuration registers
located in the Matrix User Interface.
At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either
1.8V or 3.3V. Obviously, the device cannot reach its maximum speed if the voltage supplied to
the pins is 1.8V only. The user must make sure to program the EBI voltage range before getting
the device out of its Slow Clock Mode.
17
6264C–CAP–24-Mar-09
6. I/O Line Considerations
6.1
JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.
TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 kΩ to GNDBU so that it can be left unconnected for normal operations.
The NTRST signal is described in Section 6.3 “Reset Pins” on page 18.
All the JTAG signals are supplied with VDDIOP0.
6.2
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU so that it can be left unconnected for normal
operations. Driving this line at a high level leads to unpredictable results.
This pin is supplied with VDDBU.
6.3
Reset Pins
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven
with voltage at up to VDDIOP0.
NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the
processor.
As the product integrates power-on reset cells that manage the processor and the JTAG reset,
the NRST pin can be left unconnected.
The NRST pin integrates a permanent pull-up resistor of 90 kΩ minimum to VDDIOP0.
The NRST signal is inserted in the Boundary Scan.
6.4
PIO Controllers
All the I/O lines which are managed by the PIO Controllers integrate a programmable pull-up
resistor of 90 kΩ minimum. Programming of this pull-up resistor is performed independently for
each I/O line through the PIO Controllers.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those multiplexed with the External Bus Interface signals that must be enabled as Peripheral at reset. This
is indicated in the column “Reset State” of the PIO Controller multiplexing tables.
6.5
Shutdown Logic Pins
The SHDN pin is an output only, which is driven by the Shutdown Controller only at low level. It
can be tied high with an external pull-up resistor at VDDBU only.
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
18
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
7. Processor and Architecture
7.1
ARM926EJ-S Processor
• RISC Processor based on ARM v5TEJ Architecture with Jazelle technology for Java
acceleration
• Two Instruction Sets
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
• DSP Instruction Extensions
• 5-Stage Pipeline Architecture:
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
• 16-Kbyte Data Cache, 16-Kbyte Instruction Cache
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
• Write Buffer
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
– Software Control Drain
• Standard ARM v4 and v5 Memory Management Unit (MMU)
– Access Permission for Sections
– Access Permission for large pages and small pages can be specified separately for
each quarter of the page
– 16 embedded domains
• Bus Interface Unit (BIU)
– Arbitrates and Schedules AHB Requests
– Separate Masters for both instruction and data access providing complete Matrix
system flexibility
– Separate Address and Data Buses for both the 32-bit instruction interface and the
32-bit data interface
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
(Words)
7.2
Bus Matrix
• 12-layer Matrix, handling requests from 12 masters
• Programmable Arbitration strategy
– Fixed-priority Arbitration
19
6264C–CAP–24-Mar-09
– Round-Robin Arbitration, either with no default master, last accessed default master
or fixed default master
• Burst Management
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
• One Address Decoder provided per Master
– Three different slaves may be assigned to each decoded memory area: one for
internal boot, one for external boot, one after remap
• Boot Mode Select
– Non-volatile Boot Memory can be internal or external
– Selection is made by BMS pin sampled at reset
• Remap Command
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
– Allows Handling of Dynamic Exception Vectors
7.3
Matrix Masters
The Bus Matrix of the AT91CAP9S500A/AT91CAP9S250A manages twelve Masters and thus
each master can perform an access concurrently with the others, assuming that the slave it
accesses is available.
Each Master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the masters have the same decoding.
Table 7-1.
7.4
List of Bus Matrix Masters
Master 0
ARM926™ Instruction
Master 1
ARM926 Data
Master 2
Peripheral DMA Controller
Master 3
LCD Controller
Master 4
USB High Speed Device Controller
Master 5
Image Sensor Interface
Master 6
DMA Controller
Master 7
Ethernet MAC
Master 8
OHCI USB Host Controller
Master 9
MP Block Master 0
Master 10
MP Block Master 1
Master 11
MP Block Master 2
Matrix Slaves
The Bus Matrix of the AT91CAP9S500A/AT91CAP9S250A manages ten Slaves. Each Slave
has its own arbiter, thus permitting a different arbitration per Slave to be programmed.
20
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
The LCD Controller, the USB Host and the USB High Speed Device have a user interface
mapped as a Slave of the Matrix. They share the same layer, as programming them does not
require a high bandwidth.
Table 7-2.
List of Bus Matrix Slaves
Slave 0
Internal SRAM 32 Kbytes
Slave 1
MP Block Slave 0 (MP Block Internal Memories)
Internal ROM
LCD Controller User Interface
Slave 2
USB High Speed Device Interface
OHCI USB Host Interface
7.5
Slave 3
MP Block Slave 1 (MP Block Internal Memories)
Slave 4
External Bus Interface
Slave 5
DDR Controller Port 2
Slave 6
DDR Controller Port 3
Slave 7
MP Block Slave 2 (MP Block External Chip Selects)
Slave 8
MP Block Slave 3 (MP Block Internal Peripherals)
Slave 9
Internal Peripherals for AT91CAP9
Master-to-Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
such as allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these paths
are forbidden or simply not wired, and shown as “-” in Table 7-3,
“AT91CAP9S500A/AT91CAP9S250A Masters to Slaves Access,” on page 22.
21
6264C–CAP–24-Mar-09
Table 7-3.
AT91CAP9S500A/AT91CAP9S250A Masters to Slaves Access
11
MP Block Master 2
10
MP Block Master 1
9
MP Block Master 0
8
OHCI USB Host Ctrl
7
Ethernet MAC
6
DMA Ctrl
5
Image Sensor Interface
4
USB High Speed
Device Ctrl
3
LCDCtrl
2
Peripheral DMA Ctrl
1
ARM926 Data
0
ARM926 Instruction
Master
0
Internal SRAM
32 Kbytes
X
X
X
X
X
X
X
X
X
X
X
X
1
MP Block
Slave 0
X
X
X
X
X
X
X
X
X
X
X
X
Internal ROM
X
X
X
X
X
X
X
X
X
X
X
X
LCD
Controller
User Interface
X
X
-
-
-
-
-
-
-
X
X
X
USB High
Speed Device
Interface
X
X
-
-
-
-
X
-
-
X
X
X
OHCI USB
Host Interface
X
X
-
-
-
-
-
-
-
X
X
X
3
MPBlock
Slave 1
X
X
X
X
X
X
X
X
X
X
X
X
4
External Bus
Interface
X
X
X
X
X
X
X
X
X
X
X
X
-
DDR Port 0
X
-
-
-
-
-
-
-
-
-
-
-
5
DDR Port 1
-
X
-
-
-
-
-
-
-
-
-
-
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
X
X(1)
Slave
2
-
6
DDR Port 2
X
DDR Port 3
X(1)
X(1)
X(1)
X(1)
X(1)
X(1)
X(1)
X(1)
X(1)
X(1)
X
X
X
X
X
X
X
7
MPBlock
Slave 2
X
X
X
X
X
X
X
X
X
X
X
X
8
MPBlock
Slave 3
X
X
X
X
X
X
X
X
X
X
X
X
9
Internal
Peripherals
X
X
X
-
-
-
X
-
-
X
X
X
Note:
22
1. DDR Port 2 or Port 3 is selectable for each master through the Matrix Remap Control Register.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
7.6
Peripheral DMA Controller
• Acting as one Matrix Master
• Allows data transfers from/to peripheral to/from any memory space without any intervention
of the processor.
• Next Pointer Support, forbids strong real-time constraints on buffer management.
• Twenty-two Channels
– Two for each USART
– Two for the Debug Unit
– One for the TWI
– One for the ADC Controller
– Two for the AC97 Controller
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– One for the each Multimedia Card Interface
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities):
– DBGU Transmit Channel
– USART2 Transmit Channel
– USART1 Transmit Channel
– USART0 Transmit Channel
– AC97 Transmit Channel
– SPI1 Transmit Channel
– SPI0 Transmit Channel
– SSC1 Transmit Channel
– SSC0 Transmit Channel
– DBGU Receive Channel
– TWI Transmit/Receive Channel
– ADC Receive Channel
– USART2 Receive Channel
– USART1 Receive Channel
– USART0 Receive Channel
– AC97 Receive Channel
– SPI1 Receive Channel
– SPI0 Receive Channel
– SSC1 Receive Channel
– SSC0 Receive Channel
– MCI1 Transmit/Receive Channel
– MCI0 Transmit/Receive Channel
23
6264C–CAP–24-Mar-09
7.7
DMA Controller
• Acting as one Matrix Master
• Embeds 4 unidirectional channels with programmable priority
• Address Generation
– Source / destination address programming
– Address increment, decrement or no change
– DMA chaining support for multiple non-contiguous data blocks through use of linked
lists
– Scatter support for placing fields into a system memory area from a contiguous
transfer. Writing a stream of data into non-contiguous fields in system memory
– Gather support for extracting fields from a system memory area into a contiguous
transfer
– User enabled auto-reloading of source, destination and control registers from initially
programmed values at the end of a block transfer
– Auto-loading of source, destination and control registers from system memory at end
of block transfer in block chaining mode
– Unaligned system address to data transfer width supported in hardware
• Channel Buffering
– 8-word FIFO
– Automatic packing/unpacking of data to fit FIFO width
• Channel Control
– Programmable multiple transaction size for each channel
– Support for cleanly disabling a channel without data loss
– Suspend DMA operation
– Programmable DMA lock transfer support
• Transfer Initiation
– Support four External DMA Requests and four Internal DMA request from the MP
Block
– Support for Software handshaking interface. Memory mapped registers can be used
to control the flow of a DMA transfer in place of a hardware handshaking interface
• Interrupt
– Programmable Interrupt generation on DMA Transfer completion Block Transfer
completion, Single/Multiple transaction completion or Error condition
7.8
Debug and Test Features
• ARM926 Real-time In-circuit Emulator
– Two real-time Watchpoint Units
– Two Independent Registers: Debug Control Register and Debug Status Register
– Test Access Port Accessible through JTAG Protocol
– Debug Communications Channel
• Debug Unit
– Two-pin UART
24
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
– Debug Communication Channel Interrupt Handling
– Chip ID Register
• IEEE1149.1 JTAG Boundary-scan on All Digital Pins
25
6264C–CAP–24-Mar-09
8. Memories
Figure 8-1.
AT91CAP9S500A/AT91CAP9S250A Memory Mapping
Internal Memory Mapping
Address Memory Space
0x0000 0000
0x0000 0000
Internal Memories
0x0010 0000
256M Bytes
0x0020 0000
0x0FFF FFFF
0x1000 0000
EBI
Chip Select 0
Boot Memory (1)
0x0030 0000
256M Bytes
SRAM
MPB SLAVE0
MPB SLAVE0
0x0040 0000
ROM
0x1FFF FFFF
0x2000 0000
0x2FFF FFFF
EBI
Chip Select 1/
EBI BCRAMC
0x0050 0000
LCDC
256M Bytes
0x0060 0000
USB HOST
EBI
Chip Select 2
0x0080 0000
256M Bytes
MPB SLAVE1
0x0090 0000
0x3FFF FFFF
EBI
Chip Select 3/
NAND Flash
MPB SLAVE1
0x00A0 0000
256M Bytes
MPB SLAVE1
0x00B0 0000
0x4FFF FFFF
0x5000 0000
0x5FFF FFFF
0x6000 0000
0x6FFF FFFF
0x7000 0000
UDPHS
0x0070 0000
0x3000 0000
0x4000 0000
Notes :
(1) Can be ROM, EBI_NCS0 or SRAM
depending on BMS and RCB0, RCB1
MPB SLAVE1
EBI
Chip Select 4/
Compact Flash
Slot 0
EBI
Chip Select 5/
Compact Flash
Slot 1
Peripheral Mapping
256M Bytes
0xFF00 0000
Reserved
16K Bytes
UDPHS
16K Bytes
0xFFF7 8000
256M Bytes
0xFFF7 C000
System Controller Mapping
0xFFFF C000
TCO, TC1, TC2
16K Bytes
MCI0
16K Bytes
MCI1
16K Bytes
0xFFFF E200
TWI
16K Bytes
0xFFFF E400
USART0
16K Bytes
0xFFFF E600
USART1
16K Bytes
0xFFFF E800
USART2
16K Bytes
0xFFFF EA00
MATRIX
0xFFFF EB10
SSC0
16K Bytes
CCFG
0xFFFF EC00
DMA
512 Bytes
SSC1
16K Bytes
DBGU
512 Bytes
0xFFF8 0000
EBI
DDRSDRC
256M Bytes
0xFFF8 4000
0x7FFF FFFF
0x8000 0000
Reserved
0xFFF8 8000
MPB SLAVE2
Chip Select 0
256M Bytes
0x8FFF FFFF
MPB SLAVE 2
Chip Select 1
256M Bytes
0xFFF9 4000
0xFFF9 8000
0x9FFF FFFF
0xA000 0000
MPB SLAVE 2
Chip Select 2
256M Bytes
0xFFF9 C000
0xB000 0000
MPB SLAVE 2
Chip Select 3
256M Bytes
AC97C
16K Bytes
SPI0
16K Bytes
SPI1
0xC000 0000
16K Bytes
0xFFFF F200
CAN0
16K Bytes
Reserved
16K Bytes
0xFFFB 4000
Reserved
16K Bytes
EMAC
16K Bytes
ADCC
16K Bytes
0xFFFC 4000
0xFFFF FFFF
26
16M Bytes
16M Bytes
16M Bytes
512 Bytes
512 Bytes
AIC
512 bytes
PIOA
512 bytes
PIOB
512 Bytes
PIOC
512 bytes
PIOD
512 bytes
Reserved
512 bytes
PMC
256 Bytes
0xFFFF FD00
RSTC
16 Bytes
0xFFFF FD10
SHDC
16 Bytes
0xFFFF FD20
ISI
16K Bytes
0xFFFF FD30
Reserved
16K Bytes
0xFFFF FD40
0xFFFF FD50
0xFFFC 8000
208M Bytes
0xFFFF FA00
0xFFFF FC00
0xFFFC 0000
Undefined
(Abort)
0xFCFF FFFF
0xFD00 0000
MPB SLAVE3
0xFE00 0000
MPB SLAVE3
0xFF00 0000 Internal Peripherals
SMC
16K Bytes
0xFFFB C000
0xEFFF FFFF
0xFFFF F800
0xFFFB 8000
PWMC
0xF000 0000
512 bytes
0xFFFF F600
0xFFFB 0000
768M Bytes
DDRSDRC
0xFFFF F400
0xFFFA C000
Undefined
(Abort)
512 Bytes
0xFFFF F000
0xFFFA 4000
0xFFFA 8000
0xBFFF FFFF
BCRAMC
0xFFFF EE00
0xFFFA 0000
0xAFFF FFFF
512 Bytes
0xFFF8 C000
0xFFF9 0000
0x9000 0000
ECC
0xFFFC C000
Reserved
16K Bytes
SYSC
16K Bytes
0xFFFF FD60
0xFFFF FD70
0xFFFF C000
0xFFFF FFFF
RTT
16 Bytes
PIT
16 Bytes
WDT
16 Bytes
SCKCR
16 Bytes
GPBR
16 Bytes
Reserved
0xFFFF FFFF
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the
Advanced High-performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to
7 are directed to the EBI that associates these banks to the external chip selects NCS0 to NCS5
and SDCS. The bank 0 is reserved for the addressing of the internal memories, and a second
level of decoding provides 1M byte of internal memory area. The banks 8 to 11 are directed to
MP Block (Slave 2) and may be used to address external memories. The bank 15 is split into
three parts, one reserved for the peripherals that provides access to the Advanced Peripheral
Bus (APB), the two others are directed to MP Block (Slave 3) and may provide access to the MP
Block APB or to other AHB peripherals.
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping
per Master. However, in order to simplify the mappings, all the masters have a similar address
decoding.
Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are
assigned to the memory space decoded at address 0x0: one for internal boot, one for external
boot and one after remap. Refer to Table 8-1, “Internal Memory Mapping,” on page 28 for
details.
8.1
Embedded Memories
• 32 Kbyte ROM
– Two Cycle Access at full matrix speed
• 32 Kbyte Fast SRAM
– Single Cycle Access at full matrix speed
• 20 Kbyte MP Block Fast Dual Port RAM (ten 512x36 DPR instances)
– Used as Dual Port RAM completely managed by MP Block
• 32 Kbyte MP Block Fast Single Port RAM (eight 512x72 SPR instances)
– Used as Single Port RAM completely managed by MP Block
27
6264C–CAP–24-Mar-09
8.1.1
Internal Memory Mapping
Table 8-1 summarizes the Internal Memory Mapping, depending on the Remap Command Bit
(RBC) status and the BMS state at reset.
REMAP allows the user to layout the internal SRAM bank to 0x0 to ease development. This is
done by software once the system boots. Refer to the Bus Matrix Section for more details.
When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an
external memory. This is done by way of hardware at reset.
Table 8-1.
Internal Memory Mapping
Address
ARM926 I
RCB0 = 0
0x0000 0000
BMS = 0
BMS = 1
NCS0
ROM
ARM926 D
RCB0 = 1
SRAM
Other Masters
RCB1 = 0
BMS = 0
BMS = 1
NCS0
ROM
RCB1 = 1
SRAM
Abort
8.1.1.1
Internal 32 Kbyte Fast SRAM
The AT91CAP9S500A/AT91CAP9S250A integrates a 32 Kbyte SRAM, mapped at address
0x0010 0000, which is accessible from the AHB bus. This SRAM is single cycle accessible at full
matrix speed.
8.1.1.2
Internal ROM
The AT91CAP9S500A/AT91CAP9S250A embeds an Internal ROM, which contains the
SAM-BA® program. At any time, the ROM is mapped at address 0x0040 0000. It is also accessible at address 0x0 (BMS =1) after the reset and before the Remap Command.
8.1.2
Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory
layout can be changed with two parameters.
The AT91CAP9S500A/AT91CAP9S250A Bus Matrix manages a boot memory that depends on
the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and
0x000F FFFF is reserved to this effect.
Note:
Memory blocks not affected by these parameters can always be seen at their specified base
addresses. See the complete memory map presented in Figure 8-1 on page 26.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on Chip Select 0 of the
External Bus Interface.
8.1.2.1
BMS = 1, boot on embedded ROM
The system boots on Boot Program.
• Boot on on-chip RC oscillator
• Auto baudrate detection
• Downloads and runs an application from external storage media into internal SRAM
• Downloaded code size depends on embedded SRAM size
• Automatic detection of valid application
28
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• Bootloader on a non-volatile memory
– NAND Flash
– SDCard on MCI0
– SPI DataFlash®/Serial Flash connected on NPCS0 and NPCS1 of the SPI0
– EEPROM on TWI
• SAM-BA Boot in case no valid program is detected in external NVM, supporting:
– Serial communication on a DBGU
– USB Device HS Port
8.1.2.2
BMS = 0, boot on external memory
• Boot on on-chip RC
• Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit
data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.
For optimization purposes, nothing else is done. To speed up the boot sequence user programmed software should perform a complete configuration:
• Program the PMC (main oscillator enable or bypass mode)
• Program and Start the PLL
• Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the
new clock
• Switch the main clock to the new value
8.2
External Memories
The external memories are accessed through the External Bus Interfaces. Each Chip Select line
has a 256 Mbyte memory area assigned.
Refer to Figure 8-1 on page 26.
8.2.1
External Bus Interface
The AT91CAP9S500A/AT91CAP9S250A features one External Bus Interface to offer high
bandwidth to the system and to prevent any bottleneck while accessing the external memories.
• Optimized for Application Memory Space support
• Integrates four External Memory Controllers:
– Static Memory Controller
– 4-port DDR/SDRAM Controller
– Burst/Cellular RAM Controller
– SLC NAND Flash ECC Controller
• Additional logic for NAND Flash and CompactFlashTM
• Optional Full 32-bit External Data Bus
• Up to 26-bit Address Bus (up to 64 Mbytes linear per chip select)
• Up to 6 chip selects, configurable assignment:
– Static Memory Controller on NCS0
– Burst/CellularRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS2
29
6264C–CAP–24-Mar-09
– Static Memory Controller on NCS3, Optional NAND Flash support
– Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support
• One dedicated chip select:
– DDR/SDRAM Controller on SDCS
8.2.2
Static Memory Controller
• 8-, 16- or 32-bit Data Bus
• Multiple Access Modes supported
– Byte Write or Byte Select Lines
– Asynchronous read in Page Mode supported (4- up to 32-byte page size)
• Multiple device adaptability
– Compliant with LCD Module
– Control signals programmable setup, pulse and hold time for each Memory Bank
• Multiple Wait State Management
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
• Slow Clock mode supported
8.2.3
DDR/SDRAM Controller
• Supported devices:
– Standard and Low Power SDRAM (Mobile SDRAM)
– Mobile DDR
• Numerous configurations supported
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with two or four Internal Banks
– SDRAM with 16- or 32-bit Data Path
– Mobile DDR with four Internal Banks
– Mobile DDR with 16-bit Data Path
• Programming facilities
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Multibank Ping-pong Access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Multiport (4 Ports)
• Energy-saving capabilities
– Self-refresh, power down and deep power down modes supported
• Error detection
– Refresh Error Interrupt
• DDR/SDRAM Power-up Initialization by software
30
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• SDRAM CAS Latency of 1, 2 and 3 supported
• DDR CAS latency of 3 supported
• Auto Precharge Command not used
8.2.4
Burst Cellular RAM Controller
• Supported devices:
– Synchronous Cellular RAM version 1.0, 1.5 and 2.0
• Numerous configurations supported
– 64K, 128K, 256K, 512K Row Address Memory Parts
– Cellular RAM with 16- or 32-bit Data Path
• Programming facilities
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Timing parameters specified by software
– Only Continuous read or write burst supported
• Energy-saving capabilities
– Standby and Deep Power Down (DPD) modes supported
– Low Power features (PASR/TCSR) supported
• Cellular RAM Power-up Initialization by hardware
• Cellular RAM CAS latency of 2 and 3 supported (Version 1.0)
• Cellular RAM CAS latency of 2, 3, 4, 5 and 6 supported (Version 1.5 and 2.0)
• Cellular RAM variable or fixed latency supported (Version 1.5 and 2.0)
• Multiplexed address/data bus supported (Version 2.0)
• Asynchronous and Page mode not supported
8.2.5
NAND Flash Error Corrected Code Controller
• Hardware Error Corrected Code (ECC) Generation
– Detection and Correction by Software
• Supports NAND Flash and SmartMedia™ Devices with 8- or 16-bit Data Path
• Supports NAND Flash/SmartMedia with Page Sizes of 528, 1056, 2112 and 4224 Bytes
Specified by Software
• Supports 1 bit correction for a page of 512,1024,2048 and 4096 Bytes with 8- or 16-bit Data
Path
• Supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 Bytes
with 8-bit Data Path
• Supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 Bytes
with 8-bit Data Path
31
6264C–CAP–24-Mar-09
9. System Controller
The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc.
The System Controller User Interface also embeds the registers that allow configuration of the
Matrix and a set of registers for the chip configuration. The chip configuration registers are used
to configure:
– EBI chip select assignment and voltage range for external memories
– MP Block
The System Controller peripherals are all mapped within the highest 16 Kbytes of address
space, between addresses 0xFFFF C000 and 0xFFFF FFFF.
However, all the registers of System Controller are mapped on the top of the address space.
This allows all the registers of the System Controller to be addressed from a single pointer by
using the standard ARM instruction set, as the Load/Store instructions have an indexing mode of
± 4 Kbytes.
Figure 9-1 on page 33 shows the System Controller block diagram.
Figure 8-1 on page 26 shows the mapping of the User Interfaces of the System Controller
peripherals.
32
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
9.1
System Controller Block Diagram
Figure 9-1.
AT91CAP9S500A/AT91CAP9S250A System Controller Block Diagram
System Controller
VDDCORE Powered
irq0-irq1
fiq
nirq
nfiq
Advanced
Interrupt
Controller
periph_irq[2..29]
int
pit_irq
rtt_irq
wdt_irq
dbgu_irq
pmc_irq
rstc_irq
ntrst
por_ntrst
MCK
periph_nreset
PCK
dbgu_txd
dbgu_rxd
MCK
debug
periph_nreset
proc_nreset
dbgu_irq
Debug
Unit
debug
Periodic
Interval
Timer
pit_irq
Watchdog
Timer
wdt_irq
jtag_nreset
SLCK
debug
idle
proc_nreset
ARM926EJ-S
Boundary Scan
TAP Controller
MCK
wdt_fault
WDRPROC
NRST
periph_nreset
Bus Matrix
rstc_irq
por_ntrst
jtag_nreset
VDDCORE
POR
VDDBU
POR
Reset
Controller
periph_nreset
proc_nreset
backup_nreset
VDDBU Powered
SLCK
SLCK
backup_nreset
Real-Time
Timer
rtt_irq
rtt_alarm
SLCK
SHDN
Shut-Down
Controller
WKUP
XOUT32
SLOW
CLOCK
OSC
4 General-purpose
Backup Registers
rtt_alarm
UTMI PLL
XOUT
periph_clk[28]
periph_nreset
SLCK
XIN
battery_save
UDPHSCK
backup_nreset
XIN32
Voltage
Controller
periph_clk[2..31]
pck[0-3]
int
UDPHSCK
MAIN
OSC
MAINCK
USB High-speed
Device Port
periph_irq[28]
PCK
Power
Management
Controller
UHPCK
UHPCK
periph_clk[29]
PLLRCA
PLLA
PLLACK
MCK
periph_nreset
PLLRCB
PLLB
PLLBCK
pmc_irq
periph_irq[29]
periph_nreset
idle
periph_nreset
periph_clk[2]
dbgu_rxd
periph_irq[2]
irq0-irq1
fiq
dbgu_txd
USB Host
Port
periph_clk[7..31]
PA0-PA31
PB0-PB31
PC0-PC31
PD0-PD31
PIO
Controllers
periph_nreset
periph_irq[7..27]
Embedded
Peripherals
in
out
enable
33
6264C–CAP–24-Mar-09
9.2
Reset Controller
• Based on two Power-on-Reset cells
– One on VDDBU and one on VDDCORE
• Status of the last reset
– Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software
reset, user reset or watchdog reset
• Controls the internal resets and the NRST pin output
– Allows shaping a reset signal for the external devices
9.3
Shutdown Controller
• Shutdown and Wake-Up logic
– Software programmable assertion of the SHDN pin
– Deassertion Programmable on a WKUP pin level change or on alarm
9.4
Clock Generator
• Embeds a low power 32,768 Hz Slow Clock Oscillator and a low power RC oscillator
– Provides the permanent Slow Clock SLCK to the system
• Embeds the Main Oscillator
– Oscillator bypass feature
– Supports 8 to 16 MHz crystals
– 12 MHz crystal is required for USB High-Speed Device
• Embeds 2 programmable PLLs
– Output 80 to 240 MHz clocks
– Integrates an input divider to increase output accuracy
• Embeds 1 UTMI PLL
– 480 MHz Fixed frequency from 12 MHz input clock
– Integrated filter
34
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 9-2.
Clock Generator Block Diagram
Clock Generator
XIN32
Slow Clock
Oscillator
Slow Clock
SLCK
Main
Oscillator
Main Clock
MAINCK
PLLRCA
PLL and
Divider A
PLLA Clock
PLLACK
PLLRCB
PLL and
Divider B
PLLB Clock
PLLBCK
XOUT32
XIN
XOUT
Status
Control
Power
Management
Controller
9.5
Slow Clock Selection
The AT91CAP9S500A/AT91CAP9S250A slow clock can be generated either by an external
32768Hz crystal or the on-chip RC oscillator. The 32768Hz crystal oscillator can be bypassed to
accept an external slow clock on XIN32.
Configuration is located in the slow clock control register (SCKCR) located at address
0xFFFFFD50 in the backed up part of the system controller and so is preserved while VDDBU is
present.
Refer to the “Clock Generator” section for more details.
9.6
Power Management Controller
• Provides:
– the Processor Clock PCK
– the Master Clock MCK, in particular to the Matrix and the memory interfaces
– the USB High-speed Device Clock UDPHSCK
– the USB Host Clock UHPCK
– independent peripheral clocks, typically at the frequency of MCK
– four programmable clock outputs: PCK0 to PCK3
• Five flexible operating modes:
– Normal Mode, processor and peripherals running at a programmable frequency
– Idle Mode, processor stopped waiting for an interrupt
– Slow Clock Mode, processor and peripherals running at low frequency
– Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency,
processor stopped waiting for an interrupt
– Backup Mode, Main Power Supplies off, VDDBU powered by a battery
35
6264C–CAP–24-Mar-09
Figure 9-3.
AT91CAP9S500A/AT91CAP9S250A Power Management Controller Block Diagram
Processor
Clock
Controller
int
Master Clock Controller
SLCK
MAINCK
PLLACK
PLLBCK
PCK
Idle Mode
Divider
/1,/2,/4
Prescaler
/1,/2,/4,...,/64
MCK
Peripherals
Clock Controller
periph_clk[..]
ON/OFF
DDRCK
Programmable Clock Controller
SLCK
MAINCK
PLLACK
PLLBCK
ON/OFF
Prescaler
/1,/2,/4,...,/64
pck[..]
USB Clock Controller
PLLBCK
9.7
Divider
/1,/2,/4
ON/OFF
UHPCK
Periodic Interval Timer
• Includes a 20-bit Periodic Counter, with less than 1 µs accuracy
• Includes a 12-bit Interval Overlay Counter
• Real-time OS or Linux®/WinCE® compliant tick generator
9.8
Watchdog Timer
• 16-bit key-protected only-once-Programmable Counter
• Windowed, prevents the processor to be in a dead-lock on the watchdog access
9.9
Real-time Timer
• Two Real-time Timers, allowing backup of time with different accuracies
– 32-bit Free-running back-up Counter
– Integrates a 16-bit programmable prescaler running on the embedded 32,768 Hz
oscillator
– Alarm Register to generate a wake-up of the system through the Shutdown
Controller
9.10
General-Purpose Backup Registers
• Four 32-bit backup general-purpose registers
36
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
9.11
Advanced Interrupt Controller
• Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
• Thirty-two individually maskable and vectored interrupt sources
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
– Programmable Edge-triggered or Level-sensitive Internal Sources
– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
• Four External Sources plus the Fast Interrupt signal
• 8-level Priority Controller
– Drives the Normal Interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
• Vectoring
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
• Protect Mode
– Easy debugging by preventing automatic operations when protect models are
enabled
• Fast Forcing
– Permits redirecting any normal interrupt source on the Fast Interrupt of the
processor
9.12
Debug Unit
• Composed of two functions
– Two-pin UART
– Debug Communication Channel (DCC) support
• Two-pin UART
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
• Debug Communication Channel Support
– Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from
the ARM Processor’s ICE Interface
37
6264C–CAP–24-Mar-09
9.13
Chip Identification
• Chip ID: 0x039A03A1 (for DevChip)
• JTAG ID: 0x15B1B03F
• ARM926 TAP ID: 0x0792603F
9.14
PIO Controllers
• 4 PIO Controllers, PIOA to PIOD, controlling a total of 128 I/O Lines
• Each PIO Controller controls up to 32 programmable I/O Lines
– PIOA has 32 I/O Lines
– PIOB has 32 I/O Lines
– PIOC has 32 I/O Lines
– PIOD has 32 I/O Lines
• Fully programmable through Set/Clear Registers
• Multiplexing of two peripheral functions per I/O Line
• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
– Input change interrupt
– Glitch filter
– Multi-drive option enables driving in open drain
– Programmable pull up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
• Synchronous output, provides Set and Clear of several I/O lines in a single write
38
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
10. Peripherals
10.1
User Interface
The peripherals are mapped in the upper 256 Mbytes of the address space between the
addresses 0xFFFA 0000 and 0xFFFC FFFF. Each user peripheral is allocated 16 Kbytes of
address space.
A complete memory map is presented in Figure 8-1 on page 26.
10.2
Identifiers
The AT91CAP9S500A/AT91CAP9S250A embeds a wide range of peripherals. Table 10-1
defines the Peripheral Identifiers of the AT91CAP9S500A/AT91CAP9S250A. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller
and for the control of the peripheral clock with the Power Management Controller.
Table 10-1.
AT91CAP9S500A/AT91CAP9S250A Peripheral Identifiers
Peripheral
ID
Peripheral
Mnemonic
0
AIC
1
SYSC
2
PIOA-D
3
MPB0
MP Block Peripheral 0
4
MPB1
MP Block Peripheral 1
5
MPB2
MP Block Peripheral 2
6
MPB3
MP Block Peripheral 3
7
MPB4
MP Block Peripheral 4
8
US0
USART 0
9
US1
USART 1
10
US2
USART 2
11
MCI0
Multimedia Card Interface 0
12
MCI1
Multimedia Card Interface 1
13
CAN
CAN Controller
14
TWI
Two-Wire Interface
15
SPI0
Serial Peripheral Interface 0
16
SPI1
Serial Peripheral Interface 1
17
SSC0
Synchronous Serial Controller 0
18
SSC1
Synchronous Serial Controller 1
19
AC97
AC97 Controller
20
TC0, TC1, TC2
21
PWMC
Pulse Width Modulation Controller
22
EMAC
Ethernet MAC
23
Reserved
Peripheral Name
Advanced Interrupt Controller
External
Interrupt
FIQ
System Controller Interrupt
Parallel I/O Controller A to D
Timer/Counter 0, 1 and 2
Reserved
39
6264C–CAP–24-Mar-09
Table 10-1.
10.2.1
10.2.1.1
AT91CAP9S500A/AT91CAP9S250A Peripheral Identifiers (Continued)
Peripheral
ID
Peripheral
Mnemonic
24
ADCC
25
ISI
26
LCDC
LCD Controller
27
DMA
DMA Controller
28
UDPHS
29
UHP
USB Host Port
30
AIC
Advanced Interrupt Controller
IRQ0
31
AIC
Advanced Interrupt Controller
IRQ1
Peripheral Name
External
Interrupt
ADC Controller
Image Sensor Interface
USB High Speed Device Port
Peripheral Interrupts and Clock Control
System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
• the DDR/SDRAM Controller
• the BCRAM Controller
• the Debug Unit
• the Periodic Interval Timer
• the Real-Time Timer
• the Watchdog Timer
• the Reset Controller
• the Power Management Controller
• the MP Block
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used
within the Advanced Interrupt Controller.
10.2.1.2
External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to
IRQ1, use a dedicated Peripheral ID. However, there is no clock control associated with these
peripheral IDs.
10.2.1.3
Timer Counter Interrupts
The three Timer Counter channels interrupt signals are OR-wired together to provide the interrupt source 19 of the Advanced Interrupt Controller. This forces the programmer to read all
Timer Counter status registers before branching the right Interrupt Service Routine.
The Timer Counter channels clocks cannot be deactivated independently. Switching off the
clock of the Peripheral 19 disables the clock of the 3 channels.
40
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
10.2.2
DMA Controller Request Signals
The requests to the DMA Controller may come from eight different sources:
• four external requests
• four internal requests from the MPBlock
Table 10-2.
DMA Controller Request Source and Signal Names
Internal DMA Request from MPBlock
External DMA Request
Channel 7
Channel 6
Channel 5
Channel 4
Channel 3
Channel 2
Channel 1
Channel 0
MP_DMARQ3
MP_DMARQ2
MP_DMARQ1
MP_DMARQ0
DMARQ3
DMARQ2
DMARQ1
DMARQ0
Each request source is selected through the DMAC Channel x Configuration Register.
It is also necessary to choose the hardware handshaking interface from the SRC_H2SEL and
DST_H2SEL fields.
(For more details, see the DMA Controller (DMAC) section and DMAC User Interface in the
product datasheet.)
10.3
Peripheral Signal Multiplexing on I/O Lines
The AT91CAP9S500A/AT91CAP9S250A features 4 PIO controllers, PIOA, PIOB, PIOC and
PIOD, that multiplex the I/O lines of the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral
functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of
the peripherals A and B are multiplexed on the PIO Controllers. The two columns “Function” and
“Comments” have been inserted in this table for the user’s own comments; they may be used to
track how pins are defined in an application.
Note that some peripheral functions which are output only may be duplicated within both tables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral
mode. If I/O is mentioned, the PIO Line resets in input with the pull-up enabled, so that the
device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling
memories, in particular the address lines, which require the pin to be driven as soon as the reset
is released. Note that the pull-up resistor is also enabled in this case.
41
6264C–CAP–24-Mar-09
10.3.1
PIO Controller A Multiplexing
Table 10-3.
Multiplexing on PIO Controller A
PIO Controller A
Application Usage
Reset
State
Power
Supply
SPI0_MISO
I/O
VDDIOP0
MCI0_CD
SPI0_MOSI
I/O
VDDIOP0
PA2
MCI0_CK
SPI0_SPCK
I/O
VDDIOP0
PA3
MCI0_D1
SPI0_NPCS1
I/O
VDDIOP0
PA4
MCI0_D2
SPI0_NPCS2
I/O
VDDIOP0
PA5
MCI0_D3
SPI0_NPCS0
I/O
VDDIOP0
PA6
AC97FS
I/O
VDDIOP0
PA7
AC97CK
I/O
VDDIOP0
PA8
AC97TX
I/O
VDDIOP0
PA9
AC97RX
I/O
VDDIOP0
PA10
IRQ0
PWM1
I/O
VDDIOP0
PA11
DMARQ0
PWM3
I/O
VDDIOP0
PA12
CANTX
PCK0
I/O
VDDIOP0
PA13
CANRX
I/O
VDDIOP0
PA14
TCLK2
IRQ1
I/O
VDDIOP0
PA15
DMARQ3
PCK2
I/O
VDDIOP0
PA16
MCI1_CK
ISI_D0
I/O
VDDIOP1
can be removed
PA17
MCI1_CD
ISI_D1
I/O
VDDIOP1
can be removed
PA18
MCI1_D0
ISI_D2
I/O
VDDIOP1
can be removed
PA19
MCI1_D1
ISI_D3
I/O
VDDIOP1
can be removed
PA20
MCI1_D2
ISI_D4
I/O
VDDIOP1
can be removed
PA21
MCI1_D3
ISI_D5
I/O
VDDIOP1
can be removed
PA22
TXD0
ISI_D6
I/O
VDDIOP1
can be removed
PA23
RXD0
ISI_D7
I/O
VDDIOP1
can be removed
PA24
RTS0
ISI_PCK
I/O
VDDIOP1
can be removed
PA25
CTS0
ISI_HSYNC
I/O
VDDIOP1
can be removed
PA26
SCK0
ISI_VSYNC
I/O
VDDIOP1
can be removed
PA27
PCK1
ISI_MCK
I/O
VDDIOP1
can be removed
PA28
SPI0_NPCS3
ISI_D8
I/O
VDDIOP1
can be removed
PA29
TIOA0
ISI_D9
I/O
VDDIOP1
can be removed
PA30
TIOB0
ISI_D10
I/O
VDDIOP1
can be removed
PA31
DMARQ1
ISI_D11
I/O
VDDIOP1
can be removed
I/O Line
Peripheral A
Peripheral B
PA0
MCI0_D0
PA1
Note:
42
Comments
Function
324-BGA pkg
Options(1)
1. The user must ensure that removing the designated pins does not have an adverse effect on the intended application.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
10.3.2
PIO Controller B Multiplexing
Table 10-4.
Multiplexing on PIO Controller B
PIO Controller B
Application Usage
Reset
State
Power
Supply
TF0
I/O
VDDIOP0
PB1
TK0
I/O
VDDIOP0
PB2
TD0
I/O
VDDIOP0
PB3
RD0
I/O
VDDIOP0
PB4
RK0
TWD
I/O
VDDIOP0
PB5
RF0
TWCK
I/O
VDDIOP0
PB6
TF1
TIOA1
I/O
VDDIOP0
PB7
TK1
TIOB1
I/O
VDDIOP0
PB8
TD1
PWM2
I/O
VDDIOP0
PB9
RD1
LCDCC
I/O
VDDIOP0
PB10
RK1
PCK1
I/O
VDDIOP0
PB11
RF1
I/O
VDDIOP0
PB12
SPI1_MISO
I/O
VDDIOP0
PB13
SPI1_MOSI
AD0
I/O
VDDIOP0
PB14
SPI1_SPCK
AD1
I/O
VDDIOP0
PB15
SPI1_NPCS0
AD2
I/O
VDDIOP0
PB16
SPI1_NPCS1
AD3
I/O
VDDIOP0
PB17
SPI1_NPCS2
AD4
I/O
VDDIOP0
PB18
SPI1_NPCS3
AD5
I/O
VDDIOP0
PB19
PWM0
AD6
I/O
VDDIOP0
PB20
PWM1
AD7
I/O
VDDIOP0
PB21
ETXCK/EREFCK
TIOA2
I/O
VDDIOP0
can be removed
PB22
ERXDV
TIOB2
I/O
VDDIOP0
can be removed
PB23
ETX0
PCK3
I/O
VDDIOP0
can be removed
PB24
ETX1
I/O
VDDIOP0
can be removed
PB25
ERX0
I/O
VDDIOP0
can be removed
PB26
ERX1
I/O
VDDIOP0
can be removed
PB27
ERXER
I/O
VDDIOP0
can be removed
PB28
ETXEN
TCLK0
I/O
VDDIOP0
can be removed
PB29
EMDC
PWM3
I/O
VDDIOP0
can be removed
PB30
EMDIO
I/O
VDDIOP0
can be removed
PB31
ADTRIG
I/O
VDDIOP0
can be removed
I/O Line
Peripheral A
PB0
Note:
Peripheral B
EF100
Comments
Function
324-BGA pkg
Options(1)
1. The user must ensure that removing the designated pins does not have an adverse effect on the intended application.
43
6264C–CAP–24-Mar-09
10.3.3
PIO Controller C Multiplexing
Table 10-5.
Multiplexing on PIO Controller C
PIO Controller C
Application Usage
Reset
State
Power
Supply
LCDVSYNC
I/O
VDDIOP0
can be removed
PC1
LCDHSYNC
I/O
VDDIOP0
can be removed
PC2
LCDDOTCK
I/O
VDDIOP0
can be removed
PC3
LCDDEN
PWM1
I/O
VDDIOP0
can be removed
PC4
LCDD0
LCDD3
I/O
VDDIOP0
can be removed
PC5
LCDD1
LCDD4
I/O
VDDIOP0
can be removed
PC6
LCDD2
LCDD5
I/O
VDDIOP0
can be removed
PC7
LCDD3
LCDD6
I/O
VDDIOP0
can be removed
PC8
LCDD4
LCDD7
I/O
VDDIOP0
can be removed
PC9
LCDD5
LCDD10
I/O
VDDIOP0
can be removed
PC10
LCDD6
LCDD11
I/O
VDDIOP0
can be removed
PC11
LCDD7
LCDD12
I/O
VDDIOP0
can be removed
PC12
LCDD8
LCDD13
I/O
VDDIOP0
can be removed
PC13
LCDD9
LCDD14
I/O
VDDIOP0
can be removed
PC14
LCDD10
LCDD15
I/O
VDDIOP0
can be removed
PC15
LCDD11
LCDD19
I/O
VDDIOP0
can be removed
PC16
LCDD12
LCDD20
I/O
VDDIOP0
can be removed
PC17
LCDD13
LCDD21
I/O
VDDIOP0
can be removed
PC18
LCDD14
LCDD22
I/O
VDDIOP0
can be removed
PC19
LCDD15
LCDD23
I/O
VDDIOP0
can be removed
PC20
LCDD16
ETX2
I/O
VDDIOP0
can be removed
PC21
LCDD17
ETX3
I/O
VDDIOP0
can be removed
PC22
LCDD18
ERX2
I/O
VDDIOP0
can be removed
PC23
LCDD19
ERX3
I/O
VDDIOP0
can be removed
PC24
LCDD20
ETXER
I/O
VDDIOP0
can be removed
PC25
LCDD21
ECRS
I/O
VDDIOP0
can be removed
PC26
LCDD22
ECOL
I/O
VDDIOP0
can be removed
PC27
LCDD23
ERXCK
I/O
VDDIOP0
can be removed
PC28
PWM0
TCLK1
I/O
VDDIOP0
PC29
PCK0
PWM2
I/O
VDDIOP0
PC30
DRXD
I/O
VDDIOP0
PC31
DTXD
I/O
VDDIOP0
I/O Line
Peripheral A
PC0
Note:
44
Peripheral B
Comments
Function
324-BGA pkg
Options(1)
1. The user must ensure that removing the designated pins does not have an adverse effect on the intended application.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
10.3.4
PIO Controller D Multiplexing
Table 10-6.
Multiplexing on PIO Controller D
PIO Controller D
Application Usage
Reset
State
Power
Supply
SPI0_NPCS2
I/O
VDDIOP0
can be removed
RXD1
SPI0_NPCS3
I/O
VDDIOP0
can be removed
PD2
TXD2
SPI1_NPCS2
I/O
VDDIOP0
can be removed
PD3
RXD2
SPI1_NPCS3
I/O
VDDIOP0
can be removed
PD4
FIQ
I/O
VDDIOP0
can be removed
PD5
DMARQ2
RTS2
I/O
VDDIOP0
can be removed
PD6
NWAIT
CTS2
I/O
VDDIOM
can be removed
PD7
NCS4/CFCS0
RTS1
I/O
VDDIOM
can be removed
PD8
NCS5/CFCS1
CTS1
I/O
VDDIOM
can be removed
PD9
CFCE1
SCK2
I/O
VDDIOM
can be removed
PD10
CFCE2
SCK1
I/O
VDDIOM
can be removed
PD11
NCS2
I/O
VDDIOM
PD12
A23
A23
VDDIOM
PD13
A24
A24
VDDIOM
PD14
A25/CFRNW
A25
VDDIOM
PD15
NCS3/NANDCS
I/O
VDDIOM
PD16
D16
I/O
VDDIOM
PD17
D17
I/O
VDDIOM
PD18
D18
I/O
VDDIOM
PD19
D19
I/O
VDDIOM
PD20
D20
I/O
VDDIOM
PD21
D21
I/O
VDDIOM
PD22
D22
I/O
VDDIOM
PD23
D23
I/O
VDDIOM
PD24
D24
I/O
VDDIOM
PD25
D25
I/O
VDDIOM
PD26
D26
I/O
VDDIOM
PD27
D27
I/O
VDDIOM
PD28
D28
I/O
VDDIOM
PD29
D29
I/O
VDDIOM
PD30
D30
I/O
VDDIOM
PD31
D31
I/O
VDDIOM
I/O Line
Peripheral A
Peripheral B
PD0
TXD1
PD1
Note:
Comments
Function
324-BGA pkg
Options(1)
1. The user must ensure that removing the designated pins does not have an adverse effect on the intended application.
45
6264C–CAP–24-Mar-09
10.4
10.4.1
Embedded Peripherals
Serial Peripheral Interface
• Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
• Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
and data per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
• Very fast transfers supported
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
10.4.2
Two-wire Interface
• Compatibility with standard two-wire serial memory
• One, two or three bytes for slave address
• Sequential read/write operations
10.4.3
USART
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– By 8 or by-16 over-sampling receiver frequency
– Hardware handshaking RTS-CTS
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
– Optional Manchester Encoding
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
– NACK handling, error counter with repetition and iteration limit
46
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• IrDA modulation and demodulation
– Communication at up to 115.2 Kbps
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
10.4.4
Synchronous Serial Controller
• Provides serial synchronous communication links used in audio and telecom applications
(with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)
• Contains an independent receiver and transmitter and a common clock divider
• Offers a configurable frame sync and data length
• Receiver and transmitter can be programmed to start automatically or on detection of
different event on the frame sync signal
• Receiver and transmitter include a data signal, a clock signal and a frame synchronization
signal
10.4.5
AC97 Controller
• Compatible with AC97 Component Specification V2.2
• Capable to Interface with a Single Analog Front end
• Three independent RX Channels and three independent TX Channels
– One RX and one TX channel dedicated to the AC97 Analog Front end control
– One RX and one TX channel for data transfers, associated with a PDC
– One RX and one TX channel for data transfers with no PDC
• Time Slot Assigner allowing to assign up to 12 time slots to a channel
• Channels support mono or stereo up to 20 bit sample length
– Variable sampling rate AC97 Codec Interface (48KHz and below)
10.4.6
Timer Counter
• Three 16-bit Timer Counter Channels
• Wide range of functions including:
– Frequency Measurement
– Event Counting
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
• Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
• Two global registers that act on all three TC Channels
47
6264C–CAP–24-Mar-09
10.4.7
Pulse Width Modulation Controller
• 4 channels, one 16-bit counter per channel
• Common clock generator, providing Thirteen Different Clocks
– A Modulo n counter providing eleven clocks
– Two independent Linear Dividers working on modulo n counter outputs
• Independent channel programming
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
10.4.8
Multimedia Card Interface
• 2 double-channel Multimedia Card Interface, allowing concurrent transfers with 2 cards
• Compatibility with MultiMedia Card Specification Version 3.31
• Compatibility with SD Memory Card Specification Version 1.0
• Compatibility with SDIO Specification Version V1.0.
• Cards clock rate up to Master Clock divided by 2
• Embedded power management to slow down clock rate when not used
• Each MCI has one slot supporting
– One MultiMediaCard bus (up to 30 cards) or
– One SD Memory Card
– One SDIO Card
• Support for stream, block and multi-block data read and write
10.4.9
CAN Controller
• Fully compliant with 16-mailbox CAN 2.0A and 2.0B CAN Controllers
• Bit rates up to 1Mbit/s.
• Object-oriented mailboxes, each with the following properties:
– CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
– Object Configurable as receive (with overwrite or not) or transmit
– Local Tag and Mask Filters up to 29-bit Identifier/Channel
– 32 bits access to Data registers for each mailbox data object
– Uses a 16-bit time stamp on receive and transmit message
– Hardware concatenation of ID unmasked bitfields to speedup family ID processing
– 16-bit internal timer for Time Stamping and Network synchronization
– Programmable reception buffer length up to 16 mailbox object
– Priority Management between transmission mailboxes
– Autobaud and listening mode
– Low power mode and programmable wake-up on bus activity or by the application
– Data, Remote, Error and Overload Frame handling
48
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
10.4.10
USB Host Port
• Compliance with OHCI Rev 1.0 Specification
• Compliance with USB V2.0 Full-speed and Low-speed Specification
• Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps devices
• Root hub integrated with two downstream USB ports
• Two embedded USB transceivers
• Supports power management
• Operates as a master on the Matrix
• Internal DMA Controller, operating as a Master on Bus Matrix
10.4.11
USB High Speed Device Port
• USB V2.0 high-speed compliant, 480 MBits per second
• Embedded USB V2.0 UTMI+ high-speed transceiver
• Embedded 4K-byte dual-port RAM for endpoints
• Embedded 6 channels DMA controller
• Suspend/Resume logic
• Up to 2 or 3 banks for isochronous and bulk endpoints
• Seven endpoints:
– Endpoint 0: 64 bytes
– Endpoint 1 & 2: 1024 bytes, 3 banks mode, HS isochronous capable
– Endpoint 3 & 4: 1024 bytes, 2 banks mode, HS isochronous capable
– Endpoint 5 & 6: 1024 bytes, 2 banks mode
– Endpoint 7: 1024 bytes, 2 banks mode
10.4.12
LCD Controller
• Single and Dual scan color and monochrome passive STN LCD panels supported
• Single scan active TFT LCD panels supported
• 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported
• Up to 24-bit single scan TFT interfaces supported
• Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays
• 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN
• 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN
• 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT
• Single clock domain architecture
• Resolution supported up to 2048x2048
• 2D-DMA Controller for management of virtual Frame Buffer
– Allows management of frame buffer larger than the screen size and moving the view
over this virtual frame buffer
• Automatic resynchronization of the frame buffer pointer to prevent flickering
49
6264C–CAP–24-Mar-09
10.4.13
Ethernet 10/100 MAC
• Compatibility with IEEE Standard 802.3
• 10 and 100 MBits per second data throughput capability
• Full- and half-duplex operations
• MII or RMII interface to the physical layer
• Register Interface to address, data, status and control registers
• Internal DMA Controller, operating as a Master on Bus Matrix
• Interrupt generation to signal receive and transmit completion
• 28-byte transmit and 28-byte receive FIFOs
• Automatic pad and CRC generation on transmitted frames
• Address checking logic to recognize four 48-bit addresses
• Support promiscuous mode where all valid frames are copied to memory
• Support physical layer management through MDIO interface control of alarm and update
time/calendar data in
10.4.14
Image Sensor Interface
• ITU-R BT. 601/656 8-bit mode external interface support
• Support for ITU-R BT.656-4 SAV and EAV synchronization
• Vertical and horizontal resolutions up to 2048 x 2048
• Preview Path up to 640*480
• Support for packed data formatting for YCbCr 4:2:2 formats
• Preview scaler to generate smaller size image
• Programmable frame capture rate
• Internal DMA Controller, operating as a Master on Bus Matrix
10.4.15
Analog-to-digital Converter
• 8-channel ADC
• 10-bit 440K samples/sec. Successive Approximation Register ADC
• -2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity
• Individual enable and disable of each channel
• External voltage reference for better accuracy on low voltage inputs
• Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter
0 to 2 outputs TIOA0 to TIOA2 and TIOB0 to TIOB2 triggers
• Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep
mode after conversions of all enabled channels
• Four analog inputs shared with digital signals
50
AT91CAP9S500A/AT91CAP9S250A
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AT91CAP9S500A/AT91CAP9S250A
11. Metal Programmable Block
The Metal Programmable Block (MPBlock) is connected to internal resources as the AHB bus or
interrupts and to external resources as dedicated I/O pads or UTMI+ core.
The MPBlock may be used to implement the Advanced High-speed Bus (AHB) or Advanced
Peripheral Bus (APB) custom peripherals. The MPBlock adds approximately 500K or 250K
gates of standard cell custom logic to the AT91CAP9S500A/AT91CAP9S250A base design.
Figure 11-1 shows the MPBlock and its connections to internal or external resources.
Figure 11-1. MPBlock Connectivity
ITs
DMA
AHB MASTERS
AHB SLAVES
MPBlock Test Wrapper
10x
CLOCKS
CAN,
MACB, OHCI
ENABLE
DPR
512x36
MPBLOCK
500K Gates (CAP9500)
250K Gates (CAP9250)
8x
SPR
512x72
CHIP ID
JTAG ID
UTMI+
PHY
Chip Boundary Scan
MPIOA[31:0]
11.1
MPIOB[44:0]
Internal Connectivity
In order to connect the MPBlock custom peripheral to the AT91CAP9S500A/AT91CAP9S250A
base design, the following connections are made.
11.1.1
Clocks
The MPBlock receives the following clocks:
• 32,768 Hz Slow Clock
• 8 to 16 MHz Main Oscillator Clock
• PLLA Clock
• PLLB Clock
• 48 MHz USB Clock
• 12 MHz USB Clock
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6264C–CAP–24-Mar-09
• 30 or 60 MHz UTMI+ USB Clock
• MCK System Clock
• DDRCK Dual Rate System Clock
• PCK Processor Clock
• 5 Gated Peripheral Clocks (for AHB and/or APB peripherals) corresponding to Peripheral ID
3 to 7
11.1.2
AHB Master Buses
The MPBlock may implement up to three AHB masters, each having a dedicated AHB master
bus connected to the Bus Matrix.
11.1.3
AHB Slave Buses
The MPBlock receives four different AHB slave buses coming from the Bus Matrix. Each bus
has two or four select signals that can implement up to 12 AHB slaves.
11.1.4
Interrupts
The MPBlock is connected to 5 dedicated interrupt lines corresponding to Peripheral ID 3 to 9.
It is also connected to two other interrupt lines (through OR gate) corresponding to Peripheral ID
1 and 2
11.1.5
DMA Channels
The MPBlock is connected to 4 DMA hardware handshaking interfaces, allowing it to implement
up to 4 DMA enabled peripherals.
11.1.6
Peripheral DMA Channels
The MPBlock is not connected to the Peripheral DMA Controller. In order to implement Peripheral DMA Controller (PDC) enabled APB peripherals, a PDC and an AHB-to-APB Bridge must
be integrated into the MPBlock using one AHB master and one AHB slave bus.
11.1.7
MPBlock Single Port RAMs
The MPBlock is connected to eight instances of 512x72 High-Speed Single Port RAMs.
The MPBlock has control over all memory connections.
11.1.8
MPBlock Dual Port RAMs
The MPBlock is connected to ten instances of 512x36 High-Speed Dual Port RAMs.
The MPBlock has control over all memory connections.
11.1.9
52
Optional Peripherals Enable
The MPBlock drives the enable of the optional peripherals, and so can enable or disable any of
the optional peripherals.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
11.2
External Connectivity
The MPBlock is connected to the following external resources.
11.2.1
Dedicated I/O Lines
The MPBlock is directly connected to 77 (32 MPIOA and 45 MPIOB lines) dedicated I/O Pads
with the following features:
• Supply/Drive control pin (needed for high-speed or low voltage interfaces)
• Pull-up control pin
• Supported logic levels include:
– LVCMOS33 at 100 MHz maximum frequency
– LVCMOS25 at 50 MHz maximum frequency
– LVCMOS18 at 100 MHz maximum frequency
11.2.2
11.3
UTMI+ Transceiver
The MPBlock may be connected to the UTMI+ transceiver. As only one UTMI+ transceiver is
available, the USB High-speed Device and the MPBlock do not have access to the UTMI+ at the
same time. However, a dual role Master-Slave USB High-Speed may be implemented by using
the USB High-speed Device and integrating a High-speed Host in the MPBlock as the switching
between both is generated inside the MPBlock.
Prototyping Solution
In order to prototype the final custom design, a Prototyping Platform version of the
AT91CAP9S500A/AT91CAP9S250A design has been created. The platform maps APB and
AHB masters or slaves into the FPGA located outside the chip with the following features and
restrictions:
• AT91CAP9S500A/AT91CAP9S250A to FPGA interface is provided to prototype AHB masters
and slave into the external FPGA exactly as if it were in MPBlock.
• Prototyped AHB Masters
– Prototyped AHB Masters have access to AT91CAP9S500A/AT91CAP9S250A slave
resources.
– Prototyped AHB Masters have access to MPBlock (FPGA) slave resources.
• Prototyped AHB Slaves
– Prototyped AHB Slaves may be accessed from AT91CAP9S500A/AT91CAP9S250A
master resources.
– Prototyped AHB Slaves may be accessed from MPBlock (FPGA) resources.
• Prototyped APB Slaves
– APB bus must be created locally in the FPGA by implementing AHB to APB bridge.
Peripheral DMA controller may also be necessary to implement locally in the FPGA
in order to prototype PDC enabled APB peripherals.
Figure 11-2 shows a typical prototyping solution.
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6264C–CAP–24-Mar-09
Figure 11-2. Typical Prototyping Solution
MASTERS
CAP9500
CAP9250
ARM926EJ-S
EBI
Bus Matrix
4-channel
DMA
Metal Programmable Block
500K Gates (CAP9500)
250K Gates (CAP9250)
FPGA Interface
MPIOA[31:0]
MPIOB[44:0]
FPGA
CAP9500/CAP9250 FPGA Interface
Local AHB Matrix
AHB
MASTER
DPR
AHB 2 APB
BRIDGE
AHB
MASTER
RAM
PDC
AHB
SLAVE
DPR
APB
DPR
APB
SLAVE
54
APB
SLAVE
MPBlock
Emulation Area
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
12. ARM926EJ-S Processor Overview
12.1
Overview
The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multitasking applications where full memory management, high performance, low die size and low
power are all important features.
The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets,
enabling the user to trade off between high performance and high code density. It also supports
8-bit Java instruction set and includes features for efficient execution of Java bytecode, providing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Javapowered wireless and embedded devices. It includes an enhanced multiplier design for
improved DSP performance.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist
in both hardware and software debug.
The ARM926EJ-S provides a complete high performance processor subsystem, including:
• an ARM9EJ-S™ integer core
• a Memory Management Unit (MMU)
• separate instruction and data AMBA AHB bus interfaces
• separate instruction and data TCM interfaces
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6264C–CAP–24-Mar-09
12.2
Block Diagram
Figure 12-1. ARM926EJ-S Internal Functional Block Diagram
CP15 System
Configuration
Coprocessor
External Coprocessors
ETM9
External
Coprocessor
Interface
Trace Port
Interface
Write Data
ARM9EJ-S
Processor Core
Instruction
Fetches
Read
Data
Data
Address
Instruction
Address
MMU
DTCM
Interface
Data TLB
Instruction
TLB
ITCM
Interface
Data TCM
Instruction TCM
Instruction
Address
Data
Address
Data Cache
AHB Interface
and
Write Buffer
Instruction
Cache
AMBA AHB
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AT91CAP9S500A/AT91CAP9S250A
12.3
12.3.1
ARM9EJ-S Processor
ARM9EJ-S Operating States
The ARM9EJ-S processor can operate in three different states, each with a specific instruction
set:
• ARM state: 32-bit, word-aligned ARM instructions.
• THUMB state: 16-bit, halfword-aligned Thumb instructions.
• Jazelle state: variable length, byte-aligned Jazelle instructions.
In Jazelle state, all instruction Fetches are in words.
12.3.2
Switching State
The operating state of the ARM9EJ-S core can be switched between:
• ARM state and THUMB state using the BX and BLX instructions, and loads to the PC
• ARM state and Jazelle state using the BXJ instruction
All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or
Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle
states occurs automatically on return from the exception handler.
12.3.3
Instruction Pipelines
The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions
to the processor.
A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch,
Decode, Execute, Memory and Writeback stages.
A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch,
Jazelle/Decode (two clock cycles), Execute, Memory and Writeback stages.
12.3.4
Memory Access
The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words
must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and
bytes can be placed on any byte boundary.
Because of the nature of the pipelines, it is possible for a value to be required for use before it
has been placed in the register bank by the actions of an earlier instruction. The ARM9EJ-S control logic automatically detects these cases and stalls the core or forward data.
12.3.5
Jazelle Technology
The Jazelle technology enables direct and efficient execution of Java byte codes on ARM processors, providing high performance for the next generation of Java-powered wireless and
embedded devices.
The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java
Virtual Machine). Java mode will appear as another state: instead of executing ARM or Thumb
instructions, it executes Java byte codes. The Java byte code decoder logic implemented in
ARM9EJ-S decodes 95% of executed byte codes and turns them into ARM instructions without
any overhead, while less frequently used byte codes are broken down into optimized sequences
of ARM instructions. The hardware/software split is invisible to the programmer, invisible to the
application and invisible to the operating system. All existing ARM registers are re-used in
Jazelle state and all registers then have particular functions in this mode.
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6264C–CAP–24-Mar-09
Minimum interrupt latency is maintained across both ARM state and Java state. Since byte
codes execution can be restarted, an interrupt automatically triggers the core to switch from
Java state to ARM state for the execution of the interrupt handler. This means that no special
provision has to be made for handling interrupts while executing byte codes, whether in hardware or in software.
12.3.6
ARM9EJ-S Operating Modes
In all states, there are seven operation modes:
• User mode is the usual ARM program execution state. It is used for executing most
application programs
• Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data
transfer or channel process
• Interrupt (IRQ) mode is used for general-purpose interrupt handling
• Supervisor mode is a protected mode for the operating system
• Abort mode is entered after a data or instruction prefetch abort
• System mode is a privileged user mode for the operating system
• Undefined mode is entered when an undefined instruction exception occurs
Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User Mode. The non-user
modes, known as privileged modes, are entered in order to service interrupts or exceptions or to
access protected resources.
12.3.7
ARM9EJ-S Registers
The ARM9EJ-S core has a total of 37 registers.
• 31 general-purpose 32-bit registers
• 6 32-bit status registers
Table 12-1 shows all the registers in all modes.
Table 12-1.
58
ARM9TDMI Modes and Registers Layout
User and
System Mode
Supervisor
Mode
Abort Mode
Undefined
Mode
Interrupt
Mode
Fast Interrupt
Mode
R0
R0
R0
R0
R0
R0
R1
R1
R1
R1
R1
R1
R2
R2
R2
R2
R2
R2
R3
R3
R3
R3
R3
R3
R4
R4
R4
R4
R4
R4
R5
R5
R5
R5
R5
R5
R6
R6
R6
R6
R6
R6
R7
R7
R7
R7
R7
R7
R8
R8
R8
R8
R8
R8_FIQ
R9
R9
R9
R9
R9
R9_FIQ
R10
R10
R10
R10
R10
R10_FIQ
R11
R11
R11
R11
R11
R11_FIQ
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Table 12-1.
ARM9TDMI Modes and Registers Layout
User and
System Mode
Supervisor
Mode
Abort Mode
Undefined
Mode
Interrupt
Mode
Fast Interrupt
Mode
R12
R12
R12
R12
R12
R12_FIQ
R13
R13_SVC
R13_ABORT
R13_UNDEF
R13_IRQ
R13_FIQ
R14
R14_SVC
R14_ABORT
R14_UNDEF
R14_IRQ
R14_FIQ
PC
PC
PC
PC
PC
PC
CPSR
CPSR
CPSR
CPSR
CPSR
CPSR
SPSR_SVC
SPSR_ABOR
T
SPSR_UNDE
F
SPSR_IRQ
SPSR_FIQ
Mode-specific banked registers
The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional
register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose
registers used to hold either data or address values. Register r14 is used as a Link register that
holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a program counter (PC), whereas the Current Program Status Register (CPSR) contains condition
code flags and the current mode bits.
In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers
(r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding
banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the values (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when
BL or BLX instructions are executed within interrupt or exception routines. There is another register called Saved Program Status Register (SPSR) that becomes available in privileged modes
instead of CPSR. This register contains condition code flags and the current mode bits saved as
a result of the exception that caused entry to the current (privileged) mode.
In all modes and due to a software agreement, register r13 is used as stack pointer.
The use and the function of all the registers described above should obey ARM Procedure Call
Standard (APCS) which defines:
• constraints on the use of registers
• stack conventions
• argument passing and result return
For more details, refer to ARM Software Development Kit.
The Thumb state register set is a subset of the ARM state set. The programmer has direct
access to:
• Eight general-purpose registers r0-r7
• Stack pointer, SP
• Link register, LR (ARM r14)
• PC
• CPSR
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6264C–CAP–24-Mar-09
There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see
the ARM9EJ-S Technical Reference Manual, revision r1p2 page 2-12).
12.3.7.1
Status Registers
The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The
program status registers:
• hold information about the most recently performed ALU operation
• control the enabling and disabling of interrupts
• set the processor operation mode
Figure 12-2. Status Register Format
31 30 29 28 27
24
N Z C V Q
J
7 6 5
Reserved
I F T
Jazelle state bit
Reserved
Sticky Overflow
Overflow
Carry/Borrow/Extend
Zero
Negative/Less than
0
Mode
Mode bits
Thumb state bit
FIQ disable
IRQ disable
Figure 12-2 shows the status register format, where:
• N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags
• The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic
instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve
DSP operations.
The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by
an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the
status of the Q flag.
• The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where:
– J = 0: The processor is in ARM or Thumb state, depending on the T bit
– J = 1: The processor is in Jazelle state.
• Mode: five bits to encode the current processor mode
12.3.7.2
Exceptions
Exception Types and Priorities
The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privi-
leged mode. The types of exceptions are:
• Fast interrupt (FIQ)
• Normal interrupt (IRQ)
• Data and Prefetched aborts (Abort)
• Undefined instruction (Undefined)
• Software interrupt and Reset (Supervisor)
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AT91CAP9S500A/AT91CAP9S250A
When an exception occurs, the banked version of R14 and the SPSR for the exception mode
are used to save the state.
More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen exceptions according to the following priority order:
• Reset (highest priority)
• Data Abort
• FIQ
• IRQ
• Prefetch Abort
• BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority)
The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive.
Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort
occurs at the same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to
resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer
error does not escape detection.
Exception Modes and Handling
Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an interrupt from a peripheral.
When handling an ARM exception, the ARM9EJ-S core performs the following operations:
1. Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new mode that has been entered. When the exception entry is from:
– ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction
into LR (current PC(r15) + 4 or PC + 8 depending on the exception).
– THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value
(current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the
program to resume from the correct place on return.
2. Copies the CPSR into the appropriate SPSR.
3. Forces the CPSR mode bits to a value that depends on the exception.
4. Forces the PC to fetch the next instruction from the relevant exception vector.
The register r13 is also banked across exception modes to provide each exception handler with
private stack pointer.
The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable
nesting of exceptions.
When an exception has completed, the exception handler must move both the return value in
the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies
according to the type of exception. This action restores both PC and the CPSR.
The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or
remove the requirement for register saving which minimizes the overhead of context switching.
The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be
completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as
invalid, but does not take the exception until the instruction reaches the Execute stage in the
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6264C–CAP–24-Mar-09
pipeline. If the instruction is not executed, for example because a branch occurs while it is in the
pipeline, the abort does not take place.
The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the
problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction
caused a Prefetch Abort.
A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until
the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for
example because a branch occurs while it is in the pipeline, the breakpoint does not take place.
12.3.8
ARM Instruction Set Overview
The ARM instruction set is divided into:
• Branch instructions
• Data processing instructions
• Status register transfer instructions
• Load and Store instructions
• Coprocessor instructions
• Exception-generating instructions
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition
code field (bits[31:28]).
For further details, see the ARM Technical Reference Manual.
Table 12-2 gives the ARM instruction mnemonic list.
Table 12-2.
Mnemonic
Operation
Mnemonic
Operation
MOV
Move
MVN
Move Not
ADD
Add
ADC
Add with Carry
SUB
Subtract
SBC
Subtract with Carry
RSB
Reverse Subtract
RSC
Reverse Subtract with Carry
CMP
Compare
CMN
Compare Negated
TST
Test
TEQ
Test Equivalence
AND
Logical AND
BIC
Bit Clear
EOR
Logical Exclusive OR
ORR
Logical (inclusive) OR
MUL
Multiply
MLA
Multiply Accumulate
SMULL
Sign Long Multiply
UMULL
Unsigned Long Multiply
SMLAL
Signed Long Multiply
Accumulate
UMLAL
Unsigned Long Multiply
Accumulate
MSR
B
BX
LDR
62
ARM Instruction Mnemonic List
Move to Status Register
Branch
MRS
BL
Move From Status Register
Branch and Link
Branch and Exchange
SWI
Software Interrupt
Load Word
STR
Store Word
LDRSH
Load Signed Halfword
LDRSB
Load Signed Byte
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Table 12-2.
Mnemonic
Mnemonic
Operation
Load Half Word
STRH
Store Half Word
LDRB
Load Byte
STRB
Store Byte
Load Register Byte with
Translation
STRBT
Store Register Byte with
Translation
LDRT
Load Register with Translation
STRT
Store Register with Translation
LDM
Load Multiple
STM
Store Multiple
SWP
Swap Word
MCR
Move To Coprocessor
MRC
Move From Coprocessor
LDC
Load To Coprocessor
STC
Store From Coprocessor
CDP
Coprocessor Data Processing
SWPB
Swap Byte
New ARM Instruction Set
.
Table 12-3.
Mnemonic
BXJ
New ARM Instruction Mnemonic List
Operation
Mnemonic
Operation
Branch and exchange to Java
MRRC
Move double from coprocessor
Branch, Link and exchange
MCR2
Alternative move of ARM reg to
coprocessor
SMLAxy
Signed Multiply Accumulate 16
* 16 bit
MCRR
Move double to coprocessor
SMLAL
Signed Multiply Accumulate
Long
CDP2
Alternative Coprocessor Data
Processing
SMLAWy
Signed Multiply Accumulate 32
* 16 bit
BKPT
Breakpoint
SMULxy
Signed Multiply 16 * 16 bit
PLD
SMULWy
Signed Multiply 32 * 16 bit
STRD
Store Double
Saturated Add
STC2
Alternative Store from
Coprocessor
Saturated Add with Double
LDRD
Load Double
Saturated subtract
LDC2
Alternative Load to
Coprocessor
BLX (1)
QADD
QDADD
QSUB
QDSUB
Notes:
12.3.10
Operation
LDRH
LDRBT
12.3.9
ARM Instruction Mnemonic List (Continued)
Saturated Subtract with double
CLZ
Soft Preload, Memory prepare
to load from address
Count Leading Zeroes
1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
Thumb Instruction Set Overview
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
• Branch instructions
• Data processing instructions
• Load and Store instructions
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• Load and Store multiple instructions
• Exception-generating instruction
For further details, see the ARM Technical Reference Manual.
Table 12-4 gives the Thumb instruction mnemonic list.
Table 12-4.
64
Thumb Instruction Mnemonic List
Mnemonic
Operation
Mnemonic
Operation
MOV
Move
MVN
Move Not
ADD
Add
ADC
Add with Carry
SUB
Subtract
SBC
Subtract with Carry
CMP
Compare
CMN
Compare Negated
TST
Test
NEG
Negate
AND
Logical AND
BIC
Bit Clear
EOR
Logical Exclusive OR
ORR
Logical (inclusive) OR
LSL
Logical Shift Left
LSR
Logical Shift Right
ASR
Arithmetic Shift Right
ROR
Rotate Right
MUL
Multiply
BLX
Branch, Link, and Exchange
B
Branch
BL
Branch and Link
BX
Branch and Exchange
SWI
Software Interrupt
LDR
Load Word
STR
Store Word
LDRH
Load Half Word
STRH
Store Half Word
LDRB
Load Byte
STRB
Store Byte
LDRSH
Load Signed Halfword
LDRSB
Load Signed Byte
LDMIA
Load Multiple
STMIA
Store Multiple
PUSH
Push Register to stack
POP
Pop Register from stack
BCC
Conditional Branch
BKPT
Breakpoint
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12.4
CP15 Coprocessor
Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the
items in the list below:
• ARM9EJ-S
• Caches (ICache, DCache and write buffer)
• TCM
• MMU
• Other system options
To control these features, CP15 provides 16 additional registers. See Table 12-5.
Table 12-5.
Register
0
Name
Access
(1)
Read/Unpredictable
ID Code
0
(1)
Cache type
Read/Unpredictable
0
TCM status(1)
Read/Unpredictable
1
Control
Read-write
2
Translation Table Base
Read-write
3
Domain Access Control
Read-write
4
Reserved
None
5
Notes:
CP15 Registers
(1)
Read-write
Data fault Status
(1)
5
Instruction fault status
Read-write
6
Fault Address
Read-write
7
Cache Operations
Read-write
8
TLB operations
Unpredictable/Write
(2)
9
cache lockdown
Read-write
9
TCM region
Read-write
10
TLB lockdown
Read-write
11
Reserved
None
12
Reserved
None
13
(1)
FCSE PID
Read-write
13
Context ID(1)
Read-write
14
Reserved
None
15
Test configuration
Read-write
1. Register locations 0,5, and 13 each provide access to more than one register. The register
accessed depends on the value of the opcode_2 field.
2. Register location 9 provides access to more than one register. The register accessed depends
on the value of the CRm field.
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12.4.1
CP15 Registers Access
CP15 registers can only be accessed in privileged mode by:
• MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register
to CP15.
• MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of
CP15 to an ARM register.
Other instructions like CDP, LDC, STC can cause an undefined instruction exception.
The assembler code for these instructions is:
MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.
The MCR, MRC instructions bit pattern is shown below:
31
30
29
28
cond
23
22
21
opcode_1
15
20
13
12
Rd
6
26
25
24
1
1
1
0
19
18
17
16
L
14
7
27
5
opcode_2
4
CRn
11
10
9
8
1
1
1
1
3
2
1
0
1
CRm
• CRm[3:0]: Specified Coprocessor Action
Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior.
• opcode_2[7:5]
Determines specific coprocessor operation code. By default, set to 0.
• Rd[15:12]: ARM Register
Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable.
• CRn[19:16]: Coprocessor Register
Determines the destination coprocessor register.
• L: Instruction Bit
0 = MCR instruction
1 = MRC instruction
• opcode_1[23:20]: Coprocessor Code
Defines the coprocessor specific code. Value is c15 for CP15.
• cond [31:28]: Condition
For more details, see Chapter 2 in ARM926EJ-S TRM.
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12.5
Memory Management Unit (MMU)
The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS, WindowsCE, and Linux.
These virtual memory features are memory access permission controls and virtual to physical
address translations.
The Virtual Address generated by the CPU core is converted to a Modified Virtual Address
(MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13. The
MMU translates modified virtual addresses to physical addresses by using a single, two-level
page table set stored in physical memory. Each entry in the set contains the access permissions
and the physical address that correspond to the virtual address.
The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These
entries contain a pointer to either a 1 MB section of physical memory along with attribute information (access permissions, domain, etc.) or an entry in the second level translation tables;
coarse table and fine table.
The second level translation tables contain two subtables, coarse table and fine table. An entry
in the coarse table contains a pointer to both large pages and small pages along with access
permissions. An entry in the fine table contains a pointer to large, small and tiny pages.
Table 7 shows the different attributes of each page in the physical memory.
Table 12-6.
Mapping Details
Mapping Name
Mapping Size
Access Permission By
Subpage Size
Section
1M byte
Section
-
Large Page
64K bytes
4 separated subpages
16K bytes
Small Page
4K bytes
4 separated subpages
1K byte
Tiny Page
1K byte
Tiny Page
-
The MMU consists of:
• Access control logic
• Translation Look-aside Buffer (TLB)
• Translation table walk hardware
12.5.1
Access Control Logic
The access control logic controls access information for every entry in the translation table. The
access control logic checks two pieces of access information: domain and access permissions.
The domain is the primary access control mechanism for a memory region; there are 16 of them.
It defines the conditions necessary for an access to proceed. The domain determines whether
the access permissions are used to qualify the access or whether they should be ignored.
The second access control mechanism is access permissions that are defined for sections and
for large, small and tiny pages. Sections and tiny pages have a single set of access permissions
whereas large and small pages can be associated with 4 sets of access permissions, one for
each subpage (quarter of a page).
12.5.2
Translation Look-aside Buffer (TLB)
The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going
through the translation process every time. When the TLB contains an entry for the MVA (Modi-
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fied Virtual Address), the access control logic determines if the access is permitted and outputs
the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU
signals the CPU core to abort.
If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked
to retrieve the translation information from the translation table in physical memory.
12.5.3
Translation Table Walk Hardware
The translation table walk hardware is a logic that traverses the translation tables located in
physical memory, gets the physical address and access permissions and updates the TLB.
The number of stages in the hardware table walking is one or two depending whether the
address is marked as a section-mapped access or a page-mapped access.
There are three sizes of page-mapped accesses and one size of section-mapped access. Pagemapped accesses are for large pages, small pages and tiny pages. The translation process
always begins with a level one fetch. A section-mapped access requires only a level one fetch,
but a page-mapped access requires an additional level two fetch. For further details on the
MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual.
12.5.4
MMU Faults
The MMU generates an abort on the following types of faults:
• Alignment faults (for data accesses only)
• Translation faults
• Domain faults
• Permission faults
The access control mechanism of the MMU detects the conditions that produce these faults. If
the fault is a result of memory access, the MMU aborts the access and signals the fault to the
CPU core.The MMU retains status and address information about faults generated by the data
accesses in the data fault status register and fault address register. It also retains the status of
faults generated by instruction fetches in the instruction fault status register.
The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and
the domain number of the aborted access when it happens. The fault address register (register 6
in CP15) holds the MVA associated with the access that caused the Data Abort. For further
details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual.
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12.6
Caches and Write Buffer
The ARM926EJ-S contains a 16KB Instruction Cache (ICache), a 16KB Data Cache (DCache),
and a write buffer. Although the ICache and DCache share common features, each still has
some specific mechanisms.
The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged
using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty
bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache
pollution control, and line replacement.
A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly
known as wrapping. This feature enables the caches to perform critical word first cache refilling.
This means that when a request for a word causes a read-miss, the cache performs an AHB
access. Instead of loading the whole line (eight words), the cache loads the critical word first, so
the processor can reach it quickly, and then the remaining words, no matter where the word is
located in the line.
The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7
(cache operations) and CP15 register 9 (cache lockdown).
12.6.1
Instruction Cache (ICache)
The ICache caches fetched instructions to be executed by the processor. The ICache can be
enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit.
When the MMU is enabled, all instruction fetches are subject to translation and permission
checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are
made and the physical address is flat-mapped to the modified virtual address. With the MVA use
disabled, context switching incurs ICache cleaning and/or invalidating.
When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see
Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM).
On reset, the ICache entries are invalidated and the ICache is disabled. For best performance,
ICache should be enabled as soon as possible after reset.
12.6.2
12.6.2.1
Data Cache (DCache) and Write Buffer
ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The operations of DCache and write buffer are
closely connected.
DCache
The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission
and translation checks. Data accesses that are aborted by the MMU do not cause line fills or
data accesses to appear on the AMBA ASB interface. If the MMU is disabled, all data accesses
are noncachable, nonbufferable, with no protection checks, and appear on the AHB bus. All
addresses are flat-mapped, VA = MVA = PA, which incurs DCache cleaning and/or invalidating
every time a context switch occurs.
The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and
uses it when writing modified lines back to external memory. This means that the MMU is not
involved in write-back operations.
Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other
one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the
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cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide
whether all, half or none is written back to memory.
DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see
Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM).
The DCache supports write-through and write-back cache operations, selected by memory
region using the C and B bits in the MMU translation tables.
The DCache contains an eight data word entry, single address entry write-back buffer used to
hold write-back data for cache line eviction or cleaning of dirty cache lines.
The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and
Write Buffer operations are closely connected as their configuration is set in each section by the
page descriptor in the MMU translation table.
12.6.2.2
Write Buffer
The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buffer is used for all writes to a bufferable region, write-through region and writeback region. It also allows to avoid stalling the processor when writes to external memory are
performed. When a store occurs, data is written to the write buffer at core speed (high speed).
The write buffer then completes the store to external memory at bus speed (typically slower than
the core speed). During this time, the ARM9EJ-S processor can preform other tasks.
DCache and Write Buffer support write-back and write-through memory regions, controlled by C
and B bits in each section and page descriptor within the MMU translation tables.
12.6.2.3
Write-though Operation
When a cache write hit occurs, the DCache line is updated. The updated data is then written to
the write buffer which transfers it to external memory.
When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in
the write buffer which transfers it to external memory.
12.6.2.4
Write-back Operation
When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its
contents are not up-to-date with those in the external memory.
When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in
the write buffer which transfers it to external memory.
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12.7
Bus Interface Unit
The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB
requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables
parallel access paths between multiple AHB masters and slaves in a system. This is achieved by
using a more complex interconnection matrix and gives the benefit of increased overall bus
bandwidth, and a more flexible system architecture.
The multi-master bus architecture has a number of benefits:
• It allows the development of multi-master systems with an increased bus bandwidth and a
flexible architecture.
• Each AHB layer becomes simple because it only has one master, so no arbitration or masterto-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to
support request and grant, nor do they have to support retry and split transactions.
• The arbitration becomes effective when more than one master wants to access the same
slave simultaneously.
12.7.1
Supported Transfers
The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or
bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into
packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not
support split and retry requests.
Table 8 gives an overview of the supported transfers and different kinds of transactions they are
used for.
Table 12-7.
HBurst[2:0]
Supported Transfers
Description
Single transfer of word, half word, or byte:
• data write (NCNB, NCB, WT, or WB that has missed in DCache)
SINGLE
Single transfer
• data read (NCNB or NCB)
• NC instruction fetch (prefetched and non-prefetched)
• page table walk read
INCR4
Four-word incrementing burst
Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB,
NCB, WT, or WB write.
INCR8
Eight-word incrementing burst
Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write.
WRAP8
Eight-word wrapping burst
Cache linefill
12.7.2
Thumb Instruction Fetches
All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses
on the AHB. If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time.
12.7.3
Address Alignment
The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the
necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses
are aligned to word boundaries.
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13. Debug and Test
13.1
Description
The AT91CAP9 features a number of complementary debug and test capabilities. A common
JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART
that can be used to upload an application into internal SRAM. It manages the interrupt handling
of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel.
A set of dedicated debug and test input/output pins gives direct access to these capabilities from
a PC-based test environment.
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13.2
Block Diagram
Figure 13-1. Debug and Test Block Diagram
TMS
TCK
TDI
NTRST
ICE/JTAG
TAP
Boundary
Port
JTAGSEL
TDO
RTCK
POR
Reset
and
Test
TST
ARM9EJ-S
ARM926EJ-S
ICE-RT
PIO
DTXD
DBGU
DRXD
PDC
TAP: Test Access Port
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13.3
13.3.1
Application Examples
Debug Environment
Figure 13-2 on page 75 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping
through the program.
Figure 13-2. Application Debug and Trace Environment Example
Host Debugger
ICE/JTAG
Interface
ICE/JTAG
Connector
RS232
Connector
AT91CAP9
Terminal
AT91CAP9-based Application
13.3.2
Test Environment
Figure 13-3 on page 75 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAGcompliant devices. These devices can be connected to form a single scan chain.
Figure 13-3. Application Test Environment Example
Test Adaptor
Tester
JTAG
Interface
ICE/JTAG
Connector
Chip n
AT91CAP9
Chip 2
Chip 1
AT91CAP9-based Application Board In Test
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13.4
Debug and Test Pin Description
Table 13-1.
Pin Name
Debug and Test Pin List
Function
Type
Active Level
Input/Output
Low
Input
High
Reset/Test
NRST
Microcontroller Reset
TST
Test Mode Select
ICE and JTAG
TCK
Test Clock
Input
TDI
Test Data In
Input
TDO
Test Data Out
TMS
Test Mode Select
RTCK
Returned Test Clock
NTRST
Test Reset
Input
JTAGSEL
JTAG Selection
Input
Output
Input
Output
Low
Debug Unit
13.5
13.5.1
DRXD
Debug Receive Data
Input
DTXD
Debug Transmit Data
Output
Functional Description
Test Pin
One dedicated pin, TST, is used to define the device operating mode. The user must make sure
that this pin is tied at low level to ensure normal operating conditions. Other values associated
with this pin are reserved for manufacturing test.
13.5.2
Embedded In-circuit Emulator
The ARM9EJ-S Embedded In-Circuit Emulator-RT is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an
ARM9EJ-S core embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is
examined through an ICE/JTAG port which allows instructions to be serially inserted into the
pipeline of the core without using the external data bus. Therefore, when in debug state, a storemultiple (STM) can be inserted into the instruction pipeline. This exports the contents of the
ARM9EJ-S registers. This data can be serially shifted out without affecting the rest of the
system.
There are two scan chains inside the ARM9EJ-S processor which support testing, debugging,
and programming of the EmbeddedICE-RT™. The scan chains are controlled by the ICE/JTAG
port.
EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly
between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed.
For further details on the Embedded In-Circuit-Emulator-RT, see the ARM document:
ARM9EJ-S Technical Reference Manual (DDI 0222A).
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13.5.3
JTAG Signal Description
• TMS is the Test Mode Select input which controls the transitions of the test interface state
machine.
• TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan
Register, Instruction Register, or other data registers).
• TDO is the Test Data Output line which is used to serially output the data from the JTAG
registers to the equipment controlling the test. It carries the sampled values from the
boundary scan chain (or other JTAG registers) and propagates them to the next chip in the
serial test circuit.
• NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in
ARM cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST
is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset
the debug logic with the NTRST pin assertion during 2.5 MCK periods.
• TCK is the Test Clock input which enables the test interface. TCK is pulsed by the equipment
controlling the test and not by the tested device. It can be pulsed at any frequency. Note the
maximum JTAG clock rate on ARM926EJ-S cores is 1/6th the clock of the CPU. This gives
5.45 kHz maximum initial JTAG clock rate for an ARM9E running from the 32.768 kHz slow
clock.
• RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock
handling by emulators. From some ICE Interface probes, this return signal can be used to
synchronize the TCK clock and ignore the given ratio between the ICE Interface clock and
system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in
boundary scan mode.
13.5.4
Debug Unit
The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several
debug and trace purposes and offers an ideal means for in-situ programming solutions and
debug monitor communication. Moreover, the association with two peripheral data controller
channels permits packet handling of these tasks with processor time reduced to a minimum.
The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals
that come from the ICE and that trace the activity of the Debug Communication Channel.The
Debug Unit allows blockage of access to the system through the ICE interface.
A specific register, the Debug Unit Chip ID Register, gives information about the product version
and its internal configuration.
The AT91CAP9 Debug Unit Chip ID value is 0x039A 03A0 on 32-bit width.
For further details on the Debug Unit, see the section “Debug Unit”.
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13.5.5
IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging
technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST
and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds
with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1
JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.
13.5.6
ID Code Register
Access: Read-only
31
30
29
28
27
VERSION
23
22
26
25
24
PART NUMBER
21
20
19
18
17
16
10
9
8
PART NUMBER
15
14
13
12
11
PART NUMBER
7
6
MANUFACTURER IDENTITY
5
4
3
MANUFACTURER IDENTITY
2
1
0
1
• MANUFACTURER IDENTITY[11:1]
Set to 0x01F.
Bit[0] Required by IEEE Std. 1149.1.
Set to 0x1.
JTAG ID Code value is 0x05B1_B03F.
• PART NUMBER[27:12]: Product Part Number
Product part Number is 0x5B1B
• VERSION[31:28]: Product Version Number
Set to 0x0.
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14. Boot Program
14.1
Description
The Boot Program is contained in the embedded ROM. It is also called “Rom Code” or “First
Level Bootloader”. At power on, if BMS is detected at 1, the boot memory is the embedded ROM
and the Boot Program is executed. (see Section 8.1.2 “Boot Strategies”).
The Boot Program consists of several steps. First, it performs device initialization. Then it
attempts to boot from external non-volatile memories (NVM). And finally, if no valid program has
been found in NVM, it executes a monitor called SAM-BA® monitor.
14.2
Flow Diagram
The Boot Program implements the algorithm in Figure 14-1.
Figure 14-1. Boot Program Algorithm Flow Diagram
Device Setup
Valid boot code
found in one
NVM
Yes
Copy and run it
in internal SRAM
No
SAM-BA Monitor
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14.3
Device Initialization
14.3.1
Clock at Startup
At boot startup, the processor clock (PCK) and the master clock (MCK) is the slow clock. The
slow clock can be an external 32 kHz crystal oscillator or the internal RC oscillator. By default
the slow clock is the internal RC oscillator. If a battery supplies the backup power and if the
external 32 kHz crystal oscillator was previously started up and selected, the slow clock at boot
is the external 32 kHz crystal oscillator (see Section 29.2 “Slow Clock Crystal Oscillator”).
14.3.2
Initialization Sequence
Initialization follows the steps described below:
1. Stack setup for ARM supervisor mode.
2. Main Oscillator Detection: (external crystal or external clock on XIN). The Main Oscillator is disabled at startup (MOSCEN=1). First it is bypassed (OSCBYPASS set at 1).
Then polling is done on the MAINRDY bit. As soon as this bit is raised, the Main Clock
Frequency field is analyzed (MAINF). If the value exceeds 16, an external clock connected on XIN is detected. If not, an external crystal oscillator connected between XIN
and XOUT (whose frequency is unknown at this moment) is detected.
3. Main Oscillator Enabling: If an external clock is connected on XIN, the Main Oscillator
does not need to be started. Otherwise, If an external clock is not connected on XIN,
the OSCBYPASS bit is cleared. The Main Oscillator is enabled with the maximum startup time and a polling is done on the MOSC bit to wait for stabilization.
4. Main Oscillator Selection: The Master Clock source is switched from Slow Clock to
the Main Oscillator without prescaler. Polling is done to wait for enabling. PCK and MCK
are now the Main Oscillator clock.
5. C variable initialization: Non zero-initialized data are initialized in RAM (copy from
ROM to RAM). Zero-initialized data are set to 0 in RAM.
6. PLLA initialization: PLLA is configured to allow communication on the USB link for the
SAM-BA monitor. Its configuration depends on the Main Oscillator source (external
clock or crystal) and on its frequency.
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14.4
14.4.1
NVM Boot
NVM Bootloader Program Description
Figure 14-2. NVM Bootloader Program
Start
Initialize NVM
Initialization OK ?
No
Restore the reset values
for the peripherals and
Jump to next boot solution
Yes
Valid code detection in NVM
NVM contains valid code
No
Yes
Copy the valid code
from external NVM to internal SRAM.
Restore the reset values for the peripherals.
Perform the REMAP and set the PC to 0
to jump to the downloaded application
End
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Figure 14-3. Remap Action after Download Completion
0x0000_0000
0x0000_0000
REMAP
Internal
ROM
Internal
SRAM
0x0010_0000
0x0010_0000
Internal
SRAM
Internal
SRAM
0x0040_0000
0x0040_0000
Internal
ROM
Internal
ROM
The NVM bootloader program initializes the NVM. It initializes the required PIO. It sets the right
peripheral, depending on the NVM and tries to access the memory. If the initialization fails, it
restores the reset values for the PIO and peripherals, then the next NVM bootloader program is
executed.
If the initialization is successful, the NVM bootloader program reads the beginning of the NVM
and determines if the NVM contains a valid code.
If the NVM does not contain a valid code, the NVM bootloader program restores the reset value
for the peripherals and then the next NVM bootloader program is executed.
If a valid code is found, this code is loaded from NVM into internal SRAM and executed by
branching at address 0x0000_0000 after remap. This code may be the application code or a
second-level bootloader. All the calls to functions are PC relative and do not use absolute
addresses.
14.4.2
14.4.2.1
Valid Code Detection
There are two kinds of valid code detection. Depending on the NVM bootloader, one or both of
them are used.
ARM Exception Vectors Check
The NVM bootloader program reads and analyzes the first 28 bytes corresponding to the first
seven ARM exception vectors. Except for the sixth vector, these bytes must implement the ARM
instructions for either branch or load the PC with PC relative addressing.
Figure 14-4. LDR Opcode
31
1
28 27
1
1
0
0
24 23
1
I
P
U
20 19
1
W
0
16 15
Rn
12 11
Rd
0
Offset
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Figure 14-5. B Opcode
31
1
28 27
1
1
0
1
24 23
0
1
0
0
Offset (24 bits)
Unconditional instruction: 0xE for bits 31 to 28
Load the PC with PC relative addressing instruction:
– Rn = Rd = PC = 0xF
– I==0 (12-bit immediate value)
– P==1 (pre-indexed)
– U offset added (U==1) or subtracted (U==0)
– W==1
The sixth vector, at offset 0x14, contains the size of the image to download. This vector must be
replaced by the user’s own vector. This information is described below.
Figure 14-6. Structure of the ARM Vector 6
31
0
Size of the code to download in bytes
The value has to be less than 28 Kbytes. 28 Kbytes is the maximum size for a valid code. This
size is the internal SRAM size minus the stack size used by the ROM Code at the end of the
internal SRAM.
Example:
An example of valid vectors follows:
14.4.2.2
00
ea000006
B
0x20
04
eafffffe
B
0x04
08
ea00002f
B
_main
0c
eafffffe
B
0x0c
10
eafffffe
B
0x10
14
00001234
B
0x14
18
eafffffe
B
0x18
<- Code size = 4660 bytes < 28 Kbytes
boot.bin file check
The NVM bootloader program looks for a boot.bin file in the root directory of a FAT12/16/32 formatted NVM Flash.
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14.4.3
NVM Bootloader Sequence
Figure 14-7. NVM Bootloader Sequence
Device
Setup
NAND Flash Boot
Yes
Copy from
NANDFlash to SRAM
Run
NAND Flash Bootloader
Yes
Copy from
SD Card to SRAM
Run
SD Card Bootloader
Yes
Copy from
SPI Flash to SRAM
Run
SPI Flash Bootloader
Yes
Copy from
TWI EEPROM to SRAM
Run
TWI EEPROM Bootloader
No
SD Card Boot
No
SPI Flash Boot
No
TWI EEPROM Boot
No
SAM-BA
Monitor
14.4.3.1
NAND Flash Boot
The NAND Flash bootloader program uses the EBI CS0. It uses both valid code detections. First
it searches a boot.bin file. Then it analyzes the ARM exception vectors.
The first block must be guaranteed by the manufacturer. There is no ECC check.
After NAND interface configuration, the Manufacturer ID is read. If it is different from 0xFF, the
Device ID is read. If not, the NAND Flash boot is aborted. The Boot program contains a list of
SLC small block Device ID with their characteristics (size, bus width, voltage) (see Table 14-1). If
the device ID is not found in this list, the NAND Flash device is considered as a SLC large block
and its characteristics are get by reading the Extended Device ID byte 3.
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Supported NAND Flash Devices
The SLC small block NAND Flash devices that are supported are described in the following
table.
Table 14-1.
Supported SLC Small Block NAND Flash
Device ID
Size
(Mbytes)
Page size
(bytes)
Block size
(bytes)
Bus width
Voltage (V)
0x6E
1
256
4096
8
5
0x64
2
256
4096
8
5
0x6B
4
512
8196
8
5
0xE8
1
256
4096
8
3.3
0xEC
1
256
4096
8
3.3
0xEA
2
256
4096
8
3.3
0xD5
4
512
8196
8
3.3
0xE3
4
512
8196
8
3.3
0xE5
4
512
8196
8
3.3
0xD6
8
512
8196
8
3.3
0x39
8
512
8196
8
1.8
0xE6
8
512
8196
8
3.3
0x49
8
512
8196
16
1.8
0x59
8
512
8196
16
3.3
0x33
16
512
16384
8
1.8
0x73
16
512
16384
8
3.3
0x43
16
512
16384
16
1.8
0x53
16
512
16384
16
3.3
0x35
32
512
16384
8
1.8
0x75
32
512
16384
8
3.3
0x45
32
512
16384
16
1.8
0x55
32
512
16384
16
3.3
0x36
64
512
16384
8
1.8
0x76
64
512
16384
8
3.3
0x46
64
512
16384
16
1.8
0x56
64
512
16384
16
3.3
0x78
128
512
16384
8
1.8
0x79
128
512
16384
8
3.3
0x72
128
512
16384
16
1.8
0x74
128
512
16384
16
3.3
The NAND boot also supports all the SLC large block NAND Flash devices.
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14.4.3.2
SDCard Boot
The SDCard bootloader uses the MCI0. It uses only one valid code detection. It searches a
boot.bin file.
Supported SDCard Devices
All SDCard memories compliant with SD Memory Card Specification V1.0. The SD Card boot
doesn’t support the SDHC cards.
14.4.3.3
SPI Flash Boot
The SPI Flash bootloader uses the SPI0, first on Chip Select 0, then on Chip Select 1. It uses
only one valid code detection. It analyzes the ARM exception vectors. Two kinds of SPI Flash
are supported, the DataFlash and the Serial Flash.
The SPI Flash read is done thanks to a Continuous Read command from address 0x0. This
command is common for DataFlash and Serial Flash devices.
Supported DataFlash Devices
The SPI Flash Boot program supports all Atmel DataFlash devices.
Table 14-2.
Device
DataFlash Device
Density
Page Size (bytes)
Number of Pages
AT45DB011
1 Mbit
264
512
AT45DB021
2 Mbits
264
1024
AT45DB041
4 Mbits
264
2048
AT45DB081
8 Mbits
264
4096
AT45DB161
16 Mbits
528
4096
AT45DB321
32 Mbits
528
8192
AT45DB642
64 Mbits
1056
8192
Supported Serial Flash Devices
The SPI Flash Boot program supports all Serial Flash devices.
14.4.3.4
TWI Eeprom Boot
The TWI EEPROM Bootloader uses TWI. It uses only one valid code detection. It analyzes the
ARM exception vectors.
Supported TWI EEPROM Devices
All TWI EEPROM memories using 7-bit device address 0x50.
14.4.4
Hardware and Software Constraints
The NVM drivers use several PIOs in alternate functions to communicate with devices. Care
must be taken when these PIOs are used by the application. The devices connected could be
unintentionally driven at boot time, and electrical conflicts between output pins used by the NVM
drivers and the connected devices may appear.
To assure correct functionality, it is recommended to plug in critical devices to other pins.
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Table 14-3 contains a list of pins that are driven during the boot program execution. These pins
are driven during the boot sequence for a period of less than 1 second if no correct boot program
is found.
Before performing the jump to the application in internal SRAM, all the PIOs and peripherals
used in the boot program are set to their reset state.
Table 14-3.
PIO Driven during Boot Program Execution
NVM Bootloader
Peripheral
Pin
PIO Line
EBI CS0 SMC
NANDCS
PIOD15
EBI CS0 SMC
NAND ALE
A21
EBI CS0 SMC
NAND CLE
A22
EBI CS0 SMC
Cmd/Addr/Data
D[16:0]
MCI0
MCI0_CK
PIOA2
MCI0
MCI0_CD
PIOA1
MCI0
MCI0_D0
PIOA0
MCI0
MCI0_D1
PIOA3
MCI0
MCI0_D2
PIOA4
MCI0
MCI0_D3
PIOA5
SPI0
MOSI
PIOA1
SPI0
MISO
PIOA0
SPI0
SPCK
PIOA2
SPI0
NPCS0
PIOA5
SPI0
NPCS1
PIOA3
TWI
TWD
PIOB4
TWI
TWCK
PIOB5
DBGU
DRXD
PIOC30
DBGU
DTXD
PIOC31
NAND
SD Card
SPI Flash
TWI Eeprom
SAM-BA monitor
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14.5
SAM-BA Monitor
If no valid code has been found in NVM during the NVM bootloader sequence, the SAM-BA
monitor program is performed.
The SAM-BA monitor principle is to:
– Initialize DBGU and USB
– Check if USB Device enumeration has occurred.
– Check if characters have been received on the DBGU.
– Once the communication interface is identified, the application runs in an infinite
loop waiting for different commands as in Table 14-4.
Figure 14-8. SAM-BA Monitor
No valid code in NVM
Init DBGU and USB
No
USB Enumeration
Successful ?
Yes
Run monitor
Wait for command
on the USB link
No
Character(s) received
on DBGU ?
Yes
Run monitor
Wait for command
on the DBGU link
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14.5.1
Command List
Table 14-4.
Commands Available through the SAM-BA Monitor
Command
Action
Argument(s)
Example
O
write a byte
Address, Value#
O200001,CA#
o
read a byte
Address,#
o200001,#
H
write a half word
Address, Value#
H200002,CAFE#
h
read a half word
Address,#
h200002,#
W
write a word
Address, Value#
W200000,CAFEDECA#
w
read a word
Address,#
w200000,#
S
send a file
Address,#
S200000,#
R
receive a file
Address, NbOfBytes#
R200000,1234#
G
go
Address#
G200200#
V
display version
No argument
V#
• Write commands: Write a byte (O), a halfword (H) or a word (W) to the target.
– Address: Address in hexadecimal.
– Value: Byte, halfword or word to write in hexadecimal.
– Output: ‘>’.
• Read commands: Read a byte (o), a halfword (h) or a word (w) from the target.
– Address: Address in hexadecimal
– Output: The byte, halfword or word read in hexadecimal followed by ‘>’
• Send a file (S): Send a file to a specified address
– Address: Address in hexadecimal
– Output: ‘>’.
Note:
There is a time-out on this command which is reached when the prompt ‘>’ appears before the
end of the command execution.
• Receive a file (R): Receive data into a file from a specified address
– Address: Address in hexadecimal
– NbOfBytes: Number of bytes in hexadecimal to receive
– Output: ‘>’
• Go (G): Jump to a specified address and execute the code
– Address: Address to jump in hexadecimal
– Output: ‘>’
• Get Version (V): Return the Boot Program version
– Output: the boot program version, followed by: ‘>’
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14.5.2
14.5.2.1
DBGU Serial Port
Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1.
Supported External Crystal/External Clocks
The supported frequencies by the SAM-BA monitor to allow the DBGU communication are:
• for external crystal: 12 MHz
• for external clock: 1.4 MHz, 2 MHz, 2.8 MHz, 4 MHz, 5.5 MHz, 7.5 MHz, 10 MHz, 14 MHz, 20
MHz, 28 MHz, 40 MHz, 50 MHz.
14.5.2.2
Xmodem Protocol
The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal
performing this protocol can be used to send the application file to the target. The size of the
binary file to send depends on the SRAM size embedded in the product. In all cases, the size of
the binary file must be lower than the SRAM size because the Xmodem protocol requires some
SRAM memory to work.
The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error.
Xmodem protocol with CRC is accurate provided both sender and receiver report successful
transmission. Each block of the transfer looks like:
<SOH><blk #><255-blk #><--128 data bytes--><checksum> in which:
– <SOH> = 01 hex
– <blk #> = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not
to 01)
– <255-blk #> = 1’s complement of the blk#.
– <checksum> = 2 bytes CRC16
Figure 14-9 shows a transmission using this protocol.
Figure 14-9. Xmodem Transfer Example
Host
Device
C
SOH 01 FE Data[128] CRC CRC
ACK
SOH 02 FD Data[128] CRC CRC
ACK
SOH 03 FC Data[100] CRC CRC
ACK
EOT
ACK
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14.5.3
14.5.3.1
USB Device Port
Supported External Crystal/External Clocks
The supported frequencies by the SAM-BA monitor to allow the USB communication are:
• for external crystal: 12 MHz
• for external clock: 5 MHz, 12 MHz, 27 MHz
14.5.3.2
USB Class
The device uses the USB communication device class (CDC) drivers to take advantage of the
installed PC RS-232 software to talk over the USB. The CDC class is implemented in all
releases of Windows®, from Windows 98SE to Windows XP. The CDC document, available at
www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM
ports.
The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are
used by the host operating system to mount the correct driver. On Windows systems, the INF
files contain the correspondence between vendor ID and product ID.
14.5.3.3
Enumeration Process
The USB protocol is a master/slave protocol. This is the host that starts the enumeration, sending requests to the device through the control endpoint. The device handles standard requests
as defined in the USB Specification.
Table 14-5.
Handled Standard Requests
Request
Definition
GET_DESCRIPTOR
Returns the current device configuration value.
SET_ADDRESS
Sets the device address for all future device access.
SET_CONFIGURATION
Sets the device configuration.
GET_CONFIGURATION
Returns the current device configuration value.
GET_STATUS
Returns status for the specified recipient.
SET_FEATURE
Used to set or enable a specific feature.
CLEAR_FEATURE
Used to clear or disable a specific feature.
The device also handles some class requests defined in the CDC class.
Table 14-6.
Handled Class Requests
Request
Definition
SET_LINE_CODING
Configures DTE rate, stop bits, parity and number of
character bits.
GET_LINE_CODING
Requests current DTE rate, stop bits, parity and number
of character bits.
SET_CONTROL_LINE_STATE
RS-232 signal used to tell the DCE device the DTE
device is now present.
Unhandled requests are STALLed.
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14.5.3.4
Communication Endpoints
There are two communication endpoints and endpoint 0 is used for the enumeration process.
Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAMBA Boot commands are sent by the host through the endpoint 1. If required, the message is split
by the host into several data payloads by the host driver.
If the command requires a response, the host can send IN transactions to pick up the response.
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15. Reset Controller (RSTC)
15.1
Description
The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last.
The Reset Controller also drives independently or simultaneously the external reset and the
peripheral and processor resets.
15.2
Block Diagram
Figure 15-1. Reset Controller Block Diagram
Reset Controller
Main Supply
POR
Backup Supply
POR
rstc_irq
Startup
Counter
Reset
State
Manager
proc_nreset
user_reset
NRST
nrst_out
NRST
Manager
periph_nreset
exter_nreset
backup_neset
WDRPROC
wd_fault
SLCK
15.3
15.3.1
Functional Description
Reset Controller Overview
The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State
Manager. It runs at Slow Clock and generates the following reset signals:
• proc_nreset: Processor reset line. It also resets the Watchdog Timer.
• backup_nreset: Affects all the peripherals powered by VDDBU.
• periph_nreset: Affects the whole set of embedded peripherals.
• nrst_out: Drives the NRST pin.
These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a
signal to the NRST Manager when an assertion of the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling
external device resets.
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The startup counter waits for the complete crystal oscillator startup. The wait delay is given by
the crystal oscillator startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical Characteristics section of the product documentation.
The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on.
15.3.2
NRST Manager
The NRST Manager samples the NRST input pin and drives this pin low when required by the
Reset State Manager. Figure 15-2 shows the block diagram of the NRST Manager.
Figure 15-2. NRST Manager
RSTC_MR
URSTIEN
RSTC_SR
URSTS
NRSTL
rstc_irq
RSTC_MR
URSTEN
Other
interrupt
sources
user_reset
NRST
RSTC_MR
ERSTL
nrst_out
15.3.2.1
External Reset Timer
exter_nreset
NRST Signal or Interrupt
The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low,
a User Reset is reported to the Reset State Manager.
However, the NRST Manager can be programmed to not trigger a reset when an assertion of
NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.
The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR.
As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only
when RSTC_SR is read.
The Reset Controller can also be programmed to generate an interrupt instead of generating a
reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1.
15.3.2.2
NRST External Reset Control
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this
occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the
field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts
2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs
and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that
the NRST line is driven low for a time compliant with potential external devices connected on the
system reset.
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As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system
power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator.
15.3.3
BMS Sampling
The product matrix manages a boot memory that depends on the level on the BMS pin at reset.
The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising
edge.
Figure 15-3. BMS Sampling
SLCK
Core Supply
POR output
BMS Signal
XXX
H or L
BMS sampling delay
= 3 cycles
proc_nreset
15.3.4
Reset States
The Reset State Manager handles the different reset sources and generates the internal reset
signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The
update of the field RSTTYP is performed when the processor reset is released.
15.3.4.1
General Reset
A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR
cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure the Slow Clock oscillator is stable before starting up the
device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup
time.
After this time, the processor clock is released at Slow Clock and all the other signals remain
valid for 2 cycles for proper processor and logic reset. Then, all the reset signals are released
and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the
NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0.
When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immediately asserted, even if the Main Supply POR Cell does not report a Main Supply shutdown.
VDDBU only activates the backup_nreset signal.
The backup_nreset must be released so that any other reset can be generated by VDDCORE
(Main Supply POR output).
Figure 15-4 shows how the General Reset affects the reset signals.
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Figure 15-4. General Reset State
SLCK
Any
Freq.
MCK
Backup Supply
POR output
Startup Time
Main Supply
POR output
backup_nreset
Processor Startup
= 2 cycles
proc_nreset
RSTTYP
XXX
0x0 = General Reset
XXX
periph_nreset
NRST
(nrst_out)
EXTERNAL RESET LENGTH
= 2 cycles
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15.3.4.2
Wake-up Reset
The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output
is active, all the reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled
during 2 Slow Clock cycles, depending on the requirements of the ARM processor.
At the end of this delay, the processor and other reset signals rise. The field RSTTYP in
RSTC_SR is updated to report a Wake-up Reset.
The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is
backed-up, the programmed number of cycles is applicable.
When the Main Supply is detected falling, the reset signals are immediately asserted. This transition is synchronous with the output of the Main Supply POR.
Figure 15-5. Wake-up State
SLCK
Any
Freq.
MCK
Main Supply
POR output
backup_nreset
Resynch.
2 cycles
Processor Startup
= 2 cycles
proc_nreset
RSTTYP
XXX
0x1 = WakeUp Reset
XXX
periph_nreset
NRST
(nrst_out)
EXTERNAL RESET LENGTH
= 4 cycles (ERSTL = 1)
97
6264C–CAP–24-Mar-09
15.3.4.3
User Reset
The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in
RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.
The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset
and the Peripheral Reset are asserted.
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 2-cycle
processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.
When the processor reset signal is released, the RSTTYP field of the Status Register
(RSTC_SR) is loaded with the value 0x4, indicating a User Reset.
The NRST Manager guarantees that the NRST line is asserted for
EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low
externally, the internal reset lines remain asserted until NRST actually rises.
Figure 15-6. User Reset State
SLCK
MCK
Any
Freq.
NRST
Resynch.
2 cycles
Resynch.
2 cycles
Processor Startup
= 2 cycles
proc_nreset
RSTTYP
Any
XXX
0x4 = User Reset
periph_nreset
NRST
(nrst_out)
>= EXTERNAL RESET LENGTH
98
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
15.3.4.4
Software Reset
The Reset Controller offers several commands used to assert the different reset signals. These
commands are performed by writing the Control Register (RSTC_CR) with the following bits
at 1:
• PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.
• PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory
system, and, in particular, the Remap Command. The Peripheral Reset is generally used for
debug purposes.
Except for Debug purposes, PERRST must always be used in conjunction with PROCRST
(PERRST and PROCRST set both at 1 simultaneously.)
• EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field
ERSTL in the Mode Register (RSTC_MR).
The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 2 Slow
Clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is
detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field
ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field
RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in
RSTTYP.
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left.
No other software reset can be performed while the SRCMP bit is set, and writing any value in
RSTC_CR has no effect.
99
6264C–CAP–24-Mar-09
Figure 15-7. Software Reset
SLCK
MCK
Any
Freq.
Write RSTC_CR
Resynch. Processor Startup
1 cycle
= 2 cycles
proc_nreset
if PROCRST=1
RSTTYP
Any
XXX
0x3 = Software Reset
periph_nreset
if PERRST=1
NRST
(nrst_out)
if EXTRST=1
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
SRCMP in RSTC_SR
15.3.4.5
Watchdog Reset
The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 2 Slow Clock
cycles.
When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in
WDT_MR:
• If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST
line is also asserted, depending on the programming of the field ERSTL. However, the
resulting low level on NRST does not result in a User Reset state.
• If WDRPROC = 1, only the processor reset is asserted.
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a
processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog
Reset, and the Watchdog is enabled by default and with a period set to a maximum.
When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset
controller.
100
AT91CAP9S500A/AT91CAP9S250A
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AT91CAP9S500A/AT91CAP9S250A
Figure 15-8. Watchdog Reset
SLCK
MCK
Any
Freq.
wd_fault
Processor Startup
= 2 cycles
proc_nreset
RSTTYP
Any
XXX
0x2 = Watchdog Reset
periph_nreset
Only if
WDRPROC = 0
NRST
(nrst_out)
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
15.3.5
Reset State Priorities
The Reset State Manager manages the following priorities between the different reset sources,
given in descending order:
• Backup Reset
• Wake-up Reset
• Watchdog Reset
• Software Reset
• User Reset
Particular cases are listed below:
• When in User Reset:
– A watchdog event is impossible because the Watchdog Timer is being reset by the
proc_nreset signal.
– A software reset is impossible, since the processor reset is being activated.
• When in Software Reset:
– A watchdog event has priority over the current state.
– The NRST has no effect.
• When in Watchdog Reset:
– The processor reset is active and so a Software Reset cannot be programmed.
– A User Reset cannot be entered.
101
6264C–CAP–24-Mar-09
15.3.6
Reset Controller Status Register
The Reset Controller status register (RSTC_SR) provides several status fields:
• RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
• SRCMP bit: This field indicates that a Software Reset Command is in progress and that no
further software reset should be performed until the end of the current one. This bit is
automatically cleared at the end of the current software reset.
• NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on
each MCK rising edge.
• URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR
register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure
15-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the
URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the
RSTC_SR status register resets the URSTS bit and clears the interrupt.
Figure 15-9.
Reset Controller Status and Interrupt
MCK
read
RSTC_SR
Peripheral Access
2 cycle
resynchronization
2 cycle
resynchronization
NRST
NRSTL
URSTS
rstc_irq
if (URSTEN = 0) and
(URSTIEN = 1)
102
AT91CAP9S500A/AT91CAP9S250A
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AT91CAP9S500A/AT91CAP9S250A
15.4
Reset Controller (RSTC) User Interface
Table 15-1.
Register Mapping
Offset
Register
Name
0x00
Control Register
0x04
0x08
Note:
Access
Reset
Back-up Reset
RSTC_CR
Write-only
-
Status Register
RSTC_SR
Read-only
0x0000_0001
0x0000_0000
Mode Register
RSTC_MR
Read-write
-
0x0000_0000
1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply.
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6264C–CAP–24-Mar-09
15.4.1
Name:
Reset Controller Control Register
RSTC_CR
Address:
0xFFFFFD00
Access:
Write-only
31
30
29
28
27
26
25
24
KEY
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
8
–
7
–
6
–
5
–
4
–
3
EXTRST
2
PERRST
1
–
0
PROCRST
• PROCRST: Processor Reset
0 = No effect.
1 = If KEY is correct, resets the processor.
• PERRST: Peripheral Reset
0 = No effect.
1 = If KEY is correct, resets the peripherals.
• EXTRST: External Reset
0 = No effect.
1 = If KEY is correct, asserts the NRST pin.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
104
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AT91CAP9S500A/AT91CAP9S250A
15.4.2
Name:
Reset Controller Status Register
RSTC_SR
Address:
0xFFFFFD04
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
SRCMP
16
NRSTL
15
–
14
–
13
–
12
–
11
–
10
9
RSTTYP
8
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
URSTS
• URSTS: User Reset Status
0 = No high-to-low edge on NRST happened since the last read of RSTC_SR.
1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
• RSTTYP: Reset Type
Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
RSTTYP
Reset Type
Comments
0
0
0
General Reset
Both VDDCORE and VDDBU rising
0
0
1
Wake Up Reset
VDDCORE rising
0
1
0
Watchdog Reset
Watchdog fault occurred
0
1
1
Software Reset
Processor reset required by the software
1
0
0
User Reset
NRST pin detected low
• NRSTL: NRST Pin Level
Registers the NRST Pin Level at Master Clock (MCK).
• SRCMP: Software Reset Command in Progress
0 = No software command is being performed by the reset controller. The reset controller is ready for a software command.
1 = A software reset command is being performed by the reset controller. The reset controller is busy.
105
6264C–CAP–24-Mar-09
15.4.3
Name:
Reset Controller Mode Register
RSTC_MR
Address:
0xFFFFFD08
Access:
Read-write
31
30
29
28
27
26
25
24
17
–
16
9
8
1
–
0
URSTEN
KEY
23
–
22
–
21
–
20
–
19
–
18
–
15
–
14
–
13
–
12
–
11
10
7
–
6
–
5
4
URSTIEN
3
–
ERSTL
2
–
• URSTEN: User Reset Enable
0 = The detection of a low level on the pin NRST does not generate a User Reset.
1 = The detection of a low level on the pin NRST triggers a User Reset.
• URSTIEN: User Reset Interrupt Enable
0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.
• ERSTL: External Reset Length
This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This
allows assertion duration to be programmed between 60 µs and 2 seconds.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
106
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6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
16. Real-time Timer (RTT)
16.1
Description
The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt and/or triggers an alarm on a programmed value.
16.2
Block Diagram
Figure 16-1. Real-time Timer
RTT_MR
RTTRST
RTT_MR
RTPRES
RTT_MR
SLCK
RTTINCIEN
reload
16-bit
Divider
set
0
RTT_MR
RTTRST
RTTINC
RTT_SR
1
reset
0
rtt_int
32-bit
Counter
read
RTT_SR
RTT_MR
ALMIEN
RTT_VR
reset
CRTV
RTT_SR
ALMS
set
rtt_alarm
=
RTT_AR
16.3
ALMV
Functional Description
The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by
Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field
RTPRES of the Real-time Mode Register (RTT_MR).
Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz
signal (if the Slow Clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0.
The Real-time Timer can also be used as a free-running timer with a lower time-base. The best
accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but
may result in losing status events because the status register is cleared two Slow Clock cycles
after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow
Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the
interrupt must be disabled in the interrupt handler and re-enabled when the status register is
clear.
107
6264C–CAP–24-Mar-09
The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time
Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value.
The current value of the counter is compared with the value written in the alarm register
RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in
RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF,
after a reset.
The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit
can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz.
Reading the RTT_SR status register resets the RTTINC and ALMS fields.
Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the
new programmed value. This also resets the 32-bit counter.
Note:
Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK):
1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2
slow clock cycles after the write of the RTTRST bit in the RTT_MR register.
2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the
RTT_SR (Status Register).
Figure 16-2. RTT Counting
APB cycle
APB cycle
SCLK
RTPRES - 1
Prescaler
0
RTT
0
...
ALMV-1
ALMV
ALMV+1
ALMV+2
ALMV+3
RTTINC (RTT_SR)
ALMS (RTT_SR)
APB Interface
read RTT_SR
108
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
16.4
Real-time Timer (RTT) User Interface
Table 16-1.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
Mode Register
RTT_MR
Read-write
0x0000_8000
0x04
Alarm Register
RTT_AR
Read-write
0xFFFF_FFFF
0x08
Value Register
RTT_VR
Read-only
0x0000_0000
0x0C
Status Register
RTT_SR
Read-only
0x0000_0000
109
6264C–CAP–24-Mar-09
16.4.1
Name:
Real-time Timer Mode Register
RTT_MR
Address:
0xFFFFFD20
Access Type:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
RTTRST
17
RTTINCIEN
16
ALMIEN
15
14
13
12
11
10
9
8
3
2
1
0
RTPRES
7
6
5
4
RTPRES
• RTPRES: Real-time Timer Prescaler Value
Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows:
RTPRES = 0: The prescaler period is equal to 216.
RTPRES …0: The prescaler period is equal to RTPRES.
• ALMIEN: Alarm Interrupt Enable
0 = The bit ALMS in RTT_SR has no effect on interrupt.
1 = The bit ALMS in RTT_SR asserts interrupt.
• RTTINCIEN: Real-time Timer Increment Interrupt Enable
0 = The bit RTTINC in RTT_SR has no effect on interrupt.
1 = The bit RTTINC in RTT_SR asserts interrupt.
• RTTRST: Real-time Timer Restart
1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.
110
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
16.4.2
Name:
Real-time Timer Alarm Register
RTT_AR
Address:
0xFFFFFD24
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ALMV
23
22
21
20
ALMV
15
14
13
12
ALMV
7
6
5
4
ALMV
• ALMV: Alarm Value
Defines the alarm value (ALMV+1) compared with the Real-time Timer.
16.4.3
Name:
Real-time Timer Value Register
RTT_VR
Address:
0xFFFFFD28
Access:
Read-only
31
30
29
28
CRTV
23
22
21
20
CRTV
15
14
13
12
CRTV
7
6
5
4
CRTV
• CRTV: Current Real-time Value
Returns the current value of the Real-time Timer.
111
6264C–CAP–24-Mar-09
16.4.4
Name:
Real-time Timer Status Register
RTT_SR
Address:
0xFFFFFD2C
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
RTTINC
0
ALMS
• ALMS: Real-time Alarm Status
0 = The Real-time Alarm has not occurred since the last read of RTT_SR.
1 = The Real-time Alarm occurred since the last read of RTT_SR.
• RTTINC: Real-time Timer Increment
0 = The Real-time Timer has not been incremented since the last read of the RTT_SR.
1 = The Real-time Timer has been incremented since the last read of the RTT_SR.
112
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
17. Periodic Interval Timer (PIT)
17.1
Description
The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is
designed to offer maximum accuracy and efficient management, even for systems with long
response time.
17.2
Block Diagram
Figure 17-1. Periodic Interval Timer
PIT_MR
PIV
=?
PIT_MR
PITIEN
set
0
PIT_SR
PITS
pit_irq
reset
0
MCK
Prescaler
0
0
1
12-bit
Adder
1
read PIT_PIVR
20-bit
Counter
MCK/16
CPIV
PIT_PIVR
CPIV
PIT_PIIR
PICNT
PICNT
113
6264C–CAP–24-Mar-09
17.3
Functional Description
The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems.
The PIT provides a programmable overflow counter and a reset-on-read feature. It is built
around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at
Master Clock /16.
The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the
field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to
0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in
PIT_MR).
Writing a new PIV value in PIT_MR does not reset/restart the counters.
When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register
(PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging
the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last
read of PIT_PIVR.
When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register
(PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer
interrupt clears the interrupt by reading PIT_PIVR.
The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on
reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 17-2 illustrates
the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until
the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again.
The PIT is stopped when the core enters debug state.
114
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AT91CAP9S500A/AT91CAP9S250A
Figure 17-2. Enabling/Disabling PIT with PITEN
APB cycle
APB cycle
MCK
15
restarts MCK Prescaler
MCK Prescaler 0
PITEN
CPIV
PICNT
0
1
PIV - 1
0
PIV
1
0
1
0
PITS (PIT_SR)
APB Interface
read PIT_PIVR
115
6264C–CAP–24-Mar-09
17.4
Periodic Interval Timer (PIT) User Interface
Table 17-1.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
Mode Register
PIT_MR
Read-write
0x000F_FFFF
0x04
Status Register
PIT_SR
Read-only
0x0000_0000
0x08
Periodic Interval Value Register
PIT_PIVR
Read-only
0x0000_0000
0x0C
Periodic Interval Image Register
PIT_PIIR
Read-only
0x0000_0000
116
AT91CAP9S500A/AT91CAP9S250A
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AT91CAP9S500A/AT91CAP9S250A
17.4.1
Name:
Periodic Interval Timer Mode Register
PIT_MR
Address:
0xFFFFFD30
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
23
–
22
–
21
–
20
–
19
18
15
14
13
12
25
PITIEN
24
PITEN
17
16
PIV
11
10
9
8
3
2
1
0
PIV
7
6
5
4
PIV
• PIV: Periodic Interval Value
Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to
(PIV + 1).
• PITEN: Period Interval Timer Enabled
0 = The Periodic Interval Timer is disabled when the PIV value is reached.
1 = The Periodic Interval Timer is enabled.
• PITIEN: Periodic Interval Timer Interrupt Enable
0 = The bit PITS in PIT_SR has no effect on interrupt.
1 = The bit PITS in PIT_SR asserts interrupt.
117
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
17.4.2
Name:
Periodic Interval Timer Status Register
PIT_SR
Address:
0xFFFFFD34
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
PITS
• PITS: Periodic Interval Timer Status
0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR.
1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
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17.4.3
Name:
Periodic Interval Timer Value Register
PIT_PIVR
Address:
0xFFFFFD38
Access:
Read-only
31
30
29
28
27
26
19
18
25
24
17
16
PICNT
23
22
21
20
PICNT
15
14
CPIV
13
12
11
10
9
8
3
2
1
0
CPIV
7
6
5
4
CPIV
Reading this register clears PITS in PIT_SR.
• CPIV: Current Periodic Interval Value
Returns the current value of the periodic interval timer.
• PICNT: Periodic Interval Counter
Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
119
6264C–CAP–24-Mar-09
17.4.4
Name:
Periodic Interval Timer Image Register
PIT_PIIR
Address:
0xFFFFFD3C
Access:
Read-only
31
30
29
28
27
26
19
18
25
24
17
16
PICNT
23
22
21
20
PICNT
15
14
CPIV
13
12
11
10
9
8
3
2
1
0
CPIV
7
6
5
4
CPIV
• CPIV: Current Periodic Interval Value
Returns the current value of the periodic interval timer.
• PICNT: Periodic Interval Counter
Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
120
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18. Watchdog Timer (WDT)
18.1
Description
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in
a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds
(slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition,
it can be stopped while the processor is in debug mode or idle mode.
18.2
Block Diagram
Figure 18-1. Watchdog Timer Block Diagram
write WDT_MR
WDT_MR
WDV
WDT_CR
WDRSTT
reload
1
0
12-bit Down
Counter
WDT_MR
WDD
reload
Current
Value
1/128
SLCK
<= WDD
WDT_MR
WDRSTEN
= 0
wdt_fault
(to Reset Controller)
set
set
read WDT_SR
or
reset
WDERR
reset
WDUNF
reset
wdt_int
WDFIEN
WDT_MR
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6264C–CAP–24-Mar-09
18.3
Functional Description
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in
a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset.
The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in
the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock
divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow
Clock of 32.768 kHz).
After a Processor Reset, the value of WDV is 0xFFF, corresponding to the maximum value of
the counter with the external reset generation enabled (field WDRSTEN at 1 after a Backup
Reset). This means that a default Watchdog is running at reset, i.e., at power-up. The user must
either disable it (by setting the WDDIS bit in WDT_MR) if he does not expect to use it or must
reprogram it to meet the maximum Watchdog period the application requires.
The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset
resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode
parameters.
In normal operation, the user reloads the Watchdog at regular intervals before the timer underflow occurs, by writing the Control Register (WDT_CR) with the bit WDRSTT to 1. The
Watchdog counter is then immediately reloaded from WDT_MR and restarted, and the Slow
Clock 128 divider is reset and restarted. The WDT_CR register is write-protected. As a result,
writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur,
the “wdt_fault” signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode
Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register
(WDT_SR).
To prevent a software deadlock that continuously triggers the Watchdog, the reload of the
Watchdog must occur while the Watchdog counter is within a window between 0 and WDD,
WDD is defined in the WatchDog Mode Register WDT_MR.
Any attempt to restart the Watchdog while the Watchdog counter is between WDV and WDD
results in a Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the
WDT_SR and the “wdt_fault” signal to the Reset Controller is asserted.
Note that this feature can be disabled by programming a WDD value greater than or equal to the
WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole
range [0; WDV] and does not generate an error. This is the default configuration on reset (the
WDD and WDV values are equal).
The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an interrupt, provided the bit WDFIEN is set in the mode register. The signal “wdt_fault” to the reset
controller causes a Watchdog reset if the WDRSTEN bit is set as already explained in the reset
controller programmer Datasheet. In that case, the processor and the Watchdog Timer are
reset, and the WDERR and WDUNF flags are reset.
If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared,
and the “wdt_fault” signal to the reset controller is deasserted.
Writing the WDT_MR reloads and restarts the down counter.
While the processor is in debug state or in idle mode, the counter may be stopped depending on
the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR.
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Figure 18-2. Watchdog Behavior
Watchdog Error
Watchdog Underflow
if WDRSTEN is 1
FFF
Normal behavior
if WDRSTEN is 0
WDV
Forbidden
Window
WDD
Permitted
Window
0
Watchdog
Fault
123
WDT_CR = WDRSTT
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
18.4
Watchdog Timer (WDT) User Interface
Table 18-1.
Register Mapping
Offset
Register
Name
0x00
Control Register
0x04
0x08
124
Access
Reset
WDT_CR
Write-only
-
Mode Register
WDT_MR
Read-write Once
0x3FFF_2FFF
Status Register
WDT_SR
Read-only
0x0000_0000
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
18.4.1
Name:
Watchdog Timer Control Register
WDT_CR
Address:
0xFFFFFD40
Access:
Write-only
31
30
29
28
27
26
25
24
KEY
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
WDRSTT
• WDRSTT: Watchdog Restart
0: No effect.
1: Restarts the Watchdog.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
125
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18.4.2
Name:
Watchdog Timer Mode Register
WDT_MR
Address:
0xFFFFFD44
Access:
Read-write Once
31
30
23
22
29
WDIDLEHLT
28
WDDBGHLT
27
21
20
19
11
26
25
24
18
17
16
10
9
8
1
0
WDD
WDD
15
WDDIS
14
13
12
WDRPROC
WDRSTEN
WDFIEN
7
6
5
4
WDV
3
2
WDV
• WDV: Watchdog Counter Value
Defines the value loaded in the 12-bit Watchdog Counter.
• WDFIEN: Watchdog Fault Interrupt Enable
0: A Watchdog fault (underflow or error) has no effect on interrupt.
1: A Watchdog fault (underflow or error) asserts interrupt.
• WDRSTEN: Watchdog Reset Enable
0: A Watchdog fault (underflow or error) has no effect on the resets.
1: A Watchdog fault (underflow or error) triggers a Watchdog reset.
• WDRPROC: Watchdog Reset Processor
0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets.
1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset.
• WDD: Watchdog Delta Value
Defines the permitted range for reloading the Watchdog Timer.
If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer.
If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error.
• WDDBGHLT: Watchdog Debug Halt
0: The Watchdog runs when the processor is in debug state.
1: The Watchdog stops when the processor is in debug state.
• WDIDLEHLT: Watchdog Idle Halt
0: The Watchdog runs when the system is in idle mode.
1: The Watchdog stops when the system is in idle state.
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• WDDIS: Watchdog Disable
0: Enables the Watchdog Timer.
1: Disables the Watchdog Timer.
127
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18.4.3
Name:
Watchdog Timer Status Register
WDT_SR
Address:
0xFFFFFD48
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
WDERR
0
WDUNF
• WDUNF: Watchdog Underflow
0: No Watchdog underflow occurred since the last read of WDT_SR.
1: At least one Watchdog underflow occurred since the last read of WDT_SR.
• WDERR: Watchdog Error
0: No Watchdog error occurred since the last read of WDT_SR.
1: At least one Watchdog error occurred since the last read of WDT_SR.
128
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19. General Purpose Backup Registers (GPBR)
19.1
Description
The System Controller embeds 4 general-purpose backup registers.
19.2
General Purpose Backup Registers (GPBR) User Interface
Table 19-1.
Register Mapping
Offset
0x0
...
0xC
Register
Name
General Purpose Backup Register 0
SYS_GPBR0
...
...
General Purpose Backup Register 3
SYS_GPBR3
Access
Reset
Read-write
–
...
...
Read-write
–
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6264C–CAP–24-Mar-09
19.2.1
Name:
General Purpose Backup Register x
SYS_GPBRx
Addresses: 0xFFFFFD60 [0], 0xFFFFFD64 [1], 0xFFFFFD68 [2], 0xFFFFFD6C [3]
Access:
31
Read-write
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
GPBR_VALUEx
23
22
21
20
19
GPBR_VALUEx
15
14
13
12
11
GPBR_VALUEx
7
6
5
4
3
GPBR_VALUEx
• GPBR_VALUEx: Value of GPBR x
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20. Shutdown Controller (SHDWC)
20.1
Description
The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up
detection on debounced input lines.
20.2
Block Diagram
Figure 20-1. Shutdown Controller Block Diagram
SLCK
Shutdown Controller
read SHDW_SR
SHDW_MR
CPTWK0
reset
WAKEUP0
WKMODE0
SHDW_SR
set
WKUP0
read SHDW_SR
Wake-up
reset
RTTWKEN
SHDW_MR
RTT Alarm
RTTWK
SHDW_SR
set
SHDW_CR
SHDW
20.3
SHDN
Shutdown
Output
Controller
Shutdown
I/O Lines Description
Table 20-1.
I/O Lines Description
Name
Description
Type
WKUP0
Wake-up 0 input
Input
SHDN
Shutdown output
Output
20.4
20.4.1
20.5
Product Dependencies
Power Management
The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Controller has no effect on the behavior of the Shutdown Controller.
Functional Description
The Shutdown Controller manages the main power supply. To do so, it is supplied with VDDBU
and manages wake-up input pins and one output pin, SHDN.
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A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter providing the main power supplies of the system, and especially VDDCORE and/or VDDIO. The
wake-up inputs (WKUP0) connect to any push-buttons or signal that wake up the system.
The software is able to control the pin SHDN by writing the Shutdown Control Register
(SHDW_CR) with the bit SHDW at 1. The shutdown is taken into account only 2 slow clock
cycles after the write of SHDW_CR. This register is password-protected and so the value written
should contain the correct key for the command to be taken into account. As a result, the system
should be powered down.
A level change on WKUP0 is used as wake-up. Wake-up is configured in the Shutdown Mode
Register (SHDW_MR). The transition detector can be programmed to detect either a positive or
negative transition or any level change on WKUP0. The detection can also be disabled. Programming is performed by defining WKMODE0.
Moreover, a debouncing circuit can be programmed for WKUP0. The debouncing circuit filters
pulses on WKUP0 shorter than the programmed number of 16 SLCK cycles in CPTWK0 of the
SHDW_MR register. If the programmed level change is detected on a pin, a counter starts.
When the counter reaches the value programmed in the corresponding field, CPTWK0, the
SHDN pin is released. If a new input change is detected before the counter reaches the corresponding value, the counter is stopped and cleared. WAKEUP0 of the Status Register
(SHDW_SR) reports the detection of the programmed events on WKUP0 with a reset after the
read of SHDW_SR.
The Shutdown Controller can be programmed so as to activate the wake-up using the RTT
alarm (the detection of the rising edge of the RTT alarm is synchronized with SLCK). This is
done by writing the SHDW_MR register using the RTTWKEN fields. When enabled, the detection of the RTT alarm is reported in the RTTWK bit of the SHDW_SR Status register. It is reset
after the read of SHDW_SR. When using the RTT alarm to wake up the system, the user must
ensure that the RTT alarm status flag is cleared before shutting down the system. Otherwise, no
rising edge of the status flag may be detected and the wake-up fails.
132
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20.6
Shutdown Controller (SHDWC) User Interface
Table 20-2.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
Shutdown Control Register
SHDW_CR
Write-only
-
0x04
Shutdown Mode Register
SHDW_MR
Read-write
0x0000_0003
0x08
Shutdown Status Register
SHDW_SR
Read-only
0x0000_0000
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6264C–CAP–24-Mar-09
20.6.1
Name:
Shutdown Control Register
SHDW_CR
Address:
0xFFFFFD10
Access:
Write-only
31
30
29
28
27
26
25
24
KEY
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
SHDW
• SHDW: Shutdown Command
0 = No effect.
1 = If KEY is correct, asserts the SHDN pin.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
134
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AT91CAP9S500A/AT91CAP9S250A
20.6.2
Name:
Shutdown Mode Register
SHDW_MR
Address:
0xFFFFFD14
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
RTTWKEN
15
14
13
12
11
–
10
–
9
3
–
2
–
1
–
7
6
5
4
CPTWK0
8
–
0
WKMODE0
• WKMODE0: Wake-up Mode 0
WKMODE[1:0]
Wake-up Input Transition Selection
0
0
None. No detection is performed on the wake-up input
0
1
Low to high level
1
0
High to low level
1
1
Both levels change
• CPTWK0: Counter on Wake-up 0
Defines the number of 16 Slow Clock cycles, the level detection on the corresponding input pin shall last before the wakeup event occurs. Because of the internal synchronization of WKUP0, the SHDN pin is released
(CPTWK x 16 + 1) Slow Clock cycles after the event on WKUP.
• RTTWKEN: Real-time Timer Wake-up Enable
0 = The RTT Alarm signal has no effect on the Shutdown Controller.
1 = The RTT Alarm signal forces the de-assertion of the SHDN pin.
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6264C–CAP–24-Mar-09
20.6.3
Name:
Shutdown Status Register
SHDW_SR
Address:
0xFFFFFD18
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
RTTWK
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
WAKEUP0
• WAKEUP0: Wake-up 0 Status
0 = No wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR.
1 = At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR.
• RTTWK: Real-time Timer Wake-up
0 = No wake-up alarm from the RTT occurred since the last read of SHDW_SR.
1 = At least one wake-up alarm from the RTT occurred since the last read of SHDW_SR.
136
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21. Bus Matrix
21.1
Description
The Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel
access paths between multiple AHB masters and slaves in a system, which increases the overall bandwidth. Bus Matrix interconnects 12 AHB Masters to 10 AHB Slaves. The normal latency
to connect a master to a slave is one cycle except for the default master of the accessed slave
which is connected directly (zero cycle latency).
The Bus Matrix user interface is compliant with the ARM Advanced Peripheral Bus and provides
a Chip Configuration User Interface with Registers that allow the Bus Matrix to support application specific features.
21.2
Memory Mapping
The Bus Matrix provides one decoder for every AHB Master Interface. The decoder offers each
AHB Master several memory mappings. In fact, depending on the product, each memory area
may be assigned to several slaves. Booting at the same address while using different AHB
slaves (i.e. external RAM, internal ROM or internal Flash etc.) becomes possible.
The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that
allows to perform remap action for every master independently.
21.3
Special Bus Granting Techniques
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access
requests from some masters. This mechanism allows to reduce latency at first accesses of a
burst or single transfer. The bus granting mechanism allows to set a default master for every
slave.
At the end of the current access, if no other request is pending, the slave remains connected to
its associated default master. A slave can be associated with three kinds of default masters: no
default master, last access master and fixed default master.
21.3.1
No Default Master
At the end of the current access, if no other request is pending, the slave is disconnected from
all masters. No Default Master, suits low power mode.
21.3.2
Last Access Master
At the end of the current access, if no other request is pending, the slave remains connected to
the last master that performed an access request.
21.3.3
Fixed Default Master
At the end of the current access, if no other request is pending, the slave connects to its fixed
default master. Unlike last access master, the fixed master doesn’t change unless the user modifies it by a software action (field FIXED_DEFMSTR of the related MATRIX_SCFG).
To change from one kind of default master to another, the Bus Matrix user interface provides the
Slave Configuration Registers, one for each slave, that allow to set a default master for each
slave. The Slave Configuration Register contains two fields:
• DEFMSTR_TYPE and
• FIXED_DEFMSTR
137
6264C–CAP–24-Mar-09
The 2-bit DEFMSTR_TYPE field selects the default master type (no default, last access master,
fixed default master) whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master
provided that DEFMSTR_TYPE is set to fixed default master. Refer to the Section 21.6 “Bus
Matrix (MATRIX) User Interface”.
21.4
Arbitration
The Bus Matrix provides an arbitration mechanism that allows to reduce latency when conflict
cases occur, basically when two or more masters try to access the same slave at the same time.
One arbiter per AHB slave is provided, arbitrating each slave differently.
The Bus Matrix provides to the user the possibility to choose between 2 arbitration types, and
this for each slave:
1. Round-Robin Arbitration (the default)
2. Fixed Priority Arbitration
This choice is given through the field ARBT of the Slave Configuration Registers
(MATRIX_SCFG).
Each algorithm may be complemented by selecting a default master configuration for each
slave.
When a re-arbitration has to be done, it is realized only under some specific conditions detailed
in the following paragraph.
21.4.1
Arbitration Rules
Each arbiter has the ability to arbitrate between two or more different master’s requests. In order
to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following cycles:
1. Idle Cycles: when a slave is not connected to any master or is connected to a master
which is not currently accessing it.
2. Single Cycles: when a slave is currently doing a single access.
3. End of Burst Cycles: when the current cycle is the last cycle of a burst transfer. For
defined length burst, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst (see Section 21.4.1.1 “Undefined Length
Burst Arbitration”).
4. Slot Cycle Limit: when the slot cycle counter has reach the limit value indicating that the
current master access is too long and must be broken (see Section 21.4.1.2 “Slot Cycle
Limit Arbitration”).
21.4.1.1
Undefined Length Burst Arbitration
In order to avoid too long slave handling during undefined length bursts (INCR), the Bus Matrix
provides specific logic in order to re-arbitrate before the end of the INCR transfer.
A predicted end of burst is used as for defined length burst transfer, which is selected between
the following:
1. Infinite: no predicted end of burst is generated and therefore INCR burst transfer will
never be broken.
2. Four beat bursts: predicted end of burst is generated at the end of each four beat
boundary inside INCR transfer.
3. Eight beat bursts: predicted end of burst is generated at the end of each eight beat
boundary inside INCR transfer.
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4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat
boundary inside INCR transfer.
This selection can be done through the field ULBT of the Master Configuration Registers
(MATRIX_MCFG).
21.4.1.2
21.4.2
Slot Cycle Limit Arbitration
The Bus Matrix contains specific logic to break too long accesses such as very long bursts on a
very slow slave (e.g. an external low speed memory). At the beginning of the burst access, a
counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave
Configuration Register (MATRIX_SCFG) and decreased at each clock cycle. When the counter
reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or
word transfer.
Round-Robin Arbitration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to
the same slave in a round-robin manner. If two or more master’s requests arise at the same
time, the master with the lowest number is first serviced then the others are serviced in a roundrobin manner.
There are three round-robin algorithms implemented:
• Round-Robin arbitration without default master
• Round-Robin arbitration with last access master
• Round-Robin arbitration with fixed default master
21.4.2.1
Round-Robin Arbitration without Default Master
This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch
requests from different masters to the same slave in a pure round-robin manner. At the end of
the current access, if no other request is pending, the slave is disconnected from all masters.
This configuration incurs one latency cycle for the first access of a burst. Arbitration without
default master can be used for masters that perform significant bursts.
21.4.2.2
Round-Robin Arbitration with Last Access Master
This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to
remove the one latency cycle for the last master that accessed the slave. In fact, at the end of
the current transfer, if no other master request is pending, the slave remains connected to the
last master that performs the access. Other non privileged masters still get one latency cycle if
they want to access the same slave. This technique can be used for masters that mainly perform
single accesses.
21.4.2.3
Round-Robin Arbitration with Fixed Default Master
This is another biased round-robin algorithm, it allows the Bus Matrix arbiters to remove the one
latency cycle for the fixed default master per slave. At the end of the current access, the slave
remains connected to its fixed default master. Every request attempted by this fixed default master will not cause any latency whereas other non privileged masters will still get one latency
cycle. This technique can be used for masters that mainly perform single accesses.
139
6264C–CAP–24-Mar-09
21.4.3
Fixed Priority Arbitration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to
the same slave by using the fixed priority defined by the user. If two or more master’s requests
are active at the same time, the master with the highest priority number is serviced first. If two or
more master’s requests with the same priority are active at the same time, the master with the
highest number is serviced first.
For each slave, the priority of each master may be defined through the Priority Registers for
Slaves (MATRIX_PRAS and MATRIX_PRBS).
21.5
EBI Pad Output Strength
In order to manage 1.8 or 3.3V memory devices, the Output Strength (OS) of the EBI pads are
programmable.
The EBI pads are divided into 3 groups:
• DATA (D0-D15, DQM0-DQM1)
• SDCK (DQS0-DQS1, SDCK, SDCKN, BCCK)
• ADDR (A2-A22, D16-D31, DQM2-DQM3, NANDWE, NANDOE, SDA10, NWR0, NCS0,
NCS1, NRD, RAS, CAS,SDWE,SDCKW,SDDRCS, PD7-PD15)
According to the mode, the EBI pad groups can be controlled together or independently. (See,
Section 21.7.3 “EBI Chip Select Assignment Register”, EBI_CSA.)
In the first mode (EBI_OSMODE = 0), the output strength of all the EBI pads is controlled
together via bit fields: EBI_OSALLN0 and EBI_OSALLN1 (Warning: EBI_OSALLN1 is bit 16
and EBI_OSALLN0 is bit 17).
Table 21-1.
Output Strength Configuration for EBI_OSMODE = 0
EBI_OSALLN1
EBI_OSALLN0
Description
1
1
lowest drive strength of the pads, recommended for 3.3V devices
1
0
0
1
recommended for 1.8V devices
0
0
highest drive strength of the pads.
In the second mode (EBI_OSMODE = 1), the output strength of each group is controllable independently via bit fields: EBI_OSDATA, EBI_OSSDCK, EBI_OSADDR.
Table 21-2.
140
Output Strength Configuration for EBI_OSMODE = 1
EBI_OSxxxx
Description
0
0
0
1
1
0
recommended for 1.8V devices
1
1
highest drive strength of the pads
lowest drive strength of the pads, recommended for 3.3V devices
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
21.6
Bus Matrix (MATRIX) User Interface
Table 21-3.
Register Mapping
Offset
Register
Name
Access
Reset
0x0000
Master Configuration Register 0
MATRIX_MCFG0
Read-write
0x00000000
0x0004
Master Configuration Register 1
MATRIX_MCFG1
Read-write
0x00000000
0x0008
Master Configuration Register 2
MATRIX_MCFG2
Read-write
0x00000000
0x000C
Master Configuration Register 3
MATRIX_MCFG3
Read-write
0x00000000
0x0010
Master Configuration Register 4
MATRIX_MCFG4
Read-write
0x00000000
0x0014
Master Configuration Register 5
MATRIX_MCFG5
Read-write
0x00000000
0x0018
Master Configuration Register 6
MATRIX_MCFG6
Read-write
0x00000000
0x001C
Master Configuration Register 7
MATRIX_MCFG7
Read-write
0x00000000
0x0020
Master Configuration Register 8
MATRIX_MCFG8
Read-write
0x00000000
0x0024
Master Configuration Register 9
MATRIX_MCFG9
Read-write
0x00000000
0x0028
Master Configuration Register 10
MATRIX_MCFG10
Read-write
0x00000000
0x002C
Master Configuration Register 11
MATRIX_MCFG11
Read-write
0x00000000
–
–
0x0030 - 0x003C
Reserved
–
0x0040
Slave Configuration Register 0
MATRIX_SCFG0
Read-write
0x00010010
0x0044
Slave Configuration Register 1
MATRIX_SCFG1
Read-write
0x00050010
0x0048
Slave Configuration Register 2
MATRIX_SCFG2
Read-write
0x00000010
0x004C
Slave Configuration Register 3
MATRIX_SCFG3
Read-write
0x00000010
0x0050
Slave Configuration Register 4
MATRIX_SCFG4
Read-write
0x00000010
0x0054
Slave Configuration Register 5
MATRIX_SCFG5
Read-write
0x00000010
0x0058
Slave Configuration Register 6
MATRIX_SCFG6
Read-write
0x00000010
0x005C
Slave Configuration Register 7
MATRIX_SCFG7
Read-write
0x00000010
0x0060
Slave Configuration Register 8
MATRIX_SCFG8
Read-write
0x00000010
0x0064
Slave Configuration Register 9
MATRIX_SCFG9
Read-write
0x00000010
–
–
0x0068 - 0x007C
Reserved
–
0x0080
Priority Register A for Slave 0
MATRIX_PRAS0
Read-write
0x00000000
0x0084
Priority Register B for Slave 0
MATRIX_PRBS0
Read-write
0x00000000
0x0088
Priority Register A for Slave 1
MATRIX_PRAS1
Read-write
0x00000000
0x008C
Priority Register B for Slave 1
MATRIX_PRBS1
Read-write
0x00000000
0x0090
Priority Register A for Slave 2
MATRIX_PRAS2
Read-write
0x00000000
0x0094
Priority Register B for Slave 2
MATRIX_PRBS2
Read-write
0x00000000
0x0098
Priority Register A for Slave 3
MATRIX_PRAS3
Read-write
0x00000000
0x009C
Priority Register B for Slave 3
MATRIX_PRBS3
Read-write
0x00000000
0x00A0
Priority Register A for Slave 4
MATRIX_PRAS4
Read-write
0x00000000
0x00A4
Priority Register B for Slave 4
MATRIX_PRBS4
Read-write
0x00000000
0x00A8
Priority Register A for Slave 5
MATRIX_PRAS5
Read-write
0x00000000
141
6264C–CAP–24-Mar-09
Table 21-3.
Register Mapping (Continued)
Offset
Register
Name
Access
Reset
0x00AC
Priority Register B for Slave 5
MATRIX_PRBS5
Read-write
0x00000000
0x00B0
Priority Register A for Slave 6
MATRIX_PRAS6
Read-write
0x00000000
0x00B4
Priority Register B for Slave 6
MATRIX_PRBS6
Read-write
0x00000000
0x00B8
Priority Register A for Slave 7
MATRIX_PRAS7
Read-write
0x00000000
0x00BC
Priority Register B for Slave 7
MATRIX_PRBS7
Read-write
0x00000000
0x00C0
Priority Register A for Slave 8
MATRIX_PRAS8
Read-write
0x00000000
0x00C4
Priority Register B for Slave 8
MATRIX_PRBS8
Read-write
0x00000000
0x00C8
Priority Register A for Slave 9
MATRIX_PRAS9
Read-write
0x00000000
0x00CC
Priority Register B for Slave 9
MATRIX_PRBS9
Read-write
0x00000000
–
–
Read-write
0x00000000
–
–
0x00D0 - 0x00FC
0x0100
0x0104 - 0x010C
142
Reserved
Master Remap Control Register
Reserved
–
MATRIX_MRCR
–
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
21.6.1
Name:
Bus Matrix Master Configuration Registers
MATRIX_MCFG0...MATRIX_MCFG11
Address:
0xFFFFEA00
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
ULBT
• ULBT: Undefined Length Burst Type
0: Infinite Length Burst
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
1: Single Access
The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR
burst.
2: Four-beat Burst
The undefined length burst is split into four-beat burst allowing rearbitration at each four-beat burst end.
3: Eight-beat Burst
The undefined length burst is split into eight-beat burst allowing rearbitration at each eight-beat burst end.
4: Sixteen-beat Burst
The undefined length burst is split into sixteen-beat burst allowing rearbitration at each sixteen-beat burst end.
143
6264C–CAP–24-Mar-09
21.6.2
Name:
Bus Matrix Slave Configuration Registers
MATRIX_SCFG0...MATRIX_SCFG9
Address:
0xFFFFEA40
Access:
Read-write
31
30
29
28
27
26
–
–
–
–
–
–
23
22
21
20
19
18
–
FIXED_DEFMSTR
25
24
ARBT
17
16
DEFMSTR_TYPE
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
SLOT_CYCLE
• SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking a very slow slave when very long bursts are used.
Note that an unreasonably small value breaks every burst and the Bus Matrix then arbitrates without performing any data
transfer. 16 cycles is a reasonable value for SLOT_CYCLE.
• DEFMSTR_TYPE: Default Master Type
0: No Default Master
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.
This results in a one-cycle latency for the first access of a burst transfer or for a single access.
1: Last Default Master
At the end of current slave access, if no other master request is pending, the slave remains connected to the last master
that accessed it.
This results in not having the one cycle latency when the last master tries access to the slave again.
2: Fixed Default Master
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the
number of which has been written in the FIXED_DEFMSTR field.
This results in not having the one cycle latency when the fixed master tries access to the slave again.
• FIXED_DEFMSTR: Fixed Default Master
This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
• ARBT: Arbitration Type
0: Round-Robin Arbitration
1: Fixed Priority Arbitration
2: Reserved
3: Reserved
144
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
21.6.3
Name:
Bus Matrix Priority Registers A For Slaves
MATRIX_PRAS0...MATRIX_PRAS9
Addresses: 0xFFFFEA80 [0], 0xFFFFEA88 [1], 0xFFFFEA90 [2], 0xFFFFEA98 [3], 0xFFFFEAA0 [4], 0xFFFFEAA8 [5],
0xFFFFEAB0 [6], 0xFFFFEAB8 [7], 0xFFFFEAC0 [8], 0xFFFFEAC8 [9]
Access:
Read-write
31
30
–
–
23
22
–
–
15
14
–
–
7
6
–
–
29
28
M7PR
21
20
M5PR
13
12
M3PR
5
4
M1PR
27
26
–
–
19
18
–
–
11
10
–
–
3
2
–
–
25
24
M6PR
17
16
M4PR
9
8
M2PR
1
0
M0PR
• MxPR: Master x Priority
Fixed priority of Master x for accessing to the selected slave.The higher the number, the higher the priority.
21.6.4
Name:
Bus Matrix Priority Registers B For Slaves
MATRIX_PRBS0...MATRIX_PRBS9
Addresses: 0xFFFFEA84 [0], 0xFFFFEA8C [1], 0xFFFFEA94 [2], 0xFFFFEA9C [3], 0xFFFFEAA4 [4], 0xFFFFEAAC [5],
0xFFFFEAB4 [6], 0xFFFFEABC [7], 0xFFFFEAC4 [8], 0xFFFFEACC [9]
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
–
–
–
–
7
6
3
2
–
–
–
–
M11PR
5
4
M9PR
8
M10PR
1
0
M8PR
• MxPR: Master x Priority
Fixed priority of Master x for accessing to the selected slave. The higher the number, the higher the priority.
145
6264C–CAP–24-Mar-09
21.6.5
Name:
Bus Matrix Master Remap Control Register
MATRIX_MRCR
Address:
0xFFFFEB00
Access:
Read-write
Reset:
0x0000_0000
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
RCB8
7
6
5
4
3
2
1
0
RCB7
RCB6
RCB5
RCB4
RCB3
RCB2
RCB1
RCB0
• RCBx: Remap Command Bit for AHB Master x
0: Disable remapped address decoding for the selected Master.
1: Enable remapped address decoding for the selected Master.
146
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
21.7
Chip Configuration User Interface
Table 21-4.
Chip Configuration User Interface
Offset
Register
0x0110
Reserved
0x0114
MPBlock Slave 0 Special Function Register
0x0118
Reserved
0x011C
MPBlock Slave 1 Special Function Register
0x0120
EBI Chip Select Assignment Register
0x0124 - 0x0128
Reserved
Name
Access
Reset
–
–
Read-write
0x00000000
–
–
MPBS1_SFR
Read-write
0x00000000
EBI_CSA
Read-write
0x00010000
–
–
–
MPBS0_SFR
–
–
0x012C
MPBlock Slave 2 Special Function Register
MPBS2_SFR
Read-write
0x00000000
0x0130
MPBlock Slave 3 Special Function Register
MPBS3_SFR
Read-write
0x00000000
0x0134
MPBlock Slave 1 Special Function Register
MPBS1_SFR
Read-write
0x00000000
–
–
0x0138 - 0x01FC
Reserved
–
147
6264C–CAP–24-Mar-09
21.7.1
Name:
MPBlock Slave 0 Special Function Register
MPBS0_SFR
Access:
Read-write
Reset:
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
MPBS0_SFR
23
22
21
20
MPBS0_SFR
15
14
13
12
MPBS0_SFR
7
6
5
4
MPBS0_SFR
• MPBS0_SFR: MPBlock Slave 0 Special Function Register
The value of the register is directly connected to MPBlock inputs and may be used to implement any MPBlock configuration
register.
148
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
21.7.2
Name:
MPBlock Slave 1 Special Function Register
MPBS1_SFR
Access:
Read-write
Reset:
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
MPBS1_SFR
23
22
21
20
MPBS1_SFR
15
14
13
12
MPBS1_SFR
7
6
5
4
MPBS1_SFR
• MPBS0_SFR: MPBlock Slave 1 Special Function Register
The value of the register is directly connected to MPBlock inputs and may be used to implement any MPBlock configuration
register.
149
6264C–CAP–24-Mar-09
21.7.3
Name:
EBI Chip Select Assignment Register
EBI_CSA
Access:
Read-write
Reset:
0x0001_0000
31
30
29
28
27
26
25
24
–
EBI_OSMODE
–
–
–
–
–
–
22
21
20
19
23
EBI_OSADDR
EBI_OSSDCK
18
EBI_OSDATA
17
16
EBI_OSALLAN0
EBI_OSALLAN1
15
14
13
12
11
10
9
8
–
–
–
–
–
–
EBI_DQSPDC
EBI_DBPUC
7
6
5
4
3
2
1
0
–
–
EBI_CS5A
EBI_CS4A
EBI_CS3A
–
EBI_CS1A
• EBI_CS1A: EBI Chip Select 1 Assignment
0 = EBI Chip Select 1 is assigned to the Static Memory Controller.
1 = EBI Chip Select 1 is assigned to the BCRAM Controller.
• EBI_CS3A: EBI Chip Select 3 Assignment
0 = EBI Chip Select 3 is only assigned to the Static Memory Controller and EBI_NCS3 behaves as defined by the SMC.
1 = EBI Chip Select 3 is assigned to the Static Memory Controller and the NAND Flash Logic is activated.
• EBI_CS4A: EBI Chip Select 4 Assignment
0 = EBI Chip Select 4 is only assigned to the Static Memory Controller and EBI_NCS4 behaves as defined by the SMC.
1 = EBI Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
• EBI_CS5A: EBI Chip Select 5 Assignment
0 = EBI Chip Select 5 is only assigned to the Static Memory Controller and EBI_NCS5 behaves as defined by the SMC.
1 = EBI Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
• EBI_DBPUC: EBI Data Bus Pull-Up Configuration
0 = EBI D0 - D15 Data Bus bits are internally pulled-up to the VDDIOM power supply.
1 = EBI D0 - D15 Data Bus bits are not internally pulled-up.
• EBI_DQSPDC: EBI Data Qualifier Strobe Pull-Down Configuration
0 = EBI DQS0 and DQS1 signals are internally pulled-down to the GNDIOM power ground.
1 = EBI DQS0 and DQS1 signals are not internally pulled-down.
• EBI_OSALLN1: All EBI Output Strength Configuration Bit 1
Used when EBI_OSMODE = 0. See Table 21-1, “Output Strength Configuration for EBI_OSMODE = 0”
• EBI_OSALLN1: All EBI Output Strength Configuration Bit 0
Used when EBI_OSMODE = 0. See Table 21-1, “Output Strength Configuration for EBI_OSMODE = 0”
• EBI_OSDATA: EBI DATA Output Strength Configuration
Used when EBI_OSMODE = 1. See Table 21-2, “Output Strength Configuration for EBI_OSMODE = 1”
150
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• EBI_ OSSDCK: EBI SDCK Output Strength Configuration
Used when EBI_OSMODE = 1. See Table 21-2, “Output Strength Configuration for EBI_OSMODE = 1”
• EBI_ OSADDR: EBI ADDR Output Strength Configuration
Used when EBI_OSMODE = 1. See Table 21-2, “Output Strength Configuration for EBI_OSMODE = 1”
• EBI_OSMODE: EBI Output Strength Mode
0 = EBI pads output strength are controlled by bits EBI_OSALLN0 and EBI_ OSALLN1
1 = EBI pads output strength are controlled by fields EBI_OSDATA, EBI_OSSDCK, EBI_OSADDR
151
6264C–CAP–24-Mar-09
21.7.4
Name:
MPBlock Slave 2 Special Function Register
MPBS2_SFR
Access:
Read-write
Reset:
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
MPBS2_SFR
23
22
21
20
MPBS2_SFR
15
14
13
12
MPBS2_SFR
7
6
5
4
MPBS2_SFR
• MPBS0_SFR: MPBlock Slave 2 Special Function Register
The value of the register is directly connected to MPBlock inputs and may be used to implement any MPBlock configuration
register.
152
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
21.7.5
Name:
MPBlock Slave 3 Special Function Register
MPBS3_SFR
Access:
Read-write
Reset:
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
MPBS3_SFR
23
22
21
20
MPBS3_SFR
15
14
13
12
MPBS3_SFR
7
6
5
4
MPBS3_SFR
• MPBS0_SFR: MPBlock Slave 3 Special Function Register
The value of the register is directly connected to MPBlock inputs and may be used to implement any MPBlock configuration
register.
153
6264C–CAP–24-Mar-09
21.7.6
Name:
APB Bridge Special Function Register
APB_SFR
Access:
Read-write
Reset:
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
APB_SFR
23
22
21
20
APB_SFR
15
14
13
12
APB_SFR
7
6
5
4
APB_SFR
• APB_SFR: APB Bridge Special Function Register
The value of the register is directly connected to MPBlock inputs and may be used to implement any MPBlock configuration
register.
154
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
22. External Bus Interface (EBI)
22.1
Description
The External Bus Interface (EBI) is designed to ensure the successful data transfer between
several external devices and the embedded Memory Controller of an ARM-based device. The
Static Memory, DDR/SDRAM, Burst Cellular RAM and ECC Controllers are all featured external
Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM,
EEPROM, Flash, SDRAM, Mobile DDR and Burst Cellular RAM.
The EBI also supports the CompactFlash and the NAND Flash protocols via integrated circuitry
that greatly reduces the requirements for external components. Furthermore, the EBI handles
data transfers with up to seven external devices, each assigned to seven address spaces
defined by the embedded Memory Controller. Data transfers are performed through a 16-bit or
32-bit data bus, an address bus of up to 26 bits, up to seven chip select lines (NCS[5:0] and
SDCS) and several control pins that are generally multiplexed between the different external
Memory Block Diagram
22.1.1
External Bus Interface
Figure 22-1 shows the organization of the External Bus Interface.
155
6264C–CAP–24-Mar-09
Figure 22-1. Organization of the External Bus Interface
D[15:0]
External Bus Interface
A0/NBS0
A1/NWR2/NBS2
A[15:2], A[22:18]
A16/BA0
A17/BA1
ARM926EJS
NCS0
NCS1/BCCS
NRD/CFOE
AHB
AHB
Multi-port
DDR/SDRAM
Controller
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
MUX
Logic
AHB
NWR3/NBS3/CFIOW
BCCK
AHB
BCOWAIT
AHB
SDCK
Burst
CellularRAM
Controller
SDCKN
SDCS
DQS0
Bus Matrix
DQS1
Static
Memory
Controller
SDCKE/BCCRE
RAS/BCADV
CAS/BCOE
CompactFlash
Logic
SDWE/BCWE
SDA10
NANDOE
NAND Flash
Logic
NANDWE
D[31:16]
A[24:23]
ECC
Controller
PIO
NCS3/NANDCS
A25/CFRNW
NCS4/CFCS0
Address Decoders
Chip Select
Assignor
NCS5/CFCS1
NCS2
User Interface
NWAIT
CFCE1
CFCE2
APB
156
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6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
22.2
I/O Lines Description
Table 22-1.
EBI I/O Lines Description
Name
Function
Type
Active Level
EBI
D0 - D31
Data Bus
I/O
A0 - A25
Address Bus
NWAIT
External Wait Signal
Output
Input
Low
SMC
NCS0 - NCS5
Chip Select Lines
Output
Low
NWR0 - NWR3
Write Signals
Output
Low
NRD
Read Signal
Output
Low
NWE
Write Enable
Output
Low
NBS0 - NBS3
Byte Mask Signals
Output
Low
EBI for CompactFlash Support
CFCE1 - CFCE2
CompactFlash Chip Enable
Output
Low
CFOE
CompactFlash Output Enable
Output
Low
CFWE
CompactFlash Write Enable
Output
Low
CFIOR
CompactFlash I/O Read Signal
Output
Low
CFIOW
CompactFlash I/O Write Signal
Output
Low
CFRNW
CompactFlash Read Not Write Signal
Output
CFCS0 - CFCS1
CompactFlash Chip Select Lines
Output
Low
EBI for NAND Flash Support
NANDCS
NAND Flash Chip Select Line
Output
Low
NANDOE
NAND Flash Output Enable
Output
Low
NANDWE
NAND Flash Write Enable
Output
Low
DDR/SDRAM Controller
SDCK
DDR/SDRAM Clock
Output
SDCKN
DDR Inverted Clock
Output
DQS0
DDR Data Qualifier Strobe 0
I/O
DQS1
DDR Data Qualifier Strobe 1
I/O
SDCKE
DDR/SDRAM Clock Enable
Output
High
SDCS
DDR/SDRAM Chip Select Line
Output
Low
BA0 - BA1
DDR/SDRAM Bank Select
Output
SDWE
DDR/SDRAM Write Enable
Output
Low
RAS - CAS
DDR/SDRAM Row and Column Signal
Output
Low
NBS0 - NBS3
DDR/SDRAM Byte Mask Signals
Output
Low
SDA10
DDR/SDRAM Address 10 Line
Output
Burst CellularRAM Controller
157
6264C–CAP–24-Mar-09
Table 22-1.
EBI I/O Lines Description
Name
Function
BCCK
Burst CellularRAM Clock
Output
BCCRE
Burst CellularRAM Clock Enable
Output
High
BCCS
Burst CellularRAM Chip Select Line
Output
Low
BCWE
Burst CellularRAM Write Enable
Output
Low
BCADV
Burst CellularRAM Burst Advance Signal
Output
Low
BCOE
Burst CellularRAM Output Enable
Output
Low
NBS0 - NBS1
Burst CellularRAM Byte Mask Signals
Output
Low
BCOWAIT
Burst CellularRAM Output Wait Signal
Input
158
Type
Active Level
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
22.3
Application Example
22.3.1
Hardware Interface
Table 22-3, “EBI Pins and External Device Connections,” details the connections to be applied
between the EBI pins and the external devices for each Memory Controller.
Table 22-2.
EBI Pins and External Static Devices Connections
Pins of the Interfaced Device
Signals
8-bit Static
Device
2 x 8-bit
Static
Devices
16-bit Static
Device
Controller
4 x 8-bit
Static
Devices
2 x 16-bit
Static
Devices
32-bit Static
Device
SMC
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D8 - D15
–
D8 - D15
D8 - D15
D8 - D15
D8 - D15
D8 - D15
D16 - D23
–
–
–
D16 - D23
D16 - D23
D16 - D23
D24 - D31
–
–
–
D24 - D31
D24 - D31
D24 - D31
BE0(5)
A0/NBS0
A0
–
NLB
–
A1/NWR2/NBS2
A1
A0
A0
WE(2)
NLB(4)
BE2(5)
A2 - A22
A[2:22]
A[1:21]
A[1:21]
A[0:20]
A[0:20]
A[0:20]
A23 - A25
A[23:25]
A[22:24]
A[22:24]
A[21:23]
A[21:23]
A[21:23]
NCS0
CS
CS
CS
CS
CS
CS
NCS1/BCCS
CS
CS
CS
CS
CS
CS
NCS2
CS
CS
CS
CS
CS
CS
NCS3/NANDCS
CS
CS
CS
CS
CS
CS
NCS4/CFCS0
CS
CS
CS
CS
CS
CS
NCS5/CFCS1
CS
CS
CS
CS
CS
CS
NRD/CFOE
OE
OE
OE
OE
OE
OE
WE
WE
NWR0/NWE
WE
WE
(1)
(1)
NWR1/NBS1
–
WE
NWR3/NBS3
–
–
Notes:
WE
NUB
–
NLB
(3)
WE
(2)
WE
(2)
WE(2)
(3)
BE1(5)
NUB(4)
BE3(5)
NUB
1. NWR1 enables upper byte writes. NWR0 enables lower byte writes.
2. NWRx enables corresponding byte x writes. (x = 0,1, 2 or 3).
3. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word.
4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word.
5. BEx: Byte x Enable (x = 0,1, 2 or 3).
159
6264C–CAP–24-Mar-09
Table 22-3.
EBI Pins and External Device Connections
Pins of the Interfaced Device
Signals
CompactFlash
True IDE Mode
SDRAM
Mobile DDR
Burst
CellularRAM
DDR/SDRAMC
DDR/SDRAMC
BCRAMC
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
AD0-AD7
D8 - D15
D8 - D15
D8 - D15
D8 - D15
D8 - D15
D8 - D15
AD8-AD15
D16 - D31
D16 - D31
–
–
–
–
–
A0/NBS0
DQM0
DQM0
DQM0
A0
A0
–
A1/NWR2/NBS2
DQM2
–
DQM2
A1
A1
–
A2 - A10
A[0:8]
A[0:8]
A[0:8]
A[2:10]
A[2:10]
–
A11
A9
A9
A9
–
–
–
SDA10
A10
A10
–
–
–
–
–
–
A10
–
–
–
A[11:12]
A[11:12]
A[11:12]
–
–
–
–
A13
A13
–
–
–
A16/BA0
BA0
BA0
A14
–
–
–
A17/BA1
BA1
BA1
A15
–
–
–
A18 - A20
–
–
A[16:18]
–
–
–
A21
–
–
A19
–
–
ALE(3)
A22
–
–
A20
REG
REG
CLE(3)
A23 - A24
–
–
A[21:22]
–
Controller
A12
A13 - A14
A15
CompactFlash
NAND Flash
SMC
–
–
(1)
A25
–
–
A23
NCS0
–
–
–
–
–
–
NCS1/BCCS
–
–
CS
–
–
–
NCS2
–
–
–
–
–
–
NCS3/NANDCS
–
–
–
–
–
CE(4)
NCS4/CFCS0
–
–
–
CFCS0(1)
CFCS0(1)
–
(1)
(1)
–
NCS5/CFCS1
CFRNW
(1)
–
–
–
–
CS
CS
–
–
–
–
NANDOE
–
–
–
–
–
OE
NANDWE
–
–
–
–
–
WE
NRD/CFOE
–
–
–
OE
–
–
NWR0/NWE/CFWE
–
–
–
WE
WE
–
NWR1/NBS1/CFIOR
DQM1
DQM1
DQM1
IOR
IOR
–
NWR3/NBS3/CFIOW
DQM3
–
DQM3
IOW
IOW
–
CFCE1
–
–
–
CE1
CS0
–
CFCE2
–
–
–
CE2
CS1
–
BCCK
–
–
CLK
–
–
–
SDCS
160
CFCS1
CFRNW
CFCS1
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Table 22-3.
EBI Pins and External Device Connections (Continued)
Pins of the Interfaced Device
Signals
CompactFlash
True IDE Mode
SDRAM
Mobile DDR
Burst
CellularRAM
DDR/SDRAMC
DDR/SDRAMC
BCRAMC
CLK
CLK
–
–
–
–
–
CLKN
–
–
–
–
CKE
CKE
CRE
–
–
–
–
DQS0 - DQS1
–
–
–
–
RAS/BCADV
RAS
RAS
ADV
–
–
–
CAS/BCOE
CAS
CAS
OE
–
–
–
SDWE/BCWE
WE
WE
WE
–
–
–
BCOWAIT
–
–
OWAIT
–
–
–
NWAIT
–
–
–
WAIT
WAIT
–
Pxx(2)
–
–
–
CD1 or CD2
CD1 or CD2
–
Pxx(2)
–
–
–
–
–
CE(4)
Pxx(2)
–
–
–
–
–
RDY
Controller
SDCK
SDCKN
SDCKE/BCCRE
DQS0 - DQS1
Note:
CompactFlash
NAND Flash
SMC
1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer between the EBI data bus and
the CompactFlash slot.
2. Any PIO line.
3. The CLE and ALE signals of the NAND Flash device may be driven by any address bit. For details, see “NAND Flash Support” on page 167.
4. NAND CE may be connected to any PIO line if CE don’t care mode is not supported by NAND device. Otherwise NANDCS
may be used.
161
6264C–CAP–24-Mar-09
22.4
22.4.1
Product Dependencies
I/O Lines
The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines.
The programmer must first program the PIO controller to assign the External Bus Interface pins
to their peripheral function. If I/O lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller.
22.5
Functional Description
The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the external memories or peripheral devices. It controls the waveforms and the parameters of the
external address, data and control buses and is composed of the following elements:
• the Static Memory Controller (SMC)
• the DDR/SDRAM Controller (DDR/SDRAMC)
• the Burst Cellular RAM Controller (BCRAMC)
• the ECC Controller (ECC)
• a chip select assignment feature that assigns an AHB address space to the external devices
• a multiplex controller circuit that shares the pins between the different Memory Controllers
• programmable CompactFlash support logic
• programmable NAND Flash support logic
22.5.1
Bus Multiplexing
The EBI offers a complete set of control signals that share the 32-bit data lines, the address
lines of up to 26 bits and the control signals through a multiplex logic operating in function of the
memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output control lines at a stable state while no external access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the SDRAM are executed independently by the SDRAM Controller without
delaying the other external Memory Controller accesses.
22.5.2
Pull-up Control
The EBI_CSA registers in the Chip Configuration User Interface permit enabling of on-chip pullup resistors on the data bus lines not multiplexed with the PIO Controller lines. The pull-up resistors are enabled after reset. Setting the DBPUC bit disables the pull-up resistors on the D0 to
D15 lines. Enabling the pull-up resistor on the D16-D31 lines can be performed by programming
the appropriate PIO controller.
22.5.3
Supply Control
The EBI I/O pads may be supplied with two different voltage (3.3V or 1.8V). The EBI_CSA registers in the Chip Configuration User Interface allows to choose between the two different
voltages. At power-up, the selected supply control is 3.3V, allowing the EBI to work at low system speed even supplied at 1.8V.
22.5.4
Static Memory Controller
For information on the Static Memory Controller, refer to the section “Static Memory Controller”.
162
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
22.5.5
DDR/SDRAM Controller
For information on the DDR/SDRAM Controller, refer to the section “DDR/SDRAM”.
22.5.6
BCRAM Controller
For information on the BCRAM Controller, refer to the section “BCRAM”.
22.5.7
ECC Controller
For information on the ECC Controller, refer to the section “ECC”.
22.5.8
CompactFlash Support
The External Bus Interface integrates circuitry that interfaces to CompactFlash devices.
The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 and/or
NCS5 address space. Programming the EBI_CS4A and/or EBI_CS5A bit of the EBI_CSA Register in the Chip Configuration User Interface to the appropriate value enables this logic. For
details on this register, refer to the section “Bus Matrix”. Access to an external CompactFlash
device is then made by accessing the address space reserved for NCS4 and/or NCS5 (i.e.,
between 0x5000 0000 and 0x5FFF FFFF for NCS4 and between 0x6000 0000 and 0x6FFF
FFFF for NCS5).
All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are supported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are
not handled.
22.5.8.1
I/O Mode, Common Memory Mode, Attribute Memory Mode and True IDE Mode
Within the NCS4 and/or NCS5 address space, the current transfer address is used to distinguish
I/O mode, common memory mode, attribute memory mode and True IDE mode.
The different modes are accessed through a specific memory mapping as illustrated on Figure
22-2. A[23:21] bits of the transfer address are used to select the desired mode as described in
Table 22-4 on page 164.
Figure 22-2. CompactFlash Memory Mapping
True IDE Alternate Mode Space
Offset 0x00E0 0000
True IDE Mode Space
Offset 0x00C0 0000
CF Address Space
I/O Mode Space
Offset 0x0080 0000
Common Memory Mode Space
Offset 0x0040 0000
Attribute Memory Mode Space
Offset 0x0000 0000
Note:
The A22 pin is used to drive the REG signal of the CompactFlash Device (except in True IDE
mode).
163
6264C–CAP–24-Mar-09
Table 22-4.
CompactFlash Mode Selection
A[23:21]
22.5.8.2
Mode Base Address
000
Attribute Memory
010
Common Memory
100
I/O Mode
110
True IDE Mode
111
Alternate True IDE Mode
CFCE1 and CFCE2 Signals
To cover all types of access, the SMC must be alternatively set to drive 8-bit data bus or 16-bit
data bus. The odd byte access on the D[7:0] bus is only possible when the SMC is configured to
drive 8-bit memory devices on the corresponding NCS pin (NCS4 or NCS5). The Chip Select
Register (DBW field in the corresponding Chip Select Register) of the NCS4 and/or NCS5
address space must be set as shown in Table 22-5 to enable the required access type.
NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set
in Byte Select mode on the corresponding Chip Select.
The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For
details on these waveforms and timings, refer to the section “Static Memory Controller”.
Table 22-5.
CFCE1 and CFCE2 Truth Table
Mode
CFCE2
CFCE1
DBW
Comment
SMC Access Mode
NBS1
NBS0
16 bits
Access to Even Byte on D[7:0]
Byte Select
NBS1
NBS0
16 bits
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Byte Select
1
0
8 bits
Access to Odd Byte on D[7:0]
NBS1
NBS0
16 bits
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
1
0
8 bits
Access to Odd Byte on D[7:0]
Task File
1
0
8 bits
Access to Even Byte on D[7:0]
Access to Odd Byte on D[7:0]
Data Register
1
0
16 bits
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Byte Select
Control Register
Alternate Status Read
0
1
Don’t
Care
Access to Even Byte on D[7:0]
Don’t Care
Drive Address
0
1
8 bits
Access to Odd Byte on D[7:0]
1
1
–
Attribute Memory
Common Memory
I/O Mode
Byte Select
True IDE Mode
Alternate True IDE Mode
Standby Mode or
Address Space is not
assigned to CF
164
–
–
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
22.5.8.3
Read/Write Signals
In I/O mode and True IDE mode, the CompactFlash logic drives the read and write command
signals of the SMC on CFIOR and CFIOW signals, while the CFOE and CFWE signals are deactivated. Likewise, in common memory mode and attribute memory mode, the SMC signals are
driven on the CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated. Figure
22-3 on page 165 demonstrates a schematic representation of this logic.
Attribute memory mode, common memory mode and I/O mode are supported by setting the
address setup and hold time on the NCS4 (and/or NCS5) chip select to the appropriate values.
For details on these signal waveforms, please refer to the section “Setup and Hold Cycles” in
“Static Memory Controller (SMC)”.
Figure 22-3. CompactFlash Read/Write Control Signals
External Bus Interface
SMC
CompactFlash Logic
A23
1
1
0
1
0
0
1
1
CFOE
CFWE
A22
NRD_NOE
NWR0_NWE
0
1
1
Table 22-6.
1
CFIOR
CFIOW
CompactFlash Mode Selection
Mode Base Address
CFOE
CFWE
CFIOR
CFIOW
NRD
NWR0_NWE
1
1
I/O Mode
1
1
NRD
NWR0_NWE
True IDE Mode
0
1
NRD
NWR0_NWE
Attribute Memory
Common Memory
22.5.8.4
Multiplexing of CompactFlash Signals on EBI Pins
Table 22-7 on page 166 and Table 22-8 on page 166 illustrate the multiplexing of the CompactFlash logic signals with other EBI signals on the EBI pins. The EBI pins in Table 22-7 are strictly
dedicated to the CompactFlash interface as soon as the EBI_CS4A and/or EBI_CS5A field of
the EBI_CSA Register in the Chip Configuration User Interface is set. These pins must not be
used to drive any other memory devices.
The EBI pins in Table 22-8 on page 166 remain shared between all memory areas when the corresponding CompactFlash interface is enabled (EBI_CS4A = 1 and/or EBI_CS5A = 1).
165
6264C–CAP–24-Mar-09
Table 22-7.
Dedicated CompactFlash Interface Multiplexing
CompactFlash Signals
EBI Signals
Pins
EBI_CS4A = 1
NCS4/CFCS0
CFCS0
EBI_CS4A = 0
EBI_CS5A = 0
NCS4
NCS5/CFCS1
Table 22-8.
EBI_CS5A = 1
CFCS1
NCS5
Shared CompactFlash Interface Multiplexing
Access to CompactFlash Device
Access to Other EBI Devices
Pins
CompactFlash Signals
EBI Signals
NRD/CFOE
CFOE
NRD
NWR0/NWE/CFWE
CFWE
NWR0/NWE
NWR1/NBS1/CFIOR
CFIOR
NWR1/NBS1
NWR3/NBS3/CFIOW
CFIOW
NWR3/NBS3
A25/CFRNW
CFRNW
A25
22.5.8.5
166
Application Example
Figure 22-4 on page 167 illustrates an example of a CompactFlash application. CFCS0 and
CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direction and the output enable of the buffers between the EBI and the CompactFlash Device. The
timing of the CFCS0 signal is identical to the NCS4 signal. Moreover, the CFRNW signal
remains valid throughout the transfer, as does the address bus. The CompactFlash _WAIT signal is connected to the NWAIT input of the Static Memory Controller. For details on these
waveforms and timings, refer to the section “Static Memory Controller (SMC)”.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 22-4. CompactFlash Application Example
EBI
CompactFlash Connector
D[15:0]
D[15:0]
DIR /OE
A25/CFRNW
NCS4/CFCS0
CD1
CD (PIO)
CD2
/OE
A[10:0]
A22/REG
22.5.9
22.5.9.1
A[10:0]
REG
NOE/CFOE
OE
NWE/CFWE
WE
NWR1/CFIOR
IORD
NWR3/CFIOW
IOWR
CFCE1
CE1
CFCE2
CE2
NWAIT
WAIT
NAND Flash Support
External Bus Interface integrates circuitry that interfaces to NAND Flash devices.
External Bus Interface
The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space.
Programming the EBI_CS3A field in the EBI_CSA Register in the Chip Configuration User Interface to the appropriate value enables the NAND Flash logic. For details on this register, refer to
Section 21. “Bus Matrix”. Access to an external NAND Flash device is then made by accessing
the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF).
The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE
and NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated
as soon as the transfer address fails to lie in the NCS3 address space. See Figure 22-5 on page
168 for more information. For details on these waveforms, refer to the section “Static Memory
Controller”.
167
6264C–CAP–24-Mar-09
Figure 22-5. NAND Flash Signal Multiplexing on EBI Pins
SMC
NAND Flash Logic
NCS3
NRD
NANDOE
NANDWE
NANDOE
NANDWE
NWR0_NWE
22.5.9.2
168
NAND Flash Signals
The address latch enable and command latch enable signals on the NAND Flash device are
driven by address bits A22 and A21 of the EBI address bus. The user should note that any bit on
the EBI address bus can also be used for this purpose. The command, address or data words
on the data bus of the NAND Flash device are distinguished by using their address within the
NCS3 address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NCS3 is not
selected, preventing the device from returning to standby mode.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 22-6. NAND Flash Application Example
D[7:0]
AD[7:0]
A[22:21]
ALE
CLE
NCS3/NANDCS
Not Connected
EBI
NAND Flash
NANDOE
NANDWE
NOE
NWE
PIO
CE
PIO
R/B
169
6264C–CAP–24-Mar-09
22.6
Implementation Examples
22.6.1
16-bit SDRAM
Figure 22-7. Hardware Configuration
D[0..15]
A[0..17]
(Not used A1, A12, A15)
U1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
23
24
25
26
29
30
31
32
33
34
22
35
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A16
A17
20
21
BA0
BA1
A14
36
40
A12
N.C
SDCKE
37
CKE
SDCK
38
CLK
A0 (NBS0)
NBS1
15
39
DQML
DQMH
CAS
RAS
17
18
CAS
RAS
SDWE
SDDRCS
16
19
WE
CS
A13
22.6.1.1
SDA10
SDA10
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
1
14
27
3
9
43
49
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
28
41
54
6
12
46
52
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
3V3
C1
C2
C3
C4
C5
C6
C7
100NF
100NF
100NF
100NF
100NF
100NF
100NF
Software Configuration
The following configuration has to be performed:
• Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip
Select Assignment Register located in the bus matrix memory space.
• Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.
The Data Bus Width is to be programmed to 16 bits.
The SDRAM initialization sequence is described in the “SDRAM device initialization” part of the
SDRAM controller.
170
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
22.6.2
22.6.2.1
32-bit SDRAM
Hardware Configuration
D[0..31]
A[0..17]
(Not used A12, A15)
U1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A13
SDA10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A16
A17
20 BA0
21 BA1
A14
36 A12
40 N.C
SDCKE
37 CKE
SDCK
38 CLK
A0 (NBS0)
22.6.2.2
23
24
25
26
29
30
31
32
33
34
22
35
NBS1
15 DQML
39 DQMH
CAS
RAS
17 CAS
18 RAS
SDWE
SDDRCS
16 WE
19 CS
U2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
1
14
27
3
9
43
49
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
28
41
54
6
12
46
52
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
3V3
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A13
C1
C2
C3
C4
C5
C6
C7
100NF
100NF
100NF
100NF
100NF
100NF
100NF
SDA10
23
24
25
26
29
30
31
32
33
34
22
35
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A16
A17
20 BA0
21 BA1
A14
36 A12
40 N.C
SDCKE
37 CKE
SDCK
38 CLK
A1 (NBS2)
NBS3
15 DQML
39 DQMH
CAS
RAS
17 CAS
18 RAS
SDWE
16 WE
19 CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
1
14
27
3
9
43
49
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
28
41
54
6
12
46
52
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
3V3
C8 100NF
C9 100NF
C10 100NF
C11 100NF
C12 100NF
C13 100NF
C14 100NF
Software Configuration
The following configuration has to be performed:
• Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip
Select Assignment Register located in the bus matrix memory space.
• Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.
The Data Bus Width is to be programmed to 32 bits. The data lines D[16..31] are multiplexed
with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO
controller.
The SDRAM initialization sequence is described in the “SDR-SDRAM device initialization” part
of the DDRSDR-SDRAM controller.
171
6264C–CAP–24-Mar-09
22.6.3
16-bit Mobile DDR
Figure 22-8. Hardware Configuration
D[0..15]
A[0..17]
U1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A13
A14
SDA10
J8
J9
K7
K8
K2
K3
J1
J2
J3
H1
J7
H2
H3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A16 (BA0)
A17 (BA1)
H8 BA0
H9 BA1
A0 (NBS0)
NBS1
F8 LDM
F2 UDM
SDCKE
SDCK
SDCKN
G1 CKE
G2 CK
G3 CK
DQS0
DQS1
E8 LDQS
E2 UDQS
CAS
RAS
G8 CAS
G9 RAS
SDWE
SDDRCS
G7 WE
H7 CS
F3 N.C
F7 N.C
22.6.3.1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A8
B7
B8
C7
C8
D7
D8
E7
E3
D2
D3
C2
C3
B2
B3
A2
VDD A9
VDD F9
VDD K9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A7
B1
C9
D1
E9
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A1
F1
K1
A3
B9
C1
D9
E1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
VDDIOM
C1 100NF
C2 100NF
C3 100NF
C4
C5
C6
C7
C8
100NF
100NF
100NF
100NF
100NF
Software Configuration
The following configuration has to be performed:
• Initialize the SDRAM Controller depending on the DDR device and system bus frequency.
• The Data Bus Width is to be programmed to 16 bits.
• The SDRAM initialization sequence is described in the “DDR-SDRAM device initialization”
part of the DDRSDR-SDRAM controller.
172
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
22.6.4
16-bit BCRAM
Figure 22-9. Hardware Configuration
D[0..15]
A[2..24]
U1
NBS1
22.6.4.1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A3
A4
A5
B3
B4
C3
C4
D4
H2
H3
H4
H5
G3
G4
F3
F4
E4
D3
H1
G2
H6
E3
J4
A0 (NBS0)
A1 LB
B2 UB
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
BCOWAIT
J1 WAIT
BCCRE
BCADV
BCCK
BCOE
BCWE
BCCS
A6
J3
J2
A2
G5
B5
CRE
ADV
CLK
OE
WE
CE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
B6
C5
C6
D5
E5
F5
F6
G6
B1
C1
C2
D2
E2
F2
F1
G1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
RFU J5
RFU J6
VDDIOM
VCCQ E1
VCC D6
C1 100NF
C2 100NF
VSSQ D1
VSS E6
Software Configuration
The following configuration has to be performed:
• Assign the EBI CS1 to the BCRAM by setting the bit EBI_CS1A in the EBI Chip Select
Assignment Register located in the bus matrix memory space
• The Data Bus Width is to be programmed to 16 bits.
• The BCRAM initialization sequence is described in the “Cellular Ram initialization” part of the
BCRAM controller.
173
6264C–CAP–24-Mar-09
22.6.5
22.6.5.1
8-bit NAND Flash
Hardware Configuration
D[0..7]
U1
CLE
ALE
NANDOE
NANDWE
(ANY PIO)
(ANY PIO)
R1
3V3
R2
10K
16
17
8
18
9
CLE
ALE
RE
WE
CE
7
R/B
19
WP
10K
1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
25
26
K9F2G08U0M
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
29
30
31
32
41
42
43
44
N.C
N.C
N.C
N.C
N.C
N.C
PRE
N.C
N.C
N.C
N.C
N.C
48
47
46
45
40
39
38
35
34
33
28
27
VCC
VCC
37
12
VSS
VSS
36
13
D0
D1
D2
D3
D4
D5
D6
D7
2 Gb
3V3
C2
100NF
C1
100NF
TSOP48 PACKAGE
22.6.5.2
Software Configuration
The following configuration has to be performed:
• Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select
Assignment Register located in the bus matrix memory space
• Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled
respectively by setting to 1 the address bit A21 and A22 during accesses.
• NANDOE and NANDWE signals are multiplexed with PIO lines and thus the dedicated PIOs
must be programmed in peripheral mode in the PIO controller.
• Configure a PIO line as an input to manage the Ready/Busy signal.
• Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND
Flash timings, the data bus width and the system bus frequency.
174
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
22.6.6
22.6.6.1
16-bit NAND Flash
Hardware Configuration
D[0..15]
U1
CLE
ALE
NANDOE
NANDWE
(ANY PIO)
(ANY PIO)
R1
3V3
R2
10K
16
17
8
18
9
CLE
ALE
RE
WE
CE
7
R/B
19
WP
1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
34
35
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
10K
MT29F2G16AABWP-ET
I/O0 26
I/O1 28
I/O2 30
I/O3 32
I/O4 40
I/O5 42
I/O6 44
I/O7 46
I/O8 27
I/O9 29
I/O10 31
I/O11 33
I/O12 41
I/O13 43
I/O14 45
I/O15 47
2 Gb
N.C
PRE
N.C
39
38
36
VCC
VCC
37
12
VSS
VSS
VSS
48
25
13
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
3V3
C2
100NF
C1
100NF
TSOP48 PACKAGE
22.6.6.2
Software Configuration
The software configuration is the same as for an 8-bit NAND Flash except the data bus width
programmed in the mode register of the Static Memory Controller.
175
6264C–CAP–24-Mar-09
22.6.7
22.6.7.1
NOR Flash on NCS0
Hardware Configuration
D[0..15]
A[1..22]
U1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
NRST
NWE
3V3
NCS0
NRD
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
15
10
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
12
11
14
13
26
28
RESET
WE
WP
VPP
CE
OE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
AT49BV6416
3V3
VCCQ
47
VCC
37
VSS
VSS
46
27
TSOP48 PACKAGE
22.6.7.2
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
C2
100NF
C1
100NF
Software Configuration
The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus,
Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock.
For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and
Mode depending on Flash timings and system bus frequency.
176
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
22.6.8
22.6.8.1
Compact Flash
Hardware Configuration
MEMORY & I/O MODE
D[0..15]
MN1A
D15
D14
D13
D12
D11
D10
D9
D8
A2
A1
B2
B1
C2
C1
D2
D1
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
A3
A4
1DIR
1OE
J1
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
A5
A6
B5
B6
C5
C6
D5
D6
CF_D15
CF_D14
CF_D13
CF_D12
CF_D11
CF_D10
CF_D9
CF_D8
E5
E6
F5
F6
G5
G6
H5
H6
CF_D7
CF_D6
CF_D5
CF_D4
CF_D3
CF_D2
CF_D1
CF_D0
74ALVCH32245
MN1B
D7
D6
D5
D4
D3
D2
D1
D0
A25/CFRNW
4
CFCSx
(CFCS0 or CFCS1)
6
5
E2
E1
F2
F1
G2
G1
H2
H1
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
H3
H4
2DIR
2OE
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
3V3
R1
MN2A
47K
SN74ALVC32
74ALVCH32245
MN2B
SN74ALVC32
R2
47K
CD2
1
3
(ANY PIO)
CD1
2
CF_D15
CF_D14
CF_D13
CF_D12
CF_D11
CF_D10
CF_D9
CF_D8
CF_D7
CF_D6
CF_D5
CF_D4
CF_D3
CF_D2
CF_D1
CF_D0
31
30
29
28
27
49
48
47
6
5
4
3
2
23
22
21
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CD2
CD1
25
26
CD2#
CD1#
CF_A10
CF_A9
CF_A8
CF_A7
CF_A6
CF_A5
CF_A4
CF_A3
CF_A2
CF_A1
CF_A0
8
10
11
12
14
15
16
17
18
19
20
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
REG
44
REG#
WE
OE
IOWR
IORD
36
9
35
34
WE#
OE#
IOWR#
IORD#
MN1C
A[0..10]
A10
A9
A8
A7
A6
A5
A4
A3
J5
J6
K5
K6
L5
L6
M5
M6
J3
J4
3V3
3A1
3A2
3A3
3A4
3A5
3A6
3A7
3A8
3B1
3B2
3B3
3B4
3B5
3B6
3B7
3B8
J2
J1
K2
K1
L2
L1
M2
M1
CF_A10
CF_A9
CF_A8
CF_A7
CF_A6
CF_A5
CF_A4
CF_A3
CE2
CE1
3DIR
3OE
74ALVCH32245
MN1D
A2
A1
A0
A22/REG
CFWE
CFOE
CFIOW
CFIOR
N5
N6
P5
P6
R5
R6
T6
T5
4A1
4A2
4A3
4A4
4A5
4A6
4A7
4A8
T3
T4
4DIR
4OE
4B1
4B2
4B3
4B4
4B5
4B6
4B7
4B8
N2
N1
P2
P1
R2
R1
T1
T2
CF_A2
CF_A1
CF_A0
REG
WE
OE
IOWR
IORD
VCC
38
VCC
13
GND
GND
50
1
CSEL#
39
INPACK#
43
BVD2
BVD1
45
46
32
7
CE2#
CE1#
24
WP
WAIT#
42
WAIT#
VS2#
VS1#
40
33
RESET
41
RESET
RDY/BSY
37
3V3
C1
100NF
C2
100NF
RDY/BSY
N7E50-7516VY-20
1
74ALVCH32245
2
CFCE1
5
10
4
CFCE2
9
(ANY PIO)
CFIRQ
11
13
(ANY PIO)
CFRST
MN3A
SN74ALVC125
3
CE2
MN3B
SN74ALVC125
6
CE1
MN3C
SN74ALVC125
RESET
8
MN3D
R3
SN74ALVC125
10K
RDY/BSY
12
3V3
MN4
3V3
NWAIT
5 VCC
1
4
2
GND
R4
10K
WAIT#
3V3
3
SN74LVC1G125-Q1
177
6264C–CAP–24-Mar-09
22.6.8.2
Software Configuration
The following configuration has to be performed:
• Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the
bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located in the
bus matrix memory space.
• The address line A23 is to select I/O (A23=1) or Memory mode (A23=0) and the address line
A22 for REG function.
• A23, CFRNW, CFS0, CFCS1, CFCE1 and CFCE2 signals are multiplexed with PIO lines and
thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller.
• Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and
CARD DETECT functions respectively.
• Configure SMC CS4 and/or SMC_CS5 (for Slot 0 or 1) Setup, Pulse, Cycle and Mode
accordingly to Compact Flash timings and system bus frequency.
178
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
22.6.9
22.6.9.1
Compact Flash True IDE
Hardware Configuration
TRUE IDE MODE
D[0..15]
MN1A
D15
D14
D13
D12
D11
D10
D9
D8
A2
A1
B2
B1
C2
C1
D2
D1
A3
A4
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
CF_D15
CF_D14
CF_D13
CF_D12
CF_D11
CF_D10
CF_D9
CF_D8
E5
E6
F5
F6
G5
G6
H5
H6
CF_D7
CF_D6
CF_D5
CF_D4
CF_D3
CF_D2
CF_D1
CF_D0
1DIR
1OE
74ALVCH32245
MN1B
D7
D6
D5
D4
D3
D2
D1
D0
A25/CFRNW
CFCSx
(CFCS0 or CFCS1)
4
6
5
E2
E1
F2
F1
G2
G1
H2
H1
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
H3
H4
2DIR
2OE
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
3V3
R1
MN2A
47K
SN74ALVC32
74ALVCH32245
MN2B
SN74ALVC32
CD2
1
CD1
2
J5
J6
K5
K6
L5
L6
M5
M6
3A1
3A2
3A3
3A4
3A5
3A6
3A7
3A8
J3
J4
3DIR
3OE
3V3
3B1
3B2
3B3
3B4
3B5
3B6
3B7
3B8
J2
J1
K2
K1
L2
L1
M2
M1
CF_A10
CF_A9
CF_A8
CF_A7
CF_A6
CF_A5
CF_A4
CF_A3
74ALVCH32245
MN1D
A2
A1
A0
A22/REG
CFWE
CFOE
CFIOW
CFIOR
N5
N6
P5
P6
R5
R6
T6
T5
4A1
4A2
4A3
4A4
4A5
4A6
4A7
4A8
T3
T4
4DIR
4OE
31
30
29
28
27
49
48
47
6
5
4
3
2
23
22
21
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CD2
CD1
25
26
CD2#
CD1#
CF_A2
CF_A1
CF_A0
8
10
11
12
14
15
16
17
18
19
20
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
44
REG#
IOWR
IORD
36
9
35
34
WE#
ATA SEL#
IOWR#
IORD#
CE2
CE1
32
7
CS1#
CS0#
3V3
MN1C
A10
A9
A8
A7
A6
A5
A4
A3
CF_D15
CF_D14
CF_D13
CF_D12
CF_D11
CF_D10
CF_D9
CF_D8
CF_D7
CF_D6
CF_D5
CF_D4
CF_D3
CF_D2
CF_D1
CF_D0
R2
47K
3
(ANY PIO)
A[0..10]
3V3
J1
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
A5
A6
B5
B6
C5
C6
D5
D6
4B1
4B2
4B3
4B4
4B5
4B6
4B7
4B8
N2
N1
P2
P1
R2
R1
T1
T2
CF_A2
CF_A1
CF_A0
REG
WE
OE
IOWR
IORD
24
IOIS16#
IORDY
42
IORDY
RESET#
41
VCC
38
VCC
13
GND
GND
50
1
CSEL#
39
INPACK#
43
DASP#
PDIAG#
45
46
VS2#
VS1#
40
33
INTRQ
37
RESET#
C1
100NF
C2
100NF
INTRQ
N7E50-7516VY-20
1
74ALVCH32245
2
CFCE1
5
10
4
CFCE2
9
(ANY PIO)
CFIRQ
11
13
(ANY PIO)
CFRST
MN3A
SN74ALVC125
3
CE2
MN3B
SN74ALVC125
6
CE1
MN3C
SN74ALVC125
RESET#
8
MN3D
SN74ALVC125
INTRQ
12
R3
10K
3V3
MN4
3V3
NWAIT
5 VCC
1
4
2
GND
R4
10K
IORDY
3V3
3
SN74LVC1G125-Q1
179
6264C–CAP–24-Mar-09
22.6.9.2
Software Configuration
The following configuration has to be performed:
• Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the
bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located in the
bus matrix memory space.
• The address line A21 is to select Alternate True IDE (A21=1) or True IDE (A21=0) modes.
• CFRNW, CFS0, CFCS1, CFCE1 and CFCE2 signals are multiplexed with PIO lines and thus
the dedicated PIOs must be programmed in peripheral mode in the PIO controller.
• Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and
CARD DETECT functions respectively.
• Configure SMC CS4 and/or SMC_CS5 (for Slot 0 or 1) Setup, Pulse, Cycle and Mode
accordingly to Compact Flash timings and system bus frequency.
180
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
23. Static Memory Controller (SMC)
23.1
Description
The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or peripheral devices. It has 6 Chip Selects and a 26-bit address bus. The
32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate
read and write control signals allow for direct memory and peripheral interfacing. Read and write
signal waveforms are fully parametrizable.
The SMC can manage wait requests from external devices to extend the current access. The
SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from userprogrammed waveforms to slow-rate specific waveforms on read and write signals. The SMC
supports asynchronous burst read in page mode access for page size up to 32 bytes.
23.2
I/O Lines Description
Table 23-1.
I/O Line Description
Name
Description
Type
Active Level
NCS[7:0]
Static Memory Controller Chip Select Lines
Output
Low
NRD
Read Signal
Output
Low
NWR0/NWE
Write 0/Write Enable Signal
Output
Low
A0/NBS0
Address Bit 0/Byte 0 Select Signal
Output
Low
NWR1/NBS1
Write 1/Byte 1 Select Signal
Output
Low
A1/NWR2/NBS2
Address Bit 1/Write 2/Byte 2 Select Signal
Output
Low
NWR3/NBS3
Write 3/Byte 3 Select Signal
Output
Low
A[25:2]
Address Bus
Output
D[31:0]
Data Bus
NWAIT
External Wait Signal
23.3
I/O
Input
Low
Multiplexed Signals
Table 23-2.
Static Memory Controller (SMC) Multiplexed Signals
Multiplexed Signals
Related Function
NWR0
NWE
Byte-write or byte-select access, see “Byte Write or Byte Select Access” on page 183
A0
NBS0
8-bit or 16-/32-bit data bus, see “Data Bus Width” on page 183
NWR1
NBS1
Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 183
A1
NWR2
NWR3
NBS3
NBS2
8-/16-bit or 32-bit data bus, see “Data Bus Width” on page 183.
Byte-write or byte-select access, see “Byte Write or Byte Select Access” on page 183
Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 183
181
6264C–CAP–24-Mar-09
23.4
23.4.1
Application Example
Hardware Interface
Figure 23-1. SMC Connections to Static Memory Devices
D0-D31
A0/NBS0
NWR0/NWE
NWR1/NBS1
A1/NWR2/NBS2
NWR3/NBS3
D0 - D7
128K x 8
SRAM
D8-D15
D0 - D7
CS
NRD
NWR0/NWE
A2 - A25
A2 - A18
A0 - A16
NRD
OE
NWR1/NBS1
WE
128K x 8
SRAM
D16 - D23
D24-D31
D0 - D7
A0 - A16
NRD
Static Memory
Controller
23.5
23.5.1
A2 - A18
OE
WE
128K x 8
SRAM
D0-D7
CS
CS
A1/NWR2/NBS2
D0-D7
CS
A0 - A16
NCS0
NCS1
NCS2
NCS3
NCS4
NCS5
NCS6
NCS7
128K x 8
SRAM
A2 - A18
A2 - A18
A0 - A16
NRD
OE
WE
OE
NWR3/NBS3
WE
Product Dependencies
I/O Lines
The pins used for interfacing the Static Memory Controller may be multiplexed with the PIO
lines. The programmer must first program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O Lines of the SMC are not used by the application,
they can be used for other purposes by the PIO Controller.
182
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
23.6
External Memory Mapping
The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address
up to 64 Mbytes of memory.
If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps
around and appears to be repeated within this space. The SMC correctly handles any valid
access to the memory device within the page (see Figure 23-2).
A[25:0] is only significant for 8-bit memory, A[25:1] is used for 16-bit memory, A[25:2] is used for
32-bit memory.
Figure 23-2.
Memory Connections for Eight External Devices
NCS[0] - NCS[7]
NCS7
NRD
SMC
NCS6
NWE
NCS5
A[25:0]
NCS4
D[31:0]
NCS3
NCS2
NCS1
NCS0
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Output Enable
Write Enable
A[25:0]
8 or 16 or 32
23.7
23.7.1
D[31:0] or D[15:0] or
D[7:0]
Connection to External Devices
Data Bus Width
A data bus width of 8, 16, or 32 bits can be selected for each chip select. This option is controlled by the field DBW in SMC_MODE (Mode Register) for the corresponding chip select.
Figure 23-3 shows how to connect a 512K x 8-bit memory on NCS2. Figure 23-4 shows how to
connect a 512K x 16-bit memory on NCS2. Figure 23-5 shows two 16-bit memories connected
as a single 32-bit memory
23.7.2
Byte Write or Byte Select Access
Each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of
write access: byte write or byte select access. This is controlled by the BAT field of the
SMC_MODE register for the corresponding chip select.
183
6264C–CAP–24-Mar-09
Figure 23-3.
Memory Connection for an 8-bit Data Bus
D[7:0]
D[7:0]
A[18:2]
A[18:2]
SMC
A0
A0
A1
A1
NWE
Write Enable
NRD
Output Enable
NCS[2]
Figure 23-4.
Memory Enable
Memory Connection for a 16-bit Data Bus
D[15:0]
D[15:0]
A[19:2]
A[18:1]
A1
SMC
A[0]
NBS0
Low Byte Enable
NBS1
High Byte Enable
NWE
Write Enable
NRD
Output Enable
NCS[2]
Memory Enable
Figure 23-5. Memory Connection for a 32-bit Data Bus
D[31:16]
SMC
D[15:0]
D[15:0]
A[20:2]
A[18:0]
NBS0
Byte 0 Enable
NBS1
Byte 1 Enable
NBS2
Byte 2 Enable
NBS3
Byte 3 Enable
NWE
Write Enable
NRD
Output Enable
NCS[2]
184
D[31:16]
Memory Enable
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
23.7.2.1
Byte Write Access
Byte write access supports one byte write signal per byte of the data bus and a single read
signal.
Note that the SMC does not allow boot in Byte Write Access mode.
• For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0
(lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided.
Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.
• For 32-bit devices: NWR0, NWR1, NWR2 and NWR3, are the write signals of byte0 (lower
byte), byte1, byte2 and byte 3 (upper byte) respectively. One single read signal (NRD) is
provided.
Byte Write Access is used to connect 4 x 8-bit devices as a 32-bit memory.
Byte Write option is illustrated on Figure 23-6.
23.7.2.2
Byte Select Access
In this mode, read/write operations can be enabled/disabled at a byte level. One byte-select line
per byte of the data bus is provided. One NRD and one NWE signal control read and write.
• For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals for respectively
byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus.
Byte Select Access is used to connect one 16-bit device.
• For 32-bit devices: NBS0, NBS1, NBS2 and NBS3, are the selection signals of byte0 (lower
byte), byte1, byte2 and byte 3 (upper byte) respectively. Byte Select Access is used to
connect two 16-bit devices.
Figure 23-7 shows how to connect two 16-bit devices on a 32-bit data bus in Byte Select Access
mode, on NCS3 (BAT = Byte Select Access).
185
6264C–CAP–24-Mar-09
Figure 23-6.
Connection of 2 x 8-bit Devices on a 16-bit Bus: Byte Write Option
D[7:0]
D[7:0]
D[15:8]
A[24:2]
SMC
A1
NWR0
A[23:1]
A[0]
Write Enable
NWR1
NRD
NCS[3]
Read Enable
Memory Enable
D[15:8]
A[23:1]
A[0]
Write Enable
Read Enable
Memory Enable
23.7.2.3
Signal Multiplexing
Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at
the external bus interface, control signals at the SMC interface are multiplexed. Table 23-3
shows signal multiplexing depending on the data bus width and the byte access type.
For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused.
When Byte Select Option is selected, NWR1 to NWR3 are unused. When Byte Write option is
selected, NBS0 to NBS3 are unused.
186
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 23-7. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option)
D[15:0]
D[15:0]
D[31:16]
A[25:2]
A[23:0]
NWE
Write Enable
NBS0
Low Byte Enable
NBS1
High Byte Enable
NBS2
SMC
NBS3
Read Enable
NRD
Memory Enable
NCS[3]
D[31:16]
A[23:0]
Write Enable
Low Byte Enable
High Byte Enable
Read Enable
Memory Enable
Table 23-3.
SMC Multiplexed Signal Translation
Signal Name
Device Type
32-bit Bus
16-bit Bus
8-bit Bus
1x32-bit
2x16-bit
4 x 8-bit
1x16-bit
2 x 8-bit
Byte Select
Byte Select
Byte Write
Byte Select
Byte Write
NBS0_A0
NBS0
NBS0
NWE_NWR0
NWE
NWE
NWR0
NWE
NWR0
NBS1_NWR1
NBS1
NBS1
NWR1
NBS1
NWR1
NBS2_NWR2_A1
NBS2
NBS2
NWR2
A1
A1
NBS3_NWR3
NBS3
NBS3
NWR3
Byte Access Type (BAT)
NBS0
1 x 8-bit
A0
NWE
A1
187
6264C–CAP–24-Mar-09
23.8
Standard Read and Write Protocols
In the following sections, the byte access type is not considered. Byte select lines (NBS0 to
NBS3) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR3) in byte write
access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way,
NCS represents one of the NCS[0..5] chip select lines.
23.8.1
Read Waveforms
The read cycle is shown on Figure 23-8.
The read cycle starts with the address setting on the memory address bus, i.e.:
{A[25:2], A1, A0} for 8-bit devices
{A[25:2], A1} for 16-bit devices
A[25:2] for 32-bit devices.
Figure 23-8. Standard Read Cycle
MCK
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NRD
NCS
D[31:0]
NRD_SETUP
NCS_RD_SETUP
NRD_PULSE
NCS_RD_PULSE
NRD_HOLD
NCS_RD_HOLD
NRD_CYCLE
23.8.1.1
NRD Waveform
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD
falling edge;
2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD
rising edge;
3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD
rising edge.
188
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
23.8.1.2
NCS Waveform
Similarly, the NCS signal can be divided into a setup time, pulse length and hold time:
1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before
the NCS falling edge.
2. NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and
NCS rising edge;
3. NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the
NCS rising edge.
23.8.1.3
Read Cycle
The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where
address is set on the address bus to the point where address may change. The total read cycle
time is equal to:
NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD
= NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD
All NRD and NCS timings are defined separately for each chip select as an integer number of
Master Clock cycles. To ensure that the NRD and NCS timings are coherent, user must define
the total read cycle instead of the hold timing. NRD_CYCLE implicitly defines the NRD hold time
and NCS hold time as:
NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE
NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE
23.8.1.4
Null Delay Setup and Hold
If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain
active continuously in case of consecutive read cycles in the same memory (see Figure 23-9).
189
6264C–CAP–24-Mar-09
Figure 23-9. No Setup, No Hold On NRD and NCS Read Signals
MCK
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NRD
NCS
D[31:0]
NRD_PULSE
NCS_RD_PULSE
NRD_CYCLE
23.8.1.5
NRD_PULSE
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE
NCS_RD_PULSE
NRD_CYCLE
Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to
unpredictable behavior.
23.8.2
Read Mode
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know
when the read data is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first. The READ_MODE parameter in the SMC_MODE register
of the corresponding chip select indicates which signal of NRD and NCS controls the read
operation.
23.8.2.1
190
Read is Controlled by NRD (READ_MODE = 1):
Figure 23-10 shows the waveforms of a read operation of a typical asynchronous RAM. The
read data is available tPACC after the falling edge of NRD, and turns to ‘Z’ after the rising edge of
NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate
that data is available with the rising edge of NRD. The SMC samples the read data internally on
the rising edge of Master Clock that generates the rising edge of NRD, whatever the programmed waveform of NCS may be.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 23-10. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD
MCK
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NRD
NCS
tPACC
D[31:0]
Data Sampling
23.8.2.2
Read is Controlled by NCS (READ_MODE = 0)
Figure 23-11 shows the typical read cycle of an LCD module. The read data is valid tPACC after
the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be
sampled when NCS is raised. In that case, the READ_MODE must be set to 0 (read is controlled
by NCS): the SMC internally samples the data on the rising edge of Master Clock that generates
the rising edge of NCS, whatever the programmed waveform of NRD may be.
Figure 23-11. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS
MCK
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NRD
NCS
tPACC
D[31:0]
Data Sampling
191
6264C–CAP–24-Mar-09
23.8.3
23.8.3.1
Write Waveforms
The write protocol is similar to the read protocol. It is depicted in Figure 23-12. The write cycle
starts with the address setting on the memory address bus.
NWE Waveforms
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before
the NWE falling edge;
2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE
rising edge;
3. NWE_HOLD: The NWE hold time is defined as the hold time of address and data after
the NWE rising edge.
The NWE waveforms apply to all byte-write lines in Byte Write access mode: NWR0 to NWR3.
23.8.3.2
NCS Waveforms
The NCS signal waveforms in write operation are not the same that those applied in read operations, but are separately defined:
1. NCS_WR_SETUP: the NCS setup time is defined as the setup time of address before
the NCS falling edge.
2. NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and
NCS rising edge;
3. NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the
NCS rising edge.
Figure 23-12. Write Cycle
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE
NCS
NWE_SETUP
NCS_WR_SETUP
NWE_PULSE
NCS_WR_PULSE
NWE_HOLD
NCS_WR_HOLD
NWE_CYCLE
192
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
23.8.3.3
Write Cycle
The write_cycle time is defined as the total duration of the write cycle, that is, from the time
where address is set on the address bus to the point where address may change. The total write
cycle time is equal to:
NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD
= NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD
All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user
must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold
time and NCS (write) hold times as:
NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
23.8.3.4
Null Delay Setup and Hold
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active
continuously in case of consecutive write cycles in the same memory (see Figure 23-13). However, for devices that perform write operations on the rising edge of NWE or NCS, such as
SRAM, either a setup or a hold must be programmed.
Figure 23-13. Null Setup and Hold Values of NCS and NWE in Write Cycle
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE,
NWR0, NWR1,
NWR2, NWR3
NCS
D[31:0]
NWE_PULSE
23.8.3.5
NWE_PULSE
NWE_PULSE
NCS_WR_PULSE
NCS_WR_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_CYCLE
NWE_CYCLE
Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to
unpredictable behavior.
193
6264C–CAP–24-Mar-09
23.8.4
Write Mode
The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal controls the write operation.
23.8.4.1
Write is Controlled by NWE (WRITE_MODE = 1):
Figure 23-14 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is
put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are
turned out after the NWE_SETUP time, and until the end of the write cycle, regardless of the
programmed waveform on NCS.
Figure 23-14. WRITE_MODE = 1. The write operation is controlled by NWE
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE,
NWR0, NWR1,
NWR2, NWR3
NCS
D[31:0]
23.8.4.2
194
Write is Controlled by NCS (WRITE_MODE = 0)
Figure 23-15 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is
put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are
turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of
the programmed waveform on NWE.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 23-15. WRITE_MODE = 0. The write operation is controlled by NCS
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE,
NWR0, NWR1,
NWR2, NWR3
NCS
D[31:0]
23.8.5
Coding Timing Parameters
All timing parameters are defined for one chip select and are grouped together in one
SMC_REGISTER according to their type.
The SMC_SETUP register groups the definition of all setup parameters:
• NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP
The SMC_PULSE register groups the definition of all pulse parameters:
• NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE
The SMC_CYCLE register groups the definition of all cycle parameters:
• NRD_CYCLE, NWE_CYCLE
Table 23-4 shows how the timing parameters are coded and their permitted range.
Table 23-4.
Coding and Range of Timing Parameters
Permitted Range
Coded Value
Number of Bits
Effective Value
Coded Value
Effective Value
setup [5:0]
6
128 x setup[5] + setup[4:0]
0 ≤≤31
0 ≤≤128+31
pulse [6:0]
7
256 x pulse[6] + pulse[5:0]
0 ≤≤63
0 ≤≤256+63
cycle [8:0]
9
256 x cycle[8:7] + cycle[6:0]
0 ≤≤127
0 ≤≤256+127
0 ≤≤512+127
0 ≤≤768+127
195
6264C–CAP–24-Mar-09
23.8.6
Reset Values of Timing Parameters
Table 23-5 gives the default value of timing parameters at reset.
Table 23-5.
23.8.7
Reset Values of Timing Parameters
Register
Reset Value
SMC_SETUP
0x01010101
All setup timings are set to 1
SMC_PULSE
0x01010101
All pulse timings are set to 1
SMC_CYCLE
0x00030003
The read and write operation last 3 Master Clock
cycles and provide one hold cycle
WRITE_MODE
1
Write is controlled with NWE
READ_MODE
1
Read is controlled with NRD
Usage Restriction
The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP
and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC.
For read operations:
Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the
memory interface because of the propagation delay of theses signals through external logic and
pads. If positive setup and hold values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews between address, NCS and NRD signals.
For write operations:
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address,
byte select lines, and NCS signal after the rising edge of NWE. This is true for WRITE_MODE =
1 only. See “Early Read Wait State” on page 197.
For read and write operations: a null value for pulse parameters is forbidden and may lead to
unpredictable behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the
address bus. For external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and NWE signals (write), these setup and hold times must be
converted into setup and hold times in reference to the address bus.
23.9
Automatic Wait States
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to
avoid bus contention or operation conflict.
23.9.1
Chip Select Wait States
The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle
cycle ensures that there is no bus contention between the de-activation of one device and the
activation of the next one.
During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to
NWR3, NCS[0..5], NRD lines are all set to 1.
Figure 23-16 illustrates a chip select wait state between access on Chip Select 0 and Chip
Select 2.
196
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 23-16. Chip Select Wait State between a Read Access on NCS0 and a Write Access on
NCS2
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NRD
NWE
NCS0
NCS2
NRD_CYCLE
NWE_CYCLE
D[31:0]
Read to Write Chip Select
Wait State
Wait State
23.9.2
Early Read Wait State
In some cases, the SMC inserts a wait state cycle between a write access and a read access to
allow time for the write cycle to end before the subsequent read cycle begins. This wait state is
not generated in addition to a chip select wait state. The early read cycle thus only occurs
between a write and read access to the same memory device (same chip select).
An early read wait state is automatically inserted if at least one of the following conditions is
valid:
• if the write controlling signal has no hold time and the read controlling signal has no setup
time (Figure 23-17).
• in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS
signal and the NCS_RD_SETUP parameter is set to 0, regardless of the read mode (Figure
23-18). The write operation must end with a NCS rising edge. Without an Early Read Wait
State, the write operation could not complete properly.
• in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD =
0), the feedback of the write control signal is used to control address, data, chip select and
byte select lines. If the external write control signal is not inactivated as expected due to load
capacitances, an Early Read Wait State is inserted and address, data and control signals are
maintained one more cycle. See Figure 23-19.
197
6264C–CAP–24-Mar-09
Figure 23-17. Early Read Wait State: Write with No Hold Followed by Read with No Setup
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE
NRD
no hold
no setup
D[31:0]
write cycle
Early Read
wait state
read cycle
Figure 23-18. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NCS
NRD
no hold
no setup
D[31:0]
write cycle
(WRITE_MODE = 0)
198
Early Read
wait state
read cycle
(READ_MODE = 0 or READ_MODE = 1)
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 23-19. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
internal write controlling signal
external write controlling signal
(NWE)
no hold
read setup = 1
NRD
D[31:0]
write cycle
(WRITE_MODE = 1)
23.9.3
Early Read
wait state
read cycle
(READ_MODE = 0 or READ_MODE = 1)
Reload User Configuration Wait State
The user may change any of the configuration parameters by writing the SMC user interface.
When detecting that a new user configuration has been written in the user interface, the SMC
inserts a wait state before starting the next access. The so called “Reload User Configuration
Wait State” is used by the SMC to load the new set of parameters to apply to next accesses.
The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If
accesses before and after re-programming the user interface are made to different devices
(Chip Selects), then one single Chip Select Wait State is applied.
On the other hand, if accesses before and after writing the user interface are made to the same
device, a Reload Configuration Wait State is inserted, even if the change does not concern the
current Chip Select.
23.9.3.1
User Procedure
To insert a Reload Configuration Wait State, the SMC detects a write access to any
SMC_MODE register of the user interface. If the user only modifies timing registers
(SMC_SETUP, SMC_PULSE, SMC_CYCLE registers) in the user interface, he must validate
the modification by writing the SMC_MODE, even if no change was made on the mode
parameters.
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse,
Cycle, Mode) if accesses are performed on this CS during the modification. Any change of the
Chip Select parameters, while fetching the code from a memory connected on this CS, may lead
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6264C–CAP–24-Mar-09
to unpredictable behavior. The instructions used to modify the parameters of an SMC Chip
Select can be executed from the internal RAM or from a memory connected to another CS.
23.9.3.2
23.9.4
Slow Clock Mode Transition
A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or
exited, after the end of the current transfer (see “Slow Clock Mode” on page 211).
Read to Write Wait State
Due to an internal mechanism, a wait cycle is always inserted between consecutive read and
write SMC accesses.
This wait cycle is referred to as a read to write wait state in this document.
This wait cycle is applied in addition to chip select and reload user configuration wait states
when they are to be inserted. See Figure 23-16 on page 197.
200
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
23.10 Data Float Wait States
Some memory devices are slow to release the external bus. For such devices, it is necessary to
add wait states (data float wait states) after a read access:
• before starting a read access to a different external memory
• before starting a write access to the same device or to a different external one.
The Data Float Output Time (t DF ) for each external memory device is programmed in the
TDF_CYCLES field of the SMC_MODE register for the corresponding chip select. The value of
TDF_CYCLES indicates the number of data float wait cycles (between 0 and 15) before the
external device releases the bus, and represents the time allowed for the data output to go to
high impedance after the memory is disabled.
Data float wait states do not delay internal memory accesses. Hence, a single access to an
external memory with long t DF will not slow down the execution of a program from internal
memory.
The data float wait states management depends on the READ_MODE and the TDF_MODE
fields of the SMC_MODE register for the corresponding chip select.
23.10.1
READ_MODE
Setting the READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state buffers of the external memory device. The Data Float Period then begins
after the rising edge of the NRD signal and lasts TDF_CYCLES MCK cycles.
When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives
the number of MCK cycles during which the data bus remains busy after the rising edge of NCS.
Figure 23-20 illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1),
assuming a data float period of 2 cycles (TDF_CYCLES = 2). Figure 23-21 shows the read operation when controlled by NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3.
201
6264C–CAP–24-Mar-09
Figure 23-20. TDF Period in NRD Controlled Read Access (TDF = 2)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NRD
NCS
tpacc
D[31:0]
TDF = 2 clock cycles
NRD controlled read operation
Figure 23-21. TDF Period in NCS Controlled Read Operation (TDF = 3)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NRD
NCS
tpacc
D[31:0]
TDF = 3 clock cycles
NCS controlled read operation
202
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
23.10.2
TDF Optimization Enabled (TDF_MODE = 1)
When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the
SMC takes advantage of the setup period of the next access to optimize the number of wait
states cycle to insert.
Figure 23-22 shows a read access controlled by NRD, followed by a write access controlled by
NWE, on Chip Select 0. Chip Select 0 has been programmed with:
NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)
NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)
TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).
Figure 23-22. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins
MCK
A[25:2]
NRD
NRD_HOLD= 4
NWE
NWE_SETUP= 3
NCS0
TDF_CYCLES = 6
D[31:0]
read access on NCS0 (NRD controlled)
23.10.3
Read to Write
Wait State
write access on NCS0 (NWE controlled)
TDF Optimization Disabled (TDF_MODE = 0)
When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that
the data float period is ended when the second access begins. If the hold period of the read1
controlling signal overlaps the data float period, no additional tdf wait states will be inserted.
Figure 23-23, Figure 23-24 and Figure 23-25 illustrate the cases:
• read access followed by a read access on another chip select,
• read access followed by a write access on another chip select,
• read access followed by a write access on the same chip select,
with no TDF optimization.
203
6264C–CAP–24-Mar-09
Figure 23-23. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip
selects
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
read1 controlling signal
(NRD)
read1 hold = 1
read2 controlling signal
(NRD)
read2 setup = 1
TDF_CYCLES = 6
D[31:0]
5 TDF WAIT STATES
read 2 cycle
TDF_MODE = 0
(optimization disabled)
read1 cycle
TDF_CYCLES = 6
Chip Select Wait State
Figure 23-24. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
read1 controlling signal
(NRD)
read1 hold = 1
write2 controlling signal
(NWE)
write2 setup = 1
TDF_CYCLES = 4
D[31:0]
2 TDF WAIT STATES
read1 cycle
TDF_CYCLES = 4
Read to Write Chip Select
Wait State Wait State
204
write2 cycle
TDF_MODE = 0
(optimization disabled)
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 23-25. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
read1 controlling signal
(NRD)
write2 setup = 1
read1 hold = 1
write2 controlling signal
(NWE)
TDF_CYCLES = 5
D[31:0]
4 TDF WAIT STATES
read1 cycle
TDF_CYCLES = 5
Read to Write
Wait State
write2 cycle
TDF_MODE = 0
(optimization disabled)
23.11 External Wait
Any access can be extended by an external device using the NWAIT input signal of the SMC.
The EXNW_MODE field of the SMC_MODE register on the corresponding chip select must be
set to either to “10” (frozen mode) or “11” (ready mode). When the EXNW_MODE is set to “00”
(disabled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT
signal delays the read or write operation in regards to the read or write controlling signal,
depending on the read and write modes of the corresponding chip select.
23.11.1
Restriction
When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold
cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be
used in Page Mode (“Asynchronous Page Mode” on page 214), or in Slow Clock Mode
(“Slow Clock Mode” on page 211).
The NWAIT signal is assumed to be a response of the external device to the read/write request
of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write
controlling signal. The assertion of the NWAIT signal outside the expected period has no impact
on SMC behavior.
205
6264C–CAP–24-Mar-09
23.11.2
Frozen Mode
When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control
signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC
completes the access, resuming the access from the point where it was stopped. See Figure 2326. This mode must be selected when the external device uses the NWAIT signal to delay the
access and to freeze the SMC.
The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure
23-27.
Figure 23-26. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
FROZEN STATE
4
3
2
1
1
1
1
0
3
2
2
2
2
1
NWE
6
5
4
0
NCS
D[31:0]
NWAIT
internally synchronized
NWAIT signal
Write cycle
EXNW_MODE = 10 (Frozen)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
206
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 23-27. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NCS
FROZEN STATE
4
1
NRD
3
2
2
2
1
0
2
1
0
2
1
0
0
5
5
5
4
3
NWAIT
internally synchronized
NWAIT signal
Read cycle
EXNW_MODE = 10 (Frozen)
READ_MODE = 0 (NCS_controlled)
NRD_PULSE = 2, NRD_HOLD = 6
NCS_RD_PULSE =5, NCS_RD_HOLD =3
Assertion is ignored
207
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
23.11.3
Ready Mode
In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins
the access by down counting the setup and pulse counters of the read/write controlling signal. In
the last cycle of the pulse phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in Figure 23-28 and Figure 23-29. After
deassertion, the access is completed: the hold step of the access is performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to
indicate its ability to complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the
pulse of the controlling read/write signal, it has no impact on the access length as shown in Figure 23-29.
Figure 23-28. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
Wait STATE
4
3
2
1
0
0
0
3
2
1
1
1
NWE
6
5
4
0
NCS
D[31:0]
NWAIT
internally synchronized
NWAIT signal
Write cycle
EXNW_MODE = 11 (Ready mode)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
208
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 23-29. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
Wait STATE
6
5
4
3
2
1
0
0
6
5
4
3
2
1
1
NCS
NRD
0
NWAIT
internally synchronized
NWAIT signal
Read cycle
EXNW_MODE = 11(Ready mode)
READ_MODE = 0 (NCS_controlled)
Assertion is ignored
Assertion is ignored
NRD_PULSE = 7
NCS_RD_PULSE =7
209
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
23.11.4
NWAIT Latency and Read/Write Timings
There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write
controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1
cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT
signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated on Figure 23-30.
When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the
read and write controlling signal of at least:
minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle
Figure 23-30. NWAIT Latency
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
WAIT STATE
4
3
2
1
0
0
0
NRD
minimal pulse length
NWAIT
intenally synchronized
NWAIT signal
NWAIT latency 2 cycle resynchronization
Read cycle
EXNW_MODE = 10 or 11
READ_MODE = 1 (NRD_controlled)
NRD_PULSE = 5
210
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
23.12 Slow Clock Mode
The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when
an internal signal driven by the Power Management Controller is asserted because MCK has
been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is
provided so as to avoid reprogramming the User Interface with appropriate waveforms at very
slow clock rate. When activated, the slow mode is active on all chip selects.
23.12.1
Slow Clock Mode Waveforms
Figure 23-31 illustrates the read and write operations in slow clock mode. They are valid on all
chip selects. Table 23-6 indicates the value of read and write parameters in slow clock mode.
Figure 23-31. Read/write Cycles in Slow Clock Mode
MCK
MCK
A[25:2]
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NWE
NRD
1
1
1
1
1
NCS
NCS
NRD_CYCLE = 2
NWE_CYCLE = 3
SLOW CLOCK MODE WRITE
Table 23-6.
SLOW CLOCK MODE READ
Read and Write Timing Parameters in Slow Clock Mode
Read Parameters
Duration (cycles)
Write Parameters
Duration (cycles)
NRD_SETUP
1
NWE_SETUP
1
NRD_PULSE
1
NWE_PULSE
1
NCS_RD_SETUP
0
NCS_WR_SETUP
0
NCS_RD_PULSE
2
NCS_WR_PULSE
3
NRD_CYCLE
2
NWE_CYCLE
3
211
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
23.12.2
Switching from (to) Slow Clock Mode to (from) Normal Mode
When switching from slow clock mode to the normal mode, the current slow clock mode transfer
is completed at high clock rate, with the set of slow clock mode parameters.See Figure 23-32 on
page 212. The external device may not be fast enough to support such timings.
Figure 23-33 illustrates the recommended procedure to properly switch from one mode to the
other.
Figure 23-32. Clock Rate Transition Occurs while the SMC is Performing a Write Operation
Slow Clock Mode
internal signal from PMC
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NWE
1
1
1
1
1
1
2
3
2
NCS
NWE_CYCLE = 3
NWE_CYCLE = 7
SLOW CLOCK MODE WRITE SLOW CLOCK MODE WRITE
This write cycle finishes with the slow clock mode set
of parameters after the clock rate transition
NORMAL MODE WRITE
Slow clock mode transition is detected:
Reload Configuration Wait State
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Figure 23-33. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow
Clock Mode
Slow Clock Mode
internal signal from PMC
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NWE
1
1
1
2
3
2
NCS
SLOW CLOCK MODE WRITE
IDLE STATE
NORMAL MODE WRITE
Reload Configuration
Wait State
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23.13 Asynchronous Page Mode
The SMC supports asynchronous burst reads in page mode, providing that the page mode is
enabled in the SMC_MODE register (PMEN field). The page size must be configured in the
SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte
page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The
MSB of data address defines the address of the page in memory, the LSB of address define the
address of the data in the page as detailed in Table 23-7.
With page mode memory devices, the first access to one page (tpa) takes longer than the subsequent accesses to the page (tsa ) as shown in Figure 23-34. When in page mode, the SMC
enables the user to define different read timings for the first access within one page, and next
accesses within the page.
Table 23-7.
Page Address and Data Address within a Page
Page Size
Page Address(1)
Data Address in the Page(2)
4 bytes
A[25:2]
A[1:0]
8 bytes
A[25:3]
A[2:0]
16 bytes
A[25:4]
A[3:0]
32 bytes
A[25:5]
A[4:0]
Notes:
1. A denotes the address bus of the memory device
2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored.
23.13.1
Protocol and Timings in Page Mode
Figure 23-34 shows the NRD and NCS timings in page mode access.
Figure 23-34. Page Mode Read Protocol (Address MSB and LSB are defined in Table 23-7)
MCK
A[MSB]
A[LSB]
NRD
NCS
tpa
tsa
tsa
D[31:0]
NCS_RD_PULSE
NRD_PULSE
NRD_PULSE
The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS
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timings are identical. The pulse length of the first access to the page is defined with the
NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of subsequent accesses
within the page are defined using the NRD_PULSE parameter.
In page mode, the programming of the read timings is described in Table 23-8:
Table 23-8.
Programming of Read Timings in Page Mode
Parameter
Value
Definition
READ_MODE
‘x’
No impact
NCS_RD_SETUP
‘x’
No impact
NCS_RD_PULSE
tpa
Access time of first access to the page
NRD_SETUP
‘x’
No impact
NRD_PULSE
tsa
Access time of subsequent accesses in the page
NRD_CYCLE
‘x’
No impact
The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE
timings as page access timing (tpa) and the NRD_PULSE for accesses to the page (tsa), even if
the programmed value for tpa is shorter than the programmed value for tsa.
23.13.2
Byte Access Type in Page Mode
The Byte Access Type configuration remains active in page mode. For 16-bit or 32-bit page
mode devices that require byte selection signals, configure the BAT field of the
SMC_REGISTER to 0 (byte select access type).
23.13.3
Page Mode Restriction
The page mode is not compatible with the use of the NWAIT signal. Using the page mode and
the NWAIT signal may lead to unpredictable behavior.
23.13.4
Sequential and Non-sequential Accesses
If the chip select and the MSB of addresses as defined in Table 23-7 are identical, then the current access lies in the same page as the previous one, and no page break occurs.
Using this information, all data within the same page, sequential or not sequential, are accessed
with a minimum access time (tsa). Figure 23-35 illustrates access to an 8-bit memory device in
page mode, with 8-byte pages. Access to D1 causes a page access with a long access time
(tpa). Accesses to D3 and D7, though they are not sequential accesses, only require a short
access time (tsa).
If the MSB of addresses are different, the SMC performs the access of a new page. In the same
way, if the chip select is different from the previous access, a page break occurs. If two sequential accesses are made to the page mode memory, but separated by an other internal or external
peripheral access, a page break occurs on the second access because the chip select of the
device was deasserted between both accesses.
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Figure 23-35. Access to Non-sequential Data within the Same Page
MCK
Page address
A[25:3]
A[2], A1, A0
A1
A3
A7
NRD
NCS
D[7:0]
D1
NCS_RD_PULSE
D3
NRD_PULSE
D7
NRD_PULSE
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23.14 Static Memory Controller (SMC) User Interface
The SMC is programmed using the registers listed in Table 23-9. For each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. In Table 23-9, “CS_number” denotes the chip select number.
16 bytes (0x10) are required per chip select.
The user must complete writing the configuration by writing any one of the SMC_MODE registers.
Table 23-9.
Register Mapping
Offset
Register
Name
Access
Reset
0x10 x CS_number + 0x00
SMC Setup Register
SMC_SETUP
Read-write
0x01010101
0x10 x CS_number + 0x04
SMC Pulse Register
SMC_PULSE
Read-write
0x01010101
0x10 x CS_number + 0x08
SMC Cycle Register
SMC_CYCLE
Read-write
0x00030003
0x10 x CS_number + 0x0C
SMC Mode Register
SMC_MODE
Read-write
0x10001000
0xEC-0xFC
Reserved
-
-
-
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23.14.1
Name:
SMC Setup Register
SMC_SETUP[0..5]
Addresses: 0xFFFFE800 [0], 0xFFFFE810 [1], 0xFFFFE820 [2], 0xFFFFE830 [3], 0xFFFFE840 [4], 0xFFFFE850 [5]
Access:
Read-write
31
30
–
–
23
22
–
–
15
14
–
–
7
6
–
–
29
28
27
26
25
24
18
17
16
10
9
8
1
0
NCS_RD_SETUP
21
20
19
NRD_SETUP
13
12
11
NCS_WR_SETUP
5
4
3
2
NWE_SETUP
• NWE_SETUP: NWE Setup Length
The NWE signal setup length is defined as:
NWE setup length = (128* NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles
• NCS_WR_SETUP: NCS Setup Length in WRITE Access
In write access, the NCS signal setup length is defined as:
NCS setup length = (128* NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles
• NRD_SETUP: NRD Setup Length
The NRD signal setup length is defined in clock cycles as:
NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles
• NCS_RD_SETUP: NCS Setup Length in READ Access
In read access, the NCS signal setup length is defined as:
NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles
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23.14.2
Name:
SMC Pulse Register
SMC_PULSE[0..5]
Addresses: 0xFFFFE804 [0], 0xFFFFE814 [1], 0xFFFFE824 [2], 0xFFFFE834 [3], 0xFFFFE844 [4], 0xFFFFE854 [5]
Access:
Read-write
31
30
29
28
–
23
22
21
20
–
15
26
25
24
19
18
17
16
10
9
8
2
1
0
NRD_PULSE
14
13
12
–
7
27
NCS_RD_PULSE
11
NCS_WR_PULSE
6
5
4
–
3
NWE_PULSE
• NWE_PULSE: NWE Pulse Length
The NWE signal pulse length is defined as:
NWE pulse length = (256* NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles
The NWE pulse length must be at least 1 clock cycle.
• NCS_WR_PULSE: NCS Pulse Length in WRITE Access
In write access, the NCS signal pulse length is defined as:
NCS pulse length = (256* NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles
The NCS pulse length must be at least 1 clock cycle.
• NRD_PULSE: NRD Pulse Length
In standard read access, the NRD signal pulse length is defined in clock cycles as:
NRD pulse length = (256* NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles
The NRD pulse length must be at least 1 clock cycle.
In page mode read access, the NRD_PULSE parameter defines the duration of the subsequent accesses in the page.
• NCS_RD_PULSE: NCS Pulse Length in READ Access
In standard read access, the NCS signal pulse length is defined as:
NCS pulse length = (256* NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles
The NCS pulse length must be at least 1 clock cycle.
In page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page.
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23.14.3
Name:
SMC Cycle Register
SMC_CYCLE[0..5]
Addresses: 0xFFFFE808 [0], 0xFFFFE818 [1], 0xFFFFE828 [2], 0xFFFFE838 [3], 0xFFFFE848 [4], 0xFFFFE858 [5]
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
NRD_CYCLE
23
22
21
20
19
18
17
16
NRD_CYCLE
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
NWE_CYCLE
7
6
5
4
3
2
1
0
NWE_CYCLE
• NWE_CYCLE: Total Write Cycle Length
The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse
and hold steps of the NWE and NCS signals. It is defined as:
Write cycle length = (NWE_CYCLE[8:7]*256 + NWE_CYCLE[6:0]) clock cycles
• NRD_CYCLE: Total Read Cycle Length
The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse
and hold steps of the NRD and NCS signals. It is defined as:
Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles
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23.14.4
Name:
SMC MODE Register
SMC_MODE[0..5]
Addresses: 0xFFFFE80C [0], 0xFFFFE81C [1], 0xFFFFE82C [2], 0xFFFFE83C [3], 0xFFFFE84C [4], 0xFFFFE85C [5]
Access:
Read-write
31
30
–
–
29
28
23
22
21
20
–
–
–
TDF_MODE
15
14
13
–
–
7
6
–
–
PS
12
DBW
5
4
EXNW_MODE
27
26
25
24
–
–
–
PMEN
19
18
17
16
TDF_CYCLES
11
10
9
8
–
–
–
BAT
3
2
1
0
–
–
WRITE_MODE
READ_MODE
• READ_MODE:
1: The read operation is controlled by the NRD signal.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NRD.
0: The read operation is controlled by the NCS signal.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS.
• WRITE_MODE
1: The write operation is controlled by the NWE signal.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE.
0: The write operation is controlled by the NCS signal.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS.
• EXNW_MODE: NWAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of
the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for the read and write controlling signal.
EXNW_MODE
NWAIT Mode
0
0
Disabled
0
1
Reserved
1
0
Frozen Mode
1
1
Ready Mode
• Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select.
• Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write
cycle is resumed from the point where it was stopped.
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• Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling
read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until
NWAIT returns high.
• BAT: Byte Access Type
This field is used only if DBW defines a 16- or 32-bit data bus.
• 1: Byte write access type:
– Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3.
– Read operation is controlled using NCS and NRD.
• 0: Byte select access type:
– Write operation is controlled using NCS, NWE, NBS0, NBS1, NBS2 and NBS3
– Read operation is controlled using NCS, NRD, NBS0, NBS1, NBS2 and NBS3
• DBW: Data Bus Width
DBW
Data Bus Width
0
0
8-bit bus
0
1
16-bit bus
1
0
32-bit bus
1
1
Reserved
• TDF_CYCLES: Data Float Time
This field gives the integer number of clock cycles required by the external device to release the data after the rising edge
of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The
external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can
be set.
• TDF_MODE: TDF Optimization
1: TDF optimization is enabled.
– The number of TDF wait states is optimized using the setup period of the next read/write access.
0: TDF optimization is disabled.
– The number of TDF wait states is inserted before the next access begins.
• PMEN: Page Mode Enabled
1: Asynchronous burst read in page mode is applied on the corresponding chip select.
0: Standard read is applied.
• PS: Page Size
If page mode is enabled, this field indicates the size of the page in bytes
PS
Page Size
0
0
4-byte page
0
1
8-byte page
1
0
16-byte page
1
1
32-byte page
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24. DDR/SDR SDRAM Controller (DDRSDRC)
24.1
Description
The DDR/SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises
four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are interleaved to maximize memory bandwidth and minimize transaction latency due to SDRAM
protocol.
The DDRSDRC extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDR-SDRAM device and external 16-bit DDR-SDRAM device. The page size
supports ranges from 2048 to 16384 and the number of columns from 256 to 4096. It supports
byte (8-bit), half-word (16-bit) and word (32-bit) accesses.
The DDRSDRC supports a read or write burst length of 8 locations which frees the command
and address bus to anticipate the next command, thus reducing latency imposed by the SDRAM
protocol and improving the SDRAM bandwidth. Moreover it keeps track of the active row in each
bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank
and data in the other banks. So as to optimize performance, it is advisable to avoid accessing
different rows in the same bank. The DDRSDRC supports a CAS latency of 2, 2.5 or 3 and optimizes the read access depending on the frequency.
The features of self refresh, power-down and deep power-down modes minimize the consumption of the SDRAM device.
The DDRSDRC user interface is compliant with ARM Advance Peripheral Bus (APB rev2).
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24.2
DDRSDRC Module Diagram
Figure 24-1.
DDRSDRC Module Diagram
DDR-SDR Controller
AHB Slave Interface 0
AHB Slave Interface 1
Input
Stage
Power Management
clk/nclk
Input
Stage
ras,cas,we
cke
Output
Stage
AHB Slave Interface 2
Input
Stage
Memory Controller
Finite State Machine
SDRAM Signal Management
Arbiter
Addr, DQM
DDR-SDR
Devices
DQS
Data
AHB Slave Interface 3
Input
Stage
Asynchronous Timing
Refresh Management
Interconnect Matrix
APB
Interface APB
DDRSDRC is partitioned in two blocks (see Figure 24-1):
• An Interconnect-Matrix that manages concurrent accesses on the AHB bus between four
AHB masters and integrates an arbiter.
• A controller that translates AHB requests (Read/Write) in the SDRAM protocol.
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24.3
24.3.1
Product Dependencies
SDR-SDRAM Initialization
The initialization sequence is generated by software. The SDR-SDRAM devices are initialized
by the following sequence:
1. Program the memory device type into the Memory Device Register (see Section 24.6.7
on page 254).
2. Program the features of the SDR-SDRAM device into the Timing Register (asynchronous timing (trc, tras, etc.)), and into the Configuration Register (number of columns,
rows, banks, cas latency) (see Section 24.6.3 on page 247, Section 24.6.4 on page 249
and Section 24.6.5 on page 251).
3. For low-power SDRAM, temperature-compensated self refresh (TCSR), drive strength
(DS) and partial array self refresh (PASR) must be set in the Low-power Register (see
Section 24.6.6 on page 252).
A minimum pause of 200 µs is provided to precede any signal toggle.
4. A NOP command is issued to the SDR-SDRAM. Program NOP command into Mode
Register, the application must set Mode to 1 in the Mode Register (See Section 24.6.1
on page 245). Perform a write access to any SDR-SDRAM address to acknowledge
this command. Now the clock which drives SDR-SDRAM device is enabled.
5. An all banks precharge command is issued to the SDR-SDRAM. Program all banks
precharge command into Mode Register, the application must set Mode to 2 in the
Mode Register (See Section 24.6.1 on page 245). Perform a write access to any SDRSDRAM address to acknowledge this command.
6. Eight auto-refresh (CBR) cycles are provided. Program the auto refresh command
(CBR) into Mode Register, the application must set Mode to 4 in the Mode Register
(see Section 24.6.1 on page 245).Performs a write access to any SDR-SDRAM location eight times to acknowledge these commands.
7. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRSDRAM devices, in particular CAS latency and burst length. The application must set
Mode to 3 in the Mode Register (see Section 24.6.1 on page 245) and perform a write
access to the SDR-SDRAM to acknowledge this command. The write address must be
chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDR-SDRAM
(12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done
at the address 0x20000000(1).
Note:
1. This address is for example purposes only. The real address is dependent on implementation
in the product.
8. For low-power SDR-SDRAM initialization, an Extended Mode Register set (EMRS)
cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS). The application must set Mode to 5 in the Mode Register (see Section 24.6.1 on page 245) and
perform a write access to the SDR-SDRAM to acknowledge this command. The write
address must be chosen so that BA[1] or BA[0] are set to 1. For example, with a 16-bit
128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank address the SDRAM write
access should be done at the address 0x20800000 or 0x20400000.
9. The application must go into Normal Mode, setting Mode to 0 in the Mode Register (see
Section 24.6.1 on page 245) and perform a write access at any location in the SDRAM
to acknowledge this command.
10. Write the refresh rate into the count field in the SDRAMC Refresh Timer register (see
page 246). (Refresh rate = delay between refresh cycles). The SDR-SDRAM device
requires a refresh every 15.625 µs or 7.81 µs. With a 100 MHz frequency, the refresh
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timer count register must to be set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81
/100 MHz) = 781 i.e. 0x030d
After initialization, the SDR-SDRAM device is fully functional.
24.3.2
DDR-SDRAM Initialization
The initialization sequence is generated by software. The DDR-SDRAM devices are initialized
by the following sequence:
1. Program the memory device type into the Memory Device Register (see Section 24.6.7
on page 254).
2. Program the features of DDR-SDRAM device into the Timing Register (asynchronous
timing (trc, tras, etc.)), and into the Configuration Register (number of columns, rows,
banks, cas latency and output drive strength) (see Section 24.6.3 on page 247, Section
24.6.4 on page 249 and Section 24.6.5 on page 251).
3. An NOP command is issued to the DDR-SDRAM. Program the NOP command into the
Mode Register, the application must set Mode to 1 in the Mode Register (see Section
24.6.1 on page 245). Perform a write access to any DDR-SDRAM address to acknowledge this command. Now clocks which drive DDR-SDRAM device are enabled.
A minimum pause of 200 µs is provided to precede any signal toggle.
4. An NOP command is issued to the DDR-SDRAM. Program the NOP command into the
Mode Register, the application must set Mode to 1 in the Mode Register (see Section
24.6.1 on page 245). Perform a write access to any DDR-SDRAM address to acknowledge this command. Now CKE is driven high.
5. An all banks precharge command is issued to the DDR-SDRAM. Program all banks
precharge command into the Mode Register, the application must set Mode to 2 in the
Mode Register (See Section 24.6.1 on page 245). Perform a write access to any DDRSDRAM address to acknowledge this command
6. An Extended Mode Register set (EMRS) cycle is issued to enable DLL and to program
output drive strength (DIC/DS). The application must set Mode to 5 in the Mode Register (see Section 24.6.1 on page 245) and perform a write access to the DDR-SDRAM
to acknowledge this command. The write address must be chosen so that BA[1] or
BA[0] are set to 1. For example, with a 16-bit 128 MB DDR-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR-SDRAM write access should be done at the
address 0x20800000 or 0x20400000.
An additional 200 cycles of clock are required for locking DLL
7. Program DLL field into the Configuration Register (see Section 24.6.3 on page 247) to
high (Enable DLL reset).
8. A Mode Register set (MRS) cycle is issued to reset DLL. The application must set
Mode to 3 in the Mode Register (see Section 24.6.1 on page 245) and perform a write
access to the DDR-SDRAM to acknowledge this command. The write address must be
chosen so that BA[1:0] bits are set to 0. For example, with a 16-bit 128 MB DDRSDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should
be done at the address 0x20000000.
9. Two auto-refresh (CBR) cycles are provided. Program the auto refresh command
(CBR) into the Mode Register, the application must set Mode to 4 in the Mode Register
(see Section 24.6.1 on page 245). Performs a write access to any DDR-SDRAM location twice to acknowledge these commands.
10. Program DLL field into the Configuration Register (see Section 24.6.3 on page 247) to
low (Disable DLL reset).
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11. A Mode Register set (MRS) cycle is issued to program the parameters of the DDRSDRAM devices, in particular CAS latency, burst length and to disable DLL reset. The
application must set Mode to 3 in the Mode Register (see Section 24.6.1 on page 245)
and perform a write access to the DDR-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit
128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write
access should be done at the address 0x20000000
12. A mode Normal command is provided. Program the normal mode into Mode Register
(see Section 24.6.1 on page 245). Perform a write access to any DDR-SDRAM address
to acknowledge this command.
13. Perform a write access to any DDR-SDRAM address.
14. Write the refresh rate into the count field in the Refresh Timer register (see page 246).
(Refresh rate = delay between refresh cycles). The DDR-SDRAM device requires a
refresh every 15.625 µs or 7.81 µs. With a 100 MHz frequency, the refresh timer count
register must to be set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81 /100 MHz) =
781 i.e. 0x030d
After initialization, the DDR-SDRAM devices are fully functional.
24.3.3
Low-power DDR-SDRAM Initialization
The initialization sequence is generated by software. The low-power DDR-SDRAM devices are
initialized by the following sequence:
1. Program the memory device type into the Memory Device Register (see Section 24.6.7
on page 254).
2. Program the features of the low-power DDR-SDRAM device into the Configuration
Register: asynchronous timing (trc, DDRSDRAMC, etc.), number of columns, rows,
banks, cas latency. See Section 24.6.3 on page 247, Section 24.6.4 on page 249 and
Section 24.6.5 on page 251.
3. Program temperature compensated self refresh (tcr), Partial array self refresh (pasr)
and Drive strength (ds) into the Low-power Register. See Section 24.6.6 on page 252.
A minimum pause of 200 µs will be provided to precede any signal toggle.
4. An NOP command will be issued to the DDR-SDRAM. Program NOP command into
the Mode Register, the application must set Mode to 1 in the Mode Register (see Section 24.6.1 on page 245). Perform a write access to any DDR-SDRAM address to
acknowledge this command. Now clocks which drive DDR-SDRAM device are enabled.
5. An all banks precharge command is issued to the DDR-SDRAM. Program all banks
precharge command into the Mode Register, the application must set Mode to 2 in the
Mode Register (See Section 24.6.1 on page 245). Perform a write access to any DDRSDRAM address to acknowledge this command
6. Two auto-refresh (CBR) cycles are provided. Program the auto refresh command
(CBR) into the Mode Register, the application must set Mode to 4 in the Mode Register
(see Section 24.6.1 on page 245). Perform a write access to any DDR-SDRAM location
twice to acknowledge these commands.
7. An Extended Mode Register set (EMRS) cycle is issued to program the DDR-SDRAM
parameters (TCSR, PASR, DS). The application must set Mode to 5 in the Mode Register (see Section 24.6.1 on page 245) and perform a write access to the SDRAM to
acknowledge this command. The write address must be chosen so that BA[1] or BA[0]
are set to 1. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks)
bank address, the SDRAM write access should be done at the address 0x20800000 or
0x20400000.
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6264C–CAP–24-Mar-09
8. A Mode Register set (MRS) cycle is issued to program the parameters of the DDRSDRAM devices, in particular CAS latency, burst length. The application must set Mode
to 3 in the Mode Register (see Section 24.6.1 on page 245) and perform a write access
to the DDR-SDRAM to acknowledge this command. The write address must be chosen
so that BA[1:0] bits are set to 0. For example, with a 16-bit 128 MB DDR-SDRAM (12
rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at
the address 0x20000000
9. The application must go into Normal Mode, setting Mode to 0 in the Mode Register (see
Section 24.6.1 on page 245) and performing a write access at any location in the DDRSDRAM to acknowledge this command.
10. Perform a write access to any DDR-SDRAM address.
11. Write the refresh rate into the count field in the SDRAMC Refresh Timer register (see
page 246). (Refresh rate = delay between refresh cycles). The DDR-SDRAM device
requires a refresh every 15.625 µs or 7.81 µs. With a 100 MHz frequency, the refresh
timer count register must to be set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81
/100 MHz) = 781 i.e. 0x030d
12. After initialization, the DDR-SDRAM device is fully functional.
24.4
24.4.1
Functional Description
SDRAM Controller Write Cycle
The DDRSDRC allows burst access or single access in normal mode (mode = 000). Whatever
the access type, the DDRSDRC keeps track of the active row in each bank, thus maximizing
performance.
The SDRAM device is programmed with a burst length equal to 8. This determines the length of
a sequential data input by the write command that is set to 8. The latency from write command to
data input is fixed to 1 in the case of DDR-SDRAM devices. In the case of SDR-SDRAM
devices, there is no latency from write command to data input.
To initiate a single access, the DDRSDRC checks if the page access is already open. If
row/bank addresses match with the previous row/bank addresses, the controller generates a
write command. If the bank addresses are not identical or if bank addresses are identical but the
row addresses are not identical, the controller generates a precharge command, activates the
new row and initiates a write command. To comply with SDRAM timing parameters, additional
clock cycles are inserted between precharge/active (t RP) commands and active/write (t RCD)
command. As the burst length is fixed to 8, in the case of single access, it has to stop the burst,
otherwise seven invalid values may be written. In the case of SDR-SDRAM devices, a Burst
Stop command is generated to interrupt the write operation. In the case of DDR-SDRAM
devices, Burst Stop command is not supported for the burst write operation. In order to then
interrupt the write operation, Dm must be set to 1 to mask invalid data (see Figure 24-2 on page
229 and Figure 24-4 on page 230) and DQS must continue to toggle.
To initiate a burst access, the DDRSDRC uses the transfer type signal provided by the master
requesting the access. If the next access is a sequential write access, writing to the SDRAM
device is carried out. If the next access is a write non-sequential access, then an automatic
access break is inserted, the DDRSDRC generates a precharge command, activates the new
row and initiates a write command. To comply with SDRAM timing parameters, additional clock
cycles are inserted between precharge/active (tRP) commands and active/write (tRCD)
commands.
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AT91CAP9S500A/AT91CAP9S250A
For a definition of timing parameters, refer to Section 24.6.4 “DDRSDRC Timing 0 Parameter
Register” on page 249.
Write accesses to the SDRAM devices are burst oriented and the burst length is programmed to
8. It determines the maximum number of column locations that can be accessed for a given write
command. When the write command is issued, 8 columns are selected. All accesses for that
burst take place within these eight columns, thus the burst wraps within these 8 columns if a
boundary is reached. These 8 columns are selected by addr[13:3]. addr[2:0] is used to select the
starting location within the block.
In the case of incrementing burst (INCR/INCR4/INCR8/INCR16), the addresses can cross the
16-byte boundary of the SDRAM device. For example, in the case of DDR-SDRAM devices,
when a transfer (INCR4) starts at address 0x0C, the next access is 0x10, but since the burst
length is programmed to 8, the next access is at 0x00. Since the boundary is reached, the burst
is wrapping. The DDRSDRC takes this feature of the SDRAM device into account. In the case of
transfer starting at address 0x04/0x08/0x0C (DDR-SDRAM devices) or starting at address
0x10/0x14/0x18/0x1C, two write commands are issued to avoid to wrap when the boundary is
reached. The last write command is subject to DM input logic level. If DM is registered high, the
corresponding data input is ignored and write access is not done. This avoids additional writing
being done.
Figure 24-2. Single Write Access, Row Closed, DDR-SDRAM Device
SDCLK
Row a
A[12:0]
COMMAND
BA[1:0]
NOP
PRCHG
NOP
ACT
col a
NOP
WRITE
NOP
00
DQS[1:0]
DM[1:0]
D[15:0]
Da
Trp=2
3
0
3
Db
Trcd=2
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6264C–CAP–24-Mar-09
Figure 24-3. Single Write Access, Row Closed, SDR-SDRAM Device
SDCLK
SDCLKN
A[12:0]
Row a
COMMAND
NOP
PRCHG
NOP
ACT
Col a
NOP
BST
WRITE
NOP
00
BA[1:0]
3
DM[1:0]
0
D[31:0]
3
DaDb
Trp=2
Trcd=2
Figure 24-4. Burst Write Access, Row Closed, DDR-SDRAM Devices
SDCLK
A[12:0]
Row a
COMMAND
BA[1:0]
NOP
PRCHG
NOP
col a
ACT
NOP
WRITE
NOP
0
DQS[1:0]
DM[1:0]
3
0
D [15:0]
Da
Trp=2
230
Db
Dc
Dd
3
De
Df
Dg
Dh
Trcd=2
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 24-5. Burst Write Access, Row Closed, SDR-SDRAM Devices
SDCLK
A[12:0]
COMMAND
Row a
NOP
BA[1:0]
0
DM[3:0]
F
PRCHG
Col a
NOP
ACT
NOP
NOP
WRITE
0
D[31:0]
Da Db
NOP
BST
F
Dc Dd
De Df
Dg Dhs
Trcd
Trp
A write command can be followed by a read command. To avoid breaking the current write
burst, Twtr/twrd (bl/2 + 2 = 6 cycles) should be met. See Figure 24-6 on page 231.
Figure 24-6. Write Command Followed By A Read Command without Burst Write Interrupt, DDR-SDRAM Devices t
SDCLK
A[12:0]
col a
COMMAND
BA[1:0]
NOP
col a
WRITE
NOP
READ
BST
NOP
0
DQS[1:0]
DM[1:0]
D[15:0]
3
0
3
Da
Db Dc
Dd
De
Df
Dg
Da Db
Dh
Twrd = BL/2 +2 = 8/2 +2 = 6
Twr=1
In the case of a single write access, write operation should be interrupted by a read access but
DM must be input 1 cycle prior to the read command to avoid writing invalid data. See Figure 247 on page 232.
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6264C–CAP–24-Mar-09
Figure 24-7. SINGLE Write Access Followed By a Read Access, DDR-SDRAM Devices
SDCLK
A[12:0]
COMMAND
BA[1:0]
col a
Row a
NOP
PRCHG
NOP
ACT
NOP
WRITE
NOP
READ
BST
NOP
0
DQS[1:0]
DM[1:0]
D[15:0]
3
0
Da
3
Db
Da Db
Data masked
232
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
24.4.2
SDRAM Controller Read Cycle
The DDRSDRC allows burst access or single access in normal mode (mode =000). Whatever
access type, the DDRSDRC keeps track of the active row in each bank, thus maximizing performance of the DDRSDRC.
The SDRAM devices are programmed with a burst length equal to 8 which determines the length
of a sequential data output by the read command that is set to 8. The latency from read command to data output is equal to 2, 2.5 or 3. This value is programmed during the initialization
phase (see Section 24.3.1 “SDR-SDRAM Initialization” on page 225).
To initiate a single access, the DDRSDRC checks if the page access is already open. If
row/bank addresses match with the previous row/bank addresses, the controller generates a
read command. If the bank addresses are not identical or if bank addresses are identical but the
row addresses are not identical, the controller generates a precharge command, activates the
new row and initiates a read command. To comply with SDRAM timing parameters, additional
clock cycles are inserted between precharge/active (Trp) commands and active/read (Trcd)
command. After a read command, additional wait states are generated to comply with cas
latency. The DDRSDRC supports a cas latency of two, two and half, and three (2 or 3 clocks
delay). As the burst length is fixed to 8, in the case of single access or burst access inferior to 8
data requests, it has to stop the burst otherwise seven or X values could be read. Burst Stop
Command (BST) is used to stop output during a burst read.
To initiate a burst access, the DDRSDRC checks the transfer type signal. If the next accesses
are sequential read accesses, reading to the SDRAM device is carried out. If the next access is
a read non-sequential access, then an automatic page break can be inserted. If the bank
addresses are not identical or if bank addresses are identical but the row addresses are not
identical, the controller generates a precharge command, activates the new row and initiates a
read command. In the case where the page access is already open, a read command is
generated.
To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge/active (Trp) commands and active/read (Trcd) commands. The DDRSDRC supports a
cas latency of two, two and half, and three (2 or 3 clocks delay). During this delay, the controller
uses internal signals to anticipate the next access and improve the performance of the controller. Depending on the latency(2/2.5/3), the DDRSDRC anticipates 2 or 3 read accesses. In the
case of burst of specified length, accesses are not anticipated, but if the burst is broken (border,
busy mode, etc.), the next access is treated as an incrementing burst of unspecified length, and
in function of the latency(2/2.5/3), the DDRSDRAMC anticipates 2 or 3 read accesses.
For a definition of timing parameters, refer to Section 24.6.3 “DDRSDRC Configuration Register”
on page 247.
Read accesses to the SDRAM are burst oriented and the burst length is programmed to 8. It
determines the maximum number of column locations that can be accessed for a given read
command. When the read command is issued, 8 columns are selected. All accesses for that
burst take place within these eight columns, meaning that the burst wraps within these 8 columns if the boundary is reached. These 8 columns are selected by addr[13:3]; addr[2:0] is used
to select the starting location within the block.
In the case of incrementing burst (INCR/INCR4/INCR8/INCR16), the addresses can cross the
16-byte boundary of the SDRAM device. For example, when a transfer (INCR4) starts at
address 0x0C, the next access is 0x10, but since the burst length is programmed to 8, the next
access is 0x00. Since the boundary is reached, the burst wraps. The DDRSDRC takes into
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6264C–CAP–24-Mar-09
account this feature of the SDRAM device. In the case of DDR-SDRAM devices, transfers start
at address 0x04/0x08/0x0C. In the case of SDR-SDRAM devices, transfers start at address
0x14/0x18/0x1C. Two read commands are issued to avoid wrapping when the boundary is
reached. The last read command may generate additional reading (1 read cmd = 4 DDR words
or 1 read cmd = 8 SDR words).
To avoid additional reading, it is possible to use the burst stop command to truncate the read
burst and to decrease power consumption.
Figure 24-8. Single Read Access, Row Close, Latency= 2, DDR-SDRAM Devices
SDCLK
A[12:0]
COMMAND
BA[1:0]
NOP
PRCHG
NOP
Row a
Col a
ACT
NOP
READ
BST
NOP
0
DQS[1]
DQS[0]
DM[1:0]
3
D[15:0]
Da
Trp
Db
Latency =2
Trcd
Figure 24-9. Single Read Access, Row Close, Latency= 2, SDR-SDRAM Devices
SDCLK
A[12:0]
COMMAND
Row a
NOP
BA[1:0]
0
DM[3:0]
3
PRCHG
NOP
ACT
col a
NOP
READ
BST
D[31:0]
DaDb
Trp
234
NOP
Trcd
Latency =2
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 24-10. Burst Read Access, Latency =2, DDR-SDRAM Devices
SDCLKN
SDCLK
A[12:0]
Col a
COMMAND
NOP
BA[1:0]
READ
NOP
0
DQS[1:0]
DM[1:0]
3
D[15:0]
Da
Db
Dc
Dd
De
Df
Dg
Dh
Latency =2
Figure 24-11. Burst Read Access, Latency =2, SDR-SDRAM Devices
SDCLK
A[12:0]
COMMAND
BA[1:0]
col a
NOP
READ
NOP
BST
NOP
0
DQS[1:0]
DM[3:0]
F
D[31:0]
DaDb
DcDd
DeDf
Dg Dh
Latency = 2
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6264C–CAP–24-Mar-09
24.4.3
Refresh (Auto-refresh Command)
An auto-refresh command is used to refresh the DDRSDRC. Refresh addresses are generated
internally by the SDRAM device and incremented after each auto-refresh automatically. The
DDRSDRC generates these auto-refresh commands periodically. A timer is loaded with the
value in the register DDRSDRAMC_TR that indicates the number of clock cycles between
refresh cycles. When the DDRSDRC initiates a refresh of an SDRAM device, internal memory
accesses are not delayed. However, if the CPU tries to access the SDRAM device, the slave
indicates that the device is busy. A request of refresh does not interrupt a burst transfer in
progress.
24.4.4
Power Management
24.4.4.1
Self Refresh Mode
This mode is activated by setting low-power command bits [LPCB] to ‘01’ in the
DDRSDRAMC_LPR Register
Self refresh mode is used in power-down mode, i.e., when no access to the SDRAM device is
possible. In this case, power consumption is very low. In self refresh mode, the SDRAM device
retains data without external clocking and provides its own internal clocking, thus performing its
own auto-refresh cycles. All the inputs to the SDRAM device become don’t care except CKE,
which remains low. As soon as the SDRAM device is selected, the DDRSDRC provides a
sequence of commands and exits self refresh mode.
The DDRSDRC re-enables self refresh mode as soon as the SDRAM device is not selected. It is
possible to define when self refresh mode will be enabled by setting the register LPR (see Section 24.6.6 “DDRSDRC Low-power Register” on page 252), timeout command bit:
• 00 = Self refresh mode is enabled as soon as the SDRAM device is not selected
• 01 = Self refresh mode is enabled 64 clock cycles after completion of the last access
• 10 = Self refresh mode is enabled 128 clock cycles after completion of the last access
This controller also interfaces low-power SDRAM. These devices add a new feature: A single
quarter, one half quarter or all banks of the SDRAM array can be enabled in self refresh mode.
Disabled banks will be not refreshed in self refresh mode. This feature permits to reduce the self
refresh current. The extended mode register controls this new feature, it include Temperature
Compensated Self Refresh (TSCR), Partial Array Self refresh (PASR) parameters and drives
strength (DS). These parameters are set during the initialization phase. After initialization, as
soon as PASR/DS/TCSR fields are modified and self-refresh mode is activated, the Extended
Mode Register is accessed automatically and PASR/DS/TCSR bits are updated before any
entry into self refresh mode.
The low-power SDR-SDRAM must remain in self refresh mode for a minimum period of TRAS
periods and may remain in self refresh mode for an indefinite period. (See Figure 24-12 on page
237)
The low-power DDR-SDRAM must remain in self refresh mode for a minimum of TRFC periods
and may remain in self refresh mode for an indefinite period.
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6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 24-12. Self Refresh Mode Entry, Timeout =0
SDCK
A[12:0]
COMMAND
NOP READ
BST
NOP
PRCHG
NOP
ARFSH
NOP
CKE
BA[1:0]
0
DQS[0:1]
DM[1:0]
3
D[15:0]
Da
Db
Trp
Enter Self refresh
Mode
Figure 24-13. Self Refresh Mode Entry, Timeout =1 or 2
SDCLK
A[12:0]
COMMAND
NOP READ
BST
NOP
PRCHG
NOP
ARFSH NOP
CKE
BA[1:0]
0
DQS[1:0]
DM[1:0]
D[15:0]
3
Da
Db
64 or 128
wait states
Trp
Enter Self refresh
Mode
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6264C–CAP–24-Mar-09
Figure 24-14. Self Refresh Mode Exit
SDCLK
A[12:0]
COMMAND
NOP
VALID
NOP
CKE
BA[1:0]
0
DQS[1:0]
DM[1:0]
3
D[15:0]
DaDb
Exit Self Refresh mode
clock must be stable
before exiting self refresh mode
24.4.4.2
TXNRD/TXSRD
TXSR
TXSR
(DDR device)
(Mobile DDR device)
(Mobile SDR, SDR-SDRAM device)
Power-down Mode
This mode is activated by setting the low-power command bits [LPCB] to ‘10’.
Power-down mode is used when no access to the SDRAM device is possible. In this mode,
power consumption is greater than in self refresh mode. This state is similar to normal mode (No
low-power mode/No self refresh mode), but the CKE pin is low and the input and output buffers
are deactivated as soon the SDRAM device is no longer accessible. In contrast to self refresh
mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64
ms). As no auto-refresh operations are performed in this mode, the DDRSDRC carries out the
refresh operation. In order to exit low-power mode, a NOP command is required in the case of
low-power SDR-SDRAM, SDR-SDRAM and DDR-SDRAM devices. In the case of low-power
DDR-SDRAM devices, the controller generates a NOP command during a delay of at least TXP.
In addition, low-power DDR-SDRAM must remain in power-down mode for a minimum period of
TCKE periods.
The exit procedure is faster than in self refresh mode. See Figure 24-15 on page 239. The
DDRSDRC returns to power-down mode as soon as the SDRAM device is not selected. It is
possible to define when power-down mode is enabled by setting the register LPR, timeout command bit.
• 00 = Power-down mode is enabled as soon as the SDRAM device is not selected
• 01 = Power-down mode is enabled 64 clock cycles after completion of the last access
• 10 = Power-down mode is enabled 128 clock cycles after completion of the last access
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AT91CAP9S500A/AT91CAP9S250A
Figure 24-15. Power-down Entry/Exit, Timeout =0
SDCK
A[12:0]
COMMAND
READ
EEPPWD NOP
READ
CKE
BA[1:0]
0
DQS[1:0]
DM[1:0]
3
D[15:0]
Da
Db
Exit power down mode
Entry power down mode
24.4.4.3
Deep Power-down Mode
The deep power-down mode is a new feature of the low-power SDRAM. When this mode is activated, all internal voltage generators inside the device are stopped and all data is lost.
This mode is activated by setting the low-power command bits [LPCB] to ‘11’. When this mode is
enabled, the DDRSDRC leaves normal mode (mode == 000) and the controller is frozen. To exit
deep power-down mode, the low-power command bits (LPCB) must be set to “00”, an initialization sequence must be generated by software: (see Section 24.3.3 “Low-power DDR-SDRAM
Initialization” on page 227).
Figure 24-16. Deep Power-down Mode Entry
SDCLK
A[12:0]
COMMAND
NOP READ
BST
NOP
PRCHG
NOP
DEEPOWER
NOP
CKE
BA[1:0]
0
DQS[1:0]
DM[1:0]
D[15:0]
3
Da
Db
Trp
Enter Deep
Power-down
Mode
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6264C–CAP–24-Mar-09
24.4.4.4
Multi-port Functionality
The SDRAM protocol imposes a check of timings prior to performing a read or a write access,
thus decreasing the performance of systems. An access to SDRAM is performed if banks and
rows are open (or active). To activate a row in a particular bank, it has to de-active the last open
row and open the new row. Two SDRAM commands must be performed to open a bank: Precharge and Active command with respect to Trp timing. Before performing a read or write
command, Trcd timing must checked.
This operation represents a significative loss. (see Figure 24-17)
Figure 24-17. Trp and Trcd Timings
SDCK
A[12:0]
COMMAND
BA[1:0]
NOP
PRCHG
NOP
ACT
NOP
READ
BST
NOP
0
DQS[1:0]
DM1:0]
3
D[15:0]
Da
Trp
Trcd
Db
Latency =2
4 cycles before performing a read command
The multi-port controller has been designed to mask these timings and thus improve the bandwidth of the system.
DDRSDRC is a multi-port controller since four masters can simultaneously reach the controller.
This feature improves the bandwidth of the system because it can detect four requests on the
AHB slave inputs and thus anticipate the commands that follow, PRECHARGE and ACTIVE
commands in bank X during current access in bank Y. This allows Trp and Trcd timings to be
masked (see Figure 24-18). In the best case, all accesses are done as if the banks and rows
were already open. The best condition is met when the four masters work in different banks. In
the case of four simultaneous read accesses, when the four banks and associated rows are
open, the controller reads with a continuous flow and masks the cas latency for each different
access. To allow a continuous flow, the read command must be set at 2 or 3 cycles (cas latency)
before the end of current access. This requires that the scheme of arbitration changes since the
round-robin arbitration cannot be respected. If the controller anticipates a read access, and thus
before the end of current access a master with a high priority arises, then this master will not
serviced.
The arbitration mechanism reduces latency when conflicts occur, i.e., when two or more masters
try to access the SDRAM device at the same time.
The arbitration type is round-robin arbitration. This algorithm dispatches the requests from different masters to the SDRAM device in a round-robin manner. If two or more master requests arise
at the same time, the master with the lowest number is serviced first, then the others are serviced in a round-robin manner. To avoid burst breaking and to provide the maximum throughput
for the SDRAM device, arbitration may only take place during the following cycles:
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AT91CAP9S500A/AT91CAP9S250A
1. Idle cycles: When no master is connected to the SDRAM device.
2. Single cycles: When a slave is currently doing a single access.
3. End of Burst cycles: When the current cycle is the last cycle of a burst transfer. For
bursts of defined length, predicted end of burst matches the size of the transfer. For
bursts of undefined length, predicted end of burst is generated at the end of each four
beat boundary inside the INCR transfer.
4. Anticipated Access: When an anticipate read access is done while current access is
not complete, the arbitration scheme can be changed if the anticipated access is not
the next access serviced by the arbitration scheme.
Figure 24-18. Anticipate Precharge/Active Command in Bank 2 during Read Access in Bank 1
SDCK
A[12:0]
COMMAND
BA[1:0]
NOP
0
1
READ
ACT
NOP
PRECH
READ
2
NOP
1
DQS[1:0]
DM1:0]
3
D[15:0]
Da
Db
Dc
Dd
De
Df
Dg
Dh
Di
Dj
Dk
Dl
Trp
Anticipate command, Precharge/Active Bank 2
Read access in Bank 1
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6264C–CAP–24-Mar-09
24.5
Software Interface/SDRAM Organization, Address Mapping
The SDRAM address space is organized into banks, rows and columns. The DDRSDRC maps
different memory types depending on the values set in the DDRSDRC Configuration Register.
See Section 24.6.3 “DDRSDRC Configuration Register” on page 247. The following figures illustrate the relation between CPU addresses and columns, rows and banks addresses for 16-bit
memory data bus widths and 32-bit memory data bus widths.
The DDRSDRC supports address mapping in linear mode.
Linear mode is a method for address mapping where banks alternate at each last SDRAM page
of current bank.
The DDRSDRC makes the SDRAM devices access protocol transparent to the user. Table 24-1
to Table 24-7 illustrate the SDRAM device memory mapping seen by the user in correlation with
the device structure. Various configurations are illustrated.
24.5.1
SDRAM Address Mapping for 16-bit Memory Data Bus Width(1)
Table 24-1.
Linear Mapping for SDRAM Configuration, 2K Rows, 512/1024/2048/4096 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
16
Bk[1:0]
14
13
12
11
10
9
8
7
Row[10:0]
Bk[1:0]
5
4
3
2
1
M0
M0
Column[10:0]
Row[10:0]
0
M0
Column[9:0]
Row[10:0]
Bk[1:0]
6
Column[8:0]
Row[10:0]
Bk[1:0]
Table 24-2.
15
M0
Column[11:0]
Linear Mapping for SDRAM Configuration: 4K Rows, 512/1024/2048/4096 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
Bk[1:0]
15
14
13
12
11
10
9
8
7
Row[11:0]
Bk[1:0]
5
4
3
2
1
M0
M0
Column[10:0]
Row[11:0]
0
M0
Column[9:0]
Row[11:0]
Bk[1:0]
6
Column[8:0]
Row[11:0]
Bk[1:0]
Table 24-3.
16
M0
Column[11:0]
Linear Mapping for SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
Bk[1:0]
Bk[1:0]
242
15
14
13
12
11
10
Row[12:0]
Bk[1:0]
Bk[1:0]
16
Row[12:0]
Row[12:0]
Row[12:0]
9
8
7
6
5
4
Column[8:0]
Column[9:0]
Column[10:0]
Column[11:0]
3
2
1
0
M0
M0
M0
M0
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Table 24-4.
Linear Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
Bk[1:0]
16
15
14
13
12
11
10
9
8
7
6
Row[13:0]
Bk[1:0]
5
4
3
2
1
M0
Column[9:0]
Row[13:0]
0
M0
Column[8:0]
Row[13:0]
Bk[1:0]
Note:
17
M0
Column[10:0]
1. SDR-SDRAM devices with eight columns in 16-bit mode are not supported.
24.5.2
SDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width
Table 24-5.
SDR-SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
16
Bk[1:0]
14
13
12
11
10
9
8
7
Row[10:0]
Bk[1:0]
Bk[1:0]
6
5
4
3
2
Column[7:0]
Row[10:0]
0
M[1:0]
Column[9:0]
Row[10:0]
1
M[1:0]
Column[8:0]
Row[10:0]
Bk[1:0]
Table 24-6.
15
M[1:0]
Column[10:0]
M[1:0]
SDR-SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
Bk[1:0]
15
14
13
12
11
10
9
8
7
Row[11:0]
Bk[1:0]
Bk[1:0]
6
5
4
3
2
Column[7:0]
Row[11:0]
0
M[1:0]
Column[9:0]
Row[11:0]
1
M[1:0]
Column[8:0]
Row[11:0]
Bk[1:0]
Table 24-7.
16
M[1:0]
Column[10:0]
M[1:0]
SDR-SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
Bk[1:0]
Row[12:0]
Bk[1:0]
Notes:
15
Row[12:0]
Bk[1:0]
Bk[1:0]
16
Row[12:0]
Row[12:0]
14
13
12
11
10
9
8
7
6
5
Column[7:0]
Column[8:0]
Column[9:0]
Column[10:0]
4
3
2
1
0
M[1:0]
M[1:0]
M[1:0]
M[1:0]
1. M[1:0] is the byte address inside a 32-bit word.
2. Bk[1] = BA1, Bk[0] = BA0
243
6264C–CAP–24-Mar-09
24.6
DDR/SDR SDRAM Controller (DDRSDRC) User Interface
The User Interface is connected to the APB bus.
The DDRSDRC is programmed using the registers listed in Table 24-8.
Table 24-8.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
DDRSDRC Mode Register
DDRSDRC_MR
Read-write
0x00000000
0x04
DDRSDRC Refresh Timer Register
DDRSDRC_RTR
Read-write
0x00000000
0x08
DDRSDRC Configuration Register
DDRSDRC_CR
Read-write
0x024
0x0C
DDRSDRC Timing0 Register
DDRSDRC_T0PR
Read-write
0x20227225
0x10
DDRSDRC Timing1 Register
DDRSDRC_T1PR
Read-write
0x3c80808
0x18
DDRSDRC Low-power Register
DDRSDRC_LPR
Read-write
0x0
0x1C
DDRSDRC Memory Device Register
DDRSDRC_MD
Read-write
0x10
0x20
DDRSDRC DLL Information Register
DDRSDRC_DLL
Read
0x00000001
0x28-0xE8
Reserved
244
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
24.6.1
Name:
DDRSDRC Mode Register
DDRSDRC_MR
Address:
0xFFFFE600
Access:
Read-write
Reset:
See Table 24-8
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
MODE
• MODE: DDRSDRAMC Command Mode
This field defines the command issued by the DDRSDRC when the SDRAM device is accessed. This register is used to initialize the SDRAM device and to activate deep power-down mode.
MODE
Description
000
Normal Mode. Any access to the DDRSDRAMC will be decoded normally. To activate this mode, command must be
followed by a write to the SDRAM.
001
The DDRSDRC issues a NOP Command when the SDRAM device is accessed regardless of the cycle. To activate this
mode, command must be followed by a write to the SDRAM.
010
The DDRSDRC issues an All Banks Precharge Command when the SDRAM device is accessed regardless of the cycle.
To activate this mode, command must be followed by a write to the SDRAM.
011
The DDRSDRC issues a Load mode Register command when the SDRAM device is accessed regardless of the cycle.
To activate this mode, command must be followed by a write to the SDRAM.
100
The DDRSDRC issues an Auto Refresh Command when the SDRAM device is accessed regardless of the cycle.
Previously, an All Banks Precharge Command must be issued. To activate this mode, command must be followed by a
write to the SDRAM.
101
The DDRSDRC issues an Extended Load Mode register command when the SDRAM device is accessed regardless of
the cycle. To activate this mode, the “Extended Load Mode” register command must be followed by a write to the SDRAM.
The write in the SDRAM must be done in the appropriate bank.
110
Deep power mode: Access to deep power-down mode
111
Reserved
245
6264C–CAP–24-Mar-09
24.6.2
Name:
DDRSDRC Refresh Timer Register
DDRSDRC_RTR
Address:
0xFFFFE604
Access:
Read-write
Reset:
See Table 24-8
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
7
6
5
4
1
0
COUNT
3
2
COUNT
• COUNT: DDRSDRC Refresh Timer Count
This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh
sequence is initiated.
SDRAM devices require a refresh of all rows every 64 ms. The value to be loaded depends on the DDRSDRC clock frequency (MCK: Master Clock) and the number of rows in the device.
For example, for an SDRAM with 8192 rows and a 100 MHz Master clock, the value of Refresh Timer Count bit is programmed: (((64 x 10-3)/8192) x100 x106 = 781 or 0x030D.
246
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
24.6.3
Name:
DDRSDRC Configuration Register
DDRSDRC_CR
Address:
0xFFFFE608
Access:
Read-write
Reset:
See Table 24-8
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
DIC/DS
7
6
5
4
3
2
1
DLL
CAS
NR
0
NC
• NC: Number of Column Bits.
The reset value is 9 column bits.
SDR-SDRAM devices with eight columns in 16-bit mode (b16mode ==1) are not supported.
NC
DDR - Column bits
SDR - Column bits
00
9
8
01
10
9
10
11
10
11
12
11
• NR: Number of Row Bits
The reset value is 12 row bits.
NR
Row bits
00
11
01
12
10
13
11
14
• CAS: CAS Latency
The reset value is 2 cycles.
cas
DDR-SDRAM Cas Latency SDR-SDRAM Cas Latency
000
Reserved
Reserved
001
Reserved
Reserved
010
2
2
247
6264C–CAP–24-Mar-09
cas
DDR-SDRAM Cas Latency SDR-SDRAM Cas Latency
011
3
3
100
Reserved
Reserved
101
Reserved
Reserved
110
2.5
Reserved
111
Reserved
Reserved
• DLL: Reset DLL
Reset value is 0.
This field defines the value of Reset DLL.
0: Disable DLL reset
1: Enable DLL reset
This value is used during the power-up sequence. This field is found only in DDR-SDRAM devices.
• DIC/DS: Output Driver Impedance Control
Reset value is 0.
This field defines the output drive strength.
0: Normal driver strength
1: Weak driver strength
This value is used during the power-up sequence. This parameter is found in the datasheet as DIC or DS.
This field is found only in DDR-SDRAM devices.
248
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
24.6.4
Name:
DDRSDRC Timing 0 Parameter Register
DDRSDRC_T0PR
Address:
0xFFFFE60C
Access:
Read-write
Reset:
See Table 24-8
31
30
29
28
TMRD
23
22
21
20
27
26
25
24
–
–
–
TWTR
19
18
17
16
9
8
1
0
TRRD
15
14
TRP
13
12
11
10
TRC
7
6
TWR
5
TRCD
4
3
2
TRAS
• TRAS: Active to Precharge Delay
Reset Value is 5 cycles.
This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of
cycles is between 0 and 15.
• TRCD: Row to Column Delay
Reset Value is 2 cycles.
This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of
cycles is between 0 and 15.
• TWR: Write Recovery Delay
Reset value is 2.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 1 and 15.
• TRC: Row Cycle Delay
Reset value is 7 cycles.
This field defines the delay between an Activate command and Refresh command in number of cycles. Number of cycles is
between 0 and 15
• TRP: Row Precharge Delay
Reset Value is 2 cycles.
This field defines the delay between a Precharge Command and another command in number of cycles. Number of cycles
is between 0 and 15.
• TRRD Active bankA to Active bankB
Reset value is 2.
249
6264C–CAP–24-Mar-09
This field defines the delay between an Active command in BankA and an active command in bankB in number of cycles.
Number of cycles is between 1 and 15.
• TWTR: Internal Write to Read Delay
Reset value is 0.
This field defines the internal write to read command Time in number of cycles. Number of cycles is between 1 and 2.
• TMRD: Load Mode Register Command to Active or Refresh Command
Reset Value is 2 cycles.
This field defines the delay between an Load mode register command and an active or refresh command in number of
cycles. Number of cycles is between 0 and 15.
250
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
24.6.5
Name:
DDRSDRC Timing 1 Parameter Register
DDRSDRC_T1PR
Address:
0xFFFFE610
Access:
Read-write
Reset:
See Table 24-8
31
30
29
28
–
–
–
–
23
22
21
20
27
26
25
24
TXP
19
18
17
16
11
10
9
8
2
1
0
TXSRD
15
14
13
12
TXSNR
7
6
5
–
–
–
4
3
TRFC
• TRFC: Row Cycle Delay
Reset Value is 8 cycles.
This field defines the delay between a Refresh and an Activate command or Refresh command in number of cycles. Number of cycles is between 0 and 31
• TXSNR: Exit Self Refresh Delay to Non Read Command
Reset Value is 8 cycles.
This field defines the delay between cke set high and a non Read Command in number of cycles. Number of cycles is
between 0 and 15. This field is used for SDR-SDRAM and DDR-SDRAM devices. In the case of SDR-SDRAM devices and
low-power DDR-SDRAM, this field is equivalent to TXSR timing.
• TXSRD: Exit Self Refresh Delay to Read Command
Reset Value is C8.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 255 cycles.This field is unique to DDR-SDRAM devices.
• TXP: Exit Power-down Delay to First Command
Reset Value is 3.
This field defines the delay between cke set high and a Valid Command in number of cycles. Number of cycles is between
0 and 15 cycles. This field is unique to low-power DDR-SDRAM devices.
251
6264C–CAP–24-Mar-09
24.6.6
Name:
DDRSDRC Low-power Register
DDRSDRC_LPR
Address:
0xFFFFE618
Access:
Read-write
Reset:
See Table 24-8
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
–
–
7
6
–
TIMEOUT
5
DS
4
3
PASR
8
TCR
2
CLK_FR
1
0
LPCB
• LPCB: Low-power Command Bit
Reset value is “00”.
00: Low-power Feature is inhibited: no power-down, self refresh and Deep power mode are issued to the SDRAM device.
01: The DDRSDRC issues a Self Refresh Command to the SDRAM device, the clock(s) is/are de-activated and the CKE
signal is set low. The SDRAM device leaves the self refresh mode when accessed and enters it after the access.
10: The DDRSDRC issues a Power-down Command to the SDRAM device after each access, the CKE signal is set low.
The SDRAM device leaves the power-down mode when accessed and enters it after the access.
11: The DDRSDRC issues a Deep Power-down Command to the low-power SDRAM device.This mode is unique to lowpower SDRAM devices.
• CLK_FR: Clock Frozen Command Bit
Reset value is “0”.
This field sets the clock low during power-down mode or deep power-down mode. Some SDRAM devices do not support
freezing the clock during power-down mode or deep power-down mode. Refer to the SDRAM device datasheet for details
on this.
1: Clock(s) is/are frozen.
0: Clock(s) is/are not frozen.
• PASR: Partial Array Self Refresh
Reset value is “0”.
This field is unique to low-power SDRAM. It is used to specify whether only one quarter, one half or all banks of the
SDRAM array are enabled. Disabled banks are not refreshed in self refresh mode.
The values of this field are dependant on low-power SDRAM devices.
After the initialization sequence, as soon as PASR field is modified and self refresh mode is activated, Extended Mode
Register is accessed automatically and PASR bits are updated before entering self refresh mode.
252
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• TCR: Temperature Compensated Self Refresh
Reset value is “0”.
This field is unique to low-power SDRAM. It is used to program the refresh interval during self refresh mode, depending
on the case temperature of the low-power SDRAM.
The values of this field are dependent on low-power SDRAM devices.
After the initialization sequence, as soon as TCR field is modified and self refresh mode is activated, Extended Mode Register is accessed automatically and TCR bits are updated before entering in self refresh mode.
• DS: Drive Strength
Reset value is “0”.
This field is unique to low-power SDRAM. It selects the driver strength of SDRAM output.
After the initialization sequence, as soon as DS field is modified and self refresh mode is activated, Extended Mode Register is accessed automatically and DS bits are updated before entering self refresh mode.
• TIMEOUT
Reset value is “00”.
This field defines when low-power mode is enabled.
00
The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer.
01
The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer.
10
The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer.
11
Reserved
253
6264C–CAP–24-Mar-09
24.6.7
Name:
DDRSDRC Memory Device Register
DDRSDRC_MD
Address:
0xFFFFE61C
Access:
Read-write
Reset:
See Table 24-8
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
–
–
–
DBW
–
–
0
MD
• MD Memory Device
Indicates the type of memory used.
Reset value is for SDR-SDRAM device.
00: SDR-SDRAM
01: Low-power SDR-SDRAM 1
10: DDR-SDRAM
11: Low-power DDR-SDRAM
• DBW Data Bus Width
Reset value is 16 bits.
0: Data bus width is 32 bits (reserved for SDR-SDRAM device).
1: Data bus width is 16 bits.
254
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
24.6.8
Name:
DDRSDRC DLL Information
DDRSDRC_DLL
Address:
0xFFFFE620
Access:
Read
Reset:
See Table 24-8
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
SDCVAL
23
22
21
20
SDVAL
15
14
13
12
MDVAL
7
6
5
4
3
2
1
0
–
–
SDERF
SDCUDF
SDCOVF
MDOVF
MDDEC
MDINC
The DLL logic is internally used by the controller in order to delay DQS inputs.This is necessary to center the strobe time
and the data valid window.
• MDINC: DLL Master Delay Increment
0: The DLL is not incrementing the Master delay counter.
1: The DLL is incrementing the Master delay counter.
• MDDEC: DLL Master Delay Decrement
0: The DLL is not decrementing the Master delay counter.
1: The DLL is decrementing the Master delay counter.
• MDOVF: DLL Master Delay Overflow Flag
0: The Master delay counter has not reached its maximum value, or the Master is not locked yet.
1: The Master delay counter has reached its maximum value, the Master delay counter increment is stopped and the DLL
forces the Master lock. If this flag is set, it means the DDRSDRC clock frequency is too low compared to Master delay line
number of elements.
• SDCOVF: DLL Slave Delay Correction Overflow Flag.
0: Due to the correction, the Slave delay counter has not reached its maximum value, or the Slave is not locked yet.
1: Due to the correction, the Slave delay counter has reached its maximum value, the correction is not optimal because it is
not applied entirely.
• SDCUDF: DLL Slave Delay Correction Underflow Flag
0: Due to the correction, the Slave delay counter has not reached its minimum value, or the Slave is not locked yet.
1: Due to the correction, the Slave delay counter has reached its minimum value, the correction is not optimal because it
has not been entirely applied.
255
6264C–CAP–24-Mar-09
• SDERF: DLL Slave Delay Correction Error Flag
0: The DLL has succeeded in computing the Slave delay correction, or the Slave is not locked yet.
1: The DLL has not succeeded in computing the Slave delay correction.
• MDVAL: DLL Master Delay Value
Value of the Master delay counter.
• SDVAL: DLL Slave Delay Value
Value of the Slave delay counter.
• SDCVAL: DLL Slave Delay Correction Value
Value of the correction applied to the Slave delay.
256
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
25. Burst Cellular RAM Controller (BCRAMC)
25.1
Description
The Burst Cellular RAM Controller (BCRAMC) is a synchronous pseudo-static RAM memory
controller, it supports Cellular RAM device version 1.0, 1.5 and 2.0.
The BCRAMC extends the memory capabilities of a chip by providing the interface to an external
16- or 32-bit Cellular RAM device. The page size support ranges from 64 to 512. It supports
byte, half-word and word accesses.
The BCRAMC supports continuous read or write burst. It supports a latency of 2, 3 for Cellular
RAM version 1.0 and a latency of 2, 3, 4, 5, 6 for Cellular RAM version 1.5 and 2.0 and optimizes
the read/write access depending on the frequency.
Standby and deep power down modes minimize power consumption on the Cellular RAM
device.
The BCRAMC user interface is compliant with the ARM Advanced Peripheral Bus (APB rev2).
257
6264C–CAP–24-Mar-09
25.2
BCRAMC Block Diagram
Figure 25-1. BCRAMC Block Diagram
BCRAMC
APB_LOW_POWER
APB
APB Interface
Asynchronous Timing
Management
Power Management
Control
AHB
Memory Controller Signal Management
OWAIT
Cellular RAM Device
Addr
Power Management
HWDATA
Data
HRDATA
258
Data Management
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
25.3
Product Dependencies
25.3.1
Cellular RAM Initialization
The Cellular RAM devices are initialized by the following sequence:
5. Minimum pause of 150 µs is provided to precede any signal toggle.
6. The Cellular RAM memory type must be set in the BCRAMC Memory Device Register.
7. Temperature-compensated self refresh (TCSR) and partial array self refresh (PASR)
must be set in the BCRAMC Low Power register.
8. Asynchronous timings (TCKA, TCRE) must be set in the BCRAMC Timing Register.
9. Cellular RAM features must be set in the HBCRAMC Configuration Register:
– number rows, latency, drive strength (DS), the data bus width and cram_enabled bit
must be high.
Perform a write to the Cellular RAM device and the Bus Configuration Register (BCR) and
Refresh Configuration Register (RCR) are programmed automatically.
After initialization, the Cellular RAM devices are fully functional.
Figure 25-2. Initialization Sequence
A[27:0]
BCADV
BCCS
BCCK
BCCRE
D[31:0]
BCOE
BCWE
BCOWAIT
tCRES
tCRES
tCEW
Write Bus Configuration
Register
259
tCKA
tCEW
Write Refresh Configuration
Register
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
25.4
25.4.1
Functional Description
BCRAMC Overview
The BCRAMC is a synchronous cellular RAM controller, it does not support asynchronous
access and mode page. Some version 1.0 devices which support only these features cannot be
driven.
The BCRAMC drives 16-bit memory devices but, in this mode, it does not support byte
read/write bursts. All byte burst accesses are treated as a single access because BCRAMC is
set in continuous burst where16-bit data are accessed sequentially. To support byte read/write
bursts, complex logic should be added to transform byte burst to half-word burst.
The BCRAMC drives 32-bit memory devices but, in this mode, it does not support byte/half-word
read/write bursts. All byte or half-word burst accesses are treated as single access because
BCRAMC is set in continuous burst where 32-bit data are accessed sequentially. To support
byte/half-word read/write bursts, complex logic should be added to transform byte/half-word
bursts to word bursts.
The BCRAMC supports busy transfer. This kind of access is treated as early burst termination.
The controller performances are decreased because after a busy transfer, a new initial burst
operation (adv is low) will be generated.
25.4.2
BCRAMC Write Cycle
The BCRAMC provides burst access or single access.
The Cellular RAM device is programmed with a continuous burst length.
The latency from write command to data input is a function of the Cellular RAM device.
Version 1.0 write latency is equal to the latency programmed in the bus configuration register
during the initialization sequence or in the worst case, it is equal to the refresh collision delay.
With version 1.0, the BCRAMC must monitor owait signal to detect any conflict of refresh collision during write accesses. The write latency is not constant.
In the case of version 1.5 and 2.0, write latency is equal to the latency programmed in the bus
configuration register. Write latency always uses fixed latency. The BCRAMC does not monitor
owait signal during write accesses.
To initiate a single access, the BCRAMC generates an initial burst write command. To comply
with Cellular RAM timing parameters, additional clock cycles are inserted to check programmed
latency. In the case of Cellular RAM version 1.0, the owait signal is monitored to detect a refresh
collision. As soon as owait signal is high, data is accepted into the device and write access is
achieved. In the case of Cellular RAM version 1.5 and 2.0, owait signal is not monitored and
write access is performed as soon as latency is checked.
As the burst length is fixed to continuous, in the case of single access, it has to stop the burst
else invalid values can be written. To interrupt the write operation, chip select (CS) must be set
to 1 or an initial burst read/write command can be initiated to interrupt current access if the next
access is a Cellular RAM access.
To initiate a burst access, the BCRAMC uses the transfer type signal provided by the master
requesting the access. If the next access is a sequential write access, writing to the Cellular
RAM device is carried out. If the next access is a write sequential access, but the current access
is to a boundary page, then an automatic page break is inserted and the Cellular RAM controller
generates an initial burst write command to finish access. To comply with Cellular RAM timing
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parameters, additional clock cycles are inserted to check programmed latency. A single access
owait signal is monitored, or not, in function of the Cellular RAM version.
Write accesses to the Cellular RAM are burst oriented, the programmed burst length is continuous burst. This feature makes it possible to start at a specified address and burst through the
entire memory. It is very useful for incrementing bursts (INCR/INCR4/INCR8/INCR16), as soon
as the burst command init (latch burst start address) is initiated and latency is checked, at each
BCCK rising a data is written.
In the case of a wrapping burst (WRAP4/WRAP8/WRAP16), the addresses can cross the
boundary of the current transfer. For example, when a transfer (WRAP4) starts to address 0x0C,
the next access will be 0x00, but the burst length being programmed to continuous burst in the
next access should be 0x10, the burst does not wrap automatically. The BCRAMC takes
account of this feature and in the case of a transfer starting from address 0x04/0x08/0x0C, two
initial burst write commands will be issued to wrap when boundary is reached. The last initial
burst write command will be interrupted by a BCCS (chip select) set to high or by another initial
burst read/write command to do the next access in the Cellular RAM device, if an access is
pending.
Figure 25-3. Single Write Access, No Refresh Collision
A[27:0]
BCADV
BCCS
BCCK
BCCRE
DO
D[31:0]
D1
BCOE
BCWE
BCOWAIT
Latency = 3
261
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6264C–CAP–24-Mar-09
Figure 25-4. Single Write Access with Refresh Collision
A[27:0]
BCADV
BCCS
BCCK
BCCRE
D0
D[31:0]
D1
BCOE
BCWE
BCOWAIT
Latency = 5
Figure 25-5. Burst Write Access with No Refresh Collision
A[27:0]
BCADV
BCCS
BCCK
BCCRE
D[31:0]
D0
D1
D2
D3
BCOE
BCWE
BCOWAIT
Latency = 3
262
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6264C–CAP–24-Mar-09
Figure 25-6. Four Beat Wrapping Burst With Address Starting at 0x0C
A[27:0]
BCADV
BCCS
BCCK
BCCRE
D0
D[31:0]
D1
D2
D3
BCOE
BCWE
BCOWAIT
Latency = 5
Latency = 3
Refresh Collision
No Refresh Collision
Figure 25-7. Write Command Followed by a Read Command then Interrupt Write Burst
A[27:0]
BCADV
BCCS
BCCK
BCCRE
D[31:0]
D0
D1
D2
D0
D3
D1
D2
D3
BCOE
BCWE
BCOWAIT
25.4.3
Latency = 5
Latency = 3
Refresh collision
No Refresh collision
BCRAMC Read Cycle
The BCRAMC allows burst access or single access.
The Cellular RAM device is programmed with a continuous burst length.
The latency from read command to data output is dependant on the Cellular RAM version. The
owait signal is monitored to detect any conflict of refresh collision.
To initiate a single access, the BCRAMC generates an initial burst read command. To comply
with Cellular RAM timing parameters, additional clock cycles are inserted to check programmed
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latency. The BCRAMC supports latency value which is a function of the Cellular RAM version.
The owait signal is monitored to detect a refresh collision. As soon as owait signal is high, data is
transferred out of the device and first data can be read. As the burst length is fixed to continuous, in the case of single access, it has to stop the burst else invalid values could be read. To
interrupt the read operation, BCCS (chip select) must be set to 1 or an initial burst read/write
command can be initiated to interrupt current access if the next access is a Cellular RAM
access.
To initiate a burst access, the BCRAMC uses the transfer type signals provided by the master
requesting the access. If the next access is a sequential read access, reading to the Cellular
RAM device is carried out. If the next access is a read sequential access, but the current access
is to a boundary page, then an automatic page break is inserted and the Cellular RAM controller
generates an initial burst read command to finish the access. To comply with Cellular RAM timing parameters, additional clock cycles are inserted to check programmed latency. Like a single
access, the owait signal is monitored to detect refresh collision.
The BCRAMC can anticipate 1 or 2 read accesses. In this case tdf_fr_cram is generated to alert
the EBI that data is floating on the bus and that the next external access will be delayed. In the
case of a burst of specified length, accesses are not anticipated, but, if the burst is broken (i.e.,
border, busy mode...)the next access will be treated as an incrementing burst of unspecified
length, and the BCRAMC can anticipate 1 or 2 read accesses. In this case tdf_from_cram is
generated to alert the EBI that data is floating on the bus and that the next external access will
be delayed.
Read accesses to the Cellular RAM are burst oriented, the burst length programmed is continuous burst. This feature makes it possible to start at a specified address and burst through the
entire memory. It is very useful for incrementing burst (INCR/INCR4/INCR8/INCR16), as soon
as the burst command init (latch burst start address) is initiated and latency is checked, at each
BCCK rising a data is read.
In the case of wrapping burst (WRAP4/WRAP8/WRAP16), the addresses can cross the boundary of the current transfer. For example, when a transfer (WRAP4) starts at address 0x0C, the
next access will be 0x00, but for the burst length being programmed to continuous burst, the
next access should be 0x10. The burst does not wrap automatically. The BCRAMC takes this
feature into account and in the case of a transfer starting at address 0x04/0x08/0x0C, two initial
burst read commands will be issued to wrap when the boundary is reached. The last initial burst
read command will be interrupted by BCCS set to high or by another initial burst read/write command to do the next access in the Cellular RAM device if an access is pending. tdf_fr_cram will
be generated to alert the EBI that data is floating on the bus.
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Figure 25-8. Single Read Access with Refresh Collision
A[27:0]
BCADV
BCCS
BCCK
BCCRE
D[31:0]
D0
BCOE
BCWE
BCOWAIT
Latency = 5
Refresh Collision
Unwanted Data
Figure 25-9. Single Read Access with No Refresh Collision
A[27:0]
BCADV
BCCS
BCCK
BCCRE
D[31:0]
D0
BCOE
BCWE
BCOWAIT
Latency = 3
Refresh Collision
265
Unwanted Data
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 25-10. Burst Read Access with No Refresh Collision
A[27:0]
BCADV
BCCS
BCCK
BCCRE
D[31:0]
D0
D1
D2
D3
BCOE
BCWE
BCOWAIT
Latency = 3
No Refresh Collision
Figure 25-11. Four Beat Wrapping Burst with Address Starting at 0x0C
A[27:0]
BCADV
BCCS
BCCK
BCCRE
D0
D[31:0]
D1
D2
D3
BCOE
BCWE
BCOWAIT
Latency = 5
Refresh Collision
266
Latency = 3
Unwanted Data
No Refresh Collision
Unwanted Data
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
25.4.4
Power Management
25.4.4.1
Standby Mode
This mode is activated by programming low power command bits (LPCB) to 1 (See “LPCB: Low
Power Command Bit” on page 273.)
Standby mode is used when there is no access to the Cellular RAM device. In this mode, power
consumption is reduced, BCCK pin is low and ce pin is high.
When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from external influence.
The BCRAMC leaves standby mode as soon as the Cellular RAM device is selected and returns
to standby mode as soon as the Cellular RAM device is no longer selected.
Figure 25-12. Standby Mode Entry/Exit
A[27:0]
BCADV
BCCS
BCCK
BCCRE
D[31:0]
BCOE
BCWE
BCOWAIT
Enter Standby Mode
25.4.4.2
Exit Standby Mode
Deep Power Down Mode (DPD)
This mode is selected by programming the LPCB field to 2 in the BCRAMC Low Power Register
(See “LPCB: Low Power Command Bit” on page 273.). As soon as LPCB field is programmed
and no access in Cellular RAM is pending, the Refresh Configuration Register is automatically
accessed and DPD mode is enabled.
When this mode is activated, all internal voltage generators inside the Cellular RAM are stopped
and all data is lost. Only the register values of the Bus Configuration Register and Refresh Configuration Register are kept valid during deep power down mode.
To leave this mode, the LPCB field must be programmed to 0 in the BCRAMC Low Power Register. As soon as the LPCB field is programmed and Cellular RAM access is pending, the
Refresh Configuration Register is automatically accessed and the DPD bit is disabled.
No command should be applied during 150 µs, before re-entry in idle or standby mode.
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25.4.4.3
Temperature Compensated Refresh (TCR) or Temperature Compensated Self-refresh (TCSR)
This feature is activated by adjusting Temperature Compensated Refresh bits (TCR) in
BCRAMC Low Power Register (See “TCR_TCSR: Temperature Compensated Refresh or Temperature Compensated Self-refresh” on page 273.).
This feature allows to adjust the refresh period in function of different temperatures.
Some Cellular RAM devices include an on chip temperature sensor that automatically adjusts
the refresh period according to operating temperature, in this case the value of TCR is set to 0.
On the contrary, some Cellular RAM devices do not include an internal sensor. In this case, TCR
values can be changed by modifying the TCR bits in the BCRAMC Low Power Register the
Refresh Configuration Register is automatically accessed and TCR value is adjusted before
doing the next access in the Cellular RAM device.
25.4.4.4
Partial Array Refresh (PAR)
This feature is activated by adjusting Partial Array Refresh bits (PAR) in the BCRAMC Low
Power Register (See “PAR: Partial Array Refresh” on page 273.).
PAR can restrict the refresh operation to a portion of the total memory area. Data stored in
addresses not receiving refresh will become corrupted.
As soon as TCR field is modified, the Refresh Configuration Register and theTCR bit are automatically updated before doing the next access in the Cellular RAM device.
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25.5
Burst Cellular RAM Controller (BCRAMC) User Interface
The User interface is connected to the APB bus. The BCRAMC is programmed using the registers listed in Table 25-1.
Table 25-1.
Offset
BCRAMC Memory Map
Register
Name
Access
Reset
0x00
BCRAMC Configuration Register
BCRAMC_CR
Read-write
0x00000130
0x04
BCRAMC Timing Register
BCRAMC_TR
Read-write
0x004
0x0C
BCRAMC Low Power Register
BCRAMC_LPR
Read-write
0x0
0x10
BCRAMC Memory Device Register
BCRAMC_MDR
Read-write
0x0
0x14 - 0xE8
Reserved
0xEC
BCRAMC Address Size Register
BCRAMC_ADDRSIZE
Read-only
0x-(2)
0xF0
BCRAMC IP Name 1
BCRAMC_IPNAME1
Read-only
“HBCR”
0xF4
BCRAMC IP Name 2
BCRAMC_IPNAME2
Read-only
“AMC1“
0xF8
BCRAMC Features Registers
BCRAMC_FEATURES
Read-only
0x
Notes:
1. Values in the Version Register vary with the version of the IP block implementation.
2. Values in the BCRAMC_ADDRSIZE register are product dependent. For more information, see “BCRAMC ADDRSIZE Register” on page 275.
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25.5.1
Name:
BCRAMC Configuration Register
BCRAMC_CR
Address:
0xFFFFE400
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
VAR_FIX_LAT
23
22
21
20
19
18
17
16
–
–
–
–
–
ADDRDATA_MUX
15
14
13
12
11
10
9
8
–
–
BOUNDARY_WORD
–
–
–
DBW
7
6
5
3
2
1
0
–
–
–
CRAM_EN
DS
–
4
LM
• CRAM_EN: BCRAMC Enabled
The Reset Value is 0.
This field enables or disables the BCRAMC. As soon as Cellular RAM is enabled, power up sequence can be done. When
cram_en bit is low then BCRAMC is in idle mode and the owait signal is masked. When this bit is disabled during functional
mode, an initialization procedure will be performed to again access the Cellular RAM device.
• LM: Latency Mode
The Reset Value is 3 Cycles.
LM
Latency Cycles
Cellular RAM Version
000
Reserved
Reserved
001
Reserved
Reserved
010
2
1.0/1.5/2.0
011
3
1.0/1.5/2.0
100
4
1.5/2.0
101
5
1.5/2.0
110
6
1.5/2.0
111
Reserved
Reserved
• DBW: Data Bus Width
0: Data bus width is 32 bits.
1: Data bus width is 16 bits.
• BOUNDARY_WORD: Number of Words in Row
The Reset Value is 64 words (word = 16 or 32 bits) in row.
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This field manages the row boundaries. Some Cellular RAM providers do not provide the number of words in row in their
devices, in this case the reset value is used.
Boundary Word
Number of Words in Row
00
64
01
128
10
256
11
512
• ADDRDATA_MUX
Reset Value is 0.
This field is used to multiplex the address and data bus. This feature is reserved for Cellular RAM version 2.0. In the case
of Cellular RAM version 1.0, 1.5 the value is 0.
ADDRDTAT_MUX
0
address data bus not multiplexed
1
address data bus multiplexed
• DS: Drive Strength
Reset Value is 0.
This field is used to select the driver strength of Cellular RAM output.
The table below gives an example and can change with the Cellular RAM provider.
DS
Drive Strength
00
full
01
1/2
10
1/4
11
reserved
• VAR_FIX_LAT: Variable Latency or Fixed Latency
The Reset Value is 0, variable latency.
VAR_FIX_LAT
0
variable latency
1
fixed latency
This feature is reserved for Cellular RAM version 1.5/2.0. In the case of Cellular RAM version 1.0 the value is 0.
In the variable latency mode, the latency programmed in the bus configuration register is not guaranteed, it is maintained
only if there is no refresh collision. The wait signal must be monitored.
In the fixed latency mode, the first data outputs conform to the fixed timing, including refresh collision. The wait signal can
be unmonitored. This mode is of benefit for applications with low clock frequency.
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25.5.2
Name:
BCRAMC Timing Register
BCRAMC_TR
Address:
0xFFFFE404
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
7
6
5
1
0
–
–
4
TCKA
3
TCRES
2
TCW
• TCW: Chip Enable to End of Write.
Reset value is 4.
This field defines the time between the falling edge of BCCS and the rising edge of BCWE in number of cycles. The Number of cycles is equal to TCW + 4. This time is used during initialization sequence since accesses to configuration registers
are done in asynchronous mode.
• TCRES: Control Register Enable Setup
Reset value is 0.
This field defines the time between the rising edge of cre and the falling edge of BCWE in number of cycles. The Number of
cycles is equal to TCRES + 1. This time is used during initialization sequence since accesses to configuration registers are
done in asynchronous mode.
• TCKA: BCWE High to BCCK Valid
Reset value is 0.
This field defines the time between the BCWE rising edge and BCCK switch on, in number of cycles. The number of cycles
is equal to TCKA + 2.5.
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25.5.3
Name:
BCRAMC Low Power Register
BCRAMC_LPR
Address:
0xFFFFE40C
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
–
–
–
–
–
–
7
6
5
3
2
–
–
4
TCR_TCSR
–
8
LPCB
1
0
PAR
• PAR: Partial Array Refresh
PAR restricts the refresh operation to a portion of the total memory array.
The table below gives an example of PAR but can change with the Cellular RAM provider.
PAR
Refresh Coverage
000
Full array
001
Bottom 1/2 array
010
Bottom 1/4 array
011
Bottom 1/8 array
100
None of 2 array
101
Top 1/2 array
110
Top 1/2 array
111
Top 1/2 array
• TCR_TCSR: Temperature Compensated Refresh or Temperature Compensated Self-refresh
TCR or TCSR refresh the device in function of difference in temperature.
The table below gives an example of TCR or TCSR but can change with the Cellular RAM provider.
TCR or TCSR
Temperature
11
+85° C
00
Internal sensor or +70° C
01
+45° C
10
+15° C
• LPCB: Low Power Command Bit
00: Low Power Feature is inhibited: Standby and Deep Power mode are not issued to the Cellular RAM device.
01: The Cellular RAM device Standby mode is enabled.
10: Deep Power Down mode is enabled.
11: reserved
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25.5.4
Name:
BCRAMC Memory Device Register
BCRAMC_MDR
Address:
0xFFFFE410
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
–
–
–
–
–
–
0
MD
• MD Memory Device
Gives the type of memory used.
00: Cellular RAM Version 1.0
01: Cellular RAM Version 1.5
10: Cellular RAM Version 2.0
11: reserved
274
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25.5.5
Name:
BCRAMC ADDRSIZE Register
BCRAMC_ADDRSIZE
Address:
0xFFFFE4EC
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
3
2
1
0
ADDRSIZE
7
6
5
4
ADDRSIZE
• ADDRSIZE
Reserved. Value subject to change. No functionality associated. The returned value corresponds to the number of bytes
mapped into the BCRAMC address space. It could be an integer in range of 16384, 8192, 4096, 2048, 1024, 512, 256.
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25.5.6
Name:
BCRAMC Name1 Register
BCRAMC_IPNAME1
Access:
31
Read-only
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
IPNAME
23
22
21
20
IPNAME
15
14
13
12
IPNAME
7
6
5
4
IPNAME
• IPNAME
Reserved. Value subject to change. No functionality associated. The name in ASCII format is “HBCR”.
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AT91CAP9S500A/AT91CAP9S250A
25.5.7
Name:
BCRAMC Name2 Register
BCRAMC_IPNAME2
Access:
Read-only
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
IPNAME
23
22
21
20
IPNAME
15
14
13
12
IPNAME
7
6
5
4
IPNAME
• IPNAME
Reserved. Value subject to change. No functionality associated. The name in ASCII format is “AMC1”.
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25.5.8
Name:
BCRAMC Features Register
BCRAMC_FEATURES
Address:
0xFFFFE4F8
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
Reserved
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26. Error Corrected Code (ECC) Controller
26.1
Description
NAND Flash/SmartMedia devices contain by default invalid blocks which have one or more
invalid bits. Over the NAND Flash/SmartMedia lifetime, additional invalid blocks may occur
which can be detected/corrected by ECC code.
The ECC Controller is a mechanism that encodes data in a manner that makes possible the
identification and correction of certain errors in data. The ECC controller is capable of single bit
error correction and 2-bit random detection. When NAND Flash/SmartMedia have more than 2
bits of errors, the data cannot be corrected.
The ECC user interface is compliant with the ARM Advanced Peripheral Bus (APB rev2).
26.2
Block Diagram
Figure 26-1. Block Diagram
NAND Flash
Static
Memory
Controller
SmartMedia
Logic
ECC
Controller
Ctrl/ECC Algorithm
User Interface
APB
26.3
Functional Description
A page in NAND Flash and SmartMedia memories contains an area for main data and an additional area used for redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page
size corresponds to the number of words in the main area plus the number of words in the extra
area used for redundancy.
Over time, some memory locations may fail to program or erase properly. In order to ensure that
data is stored properly over the life of the NAND Flash device, NAND Flash providers recom-
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mend to utilize either 1 ECC per 256 bytes of data, 1 ECC per 512 bytes of data or 1 ECC for all
of the page.
The only configurations required for ECC are the NAND Flash or the SmartMedia page size
(528/2112/4224) and the type of correction wanted (1 ECC for all the page/1 ECC per 256 bytes
of data /1 ECC per 512 bytes of data). Page size is configured setting the PAGESIZE field in the
ECC Mode Register (ECC_MR). Type of correction is configured setting the TYPECORRECT
field in the ECC Mode Register (ECC_MR).
ECC is automatically computed as soon as a read (00h)/write (80h) command to the NAND
Flash or the SmartMedia is detected. Read and write access must start at a page boundary.
ECC results are available as soon as the counter reaches the end of the main area. Values in
the ECC Parity Registers (ECC_PR0 to ECC_PR15) are then valid and locked until a new start
condition occurs (read/write command followed by address cycles).
26.3.1
Write Access
Once the Flash memory page is written, the computed ECC codes are available in the ECC Parity (ECC_PR0 to ECC_PR15) registers. The ECC code values must be written by the software
application in the extra area used for redundancy. The number of write accesses in the extra
area is a function of the value of the type of correction field. For example, for 1 ECC per 256
bytes of data for a page of 512 bytes, only the values of ECC_PR0 and ECC_PR1 must be written by the software application. Other registers are meaningless.
26.3.2
Read Access
After reading the whole data in the main area, the application must perform read accesses to the
extra area where ECC code has been previously stored. Error detection is automatically performed by the ECC controller. Please note that it is mandatory to read consecutively the entire
main area and the locations where Parity and NParity values have been previously stored to let
the ECC controller perform error detection.
The application can check the ECC Status Registers (ECC_SR1/ECC_SR2) for any detected
errors. It is up to the application to correct any detected error. ECC computation can detect four
different circumstances:
• No error: XOR between the ECC computation and the ECC code stored at the end of the
NAND Flash or SmartMedia page is equal to 0. No error flags in the ECC Status Registers
(ECC_SR1/ECC_SR2).
• Recoverable error: Only the RECERR flags in the ECC Status registers
(ECC_SR1/ECC_SR2) are set. The corrupted word offset in the read page is defined by the
WORDADDR field in the ECC Parity Registers (ECC_PR0 to ECC_PR15). The corrupted bit
position in the concerned word is defined in the BITADDR field in the ECC Parity Registers
(ECC_PR0 to ECC_PR15).
• ECC error: The ECCERR flag in the ECC Status Registers (ECC_SR1/ECC_SR2) are set.
An error has been detected in the ECC code stored in the Flash memory. The position of the
corrupted bit can be found by the application performing an XOR between the Parity and the
NParity contained in the ECC code stored in the Flash memory.
• Non correctable error: The MULERR flag in the ECC Status Registers
(ECC_SR1/ECC_SR2) are set. Several unrecoverable errors have been detected in the
Flash memory page.
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ECC Status Registers, ECC Parity Registers are cleared when a read/write command is
detected or a software reset is performed.
For Single-bit Error Correction and Double-bit Error Detection (SEC-DED) hsiao code is used.
24-bit ECC is generated in order to perform one bit correction per 256 or 512 bytes for pages of
512/2048/4096 8-bit words. 32-bit ECC is generated in order to perform one bit correction per
512/1024/2048/4096 8- or 16-bit words.They are generated according to the schemes shown in
Figure 26-2 and Figure 26-3.
Figure 26-2. Parity Generation for 512/1024/2048/4096 8-bit Words
1st byte
2nd byte
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
P8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
P8'
3rd byte
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
P8
4 th byte
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
P8'
(page size -3 )th byte
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
P8
(page size -2 )th byte
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
P8'
(page size -1 )th byte
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
P8
Page size th byte
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
P8'
P1
P1'
P1
P2
P1'
P1
P2
P2'
P4
Page size
Page size
Page size
Page size
= 512
= 1024
= 2048
= 4096
P1'
P16
P32
PX
P16'
P16
P32
PX'
P16'
P1'
P1
P2'
P4'
P1=bit7(+)bit5(+)bit3(+)bit1(+)P1
P2=bit7(+)bit6(+)bit3(+)bit2(+)P2
P4=bit7(+)bit6(+)bit5(+)bit4(+)P4
P1'=bit6(+)bit4(+)bit2(+)bit0(+)P1'
P2'=bit5(+)bit4(+)bit1(+)bit0(+)P2'
P4'=bit7(+)bit6(+)bit5(+)bit4(+)P4'
Px = 2048
Px = 4096
Px = 8192
Px = 16384
To calculate P8’ to PX’ and P8 to PX, apply the algorithm that follows.
Page size = 2n
for i =0 to n
begin
for (j = 0 to page_size_byte)
begin
if(j[i] ==1)
P[2i+3]=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
bit2(+)bit1(+)bit0(+)P[2i+3]
else
P[2i+3]’=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
bit2(+)bit1(+)bit0(+)P[2i+3]'
end
end
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(Page size -3 )th word
(Page size -2 )th word
(Page size -1 )th word
Page size th word
3rd word
4th word
1st word
2nd word
Figure 26-3. Parity Generation for 512/1024/2048/4096 16-bit Words
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To calculate P8’ to PX’ and P8 to PX, apply the algorithm that follows.
Page size = 2n
for i =0 to n
begin
for (j = 0 to page_size_word)
begin
if(j[i] ==1)
P[2i+3]= bit15(+)bit14(+)bit13(+)bit12(+)
bit11(+)bit10(+)bit9(+)bit8(+)
bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
bit2(+)bit1(+)bit0(+)P[2n+3]
else
P[2i+3]’=bit15(+)bit14(+)bit13(+)bit12(+)
bit11(+)bit10(+)bit9(+)bit8(+)
bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
bit2(+)bit1(+)bit0(+)P[2i+3]'
end
end
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26.4
Error Corrected Code Controller (ECC) User Interface
Table 26-1.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
ECC Control Register
ECC_CR
Write-only
0x0
0x04
ECC Mode Register
ECC_MR
Read-write
0x0
0x08
ECC Status1 Register
ECC_SR1
Read-only
0x0
0x0C
ECC Parity Register 0
ECC_PR0
Read-only
0x0
0x10
ECC Parity Register 1
ECC_PR1
Read-only
0x0
0x14
ECC Status2 Register
ECC_SR2
Read-only
0x0
0x18
ECC Parity 2
ECC_PR2
Read-only
0x0
0x1C
ECC Parity 3
ECC_PR3
Read-only
0x0
0x20
ECC Parity 4
ECC_PR4
Read-only
0x0
0x24
ECC Parity 5
ECC_PR5
Read-only
0x0
0x28
ECC Parity 6
ECC_PR6
Read-only
0x0
0x2C
ECC Parity 7
ECC_PR7
Read-only
0x0
0x30
ECC Parity 8
ECC_PR8
Read-only
0x0
0x34
ECC Parity 9
ECC_PR9
Read-only
0x0
0x38
ECC Parity 10
ECC_PR10
Read-only
0x0
0x3C
ECC Parity 11
ECC_PR11
Read-only
0x0
0x40
ECC Parity 12
ECC_PR12
Read-only
0x0
0x44
ECC Parity 13
ECC_PR13
Read-only
0x0
0x48
ECC Parity 14
ECC_PR14
Read-only
0x0
0x4C
ECC Parity 15
ECC_PR15
Read-only
0x0
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26.4.1
Name:
ECC Control Register
ECC_CR
Address:
0xFFFFE200
Access:
Write-only
31
–
23
–
15
–
7
–
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
SRST
24
–
16
–
8
–
0
RST
• RST: RESET Parity
Provides reset to current ECC by software.
1: Reset ECC Parity registers
0: No effect
• SRST: Soft Reset
Provides soft reset to ECC block
1: Resets all registers.
0: No effect.
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26.4.2
Name:
ECC Mode Register
ECC_MR
Address:
0xFFFFE204
Access:
Read-write
31
–
23
–
15
–
7
–
30
–
22
–
14
–
6
–
29
28
–
–
21
20
–
–
13
12
–
–
5
4
TYPECORRECT
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
24
–
16
–
8
–
0
PAGESIZE
• PAGESIZE: Page Size
This field defines the page size of the NAND Flash device.
Page Size
Description
00
528 words
01
1056 words
10
2112 words
11
4224 words
A word has a value of 8 bits or 16 bits, depending on the NAND Flash or SmartMedia memory organization.
• TYPECORRECT: Type of Correction
00: 1 bit correction for a page size of 512/1024/2048/4096 bytes.
01: 1 bit correction for 256 bytes of data for a page size of 512/2048/4096 bytes.
10: 1 bit correction for 512 bytes of data for a page size of 512/2048/4096 bytes.
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26.4.3
Name:
ECC Status Register 1
ECC_SR1
Address:
0xFFFFE208
Access:
Read-only
31
–
23
–
15
–
7
–
30
MULERR7
22
MULERR5
14
MULERR3
6
MULERR1
29
ECCERR7
21
ECCERR5
13
ECCERR3
5
ECCERR1
28
RECERR7
20
RECERR5
12
RECERR3
4
RECERR1
27
–
19
–
11
–
3
–
26
MULERR6
18
MULERR4
10
MULERR2
2
MULERR0
25
ECCERR6
17
ECCERR4
9
ECCERR2
1
ECCERR0
24
RECERR6
16
RECERR4
8
RECERR2
0
RECERR0
• RECERR0: Recoverable Error
0 = No Errors Detected.
1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors
were detected.
• ECCERR0: ECC Error
0 = No Errors Detected.
1 = A single bit error occurred in the ECC bytes.
If TYPECORRECT = 0, read both ECC Parity 0 and ECC Parity 1 registers, the error occurred at the location which contains a 1 in the least significant 16 bits; else read ECC Parity 0 register, the error occurred at the location which contains a
1 in the least significant 24 bits.
• MULERR0: Multiple Error
0 = No Multiple Errors Detected.
1 = Multiple Errors Detected.
• RECERR1: Recoverable Error in the page between the 256th and the 511th bytes or the 512th and the 1023rd
bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors
were detected.
• ECCERR1: ECC Error in the page between the 256th and the 511th bytes or the 512th and the 1023rd bytes
Fixed to 0 if TYPECORREC = 0
0 = No Errors Detected.
1 = A single bit error occurred in the ECC bytes.
Read ECC Parity 1 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
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• MULERR1: Multiple Error in the page between the 256th and the 511th bytes or the 512th and the 1023rd bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Multiple Errors Detected.
1 = Multiple Errors Detected.
• RECERR2: Recoverable Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th
bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors
were detected.
• ECCERR2: ECC Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = A single bit error occurred in the ECC bytes.
Read ECC Parity 2 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR2: Multiple Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Multiple Errors Detected.
1 = Multiple Errors Detected.
• RECERR3: Recoverable Error in the page between the 768th and the 1023rd bytes or the 1536th and the 2047th
bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors
were detected.
• ECCERR3: ECC Error in the page between the 768th and the 1023rd bytes or the 1536th and the 2047th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = A single bit error occurred in the ECC bytes.
Read ECC Parity 3 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR3: Multiple Error in the page between the 768th and the 1023rd bytes or the 1536th and the 2047th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Multiple Errors Detected.
1 = Multiple Errors Detected.
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• RECERR4: Recoverable Error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th
bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors
were detected.
• ECCERR4: ECC Error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = A single bit error occurred in the ECC bytes.
Read ECC Parity 4 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR4: Multiple Error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th
bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Multiple Errors Detected.
1 = Multiple Errors Detected.
• RECERR5: Recoverable Error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st
bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors
were detected
• ECCERR5: ECC Error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = A single bit error occurred in the ECC bytes.
Read ECC Parity 5 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR5: Multiple Error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st
bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Multiple Errors Detected.
1 = Multiple Errors Detected.
• RECERR6: Recoverable Error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd
bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
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1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors
were detected.
• ECCERR6: ECC Error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = A single bit error occurred in the ECC bytes.
Read ECC Parity 6 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR6: Multiple Error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd
bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Multiple Errors Detected.
1 = Multiple Errors Detected.
• RECERR7: Recoverable Error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th
bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors
were detected.
• ECCERR7: ECC Error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = A single bit error occurred in the ECC bytes.
Read ECC Parity 7 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR7: Multiple Error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th
bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Multiple Errors Detected.
1 = Multiple Errors Detected.
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26.4.4
Name:
ECC Status Register 2
ECC_SR2
Address:
0xFFFFE214
Access:
Read-only
31
–
23
–
15
–
7
–
30
MULERR15
22
MULERR13
14
MULERR11
6
MULERR9
29
ECCERR15
21
ECCERR13
13
ECCERR11
5
ECCERR9
28
RECERR15
20
RECERR13
12
RECERR11
4
RECERR9
27
–
19
–
11
–
3
–
26
MULERR14
18
MULERR12
10
MULERR10
2
MULERR8
25
ECCERR14
17
ECCERR12
9
ECCERR10
1
ECCERR8
24
RECERR14
16
RECERR12
8
RECERR10
0
RECERR8
• RECERR8: Recoverable Error in the page between the 2048th and the 2303rd bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors
were detected
• ECCERR8: ECC Error in the page between the 2048th and the 2303rd bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = A single bit error occurred in the ECC bytes.
Read ECC Parity 8 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR8: Multiple Error in the page between the 2048th and the 2303rd bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Multiple Errors Detected.
1 = Multiple Errors Detected.
• RECERR9: Recoverable Error in the page between the 2304th and the 2559th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors
were detected.
• ECCERR9: ECC Error in the page between the 2304th and the 2559th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = A single bit error occurred in the ECC bytes.
Read ECC Parity 9 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
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• MULERR9: Multiple Error in the page between the 2304th and the 2559th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Multiple Errors Detected.
1 = Multiple Errors Detected.
• RECERR10: Recoverable Error in the page between the 2560th and the 2815th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors
were detected.
• ECCERR10: ECC Error in the page between the 2560th and the 2815th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = A single bit error occurred in the ECC bytes.
Read ECC Parity 10 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR10: Multiple Error in the page between the 2560th and the 2815th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Multiple Errors Detected.
1 = Multiple Errors Detected.
• RECERR11: Recoverable Error in the page between the 2816th and the 3071st bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors
were detected
• ECCERR11: ECC Error in the page between the 2816th and the 3071st bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = A single bit error occurred in the ECC bytes.
Read ECC Parity 11 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR11: Multiple Error in the page between the 2816th and the 3071st bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Multiple Errors Detected.
1 = Multiple Errors Detected.
• RECERR12: Recoverable Error in the page between the 3072nd and the 3327th bytes
Fixed to 0 if TYPECORREC = 0
0 = No Errors Detected
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1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors
were detected
• ECCERR12: ECC Error in the page between the 3072nd and the 3327th bytes
Fixed to 0 if TYPECORREC = 0
0 = No Errors Detected
1 = A single bit error occurred in the ECC bytes.
Read ECC Parity 12 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR12: Multiple Error in the page between the 3072nd and the 3327th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Multiple Errors Detected.
1 = Multiple Errors Detected.
• RECERR13: Recoverable Error in the page between the 3328th and the 3583rd bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors
were detected.
• ECCERR13: ECC Error in the page between the 3328th and the 3583rd bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = A single bit error occurred in the ECC bytes.
Read ECC Parity 13 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR13: Multiple Error in the page between the 3328th and the 3583rd bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Multiple Errors Detected.
1 = Multiple Errors Detected.
• RECERR14: Recoverable Error in the page between the 3584th and the 3839th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors
were detected.
• ECCERR14: ECC Error in the page between the 3584th and the 3839th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = A single bit error occurred in the ECC bytes.
Read ECC Parity 14 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
293
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• MULERR14: Multiple Error in the page between the 3584th and the 3839th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Multiple Errors Detected.
1 = Multiple Errors Detected.
• RECERR15: Recoverable Error in the page between the 3840th and the 4095th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Errors Detected.
1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors
were detected
• ECCERR15: ECC Error in the page between the 3840th and the 4095th bytes
Fixed to 0 if TYPECORREC = 0
0 = No Errors Detected.
1 = A single bit error occurred in the ECC bytes.
Read ECC Parity 15 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR15: Multiple Error in the page between the 3840th and the 4095th bytes
Fixed to 0 if TYPECORREC = 0.
0 = No Multiple Errors Detected.
1 = Multiple Errors Detected.
294
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.5
Registers for 1 ECC for a page of 512/1024/2048/4096 bytes
26.5.1
Name:
ECC Parity Register 0
ECC_PR0
Address:
0xFFFFE20C
Access:
Read-only
31
–
23
–
15
30
–
22
–
14
29
–
21
–
13
28
–
20
–
12
27
–
19
–
11
26
–
18
–
10
3
2
25
–
17
–
9
24
–
16
–
8
1
0
WORDADDR
7
6
5
WORDADDR
4
BITADDR
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR: Bit Address
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR: Word Address
During a page read, this value contains the word address (8-bit or 16-bit word depending on the memory plane organization) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless.
295
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.5.2
Name:
ECC Parity Register 1
ECC_PR1
Address:
0xFFFFE210
Access:
Read-only
31
–
23
–
15
30
–
22
–
14
29
–
21
–
13
28
–
20
–
12
7
6
5
4
27
–
19
–
11
26
–
18
–
10
25
–
17
–
9
24
–
16
–
8
3
2
1
0
NPARITY
NPARITY
• NPARITY:
Parity N
296
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.6
Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word
26.6.1
Name:
ECC Parity Register 0
ECC_PR0
Address:
0xFFFFE20C
Access:
Read-only
31
–
23
30
–
22
15
14
29
–
21
13
28
–
20
NPARITY0
12
27
–
19
26
–
18
11
10
NPARITY0
7
6
5
WORDADDR0
25
–
17
24
–
16
9
8
1
BITADDR0
0
WORDADD0
4
3
2
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR0: corrupted Bit Address in the page between the first byte and the 511th bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR0: corrupted Word Address in the page between the first byte and the 511th bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY0:
Parity N
297
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.6.2
Name:
ECC Parity Register 1
ECC_PR1
Address:
0xFFFFE210
Access:
Read-only
31
–
23
30
–
22
29
–
21
15
14
13
7
6
28
–
20
NPARITY1
12
27
–
19
26
–
18
25
–
17
24
–
16
11
10
9
8
4
3
2
1
BITADDR1
0
NPARITY1
5
WORDADDR1
WORDADD1
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR1: corrupted Bit Address in the page between the 512th and the 1023rd bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR1: corrupted Word Address in the page between the 512th and the 1023rd bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY1:
Parity N
298
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.6.3
Name:
ECC Parity Register 2
ECC_PR2
Address:
0xFFFFE218
Access:
Read-only
31
–
23
30
–
22
29
–
21
15
14
13
7
6
28
–
20
NPARITY2
12
27
–
19
26
–
18
11
4
3
10
9
WORDADDR2
2
1
BITADDR2
NPARITY2
5
WORDADDR2
25
–
17
24
–
16
8
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR2: corrupted Bit Address in the page between the 1023rd and the 1535th bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR2: corrupted Word Address in the page in the page between the 1023rd and the 1535th bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY2:
Parity N
299
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.6.4
Name:
ECC Parity Register 3
ECC_PR3
Address:
0xFFFFE21C
Access:
Read-only
31
–
23
30
–
22
29
–
21
15
14
13
7
6
28
–
20
NPARITY3
12
27
–
19
26
–
18
11
4
3
10
9
WORDADDR3
2
1
BITADDR3
NPARITY3
5
WORDADDR3
25
–
17
24
–
16
8
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR3: corrupted Bit Address in the page between the1536th and the 2047th bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR3 corrupted Word Address in the page between the 1536th and the 2047th bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY3
Parity N
300
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.6.5
Name:
ECC Parity Register 4
ECC_PR4
Address:
0xFFFFE220
Access:
Read-only
31
–
23
30
–
22
29
–
21
15
14
13
7
6
28
–
20
NPARITY4
12
27
–
19
26
–
18
11
4
3
10
9
WORDADDR4
2
1
BITADDR4
NPARITY4
5
WORDADDR4
25
–
17
24
–
16
8
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR4: corrupted Bit Address in the page between the 2048th and the 2559th bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR4: corrupted Word Address in the page between the 2048th and the 2559th bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY4:
Parity N
301
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.6.6
Name:
ECC Parity Register 5
ECC_PR5
Address:
0xFFFFE224
Access:
Read-only
31
–
23
30
–
22
29
–
21
15
14
13
7
6
28
–
20
NPARITY5
12
27
–
19
26
–
18
11
4
3
10
9
WORDADDR5
2
1
BITADDR5
NPARITY5
5
WORDADDR5
25
–
17
24
–
16
8
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR5: corrupted Bit Address in the page between the 2560th and the 3071st bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR5: corrupted Word Address in the page between the 2560th and the 3071st bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY5:
Parity N
302
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.6.7
Name:
ECC Parity Register 6
ECC_PR6
Address:
0xFFFFE228
Access:
Read-only
31
–
23
30
–
22
29
–
21
15
14
13
7
6
28
–
20
NPARITY6
12
27
–
19
26
–
18
11
4
3
10
9
WORDADDR6
2
1
BITADDR6
NPARITY6
5
WORDADDR6
25
–
17
24
–
16
8
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR6: corrupted Bit Address in the page between the 3072nd and the 3583rd bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR6: corrupted Word Address in the page between the 3072nd and the 3583rd bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY6:
Parity N
303
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.6.8
Name:
ECC Parity Register 7
ECC_PR7
Address:
0xFFFFE22C
Access:
Read-only
31
–
23
30
–
22
29
–
21
15
14
13
7
6
28
–
20
NPARITY7
12
27
–
19
26
–
18
11
4
3
10
9
WORDADDR7
2
1
BITADDR7
NPARITY7
5
WORDADDR7
25
–
17
24
–
16
8
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR7: corrupted Bit Address in the page between the 3584h and the 4095th bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR7: corrupted Word Address in the page between the 3584th and the 4095th bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY7:
Parity N
304
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.7
Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word
26.7.1
Name:
ECC Parity Register 0
ECC_PR0
Address:
0xFFFFE20C
Access:
Read-only
31
–
23
0
15
30
–
22
14
29
–
21
28
–
20
13
12
NPARITY0
7
6
5
WORDADDR0
4
27
–
19
NPARITY0
11
0
3
26
–
18
25
–
17
24
–
16
10
9
WORDADDR0
1
BITADDR0
8
2
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR0: corrupted Bit Address in the page between the first byte and the 255th bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR0: corrupted Word Address in the page between the first byte and the 255th bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY0:
Parity N
305
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.7.2
Name:
ECC Parity Register 1
ECC_PR1
Address:
0xFFFFE210
Access:
Read-only
31
–
23
0
15
30
–
22
29
–
21
28
–
20
14
13
12
7
6
NPARITY1
5
WORDADDR1
4
27
–
19
NPARITY1
11
0
3
26
–
18
25
–
17
24
–
16
10
9
WORDADDR1
1
BITADDR1
8
2
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area
• BITADDR1: corrupted Bit Address in the page between the 256th and the 511th bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR1: corrupted Word Address in the page between the 256th and the 511th bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY1:
Parity N
306
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.7.3
Name:
ECC Parity Register 2
ECC_PR2
Address:
0xFFFFE218
Access:
Read-only
31
–
23
0
15
30
–
22
29
–
21
28
–
20
14
13
12
7
6
NPARITY2
5
WORDADDR2
4
27
–
19
NPARITY2
11
0
3
26
–
18
25
–
17
24
–
16
10
9
WORDADD2
1
BITADDR2
8
2
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR2: corrupted Bit Address in the page between the 512th and the 767th bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR2: corrupted Word Address in the page between the 512th and the 767th bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY2:
Parity N
307
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.7.4
Name:
ECC Parity Register 3
ECC_PR3
Address:
0xFFFFE21C
Access:
Read-only
31
–
23
0
15
30
–
22
29
–
21
28
–
20
14
13
12
7
6
NPARITY3
5
WORDADDR3
4
27
–
19
NPARITY3
11
0
3
26
–
18
25
–
17
24
–
16
10
9
WORDADDR3
1
BITADDR3
8
2
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR3: corrupted Bit Address in the page between the 768th and the 1023rd bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR3: corrupted Word Address in the page between the 768th and the 1023rd bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless
• NPARITY3:
Parity N
308
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.7.5
Name:
ECC Parity Register 4
ECC_PR4
Address:
0xFFFFE220
Access:
Read-only
31
–
23
0
15
30
–
22
29
–
21
28
–
20
14
13
12
7
6
NPARITY4
5
WORDADDR4
4
27
–
19
NPARITY4
11
0
3
26
–
18
10
2
25
–
17
9
WORDADDR4
1
BITADDR4
24
–
16
8
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area
• BITADDR4: corrupted bit address in the page between the 1024th and the 1279th bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR4: corrupted word address in the page between the 1024th and the 1279th bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY4
Parity N
309
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.7.6
Name:
ECC Parity Register 5
ECC_PR5
Address:
0xFFFFE224
Access:
Read-only
31
–
23
0
15
30
–
22
29
–
21
28
–
20
14
13
12
7
6
NPARITY5
5
WORDADDR5
4
27
–
19
NPARITY5
11
0
3
26
–
18
10
2
25
–
17
9
WORDADDR5
1
BITADDR5
24
–
16
8
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR5: corrupted Bit Address in the page between the 1280th and the 1535th bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR5: corrupted Word Address in the page between the 1280th and the 1535th bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY5:
Parity N
310
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.7.7
Name:
ECC Parity Register 6
ECC_PR6
Address:
0xFFFFE228
Access:
Read-only
31
–
23
0
15
30
–
22
29
–
21
28
–
20
14
13
12
7
6
NPARITY6
5
WORDADDR6
4
27
–
19
NPARITY6
11
0
3
26
–
18
25
–
17
24
–
16
10
9
WORDADDR6
1
BITADDR6
8
2
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR6: corrupted bit address in the page between the 1536th and the1791st bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR6: corrupted word address in the page between the 1536th and the1791st bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY6:
Parity N
311
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.7.8
Name:
ECC Parity Register 7
ECC_PR7
Address:
0xFFFFE22C
Access:
Read-only
31
–
23
0
15
30
–
22
29
–
21
28
–
20
14
13
12
7
6
NPARITY7
5
WORDADDR7
4
27
–
19
NPARITY7
11
0
3
26
–
18
25
–
17
24
–
16
10
9
WORDADDR7
1
BITADDR7
8
2
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR7: corrupted Bit Address in the page between the 1792nd and the 2047th bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR7: corrupted Word Address in the page between the 1792nd and the 2047th bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY7:
Parity N
312
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.7.9
Name:
ECC Parity Register 8
ECC_PR8
Address:
0xFFFFE230
Access:
Read-only
31
–
23
0
15
30
–
22
29
–
21
28
–
20
14
13
12
7
6
NPARITY8
5
WORDADDR8
4
27
–
19
NPARITY8
11
0
3
26
–
18
25
–
17
24
–
16
10
9
WORDADDR8
1
BITADDR8
8
2
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR8: corrupted Bit Address in the page between the 2048th and the2303rd bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR8: corrupted Word Address in the page between the 2048th and the 2303rd bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY8:
Parity N.
313
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.7.10
Name:
ECC Parity Register 9
ECC_PR9
Address:
0xFFFFE234
Access:
Read-only
31
–
23
0
15
30
–
22
29
–
21
28
–
20
14
13
12
7
6
NPARITY9
5
WORDADDR9
4
27
–
19
NPARITY9
11
0
3
26
–
18
25
–
17
24
–
16
10
9
WORDADDR9
1
BITADDR9
8
2
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area
• BITADDR9: corrupted bit address in the page between the 2304th and the 2559th bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR9: corrupted word address in the page between the 2304th and the 2559th bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless
• NPARITY9
Parity N
314
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.7.11
Name:
ECC Parity Register 10
ECC_PR10
Address:
0xFFFFE238
Access:
Read-only
31
–
23
0
15
7
30
–
22
29
–
21
14
13
NPARITY10
6
5
WORDADDR10
28
–
20
12
4
27
–
19
NPARITY10
11
0
3
26
–
18
25
–
17
24
–
16
10
9
WORDADDR10
1
BITADDR10
8
2
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR10: corrupted Bit Address in the page between the 2560th and the2815th bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR10: corrupted Word Address in the page between the 2560th and the 2815th bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY10:
Parity N
315
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.7.12
Name:
ECC Parity Register 11
ECC_PR11
Address:
0xFFFFE23C
Access:
Read-only
31
–
23
0
15
7
30
–
22
29
–
21
14
13
NPARITY11
6
5
WORDADDR11
28
–
20
12
4
27
–
19
NPARITY11
11
0
3
26
–
18
25
–
17
24
–
16
10
9
WORDADDR11
1
BITADDR11
8
2
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR11: corrupted Bit Address in the page between the 2816th and the 3071st bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR11: corrupted Word Address in the page between the 2816th and the 3071st bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY11:
Parity N
316
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.7.13
Name:
ECC Parity Register 12
ECC_PR12
Address:
0xFFFFE240
Access:
Read-only
31
–
23
0
15
7
30
–
22
29
–
21
14
13
NPARITY12
6
5
WORDADDR12
28
–
20
12
4
27
–
19
NPARITY12
11
0
3
26
–
18
25
–
17
24
–
16
10
9
WORDADDR12
1
BITADDR12
8
2
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR12; corrupted Bit Address in the page between the 3072nd and the 3327th bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR12: corrupted Word Address in the page between the 3072nd and the 3327th bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY12:
Parity N
317
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.7.14
Name:
ECC Parity Register 13
ECC_PR13
Address:
0xFFFFE244
Access:
Read-only
31
–
23
0
15
7
30
–
22
29
–
21
14
13
NPARITY13
6
5
WORDADDR13
28
–
20
12
4
27
–
19
NPARITY13
11
0
3
26
–
18
25
–
17
24
–
16
10
9
WORDADDR13
1
BITADDR13
8
2
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR13: corrupted Bit Address in the page between the 3328th and the 3583rd bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR13: corrupted Word Address in the page between the 3328th and the 3583rd bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY13:
Parity N
318
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.7.15
Name:
ECC Parity Register 14
ECC_PR14
Address:
0xFFFFE248
Access:
Read-only
31
–
23
0
15
7
30
–
22
29
–
21
14
13
NPARITY14
6
5
WORDADDR14
28
–
20
12
4
27
–
19
NPARITY14
11
0
3
26
–
18
25
–
17
24
–
16
10
9
WORDADDR14
1
BITADDR14
8
2
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR14: corrupted Bit Address in the page between the 3584th and the 3839th bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR14: corrupted Word Address in the page between the 3584th and the 3839th bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY14:
Parity N
319
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
26.7.16
Name:
ECC Parity Register 15
ECC_PR15
Address:
0xFFFFE24C
Access:
Read-only
31
–
23
0
15
7
30
–
22
29
–
21
14
13
NPARITY15
6
5
WORDADDR15
28
–
20
12
4
27
–
19
NPARITY15
11
0
3
26
–
18
25
–
17
24
–
16
10
9
WORDADDR15
1
BITADDR15
8
2
0
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area
• BITADDR15: corrupted Bit Address in the page between the 3840th and the 4095th bytes
During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If
multiple errors were detected, this value is meaningless.
• WORDADDR15: corrupted Word Address in the page between the 3840th and the 4095th bytes
During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was
detected. If multiple errors were detected, this value is meaningless.
• NPARITY15
Parity N
320
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
27. DMA Controller (DMAC)
27.1
Description
The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a
source peripheral to a destination peripheral over one or more AMBA buses. One channel is
required for each source/destination pair. In the most basic configuration, the DMAC has one
master interface and one channel. The master interface reads the data from a source and writes
it to a destination. Two AMBA transfers are required for each DMAC data transfer. This is also
known as a dual-access transfer.
The DMAC is programmed via the APB interface.
321
6264C–CAP–24-Mar-09
27.2
Block Diagram
Figure 27-1. DMA Controller (DMAC) Block Diagram
AMBA AHB Layer 1
DMA AHB Lite Master Interface 1
DMA Global
Request Arbiter
DMA Global Control
and Data Mux
DMA Destination
Requests Pool
DMA Write
Datapath Bundles
DMA Channel n
DMA Destination
Atmel APB rev2 Interface
DMA Channel 2
Status
Registers
DMA Channel 1
DMA Channel 0
DMA Channel 0
Write data path
to destination
DMA
Atmel
APB
Interface
Configuration
Registers
DMA Destination
Control State Machine
Destination Pointer
Management
DMA Interrupt
Controller
DMA Interrupt
DMA FIFO Controller
DMA FIFO
Trigger Manager
Up to 64 bytes
External
Triggers
Soft
Triggers
DMA Channel 0
Read data path
from source
DMA
REQ/ACK
Interface
DMA
Hardware
Handshaking
Interface
DMA Source
Control State Machine
Source Pointer
Management
DMA Source
Requests Pool
DMA Read
Datapath Bundles
DMA Global Control
and Data Mux
DMA Global
Request Arbiter
DMA AHB Lite Master Interface 0
AMBA AHB Layer 0
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AT91CAP9S500A/AT91CAP9S250A
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AT91CAP9S500A/AT91CAP9S250A
27.3
27.3.1
Functional Description
Basic Definitions
Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then
stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form
a channel.
Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previously read from the source peripheral).
Memory: Source or destination that is always “ready” for a DMAC transfer and does not require
a handshaking interface to interact with the DMAC.
Channel: Read/write datapath between a source peripheral on one configured AMBA layer and
a destination peripheral on the same or different AMBA layer that occurs through the channel
FIFO. If the source peripheral is not memory, then a source handshaking interface is assigned to
the channel. If the destination peripheral is not memory, then a destination handshaking interface is assigned to the channel. Source and destination handshaking interfaces can be assigned
dynamically by programming the channel registers.
Master interface: DMAC is a master on the AHB bus reading data from the source and writing it
to the destination over the AHB bus.
Slave interface: The APB interface over which the DMAC is programmed. The slave interface
in practice could be on the same layer as any of the master interfaces or on a separate layer.
Handshaking interface: A set of signal registers that conform to a protocol and handshake
between the DMAC and source or destination peripheral to control the transfer of a single or
chunk transfer between them. This interface is used to request, acknowledge, and control a
DMAC transaction. A channel can receive a request through one of two types of handshaking
interface: hardware or software.
Hardware handshaking interface: Uses hardware signals to control the transfer of a single or
chunk transfer between the DMAC and the source or destination peripheral.
Software handshaking interface: Uses software registers to contr5ol the transfer of a single or
chunk transfer between the DMAC and the source or destination peripheral. No special DMAC
handshaking signals are needed on the I/O of the peripheral. This mode is useful for interfacing
an existing peripheral to the DMAC without modifying it.
Flow controller: The device (either the DMAC or source/destination peripheral) that determines
the length of and terminates a DMAC buffer transfer. If the length of a buffer is known before
enabling the channel, then the DMAC should be programmed as the flow controller. If the length
of a buffer is not known prior to enabling the channel, the source or destination peripheral needs
to terminate a buffer transfer. In this mode, the peripheral is the flow controller.
Transfer hierarchy: Figure 27-2 on page 324 illustrates the hierarchy between DMAC transfers,
buffer transfers, chunk or single, and AMBA transfers (single or burst) for non-memory peripherals. Figure 27-3 on page 324 shows the transfer hierarchy for memory.
323
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 27-2. DMAC Transfer Hierarchy for Non-Memory Peripheral
HDMA Transfer
Buffer
Buffer
Chunk
Transfer
AMBA
Burst
Transfer
DMA Transfer
Level
Buffer Transfer
Level
Buffer
Chunk
Transfer
Chunk
Transfer
AMBA
Single
Transfer
AMBA
Burst
Transfer
AMBA
Burst
Transfer
Single
Transfer
DMA Transaction
Level
AMBA
Single
Transfer
AMBA Transfer
Level
Figure 27-3. DMAC Transfer Hierarchy for Memory
HDMA Transfer
Buffer
AMBA
Burst
Transfer
Buffer
AMBA
Burst
Transfer
DMA Transfer
Level
Buffer
AMBA
Burst
Transfer
AMBA
Single
Transfer
Buffer Transfer
Level
AMBA Transfer
Level
Buffer: A buffer of DMAC data. The amount of data (length) is determined by the flow controller.
For transfers between the DMAC and memory, a buffer is broken directly into a sequence of
AMBA bursts and AMBA single transfers.
For transfers between the DMAC and a non-memory peripheral, a buffer is broken into a
sequence of DMAC transactions (single and chunks). These are in turn broken into a sequence
of AMBA transfers.
Transaction: A basic unit of a DMAC transfer as determined by either the hardware or software
handshaking interface. A transaction is only relevant for transfers between the DMAC and a
source or destination peripheral if the source or destination peripheral is a non-memory device.
There are two types of transactions: single transfer and chunk transfer.
– Single transfer: The length of a single transaction is always 1 and is converted to a
single AMBA access.
– Chunk transfer: The length of a chunk is programmed into the DMAC. The chunk is
then converted into a sequence of AHB access.DMAC executes each AMBA burst
transfer by performing incremental bursts that are no longer than 16 beats.
324
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
DMAC transfer: Software controls the number of buffers in a DMAC transfer. Once the DMAC
transfer has completed, then hardware within the DMAC disables the channel and can generate
an interrupt to signal the completion of the DMAC transfer. You can then re-program the channel
for a new DMAC transfer.
Single-buffer DMAC transfer: Consists of a single buffer.
Multi-buffer DMAC transfer: A DMAC transfer may consist of multiple DMAC buffers. Multi-buffer DMAC transfers are supported through buffer chaining (linked list pointers), auto-reloading of
channel registers, and contiguous buffers. The source and destination can independently select
which method to use.
– Linked lists (buffer chaining) – A descriptor pointer (DSCR) points to the location
in system memory where the next linked list item (LLI) exists. The LLI is a set of
registers that describe the next buffer (buffer descriptor) and a descriptor pointer
register. The DMAC fetches the LLI at the beginning of every buffer when buffer
chaining is enabled.
– Replay – The DMAC automatically reloads the channel registers at the end of each
buffers to the value when the channel was first enabled.
– Contiguous buffers – Where the address of the next buffer is selected to be a
continuation from the end of the previous buffer.
Picture-in-Picture Mode: DMAC contains a picture-in-picture mode support. When this mode is
enabled, addresses are automatically incremented by a programmable value when the DMAC
channel transfer count reaches a user defined boundary.
Figure 27-4 on page 325 illustrates a memory mapped image 4:2:2 encoded located at
image_base_address in memory. A user defined start address is defined at
Picture_start_address. The incremented value is set to memory_hole_size = image_width picture_width, and the boundary is set to picture_width.
Figure 27-4. Picture-In-Picture Mode Support
325
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Channel locking: Software can program a channel to keep the AHB master interface by locking
the arbitration for the master bus interface for the duration of a DMAC transfer, buffer, or chunk.
Bus locking: Software can program a channel to maintain control of the AMBA bus by asserting
hmastlock for the duration of a DMAC transfer, buffer, or transaction (single or chunk). Channel
locking is asserted for the duration of bus locking at a minimum.
27.3.2
Memory Peripherals
Figure 27-3 on page 324 shows the DMAC transfer hierarchy of the DMAC for a memory peripheral. There is no handshaking interface with the DMAC, and therefore the memory peripheral
can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately
without waiting for a transaction request. The alternative to not having a transaction-level handshaking interface is to allow the DMAC to attempt AMBA transfers to the peripheral once the
channel is enabled. If the peripheral slave cannot accept these AMBA transfers, it inserts wait
states onto the bus until it is ready; it is not recommended that more than 16 wait states be
inserted onto the bus. By using the handshaking interface, the peripheral can signal to the
DMAC that it is ready to transmit/receive data, and then the DMAC can access the peripheral
without the peripheral inserting wait states onto the bus.
27.3.3
Handshaking Interface
Handshaking interfaces are used at the transaction level to control the flow of single or chunk
transfers. The operation of the handshaking interface is different and depends on whether the
peripheral or the DMAC is the flow controller.
The peripheral uses the handshaking interface to indicate to the DMAC that it is ready to transfer/accept data over the AMBA bus. A non-memory peripheral can request a DMAC transfer
through the DMAC using one of two handshaking interfaces:
• Hardware handshaking
• Software handshaking
Software selects between the hardware or software handshaking interface on a per-channel
basis. Software handshaking is accomplished through memory-mapped registers, while hardware handshaking is accomplished using a dedicated handshaking interface.
27.3.3.1
Software Handshaking
When the slave peripheral requires the DMAC to perform a DMAC transaction, it communicates
this request by sending an interrupt to the CPU or interrupt controller.
The interrupt service routine then uses the software registers to initiate and control a DMAC
transaction. These software registers are used to implement the software handshaking
interface.
The SRC_H2SEL/DST_H2SEL bit in the DMAC_CFGx channel configuration register must be
set to zero to enable software handshaking.
When the peripheral is not the flow controller, then the last transaction register DMAC_LAST is
not used, and the values in these registers are ignored.
27.3.3.2
Chunk Transactions
Writing a 1 to the DMAC_CREQ[2x] register starts a source chunk transaction request, where x
is the channel number. Writing a 1 to the DMAC_CREQ[2x+1] register starts a destination chunk
transfer request, where x is the channel number.
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AT91CAP9S500A/AT91CAP9S250A
Upon completion of the chunk transaction, the hardware clears the DMAC_CREQ[2x] or
DMAC_CREQ[2x+1].
27.3.3.3
Single Transactions
Writing a 1 to the DMAC_SREQ[2x] register starts a source single transaction request, where x
is the channel number. Writing a 1 to the DMAC_SREQ[2x+1] register starts a destination single
transfer request, where x is the channel number.
Upon completion of the chunk transaction, the hardware clears the DMAC_SREQ[x] or
DMAC_SREQ[2x+1].
Software can poll the relevant channel bit in the DMAC_CREQ[2x]/DMAC_CREQ[2x+1] and
DMAC_SREQ[x]/DMAC_SREQ[2x+1] registers. When both are 0, then either the requested
chunk or single transaction has completed.
27.3.4
DMAC Transfer Types
A DMAC transfer may consist of single or multi-buffers transfers. On successive buffers of a
multi-buffer transfer, the DMAC_SADDRx/DMAC_DADDRx registers in the DMAC are reprogrammed using either of the following methods:
• Buffer chaining using linked lists
• Replay mode
• Contiguous address between buffers
On successive buffers of a multi-buffer transfer, the DMAC_CTRLAx and DMAC_CTRLBx registers in the DMAC are re-programmed using either of the following methods:
• Buffer chaining using linked lists
• Replay mode
When buffer chaining, using linked lists is the multi-buffer method of choice, and on successive
buffers, the DMAC_DSCRx register in the DMAC is re-programmed using the following method:
• Buffer chaining using linked lists
A buffer descriptor (LLI) consists of following registers, DMAC_SADDRx, DMAC_DADDRx,
DMAC_DSCRx, DMAC_CTRLAx, DMAC_CTRLBx.These registers, along with the
DMAC_CFGx register, are used by the DMAC to set up and describe the buffer transfer.
27.3.4.1
Multi-buffer Transfers
27.3.4.2
Buffer Chaining Using Linked Lists
In this case, the DMAC re-programs the channel registers prior to the start of each buffer by
fetching the buffer descriptor for that buffer from system memory. This is known as an LLI
update.
DMAC buffer chaining is supported by using a Descriptor Pointer register (DMAC_DSCRx) that
stores the address in memory of the next buffer descriptor. Each buffer descriptor contains the
corresponding buffer descriptor (DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx,
DMAC_CTRLAx DMAC_CTRLBx).
To set up buffer chaining, a sequence of linked lists must be programmed in memory.
The DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx
registers are fetched from system memory on an LLI update. The updated content of the
DMAC_CTRLAx register is written back to memory on buffer completion. Figure 27-5 on page
327
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
328 shows how to use chained linked lists in memory to define multi-buffer transfers using buffer
chaining.
The Linked List multi-buffer transfer is initiated by programming DMAC_DSCRx with DSCRx(0)
(LLI(0) base address) and DMAC_CTRLBx register with both SRC_DSCR and DST_DSCR set
to 0. Other fields and registers are ignored and overwritten when the descriptor is retrieved from
memory.
The last transfer descriptor must be written to memory with its next descriptor address set to 0.
Figure 27-5. Multi Buffer Transfer Using Linked List
System Memory
LLI(0)
DSCRx(0)
LLI(1)
DSCRx(1)= DSCRx(0) + 0x10
DSCRx(2)= DSCRx(1) + 0x10
CTRLBx= DSCRx(0) + 0xC
CTRLBx= DSCRx(1) + 0xC
CTRLAx= DSCRx(0) + 0x8
CTRLBx= DSCRx(1) + 0x8
DADDRx= DSCRx(0) + 0x4
DADDRx= DSCRx(1) + 0x4
SADDRx= DSCRx(1) + 0x0
SADDRx= DSCRx(0) + 0x0
DSCRx(1)
DSCRx(2)
(points to 0 if
LLI(1) is the last
transfer descriptor
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AT91CAP9S500A/AT91CAP9S250A
27.3.4.3
Table 27-1.
Programming DMAC for Multiple Buffer Transfers
Multiple Buffers Transfer Management Table
Transfer Type
AUTO
SRC_REP
DST_REP
SRC_DSCR
DST_DSCR
BTSIZE
SADDR
DADDR
Other
Fields
1) Single Buffer or Last
buffer of a multiple buffer
transfer
0
–
–
1
1
USR
USR
USR
USR
2) Multi Buffer transfer
with contiguous DADDR
0
–
0
0
1
LLI
LLI
CONT
LLI
3) Multi Buffer transfer
with contiguous SADDR
0
0
–
1
0
LLI
CONT
LLI
LLI
4) Multi Buffer transfer
with LLI support
0
–
–
0
0
LLI
LLI
LLI
LLI
5) Multi Buffer transfer
with DADDR reloaded
0
–
1
0
1
LLI
LLI
REP
LLI
6) Multi Buffer transfer
with SADDR reloaded
0
1
–
1
0
LLI
REP
LLI
LLI
7) Multi Buffer transfer
with BTSIZE reloaded and
contiguous DADDR
1
–
0
0
1
REP
LLI
CONT
LLI
8) Multi Buffer transfer
with BTSIZE reloaded and
contiguous SADDR
1
0
–
1
0
REP
CONT
LLI
LLI
9) Automatic mode
channel is stalling
BTsize is reloaded
1
0
0
1
1
REP
CONT
CONT
REP
10) Automatic mode
BTSIZE, SADDR and
DADDR reloaded
1
1
1
1
1
REP
REP
REP
REP
11) Automatic mode
BTSIZE, SADDR reloaded
and DADDR contiguous
1
1
0
1
1
REP
REP
CONT
REP
Notes:
1. USR means that the register field is manually programmed by the user.
2. CONT means that address is contiguous.
3. REP means that the register field is updated with its previous value. If the transfer is the first one, then the user must manually program the value.
4. Channel stalled is true if the relevant BTC interrupt is not masked.
5. LLI means that the register field is updated with the content of the linked list item.
27.3.4.4
Replay Mode of Channel Registers
During automatic replay mode, the channel registers are reloaded with their initial values at the
completion of each buffer and the new values used for the new buffer. Depending on the row
number in Table 27-1 on page 329, some or all of the DMAC_SADDRx, DMAC_DADDRx,
DMAC_CTRLAx and DMAC_CTRLBx channel registers are reloaded from their initial value at
the start of a buffer transfer.
27.3.4.5
Contiguous Address Between Buffers
In this case, the address between successive buffers is selected to be a continuation from the
end of the previous buffer. Enabling the source or destination address to be contiguous between
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buffers is a function of DMAC_CTRLAx.SRC_DSCR, DMAC_CFGx.SRC_REP,
DMAC_CTRLAx.DST_DSCR and DMAC_CFGx.DST_REP registers.
27.3.4.6
Suspension of Transfers Between buffers
At the end of every buffer transfer, an end of buffer interrupt is asserted if:
• the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTC[n] = ‘1’, where n is the
channel number.
Note:
The buffer complete interrupt is generated at the completion of the buffer transfer to the
destination.
At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if:
• the channel end of chained buffer interrupt is unmasked, DMAC_EBCIMR.CBTC[n] = ‘1’,
when n is the channel number.
27.3.4.7
Ending Multi-buffer Transfers
All multi-buffer transfers must end as shown in Row 1 of Table 27-1 on page 329. At the end of
every buffer transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state,
then the previous buffer transferred was the last buffer and the DMAC transfer is terminated.
For rows 9, 10 and 11 of Table 27-1 on page 329, (DMAC_DSCRx = 0 and
DMAC_CTRLBx.AUTO is set), multi-buffer DMAC transfers continue until the automatic mode is
disabled by writing a ‘1’ in DMAC_CTRLBx.AUTO bit. This bit should be programmed to zero in
the end of buffer interrupt service routine that services the next-to-last buffer transfer. This puts
the DMAC into Row 1 state.
For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared) the user must setup the last buffer
descriptor in memory such that both LLI.DMAC_CTRLBx.SRC_DSCR and
LLI.DMAC_CTRLBx.DST_DSCR are one and LLI.DMAC_DSCRx is set to 0.
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27.3.5
Programming a Channel
Four registers, the DMAC_DSCRx, the DMAC_CTRLAx, the DMAC_CTRLBx and
DMAC_CFGx, need to be programmed to set up whether single or multi-buffer transfers take
place, and which type of multi-buffer transfer is used. The different transfer types are shown in
Table 27-1 on page 329.
The “BTSIZE, SADDR and DADDR” columns indicate where the values of DMAC_SARx,
DMAC_DARx, DMAC_CTLx, and DMAC_LLPx are obtained for the next buffer transfer when
multi-buffer DMAC transfers are enabled.
27.3.5.1
Programming Examples
27.3.5.2
Single-buffer Transfer (Row 1)
1. Read the Channel Handler Status Register DMAC_CHSR.ENABLE Field to choose a
free (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register, DMAC_EBCISR.
3. Program the following channel registers:
a. Write the starting source address in the DMAC_SADDRx register for channel x.
b.
Write the starting destination address in the DMAC_DADDRx register for channel
x.
c.
Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 1
as shown in Table 27-1 on page 329. Program the DMAC_CTRLBx register with
both DST_DSCR and SRC_DSCR fields set to one and AUTO field set to 0.
d. Write the control information for the DMAC transfer in the DMAC_CTRLAx and
DMAC_CTRLBx registers for channel x. For example, in the register, you can program the following:
– i. Set up the transfer type (memory or non-memory peripheral for source and
destination) and flow control device by programming the FC of the DMAC_CTRLBx
register.
– ii. Set up the transfer characteristics, such as:
– Transfer width for the source in the SRC_WIDTH field.
– Transfer width for the destination in the DST_WIDTH field.
– Source AHB Master interface layer in the SIF field where source resides.
– Destination AHB Master Interface layer in the DIF field where destination resides.
– Incrementing/decrementing or fixed address for source in SRC_INC field.
– Incrementing/decrementing or fixed address for destination in DST_INC field.
e. Write the channel configuration information into the DMAC_CFGx register for channel x.
– i. Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires
programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates
the hardware handshaking interface to handle source/destination requests. Writing a
‘0’ activates the software handshaking interface to handle source/destination
requests.
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– ii. If the hardware handshaking interface is activated for the source or destination
peripheral, assign a handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DST_PER bits, respectively.
f.
If source picture-in-picture mode is enabled (DMAC_CTRLBx.SRC_PIP is
enabled), program the DMAC_SPIPx register for channel x.
g. If destination picture-in-picture mode is enabled (DMAC_CTRLBx.DST_PIP is
enabled), program the DMAC_DPIPx register for channel x.
4. After the DMAC selected channel has been programmed, enable the channel by writing
a ‘1’ to the DMAC_CHER.ENABLE[n] bit, where n is the channel number. Make sure
that bit 0 of DMAC_EN.ENABLE register is enabled.
5. Source and destination request single and chunk DMAC transactions to transfer the
buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the
completion of every transaction (chunk and single) in the buffer and carry out the buffer
transfer.
6. Once the transfer completes, hardware sets the interrupts and disables the channel. At
this time you can either respond to the buffer Complete or Transfer Complete interrupts,
or poll for the Channel Handler Status Register (DMAC_CHSR.ENABLE[n]) bit until it is
cleared by hardware, to detect when the transfer is complete.
27.3.5.3
Multi-buffer Transfer with Linked List for Source and Linked List for Destination (Row 4)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the chain of Linked List Items (otherwise known as buffer descriptors) in memory. Write the control information in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx
registers location of the buffer descriptor for each LLI in memory (see Figure 27-6 on
page 334) for channel x. For example, in the register, you can program the following:
a. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx
register.
b.
Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_WIDTH field.
– ii. Transfer width for the destination in the DST_WIDTH field.
– iii. Source AHB master interface layer in the SIF field where source resides.
– iv. Destination AHB master interface layer in the DIF field where destination resides.
– v. Incrementing/decrementing or fixed address for source in SRC_INCR field.
– vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
3. Write the channel configuration information into the DMAC_CFGx register for channel
x.
a. Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates
the hardware handshaking interface to handle source/destination requests for the
specific channel. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests.
b.
If the hardware handshaking interface is activated for the source or destination
peripheral, assign the handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively.
4. Make sure that the LLI.DMAC_CTRLBx register locations of all LLI entries in memory
(except the last) are set as shown in Row 4 of Table 27-1 on page 329. The
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LLI.DMAC_CTRLBx register of the last Linked List Item must be set as described in
Row 1 of Table 27-1. Figure 27-5 on page 328 shows a Linked List example with two
list items.
5. Make sure that the LLI.DMAC_DSCRx register locations of all LLI entries in memory
(except the last) are non-zero and point to the base address of the next Linked List
Item.
6. Make sure that the LLI.DMAC_SADDRx/LLI.DMAC_DADDRx register locations of all
LLI entries in memory point to the start source/destination buffer address preceding
that LLI fetch.
7. Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register
locations of all LLI entries in memory are cleared.
8. If source picture-picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), program the DMAC_SPIPx register for channel x.
9. If destination picture-in-picture is enabled (DMAC_CTRLBx.DST_PIP is enabled), program the DMAC_DPIPx register for channel x.
10. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the status register: DMAC_EBCISR.
11. Program the DMAC_CTRLBx, DMAC_CFGx registers according to Row 4 as shown in
Table 27-1 on page 329.
12. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first
Linked List item.
13. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit, where n
is the channel number. The transfer is performed.
14. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
Note:
The LLI.DMAC_SADDRx, LLI. DMAC_DADDRx, LLI.DMAC_DSCRx, LLI.DMAC_CTRLAx and
LLI.DMAC_CTRLBx registers are fetched. The DMAC automatically reprograms the
DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLBx and DMAC_CTRLAx channel registers from the DMAC_DSCRx(0).
15. Source and destination request single and chunk DMAC transactions to transfer the
buffer of data (assuming non-memory peripheral). The DMAC acknowledges at the
completion of every transaction (chunk and single) in the buffer and carry out the buffer
transfer.
16. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to system memory at the same location and on the same layer (DMAC_DSCRx.DSCR_IF)
where it was originally fetched, that is, the location of the DMAC_CTRLAx register of
the linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx
register is written out because only the DMAC_CTRLAx.BTSIZE and
DMAC_CTRLAX.DONE bits have been updated by DMAC hardware. Additionally, the
DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed.
Note:
Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is
asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared
at the start of the transfer.
17. The DMAC does not wait for the buffer interrupt to be cleared, but continues fetching
the next LLI from the memory location pointed to by current DMAC_DSCRx register
and automatically reprograms the DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx,
DMAC_CTRLAx and DMAC_CTRLBx channel registers. The DMAC transfer continues
until the DMAC determines that the DMAC_CTRLBx and DMAC_DSCRx registers at
the end of a buffer transfer match described in Row 1 of Table 27-1 on page 329. The
DMAC then knows that the previous buffer transferred was the last buffer in the DMAC
transfer. The DMAC transfer might look like that shown in Figure 27-6 on page 334.
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Figure 27-6. Multi-buffer with Linked List Address for Source and Destination
Address of
Destination Layer
Address of
Source Layer
Buffer 2
SADDR(2)
Buffer 2
DADDR(2)
Buffer 1
SADDR(1)
Buffer 1
DADDR(1)
Buffer 0
Buffer 0
DADDR(0)
SADDR(0)
Source Buffers
Destination Buffers
If the user needs to execute a DMAC transfer where the source and destination address are
contiguous but the amount of data to be transferred is greater than the maximum buffer size
DMAC_CTRLAx.BTSIZE, then this can be achieved using the type of multi-buffer transfer as
shown in Figure 27-7 on page 335.
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Figure 27-7. Multi-buffer with Linked Address for Source and Destination Buffers are Contiguous
Address of
Source Layer
Address of
Destination Layer
Buffer 2
DADDR(3)
Buffer 2
Buffer 2
SADDR(3)
DADDR(2)
Buffer 2
Buffer 1
SADDR(2)
DADDR(1)
Buffer 1
SADDR(1)
Buffer 0
DADDR(0)
Buffer 0
SADDR(0)
Source Buffers
Destination Buffers
The DMAC transfer flow is shown in Figure 27-8 on page 336.
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Figure 27-8. DMAC Transfer Flow for Source and Destination Linked List Address
Channel enabled by
software
LLI Fetch
Hardware reprograms
SADDRx, DADDRx, CTRLA/Bx, DSCRx
DMAC buffer transfer
Writeback of HDMA_CTRLAx
register in system memory
Buffer Complete interrupt
generated here
Is HDMA in
Row1 of
HDMA State Machine Table?
HDMA Transfer Complete
interrupt generated here
no
yes
Channel Disabled by
hardware
27.3.5.4
Multi-buffer Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 10)
1. Read the Channel Enable register to choose an available (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register. Program the following channel registers:
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a. Write the starting source address in the DMAC_SADDRx register for channel x.
b.
Write the starting destination address in the DMAC_DADDRx register for channel
x.
c.
Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row
10 as shown in Table 27-1 on page 329. Program the DMAC_DSCRx register with
‘0’.
d. Write the control information for the DMAC transfer in the DMAC_CTRLAx and
DMAC_CTRLBx register for channel x. For example, in the register, you can program the following:
– i. Set up the transfer type (memory or non-memory peripheral for source and
destination) and flow control device by programming the FC of the DMAC_CTRLBx
register.
– ii. Set up the transfer characteristics, such as:
– Transfer width for the source in the SRC_WIDTH field.
– Transfer width for the destination in the DST_WIDTH field.
– Source AHB master interface layer in the SIF field where source resides.
– Destination AHB master interface layer in the DIF field where destination resides.
– Incrementing/decrementing or fixed address for source in SRC_INCR field.
– Incrementing/decrementing or fixed address for destination in DST_INCR field.
e. If source picture-in-picture mode is enabled (DMAC_CTRLBx.SPIP is enabled),
program the DMAC_SPIPx register for channel x.
f.
If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP), program the
DMAC_DPIPx register for channel x.
g. Write the channel configuration information into the DMAC_CFGx register for channel x. Ensure that the reload bits, DMAC_CFGx.SRC_REP,
DMAC_CFGx.DST_REP and DMAC_CTRLBx.AUTO are enabled.
– i. Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires
programming the SRC_H2SEL/DST_h2SEL bits, respectively. Writing a ‘1’ activates
the hardware handshaking interface to handle source/destination requests for the
specific channel. Writing a ‘0’ activates the software handshaking interface to handle
source/destination requests.
– ii. If the hardware handshaking interface is activated for the source or destination
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DST_PER bits, respectively.
3. After the DMAC selected channel has been programmed, enable the channel by writing
a ‘1’ to the DMAC_CHER.ENABLE[n] bit where is the channel number. Make sure that
bit 0 of the DMAC_EN register is enabled.
4. Source and destination request single and chunk DMAC transactions to transfer the
buffer of data (assuming non-memory peripherals). The DMAC acknowledges on completion of each chunk/single transaction and carry out the buffer transfer.
5. When the buffer transfer has completed, the DMAC reloads the DMAC_SADDRx,
DMAC_DADDRx and DMAC_CTRLAx registers. Hardware sets the buffer Complete
interrupt. The DMAC then samples the row number as shown in Table 27-1 on page
329. If the DMAC is in Row 1, then the DMAC transfer has completed. Hardware sets
the transfer complete interrupt and disables the channel. So you can either respond to
the Buffer Complete or Chained buffer transfer Complete interrupts, or poll for the
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Channel Enable in the Channel Status Register (DMAC_CHSR.ENABLE[n]) until it is
disabled, to detect when the transfer is complete. If the DMAC is not in Row 1, the next
step is performed.
6. The DMAC transfer proceeds as follows:
a. If interrupts is un-masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is the channel
number) hardware sets the buffer complete interrupt when the buffer transfer has
completed. It then stalls until the STALLED[n] bit of DMAC_CHSR register is
cleared by software, writing ‘1’ to DMAC_CHER.KEEPON[n] bit where n is the
channel number. If the next buffer is to be the last buffer in the DMAC transfer, then
the buffer complete ISR (interrupt service routine) should clear the automatic mode
bit in the DMAC_CTRLBx.AUTO bit. This put the DMAC into Row 1 as shown in
Table 27-1 on page 329. If the next buffer is not the last buffer in the DMAC transfer, then the reload bits should remain enabled to keep the DMAC in Row 4.
b.
If the buffer complete interrupt is masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is
the channel number), then hardware does not stall until it detects a write to the buffer complete interrupt enable register DMAC_EBCIER register but starts the next
buffer transfer immediately. In this case software must clear the automatic mode bit
in the DMAC_CTRLB to put the DMAC into ROW 1 of Table 27-1 on page 329
before the last buffer of the DMAC transfer has completed. The transfer is similar to
that shown in Figure 27-9 on page 338. The DMAC transfer flow is shown in Figure
27-10 on page 339.
Figure 27-9. Multi-buffer DMAC Transfer with Source and Destination Address Auto-reloaded
Address of
Source Layer
Address of
Destination Layer
Block0
Block1
Block2
SADDR
DADDR
BlockN
Source Buffers
Destination Buffers
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Figure 27-10. DMAC Transfer Flow for Source and Destination Address Auto-reloaded
Channel Enabled by
software
Buffer Transfer
Replay mode for SADDRx,
DADDRx, CTRLAx, CTRLBx
Buffer Complete interrupt
generated here
HDMA Transfer Complete
Interrupt generated here
yes
Is HDMA in Row1 of
HDMA State Machine table?
Channel Disabled by
hardware
no
EBCIMR[x]=1?
no
yes
Stall until STALLED is cleared
by writing to KEEPON field
27.3.5.5
Multi-buffer Transfer with Source Address Auto-reloaded and Linked List Destination Address (Row 6)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the chain of linked list items (otherwise known as buffer descriptors) in memory.
Write the control information in the LLI.DMAC_CTRLAx and DMAC_CTRLBx registers
location of the buffer descriptor for each LLI in memory for channel x. For example, in
the register you can program the following:
a. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control peripheral by programming the FC of the DMAC_CTRLBx
register.
b.
Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_WIDTH field.
– ii. Transfer width for the destination in the DST_WIDTH field.
– iii. Source AHB master interface layer in the SIF field where source resides.
– iv. Destination AHB master interface layer in the DIF field where destination resides.
– v. Incrementing/decrementing or fixed address for source in SRC_INCR field.
– vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
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3. Write the starting source address in the DMAC_SADDRx register for channel x.
Note:
The values in the LLI.DMAC_SADDRx register locations of each of the Linked List Items (LLIs)
setup up in memory, although fetched during a LLI fetch, are not used.
4. Write the channel configuration information into the DMAC_CFGx register for channel
x.
a. Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates
the hardware handshaking interface to handle source/destination requests for the
specific channel. Writing a ‘0’ activates the software handshaking interface
source/destination requests.
b.
If the hardware handshaking interface is activated for the source or destination
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DST_PER bits, respectively.
5. Make sure that the LLI.DMAC_CTRLBx register locations of all LLIs in memory (except
the last) are set as shown in Row 6 of Table 27-1 on page 329 while the
LLI.DMAC_CTRLBx register of the last Linked List item must be set as described in
Row 1 of Table 27-1. Figure 27-5 on page 328 shows a Linked List example with two
list items.
6. Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except
the last) are non-zero and point to the next Linked List Item.
7. Make sure that the LLI.DMAC_DADDRx register location of all LLIs in memory point to
the start destination buffer address proceeding that LLI fetch.
8. Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTRLA register
locations of all LLIs in memory is cleared.
9. If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the
DMAC_SPIPx register for channel x.
10. If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP is enabled), program
the DMAC_DPIPx register for channel x.
11. Clear any pending interrupts on the channel from the previous DMAC transfer by reading to the DMAC_EBCISR register.
12. Program the DMAC_CTLx, DMAC_CFGx registers according to Row 6 as shown in
Table 27-1 on page 329.
13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first
Linked List item.
14. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit where n
is the channel number. The transfer is performed. Make sure that bit 0 of the DMAC_EN
register is enabled.
15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
Note:
The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI. DMAC_LLPx LLI.DMAC_CTRLAx and
LLI.DMAC_CTRLBx registers are fetched. The LLI.DMAC_SADDRx register although fetched is
not used.
16. Source and destination request single and chunk DMAC transactions to transfer the
buffer of data (assuming non-memory peripherals). DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carry out the buffer
transfer.
17. The DMAC_CTRLAx register is written out to system memory. The DMAC_CTRLAx
register is written out to the same location on the same layer
(DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is the location of the
DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer
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transfer. Only DMAC_CTRLAx register is written out, because only the
DMAC_CTRLAx.BTSIZE and DMAC_CTRLAx.DONE fields have been updated by
hardware within the DMAC. The LLI.DMAC_CTRLAx.DONE bit is asserted to indicate
buffer completion Therefore, software can poll the LLI.DMAC_CTRLAx.DONE field of
the DMAC_CTRLAx register in the LLi to ascertain when a buffer transfer has
completed.
Note:
Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead poll the
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the polled LLI.DMAC_CTRLAx.DONE bit
is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLA.DONE bit was
cleared at the start of the transfer.
18. The DMAC reloads the DMAC_SADDRx register from the initial value. Hardware sets
the buffer complete interrupt. The DMAC samples the row number as shown in Table
27-1 on page 329. If the DMAC is in Row 1, then the DMAC transfer has completed.
Hardware sets the transfer complete interrupt and disables the channel. You can either
respond to the Buffer Complete or Chained buffer Transfer Complete interrupts, or poll
for the Channel Enable (DMAC_CHSR.ENABLE) bit until it is cleared by hardware, to
detect when the transfer is complete. If the DMAC is not in Row 1 as shown in Table 271 on page 329, the following step is performed.
19. The DMAC fetches the next LLI from memory location pointed to by the current
DMAC_DSCRx register, and automatically reprograms the DMAC_DADDRx,
DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. Note that the
DMAC_SADDRx is not re-programmed as the reloaded value is used for the next
DMAC buffer transfer. If the next buffer is the last buffer of the DMAC transfer then the
DMAC_CTRLBx and DMAC_DSCRx registers just fetched from the LLI should match
Row 1 of Table 27-1 on page 329. The DMAC transfer might look like that shown in Figure 27-11 on page 341.
Figure 27-11. Multi-buffer DMAC Transfer with Source Address Auto-reloaded and Linked List Destination Address
Address of
Destination Layer
Address of
Source Layer
Buffer0
DADDR(0)
Buffer1
DADDR(1)
SADDR
Buffer2
DADDR(2)
BufferN
DADDR(N)
Source Buffers
Destination Buffers
The DMAC Transfer flow is shown in Figure 27-12 on page 342.
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Figure 27-12. DMAC Transfer Flow for Replay Mode at Source and Linked List Destination Address
Channel Enabled by
software
LLI Fetch
Hardware reprograms
DADDRx, CTRLAx, CTRLBx, DSCRx
DMA buffer transfer
Writeback of control
status information in LLI
Reload SADDRx
Buffer Complete interrupt
generated here
yes
HDMA Transfer Complete
interrupt generated here
Is HDMA in
Row1 of
HDMA State Machine Table?
Channel Disabled by
hardware
27.3.5.6
no
Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 11)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading to the Interrupt Status Register.
3. Program the following channel registers:
a. Write the starting source address in the DMAC_SADDRx register for channel x.
b.
Write the starting destination address in the DMAC_DADDRx register for channel
x.
c.
Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row
11 as shown in Table 27-1 on page 329. Program the DMAC_DSCRx register with
‘0’. DMAC_CTRLBx.AUTO field is set to ‘1’ to enable automatic mode support.
d. Write the control information for the DMAC transfer in the DMAC_CTRLBx and
DMAC_CTRLAx register for channel x. For example, in this register, you can program the following:
– i. Set up the transfer type (memory or non-memory peripheral for source and
destination) and flow control device by programming the FC of the DMAC_CTRLBx
register.
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– ii. Set up the transfer characteristics, such as:
– Transfer width for the source in the SRC_WIDTH field.
– Transfer width for the destination in the DST_WIDTH field.
– Source AHB master interface layer in the SIF field where source resides.
– Destination AHB master interface master layer in the DIF field where destination
resides.
– Incrementing/decrementing or fixed address for source in SRC_INCR field.
– Incrementing/decrementing or fixed address for destination in DST_INCR field.
e. If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program
the DMAC_SPIPx register for channel x.
f.
If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP), program the
DMAC_DPIPx register for channel x.
g. Write the channel configuration information into the DMAC_CFGx register for channel x.
– i. Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires
programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates
the hardware handshaking interface to handle source/destination requests for the
specific channel. Writing a ‘0’ activates the software handshaking interface to handle
source/destination requests.
– ii. If the hardware handshaking interface is activated for the source or destination
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DST_PER bits, respectively.
4. After the DMAC channel has been programmed, enable the channel by writing a ‘1’ to
the DMAC_CHER.ENABLE[n] bit where n is the channel number. Make sure that bit 0
of the DMAC_EN.ENABLE register is enabled.
5. Source and destination request single and chunk DMAC transactions to transfer the
buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the
completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer.
6. When the buffer transfer has completed, the DMAC reloads the DMAC_SADDRx register. The DMAC_DADDRx register remains unchanged. Hardware sets the buffer
complete interrupt. The DMAC then samples the row number as shown in Table 27-1
on page 329. If the DMAC is in Row 1, then the DMAC transfer has completed. Hardware sets the transfer complete interrupt and disables the channel. So you can either
respond to the Buffer Complete or Transfer Complete interrupts, or poll for ENABLE
field in the Channel Status Register (DMAC_CHSR.ENABLE[n] bit) until it is cleared by
hardware, to detect when the transfer is complete. If the DMAC is not in Row 1, the next
step is performed.
7. The DMAC transfer proceeds as follows:
a. If the buffer complete interrupt is un-masked (DMAC_EBCIMR.BTC[x] = ‘1’, where
x is the channel number) hardware sets the buffer complete interrupt when the buffer transfer has completed. It then stalls until STALLED[n] bit of DMAC_CHSR is
cleared by writing in the KEEPON[n] field of DMAC_CHER register where n is the
channel number. If the next buffer is to be the last buffer in the DMAC transfer, then
the buffer complete ISR (interrupt service routine) should clear the automatic mode
bit, DMAC_CTRLBx.AUTO. This puts the DMAC into Row 1 as shown in Table 271 on page 329. If the next buffer is not the last buffer in the DMAC transfer then the
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automatic transfer mode bit should remain enabled to keep the DMAC in Row 11 as
shown in Table 27-1 on page 329.
b.
If the buffer complete interrupt is masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is
the channel number) then hardware does not stall until it detects a write to the buffer transfer completed interrupt enable register but starts the next buffer transfer
immediately. In this case software must clear the automatic mode bit,
DMAC_CTRLBx.AUTO, to put the device into ROW 1 of Table 27-1 on page 329
before the last buffer of the DMAC transfer has completed.
The transfer is similar to that shown in Figure 27-13 on page 344.
The DMAC Transfer flow is shown in Figure 27-14 on page 345.
Figure 27-13. Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address
Address of
Destination Layer
Address of
Source Layer
Buffer2
DADDR(2)
Buffer1
DADDR(1)
Buffer0
SADDR
DADDR(0)
Source Buffers
Destination Buffers
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Figure 27-14. DMAC Transfer Replay Mode is Enabled for the Source and Contiguous Destination Address
Channel Enabled by
software
Buffer Transfer
Replay mode for SADDRx,
Contiguous mode for DADDRx
CTRLAx, CTRLBx
Buffer Complete interrupt
generated here
Buffer Transfer Complete
interrupt generated here
yes
Is HDMA in Row1of
HDMA State Machine Table?
Channel Disabled by
hardware
no
no
DMA_EBCIMR[x]=1?
yes
Stall until STALLED field is
cleared by software writing
KEEPON Field
27.3.5.7
Multi-buffer DMAC Transfer with Linked List for Source and Contiguous Destination Address (Row 2)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the linked list in memory. Write the control information in the
LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx register location of the buffer descriptor
for each LLI in memory for channel x. For example, in the register, you can program the
following:
a. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx
register.
b.
Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_WIDTH field.
– ii. Transfer width for the destination in the DST_WIDTH field.
– iii. Source AHB master interface layer in the SIF field where source resides.
– iv. Destination AHB master interface layer in the DIF field where destination resides.
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– v. Incrementing/decrementing or fixed address for source in SRC_INCR field.
– vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
3. Write the starting destination address in the DMAC_DADDRx register for channel x.
Note:
The values in the LLI.DMAC_DADDRx register location of each Linked List Item (LLI) in memory,
although fetched during an LLI fetch, are not used.
4. Write the channel configuration information into the DMAC_CFGx register for channel
x.
a. Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates
the hardware handshaking interface to handle source/destination requests for the
specific channel. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests.
b.
If the hardware handshaking interface is activated for the source or destination
peripheral, assign handshaking interface to the source and destination peripherals.
This requires programming the SRC_PER and DST_PER bits, respectively.
5. Make sure that all LLI.DMAC_CTRLBx register locations of the LLI (except the last) are
set as shown in Row 2 of Table 27-1 on page 329, while the LLI.DMAC_CTRLBx register of the last Linked List item must be set as described in Row 1 of Table 27-1. Figure
27-5 on page 328 shows a Linked List example with two list items.
6. Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except
the last) are non-zero and point to the next Linked List Item.
7. Make sure that the LLI.DMAC_SADDRx register location of all LLIs in memory point to
the start source buffer address proceeding that LLI fetch.
8. Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register
locations of all LLIs in memory is cleared.
9. If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the
DMAC_SPIPx register for channel x.
10. If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP is enabled), program
the DMAC_DPIPx register for channel x.
11. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register.
12. Program the DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx registers according
to Row 2 as shown in Table 27-1 on page 329
13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first
Linked List item.
14. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit. The
transfer is performed. Make sure that bit 0 of the DMAC_EN register is enabled.
15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
Note:
The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI.DMAC_DSCRx and LLI.DMAC_CTRLA/Bx
registers are fetched. The LLI.DMAC_DADDRx register location of the LLI although fetched is not
used. The DMAC_DADDRx register in the DMAC remains unchanged.
16. Source and destination requests single and chunk DMAC transactions to transfer the
buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the
completion of every transaction (chunk and single) in the buffer and carry out the buffer
transfer
17. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to system memory at the same location and on the same layer (DMAC_DSCRx.DSCR_IF)
where it was originally fetched, that is, the location of the DMAC_CTRLAx register of
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the linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx
register is written out because only the DMAC_CTRLAx.BTSIZE and
DMAC_CTRLAX.DONE fields have been updated by DMAC hardware. Additionally, the
DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed.
Note:
Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is
asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared
at the start of the transfer.
18. The DMAC does not wait for the buffer interrupt to be cleared, but continues and
fetches the next LLI from the memory location pointed to by current DMAC_DSCRx
register and automatically reprograms the DMAC_SADDRx, DMAC_CTRLAx,
DMAC_CTRLBx and DMAC_DSCRx channel registers. The DMAC_DADDRx register
is left unchanged. The DMAC transfer continues until the DMAC samples the
DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer
transfer match that described in Row 1 of Table 27-1 on page 329. The DMAC then
knows that the previous buffer transferred was the last buffer in the DMAC transfer.
The DMAC transfer might look like that shown in Figure 27-15 on page 347 Note that the destination address is decrementing.
Figure 27-15. DMAC Transfer with Linked List Source Address and Contiguous Destination Address
Address of
Source Layer
Address of
Destination Layer
Buffer 2
SADDR(2)
Buffer 2
DADDR(2)
Buffer 1
Buffer 1
SADDR(1)
DADDR(1)
Buffer 0
DADDR(0)
Buffer 0
SADDR(0)
Source Buffers
Destination Buffers
The DMAC transfer flow is shown in Figure 27-16 on page 348.
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Figure 27-16. DMAC Transfer Flow for Linked List Source Address and Contiguous Destination Address
Channel Enabled by
software
LLI Fetch
Hardware reprograms
SADDRx, CTRLAx,CTRLBx, DSCRx
HDMA buffer transfer
Writeback of control
information of LLI
Buffer Complete interrupt
generated here
Is HDMA in
Row 1 ?
HDMA Transfer Complete
interrupt generated here
no
yes
Channel Disabled by
hardware
27.3.6
Disabling a Channel Prior to Transfer Completion
Under normal operation, software enables a channel by writing a ‘1’ to the Channel Handler
Enable Register, DMAC_CHER.ENABLE[n], and hardware disables a channel on transfer completion by clearing the DMAC_CHSR.ENABLE[n] register bit.
The recommended way for software to disable a channel without losing data is to use the SUSPEND[n] bit in conjunction with the EMPTY[n] bit in the Channel Handler Status Register.
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1. If software wishes to disable a channel n prior to the DMAC transfer completion, then it
can set the DMAC_CHER.SUSPEND[n] bit to tell the DMAC to halt all transfers from
the source peripheral. Therefore, the channel FIFO receives no new data.
2. Software can now poll the DMAC_CHSR.EMPTY[n] bit until it indicates that the channel
n FIFO is empty, where n is the channel number.
3. The DMAC_CHER.ENABLE[n] bit can then be cleared by software once the channel n
FIFO is empty, where n is the channel number.
When DMAC_CTRLAx.SRC_WIDTH is less than DMAC_CTRLAx.DST_WIDTH and the
DMAC_CHSRx.SUSPEND[n] bit is high, the DMAC_CHSRx.EMPTY[n] is asserted once the
contents of the FIFO do not permit a single word of DMAC_CTRLAx.DST_WIDTH to be formed.
However, there may still be data in the channel FIFO but not enough to form a single transfer of
DMAC_CTLx.DST_WIDTH width. In this configuration, once the channel is disabled, the remaining data in the channel FIFO are not transferred to the destination peripheral. It is permitted to
remove the channel from the suspension state by writing a ‘1’ to the DMAC_CHER.RESUME[n]
field register. The DMAC transfer completes in the normal manner. n defines the channel
number.
Note:
27.3.6.1
If a channel is disabled by software, an active single or chunk transaction is not guaranteed to
receive an acknowledgement.
Abnormal Transfer Termination
A DMAC transfer may be terminated abruptly by software by clearing the channel enable bit,
DMAC_CHDR.ENABLE[n] where n is the channel number. This does not mean that the channel
is disabled immediately after the DMAC_CHSR.ENABLE[n] bit is cleared over the APB interface. Consider this as a request to disable the channel. The DMAC_CHSR.ENABLE[n] must be
polled and then it must be confirmed that the channel is disabled by reading back 0.
Software may terminate all channels abruptly by clearing the global enable bit in the DMAC Configuration Register (DMAC_EN.ENABLE bit). Again, this does not mean that all channels are
disabled immediately after the DMAC_EN.ENABLE is cleared over the APB slave interface.
Consider this as a request to disable all channels. The DMAC_CHSR.ENABLE must be polled
and then it must be confirmed that all channels are disabled by reading back ‘0’.
27.4
Note:
If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to
the destination peripheral and is not present when the channel is re-enabled. For read sensitive
source peripherals, such as a source FIFO, this data is therefore lost. When the source is not a
read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to
empty may be acceptable as the data is available from the source peripheral upon request and is
not lost.
Note:
If a channel is disabled by software, an active single or chunk transaction is not guaranteed to
receive an acknowledgement.
DMAC Software Requirements
• There must not be any write operation to Channel registers in an active channel after the
channel enable is made HIGH. If any channel parameters must be reprogrammed, this can
only be done after disabling the DMAC channel.
• When destination peripheral is defined as the flow controller, source single transfer request
are not serviced until Destination Peripheral has asserted its Last Transfer Flag.
• When Source Peripheral is flow controller, destination single transfer request are not serviced
until Source Peripheral has asserted its Last Transfer Flag.
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• When destination peripheral is defined as the flow controller, if the destination width is
smaller than the source width, then a data loss may occur, and the loss is equal to Source
Single Transfer size in bytes- destination Single Transfer size in bytes.
• When a Memory to Peripheral transfer occurs if the destination peripheral is flow controller,
then a prefetch operation is performed. It means that data are extracted from memory before
any request from the peripheral is generated.
• You must program the DMAC_SADDRx and DMAC_DADDRx channel registers with a byte,
half-word and word aligned address depending on the source width and destination width.
• After the software disables a channel by writing into the channel disable register, it must reenable the channel only after it has polled a 0 in the corresponding channel enable status
register. This is because the current AHB Burst must terminate properly.
• If you program the BTSIZE field in the DMAC_CTRLA, as zero, and the DMAC is defined as
the flow controller, then the channel is automatically disabled.
• When hardware handshaking interface protocol is fully implemented, a peripheral is expected
to deassert any sreq or breq signals on receiving the ack signal irrespective of the request
the ack was asserted in response to.
• Multiple Transfers involving the same peripheral must not be programmed and enabled on
different channel, unless this peripheral integrates several hardware handshaking interface.
• When a Peripheral is flow controller, the targeted DMAC Channel must be enabled before the
Peripheral. If you do not ensure this the DMAC Channel might miss a Last Transfer Flag, if
the First DMAC request is also the last transfer.
• When AUTO Field is set to TRUE, then the BTSIZE Field is automatically reloaded from its
previous value. BTSIZE must be initialized to a non zero value if the first transfer is initiated
with AUTO field set to TRUE even if LLI mode is enabled because the LLI fetch operation will
not update this field.
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27.5
DMA Controller (DMAC) User Interface
Table 27-2.
Register Mapping
Offset
Register
Name
Access
Reset
0x000
DMAC Global Configuration Register
DMAC_GCFG
Read-write
0x10
0x004
DMAC Enable Register
DMAC_EN
Read-write
0x0
0x008
DMAC Software Single Request Register
DMAC_SREQ
Read-write
0x0
0x00C
DMAC Software Chunk Transfer Request Register
DMAC_CREQ
Read-write
0x0
0x010
DMAC Software Last Transfer Flag Register
DMAC_LAST
Read-write
0x0
0x014
DMAC Request Synchronization Register
DMAC_SYNC
Read-write
0x0
0x018
DMAC Error, Chained Buffer transfer completed and Buffer
transfer completed Interrupt Enable register.
DMAC_EBCIER
Write-only
–
0x01C
DMAC Error, Chained Buffer transfer completed and Buffer
transfer completed Interrupt Disable register.
DMAC_EBCIDR
Write-only
–
0x020
DMAC Error, Chained Buffer transfer completed and Buffer
transfer completed Mask Register.
DMAC_EBCIMR
Read-only
0x0
0x024
DMAC Error, Chained Buffer transfer completed and Buffer
transfer completed Status Register.
DMAC_EBCISR
Read-only
0x0
0x028
DMAC Channel Handler Enable Register
DMAC_CHER
Write-only
–
0x02C
DMAC Channel Handler Disable Register
DMAC_CHDR
Write-only
–
0x030
DMAC Channel Handler Status Register
DMAC_CHSR
Read-only
0x00FF0000
0x034
Reserved
–
–
–
0x038
Reserved
–
–
–
0x03C+ch_num*(0x28)+(0x0)
DMAC Channel Source Address Register
DMAC_SADDR
Read-write
0x0
0x03C+ch_num*(0x28)+(0x4)
DMAC Channel Destination Address Register
DMAC_DADDR
Read-write
0x0
0x03C+ch_num*(0x28)+(0x8)
DMAC Channel Descriptor Address Register
DMAC_DSCR
Read-write
0x0
0x03C+ch_num*(0x28)+(0xC)
DMAC Channel Control A Register
DMAC_CTRLA
Read-write
0x0
0x03C+ch_num*(0x28)+(0x10)
DMAC Channel Control B Register
DMAC_CTRLB
Read-write
0x0
0x03C+ch_num*(0x28)+(0x14)
DMAC Channel Configuration Register
DMAC_CFG
Read-write
0x01000000
0x03C+ch_num*(0x28)+(0x18)
DMAC Channel Source Picture in Picture Configuration
Register
DMAC_SPIP
Read-write
0x0
0x03C+ch_num*(0x28)+(0x1C)
DMAC Channel Destination Picture in Picture Configuration
Register
DMAC_DPIP
Read-write
0x0
0x03C+ch_num*(0x28)+(0x20)
Reserved
–
–
–
0x03C+ch_num*(0x28)+(0x24)
Reserved
–
–
–
0x064 - 0x100
DMAC Channel 1 to 3 Register(1)
Read-write
0x0
0x017C- 0x1FC
Reserved
–
–
Note:
–
1. The addresses for the DMAC registers shown here are for DMA Channel 0. This sequence of registers is repeated successively for each DMA channel located between 0x064 and 0x100.
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27.5.1
Name:
DMAC Global Configuration Register
DMAC_GCFG
Address:
0xFFFFEC00
Access:
Read-write
Reset:
0x00000010
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
ARB_CFG
3
–
2
–
1
–
0
IF0_BIGEND
• IF0_BIGEND
0: AHB-Lite Interface 0 is little endian.
1: AHB-Lite Interface 0 is big endian.
• ARB_CFG
0: Fixed priority arbiter.
1: Modified round robin arbiter.
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27.5.2
Name:
DMAC Enable Register
DMAC_EN
Address:
0xFFFFEC04
Access:
Read-write
Reset: 0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
ENABLE
• ENABLE
0: DMA Controller is disabled.
1: DMA Controller is enabled.
27.5.3
Name:
DMAC Software Single Request Register
DMAC_SREQ
Address:
0xFFFFEC08
Access:
Read-write
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
DSREQ3
6
SSREQ3
5
DSREQ2
4
SSREQ2
3
DSREQ1
2
SSREQ1
1
DSREQ0
0
SSREQ0
• DSREQx
Request a destination single transfer on channel i.
• SSREQx
Request a source single transfer on channel i.
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27.5.4
Name:
DMAC Software Chunk Transfer Request Register
DMAC_CREQ
Address:
0xFFFFEC0C
Access:
Read-write
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
DCREQ3
6
SCREQ3
5
DCREQ2
4
SCREQ2
3
DCREQ1
2
SCREQ1
1
DCREQ0
0
SCREQ0
• DCREQx
Request a destination chunk transfer on channel i.
• SCREQx
Request a source chunk transfer on channel i.
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27.5.5
Name:
DMAC Software Last Transfer Flag Register
DMAC_LAST
Address:
0xFFFFEC10
Access:
Read-write
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
DLAST3
6
SLAST3
5
DLAST2
4
SLAST2
3
DLAST1
2
SLAST1
1
DLAST0
0
SLAST0
• DLASTx
Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer
of the buffer.
• SLASTx
Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of
the buffer.
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27.5.6
Name:
DMAC Request Synchronization Register
DMAC_SYNC
Address:
0xFFFFEC14
Access:
Read-write
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
–
7
SYR7
6
SYR6
5
SYR5
4
SYR4
3
SYR3
2
SYR2
1
SYR1
0
SYR0
• SYR[7:0]
Request Synchronizer Register. Write one to DMAC_SYNCx to synchronize peripheral i request lines.
356
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
27.5.7
Name:
DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register
DMAC_EBCIER
Address:
0xFFFFEC18
Access:
Write-only
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
ERR3
18
ERR2
17
ERR1
16
ERR0
15
–
14
–
13
–
12
–
11
CBTC3
10
CBTC2
9
CBTC1
8
CBTC0
7
–
6
–
5
–
4
–
3
BTC3
2
BTC2
1
BTC1
0
BTC0
• BTC[3:0]
Buffer Transfer Completed Interrupt Enable Register. Set the relevant bit in the BTC field to enable the interrupt for channel
i.
• CBTC[3:0]
Chained Buffer Transfer Completed Interrupt Enable Register. Set the relevant bit in the CBTC field to enable the interrupt
for channel i.
• ERR[3:0]
Access Error Interrupt Enable Register. Set the relevant bit in the ERR field to enable the interrupt for channel i.
357
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
27.5.8
Name:
DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register
DMAC_EBCIDR
Address:
0xFFFFEC1C
Access:
Write-only
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
ERR3
18
ERR2
17
ERR1
16
ERR0
15
–
14
–
13
–
12
–
11
CBTC3
10
CBTC2
9
CBTC1
8
CBTC0
7
–
6
–
5
–
4
–
3
BTC3
2
BTC2
1
BTC1
0
BTC0
• BTC[3:0]
Buffer transfer completed Disable Interrupt Register. When set, a bit of the BTC field disables the interrupt from the relevant DMAC channel.
• CBTC[3:0]
Chained Buffer transfer completed Disable Register. When set, a bit of the CBTC field disables the interrupt from the relevant DMAC channel.
• ERR[3:0]
Access Error Interrupt Disable Register. When set, a bit of the ERR field disables the interrupt from the relevant DMAC
channel.
358
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
27.5.9
Name:
DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register
DMAC_EBCIMR
Address:
0xFFFFEC20
Access:
Read-only
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
ERR3
18
ERR2
17
ERR1
16
ERR0
15
–
14
–
13
–
12
–
11
CBTC3
10
CBTC2
9
CBTC1
8
CBTC0
7
–
6
–
5
–
4
–
3
BTC3
2
BTC2
1
BTC1
0
BTC0
• BTC[3:0]
0: Buffer Transfer completed interrupt is disabled for channel i.
1: Buffer Transfer completed interrupt is enabled for channel i.
• CBTC[3:0]
0: Chained Buffer Transfer interrupt is disabled for channel i.
1: Chained Buffer Transfer interrupt is enabled for channel i.
• ERR[3:0]
0: Transfer Error Interrupt is disabled for channel i.
1: Transfer Error Interrupt is enabled for channel i.
359
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
27.5.10
Name:
DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register
DMAC_EBCISR
Address:
0xFFFFEC24
Access:
Read-only
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
ERR3
18
ERR2
17
ERR1
16
ERR0
15
–
14
–
13
–
12
–
11
CBTC3
10
CBTC2
9
CBTC1
8
CBTC0
7
–
6
–
5
–
4
–
3
BTC3
2
BTC2
1
BTC1
0
BTC0
• BTC[3:0]
When BTC[i] is set, Channel i buffer transfer has terminated.
• CBTC[3:0]
When CBTC[i] is set, Channel i Chained buffer has terminated. LLI Fetch operation is disabled.
• ERR[3:0]
When ERR[i] is set, Channel i has detected an AHB Read or Write Error Access.
360
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
27.5.11
Name:
DMAC Channel Handler Enable Register
DMAC_CHER
Address:
0xFFFFEC28
Access:
Write-only
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
KEEP3
26
KEEP2
25
KEEP1
24
KEEP0
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
SUSP3
10
SUSP2
9
SUSP1
8
SUSP0
7
–
6
–
5
–
4
–
3
ENA3
2
ENA2
1
ENA1
0
ENA0
• ENA[3:0]
When set, a bit of the ENA field enables the relevant channel.
• SUSP[3:0]
When set, a bit of the SUSPfield freezes the relevant channel and its current context.
• KEEP[3:0]
When set, a bit of the KEEP field resumes the current channel from an automatic stall state.
361
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
27.5.12
Name:
DMAC Channel Handler Disable Register
DMAC_CHDR
Address:
0xFFFFEC2C
Access:
Write-only
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
RES3
10
RES2
9
RES1
8
RES0
7
–
6
–
5
–
4
–
3
DIS3
2
DIS2
1
DIS1
0
DIS0
• DIS[3:0]
Write one to this field to disable the relevant DMAC Channel. The content of the FIFO is lost and the current AHB access is
terminated. Software must poll DIS[3:0] field in the DMAC_CHSR register to be sure that the channel is disabled.
• RES[3:0]
Write one to this field to resume the channel transfer restoring its context.
362
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
27.5.13
Name:
DMAC Channel Handler Status Register
DMAC_CHSR
Address:
0xFFFFEC30
Access:
Read-only
Reset:
0x00FF0000
31
–
30
–
29
–
28
–
27
STAL3
26
STAL2
25
STAL1
24
STAL0
23
–
22
–
21
–
20
–
19
EMPT3
18
EMPT2
17
EMPT1
16
EMPT0
15
–
14
–
13
–
12
–
11
SUSP3
10
SUSP2
9
SUSP1
8
SUSP0
7
–
6
–
5
–
4
–
3
ENA3
2
ENA2
1
ENA1
0
ENA0
• ENA[3:0]
A one in any position of this field indicates that the relevant channel is enabled.
• SUSP[3:0]
A one in any position of this field indicates that the channel transfer is suspended.
• EMPT[3:0]
A one in any position of this field indicates that the relevant channel is empty.
• STAL[3:0]
A one in any position of this field indicates that the relevant channel is stalling.
363
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
27.5.14
Name:
DMAC Channel x [x = 0..3] Source Address Register
DMAC_SADDRx [x = 0..3]
Addresses: 0xFFFFEC3C [0], 0xFFFFEC64 [1], 0xFFFFEC8C [2], 0xFFFFECB4 [3]
Access:
Read-write
Reset:
0x00000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
SADDRx
23
22
21
20
SADDRx
15
14
13
12
SADDRx
7
6
5
4
SADDRx
• SADDRx
Channel x source address. This register must be aligned with the source transfer width.
364
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
27.5.15
Name:
DMAC Channel x [x = 0..3] Destination Address Register
DMAC_DADDRx [x = 0..3]
Addresses: 0xFFFFEC40 [0], 0xFFFFEC68 [1], 0xFFFFEC90 [2], 0xFFFFECB8 [3]
Access:
Read-write
Reset:
0x00000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
DADDRx
23
22
21
20
DADDRx
15
14
13
12
DADDRx
7
6
5
4
DADDRx
• DADDRx
Channel x destination address. This register must be aligned with the destination transfer width.
365
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
27.5.16
Name:
DMAC Channel x [x = 0..3] Descriptor Address Register
DMAC_DSCRx [x = 0..3]
Addresses: 0xFFFFEC44 [0], 0xFFFFEC6C [1], 0xFFFFEC94 [2], 0xFFFFECBC [3]
Access:
Read-write
Reset:
0x00000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
DSCRx
23
22
21
20
DSCRx
15
14
13
12
DSCRx
7
6
5
4
DSCRx
DSCRx_IF
• DSCRx_IF
00: The Buffer Transfer descriptor is fetched via AHB-Lite Interface 0.
01: Reserved.
10: Reserved.
11: Reserved.
• DSCRx
Buffer Transfer descriptor address. This address is word aligned.
366
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
27.5.17
Name:
DMAC Channel x [x = 0..3] Control A Register
DMAC_CTRLAx [x = 0..3]
Addresses: 0xFFFFEC48 [0], 0xFFFFEC70 [1], 0xFFFFEC98 [2], 0xFFFFECC0 [3]
Access:
Read-write
Reset:
0x00000000
31
DONE
30
–
29
28
23
–
22
21
DCSIZE
20
15
14
13
12
DST_WIDTH
27
–
26
–
25
24
19
–
18
17
SCSIZE
16
11
10
9
8
3
2
1
0
SRC_WIDTH
BTSIZE
7
6
5
4
BTSIZE
• BTSIZE
Buffer Transfer Size. The transfer size relates to the number of transfers to be performed, that is, for writes it refers to the
number of source width transfers to perform when DMAC is flow controller. For Reads, BTSIZE refers to the number of
transfers completed on the Source Interface. When this field is set to 0, the DMAC module is automatically disabled when
the relevant channel is enabled.
• SCSIZE
Source Chunk Transfer Size.
SCSIZE value
Number of data transferred
000
1
001
4
010
8
011
16
100
32
101
64
110
128
111
256
• DCSIZE
Destination Chunk Transfer size.
DCSIZE
Number of data transferred
000
1
001
4
010
8
011
16
367
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
DCSIZE
Number of data transferred
100
32
101
64
110
128
111
256
• SRC_WIDTH
SRC_WIDTH
Single Transfer Size
00
BYTE
01
HALF-WORD
1X
WORD
• DST_WIDTH
DST_WIDTH
Single Transfer Size
00
BYTE
01
HALF-WORD
1X
WORD
• DONE
0: The transfer is performed.
1: If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the content of this register.
The DONE field is written back to memory at the end of the transfer.
368
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
27.5.18
Name:
DMAC Channel x [x = 0..3] Control B Register
DMAC_CTRLBx [x = 0..3]
Addresses: 0xFFFFEC4C [0], 0xFFFFEC74 [1], 0xFFFFEC9C [2], 0xFFFFECC4 [3]
Access:
Read-write
Reset:
0x00000000
31
AUTO
30
IEN
29
23
22
FC
21
15
–
14
–
7
–
6
–
28
27
–
26
–
25
20
DST_DSCR
19
–
18
–
17
–
16
SRC_DSCR
13
12
DST_PIP
11
–
10
–
9
–
8
SRC_PIP
5
4
3
–
2
–
1
0
DST_INCR
DIF
24
SRC_INCR
SIF
• SIF: Source Interface Selection Field
00: The source transfer is done via AHB-Lite Interface 0.
01: Reserved.
10: Reserved.
11: Reserved.
• DIF: Destination Interface Selection Field
00: The destination transfer is done via AHB-Lite Interface 0.
01: Reserved.
10: Reserved.
11: Reserved.
• SRC_PIP
0: Picture-in-Picture mode is disabled. The source data area is contiguous.
1: Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is
automatically increment of a user defined amount.
• DST_PIP
0: Picture-in-Picture mode is disabled. The Destination data area is contiguous.
1: Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address
is automatically incremented by a user-defined amount.
• SRC_DSCR
0: Source address is updated when the descriptor is fetched from the memory.
1: Buffer Descriptor Fetch operation is disabled for the source.
369
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• DST_DSCR
0: Destination address is updated when the descriptor is fetched from the memory.
1: Buffer Descriptor Fetch operation is disabled for the destination.
• FC
This field defines which device controls the size of the buffer transfer, also referred as to the Flow Controller.
FC
Type of transfer
Flow Controller
000
Memory-to-Memory
DMA Controller
001
Memory-to-Peripheral
DMA Controller
010
Peripheral-to-Memory
DMA Controller
011
Peripheral-to-Peripheral
DMA Controller
100
Peripheral-to-Memory
Peripheral
101
Memory-to-Peripheral
Peripheral
110
Peripheral-to-Peripheral
Source Peripheral
111
Peripheral-to-Peripheral
Destination Peripheral
• SRC_INCR
SRC_INCR
Type of addressing mode
00
INCREMENTING
01
DECREMENTING
10
FIXED
• DST_INCR
DST_INCR
Type of addressing scheme
00
INCREMENTING
01
DECREMENTING
10
FIXED
• IEN
If this bit is cleared, when the buffer transfer is completed, the BTC[x] flag is set in the EBCISR status register. This bit is
active low.
• AUTO
Automatic multiple buffer transfer is enabled. When set, this bit enables replay mode or contiguous mode when several buffers are transferred.
370
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
27.5.19
Name:
DMAC Channel x [x = 0..3] Configuration Register
DMAC_CFGx [x = 0..3]
Addresses: 0xFFFFEC50 [0], 0xFFFFEC78 [1], 0xFFFFECA0 [2], 0xFFFFECC8 [3]
Access:
Read-write
Reset:
0x0100000000
31
–
30
–
29
28
27
–
26
25
AHB_PROT
24
23
–
22
LOCK_IF_L
21
LOCK_B
20
LOCK_IF
19
–
18
–
17
–
16
SOD
15
–
14
–
13
DST_H2SEL
12
DST_REP
11
–
10
–
9
SRC_H2SEL
8
SRC_REP
7
6
5
4
3
2
1
0
FIFOCFG
DST_PER
SRC_PER
• SRC_PER
Channel x Source Request is associated with peripheral identifier coded SRC_PER handshaking interface.
• DST_PER
Channel x Destination Request is associated with peripheral identifier coded DST_PER handshaking interface.
• SRC_REP
0: When automatic mode is activated, source address is contiguous between two buffers.
1: When automatic mode is activated, the source address and the control register are reloaded from previous transfer.
• SRC_H2SEL
0: Software handshaking interface is used to trigger a transfer request.
1: Hardware handshaking interface is used to trigger a transfer request.
• DST_REP
0: When automatic mode is activated, destination address is contiguous between two buffers.
1: When automatic mode is activated, the destination and the control register are reloaded from the previous transfer.
• DST_H2SEL
0: Software handshaking interface is used to trigger a transfer request.
1: Hardware handshaking interface is used to trigger a transfer request.
• SOD
0: STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
1: STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
• LOCK_IF
0: Interface Lock capability is disabled
371
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
1: Interface Lock capability is enabled
• LOCK_B
0: AHB Bus Locking capability is disabled.
1: AHB Bus Locking capability is enabled.
• LOCK_IF_L
0: The Master Interface Arbiter is locked by the channel x for a chunk transfer.
1: The Master Interface Arbiter is locked by the channel x for a buffer transfer.
• AHB_PROT
AHB_PROT field provides additional information about a bus access and is primarily used to implement some level of
protection.
HPROT[3]
HPROT[2]
HPROT[1]
HPROT[0]
Description
1
Data access
0: User Access
1: Privileged Access
AHB_PROT[0]
0: Not Bufferable
1: Bufferable
AHB_PROT[1]
0: Not cacheable
1: Cacheable
AHB_PROT[2]
• FIFOCFG
FIFOCFG
FIFO request
00
The largest defined length AHB burst is performed on the destination AHB interface.
01
When half FIFO size is available/filled, a source/destination request is serviced.
10
When there is enough space/data available to perform a single AHB access, then the request is serviced.
372
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
27.5.20
Name:
DMAC Channel x [x = 0..3] Source Picture in Picture Configuration Register
DMAC_SPIPx [x = 0..3]
Addresses: 0xFFFFEC54 [0], 0xFFFFEC7C [1], 0xFFFFECA4 [2], 0xFFFFECCC [3]
Access:
Read-write
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
24
SPIP_BOUNDARY
23
22
21
20
19
SPIP_BOUNDARY
18
17
16
15
14
13
12
11
10
9
8
3
2
1
0
SPIP_HOLE
7
6
5
4
SPIP_HOLE
• SPIP_HOLE
This field indicates the value to add to the address when the programmable boundary has been reached.
• SPIP_BOUNDARY
This field indicates the number of source transfers to perform before the automatic address increment operation.
373
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
27.5.21
Name:
DMAC Channel x [x = 0..3] Destination Picture in Picture Configuration Register
DMAC_DPIPx [x = 0..3]
Addresses:
0xFFFFEC58 [0], 0xFFFFEC80 [1], 0xFFFFECA8 [2], 0xFFFFECD0 [3]
Access:
Read-write
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
24
DPIP_BOUNDARY
23
22
21
20
19
DPIP_BOUNDARY
18
17
16
15
14
13
12
11
10
9
8
3
2
1
0
DPIP_HOLE
7
6
5
4
DPIP_HOLE
• DPIP_HOLE
This field indicates the value to add to the address when the programmable boundary has been reached.
• DPIP_BOUNDARY
This field indicates the number of source transfers to perform before the automatic address increment operation.
374
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
28. Peripheral DMA Controller (PDC)
28.1
Description
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the
on- and/or off-chip memories. The link between the PDC and a serial peripheral is operated by
the AHB to ABP bridge.
The PDC contains 24 channels. The full-duplex peripherals feature 22 mono directional channels used in pairs (transmit only or receive only). The half-duplex peripherals feature 2 bidirectional channels.
The user interface of each PDC channel is integrated into the user interface of the peripheral it
serves. The user interface of mono directional channels (receive only or transmit only), contains
two 32-bit memory pointers and two 16-bit counters, one set (pointer, counter) for current transfer and one set (pointer, counter) for next transfer. The bi-directional channel user interface
contains four 32-bit memory pointers and four 16-bit counters. Each set (pointer, counter) is
used by current transmit, next transmit, current receive and next receive.
Using the PDC removes processor overhead by reducing its intervention during the transfer.
This significantly reduces the number of clock cycles required for a data transfer, which
improves microcontroller performance.
To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and
receive signals. When the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself.
375
6264C–CAP–24-Mar-09
28.2
Block Diagram
Figure 28-1. Block Diagram
FULL DUPLEX
PERIPHERAL
PDC
THR
PDC Channel A
RHR
PDC Channel B
Control
Status & Control
HALF DUPLEX
PERIPHERAL
Control
THR
PDC Channel C
RHR
Control
Status & Control
RECEIVE or TRANSMIT
PERIPHERAL
RHR or THR
Control
28.3
28.3.1
PDC Channel D
Status & Control
Functional Description
Configuration
The PDC channel user interface enables the user to configure and control data transfers for
each channel. The user interface of each PDC channel is integrated into the associated peripheral user interface.
The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit
pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR,
TNCR). However, the transmit and receive parts of each type are programmed differently: the
376
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
transmit and receive parts of a full duplex peripheral can be programmed at the same time,
whereas only one part (transmit or receive) of a half duplex peripheral can be programmed at a
time.
32-bit pointers define the access location in memory for current and next transfer, whether it is
for read (transmit) or write (receive). 16-bit counters define the size of current and next transfers.
It is possible, at any moment, to read the number of transfers left for each channel.
The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for
each channel. The status for each channel is located in the associated peripheral status register.
Transfers can be enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in
the peripheral’s Transfer Control Register.
At the end of a transfer, the PDC channel sends status flags to its associated peripheral. These
flags are visible in the peripheral status register (ENDRX, ENDTX, RXBUFF, and TXBUFE).
Refer to Section 1.3.3 and to the associated peripheral user interface.
28.3.2
Memory Pointers
Each full duplex peripheral is connected to the PDC by a receive channel and a transmit channel. Both channels have 32-bit memory pointers that point respectively to a receive area and to
a transmit area in on- and/or off-chip memory.
Each half duplex peripheral is connected to the PDC by a bidirectional channel. This channel
has two 32-bit memory pointers, one for current transfer and the other for next transfer. These
pointers point to transmit or receive data depending on the operating mode of the peripheral.
Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented
respectively by 1, 2 or 4 bytes.
If a memory pointer address changes in the middle of a transfer, the PDC channel continues
operating using the new address.
28.3.3
Transfer Counters Access
Each channel has two 16-bit counters, one for current transfer and the other one for next transfer. These counters define the size of data to be transferred by the channel. The current transfer
counter is decremented first as the data addressed by current memory pointer starts to be transferred. When the current transfer counter reaches zero, the channel checks its next transfer
counter. If the value of next counter is zero, the channel stops transferring data and sets the
appropriate flag. But if the next counter value is greater then zero, the values of the next
pointer/next counter are copied into the current pointer/current counter and the channel resumes
the transfer whereas next pointer/next counter get zero/zero as values. At the end of this transfer the PDC channel sets the appropriate flags in the Peripheral Status Register.
The following list gives an overview of how status register flags behave depending on the counters’ values:
• ENDRX flag is set when the PERIPH_RCR register reaches zero.
• RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero.
• ENDTX flag is set when the PERIPH_TCR register reaches zero.
• TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero.
These status flags are described in the Peripheral Status Register.
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6264C–CAP–24-Mar-09
28.3.4
Data Transfers
The serial peripheral triggers its associated PDC channels’ transfers using transmit enable
(TXEN) and receive enable (RXEN) flags in the transfer control register integrated in the peripheral’s user interface.
When the peripheral receives an external data, it sends a Receive Ready signal to its PDC
receive channel which then requests access to the Matrix. When access is granted, the PDC
receive channel starts reading the peripheral Receive Holding Register (RHR). The read data
are stored in an internal buffer and then written to memory.
When the peripheral is about to send data, it sends a Transmit Ready to its PDC transmit channel which then requests access to the Matrix. When access is granted, the PDC transmit
channel reads data from memory and puts them to Transmit Holding Register (THR) of its associated peripheral. The same peripheral sends data according to its mechanism.
28.3.5
PDC Flags and Peripheral Status Register
Each peripheral connected to the PDC sends out receive ready and transmit ready flags and the
PDC sends back flags to the peripheral. All these flags are only visible in the Peripheral Status
Register.
Depending on the type of peripheral, half or full duplex, the flags belong to either one single
channel or two different channels.
28.3.5.1
Receive Transfer End
This flag is set when PERIPH_RCR register reaches zero and the last data has been transferred
to memory.
It is reset by writing a non zero value in PERIPH_RCR or PERIPH_RNCR.
28.3.5.2
Transmit Transfer End
This flag is set when PERIPH_TCR register reaches zero and the last data has been written into
peripheral THR.
It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
28.3.5.3
Receive Buffer Full
This flag is set when PERIPH_RCR register reaches zero with PERIPH_RNCR also set to zero
and the last data has been transferred to memory.
It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
28.3.5.4
Transmit Buffer Empty
This flag is set when PERIPH_TCR register reaches zero with PERIPH_TNCR also set to zero
and the last data has been written into peripheral THR.
It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
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28.4
Peripheral DMA Controller (PDC) User Interface
Table 28-1.
Register Mapping
Offset
Register
Name
(1)
Access
Reset
0x100
Receive Pointer Register
PERIPH _RPR
Read-write
0
0x104
Receive Counter Register
PERIPH_RCR
Read-write
0
0x108
Transmit Pointer Register
PERIPH_TPR
Read-write
0
0x10C
Transmit Counter Register
PERIPH_TCR
Read-write
0
0x110
Receive Next Pointer Register
PERIPH_RNPR
Read-write
0
0x114
Receive Next Counter Register
PERIPH_RNCR
Read-write
0
0x118
Transmit Next Pointer Register
PERIPH_TNPR
Read-write
0
0x11C
Transmit Next Counter Register
PERIPH_TNCR
Read-write
0
0x120
Transfer Control Register
PERIPH_PTCR
Write-only
0
0x124
Transfer Status Register
PERIPH_PTSR
Read-only
0
Note:
1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user
according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI, etc.)
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28.4.1
Name:
Receive Pointer Register
PERIPH_RPR
Access:
31
Read-write
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
RXPTR
23
22
21
20
RXPTR
15
14
13
12
RXPTR
7
6
5
4
RXPTR
• RXPTR: Receive Pointer Register
RXPTR must be set to receive buffer address.
When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
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28.4.2
Name:
Receive Counter Register
PERIPH_RCR
Access:
Read-write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
3
2
1
0
RXCTR
7
6
5
4
RXCTR
• RXCTR: Receive Counter Register
RXCTR must be set to receive buffer size.
When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
0 = Stops peripheral data transfer to the receiver
1 - 65535 = Starts peripheral data transfer if corresponding channel is active
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6264C–CAP–24-Mar-09
28.4.3
Name:
Transmit Pointer Register
PERIPH_TPR
Access:
31
Read-write
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
TXPTR
23
22
21
20
TXPTR
15
14
13
12
TXPTR
7
6
5
4
TXPTR
• TXPTR: Transmit Counter Register
TXPTR must be set to transmit buffer address.
When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
28.4.4
Name:
Transmit Counter Register
PERIPH_TCR
Access:
Read-write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
3
2
1
0
TXCTR
7
6
5
4
TXCTR
• TXCTR: Transmit Counter Register
TXCTR must be set to transmit buffer size.
When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
0 = Stops peripheral data transfer to the transmitter
1- 65535 = Starts peripheral data transfer if corresponding channel is active
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AT91CAP9S500A/AT91CAP9S250A
28.4.5
Name:
Receive Next Pointer Register
PERIPH_RNPR
Access:
Read-write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
RXNPTR
23
22
21
20
RXNPTR
15
14
13
12
RXNPTR
7
6
5
4
RXNPTR
• RXNPTR: Receive Next Pointer
RXNPTR contains next receive buffer address.
When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
28.4.6
Name:
Receive Next Counter Register
PERIPH_RNCR
Access:
Read-write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
3
2
1
0
RXNCTR
7
6
5
4
RXNCTR
• RXNCTR: Receive Next Counter
RXNCTR contains next receive buffer size.
When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
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28.4.7
Name:
Transmit Next Pointer Register
PERIPH_TNPR
Access:
Read-write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
TXNPTR
23
22
21
20
TXNPTR
15
14
13
12
TXNPTR
7
6
5
4
TXNPTR
• TXNPTR: Transmit Next Pointer
TXNPTR contains next transmit buffer address.
When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
28.4.8
Name:
Transmit Next Counter Register
PERIPH_TNCR
Access:
Read-write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
3
2
1
0
TXNCTR
7
6
5
4
TXNCTR
• TXNCTR: Transmit Counter Next
TXNCTR contains next transmit buffer size.
When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
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28.4.9
Name:
Transfer Control Register
PERIPH_PTCR
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
TXTDIS
8
TXTEN
7
–
6
–
5
–
4
–
3
–
2
–
1
RXTDIS
0
RXTEN
• RXTEN: Receiver Transfer Enable
0 = No effect.
1 = Enables PDC receiver channel requests if RXTDIS is not set.
When a half duplex peripheral is connected to the PDC, enabling the receiver channel requests automatically disables the
transmitter channel requests. It is forbidden to set both TXTEN and RXTEN for a half duplex peripheral.
• RXTDIS: Receiver Transfer Disable
0 = No effect.
1 = Disables the PDC receiver channel requests.
When a half duplex peripheral is connected to the PDC, disabling the receiver channel requests also disables the transmitter channel requests.
• TXTEN: Transmitter Transfer Enable
0 = No effect.
1 = Enables the PDC transmitter channel requests.
When a half duplex peripheral is connected to the PDC, it enables the transmitter channel requests only if RXTEN is not
set. It is forbidden to set both TXTEN and RXTEN for a half duplex peripheral.
• TXTDIS: Transmitter Transfer Disable
0 = No effect.
1 = Disables the PDC transmitter channel requests.
When a half duplex peripheral is connected to the PDC, disabling the transmitter channel requests disables the receiver
channel requests.
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AT91CAP9S500A/AT91CAP9S250A
28.4.10
Name:
Transfer Status Register
PERIPH_PTSR
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
TXTEN
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
RXTEN
• RXTEN: Receiver Transfer Enable
0 = PDC Receiver channel requests are disabled.
1 = PDC Receiver channel requests are enabled.
• TXTEN: Transmitter Transfer Enable
0 = PDC Transmitter channel requests are disabled.
1 = PDC Transmitter channel requests are enabled.
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AT91CAP9S500A/AT91CAP9S250A
29. Clock Generator
29.1
Overview
The Clock Generator is made up of 2 programmable PLLs, a UTMI PLL, a Main Oscillator, as
well as an RC Oscillator and a 32,768 Hz low-power Oscillator.
It provides the following clocks:
• SLCK, the Slow Clock, which is the only permanent clock within the system
• MAINCK is the output of the Main Oscillator
The Clock Generator User Interface is embedded within the Power Management Controller one
and is described in Section 30.9. However, the Clock Generator registers are named CKGR_.
• PLLACK is the output of the Divider and PLL A block
• PLLBCK is the output of the Divider and PLL B block
29.2
Slow Clock Crystal Oscillator
The Clock Generator integrates a 32,768 Hz low-power oscillator. The XIN32 and XOUT32 pins
must be connected to a 32,768 Hz crystal. Two external capacitors must be wired as shown in
Figure 29-1.
Figure 29-1. Typical Slow Clock Crystal Oscillator Connection
XIN32
XOUT32
GNDPLL
32,768 Hz
Crystal
29.3
Slow Clock RC Oscillator
The user has to take into account the possible drifts of the RC Oscillator. More details are given
in the section “DC Characteristics” of the product datasheet.
29.4
Slow Clock Selection
The AT91CAP9 slow clock can be generated either by an external 32768Hz crystal or the onchip RC oscillator. The 32768Hz crystal oscillator can be bypassed, by setting the bit
OSC32BYP, to accept an external slow clock on XIN32.
The internal RC oscillator and the 32768Hz oscillator can be enabled by setting to 1 respectively
RCEN bit and OSC32EN bit in the system controller user interface. OSCSEL command selects
the slow clock source.
By default the AT91CAP9S500A/AT91CAP9S250A slow clock source is the internal RC oscillator. System startup time is 4 slow clock periods, typically 125 µs.
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6264C–CAP–24-Mar-09
Figure 29-2. Slow Clock Selection
Clock Generator
RCEN
On Chip
RC OSC
Slow Clock
SLCK
XIN32
Slow Clock
Oscillator
XOUT32
OSCSEL
OSC32EN
OSC32BYP
RCEN, OSC32EN,OSCSEL and OSC32BYP bits are located in the slow clock control register
(SCKCR) located at address 0xFFFFFD50 in the backed up part of the system controller and so
are preserved while VDDBU is present.
After a VDDBU power on reset, the default configuration is RCEN=1, OSC32EN=0 and OSCSEL=0 allowing the system to start on the internal RC oscillator.
The programmer controls by software the slow clock switching and so must take precautions
during the switching phase.
29.4.1
Switching from Internal RC Oscillator to the 32768 Hz Crystal
To switch from internal RC oscillator to the 32768 Hz crystal, the programmer must execute the
following sequence:
• Switch the master clock to a source different from slow clock (PLL or Main Oscillator) through
the Power Management Controller.
• Enable the 32768 Hz oscillator by setting the bit OSC32EN to 1.
• Wait 32768 Hz Startup Time for clock stabilization (software loop)
• Switch from internal RC to 32768 Hz oscillator by setting the bit OSCSEL to 1.
• Wait 5 slow clock cycles for internal resynchronization
• Disable the RC oscillator by setting the bit RCEN to 0.
29.4.2
Bypassing the 32768 Hz Oscillator
Following steps must be added to bypass the 32,768 Hz oscillator:
• An external clock must be connected on XIN32.
• Enable the bypass path OSC32BYP bit set to 1.
Disable the 32,768 Hz oscillator by setting the bit OSC32EN to 0.
29.4.3
Switching from 32768 Hz Crystal to the Internal RC Oscillator
The same procedure must be followed to switch from 32768 Hz crystal to the internal RC
oscillator.
• Switch the master clock to a source different from slow clock (PLL or Main Oscillator)
• Enable the internal RC oscillator by setting the bit RCEN to 1.
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• Wait internal RC Startup Time for clock stabilization (software loop)
• Switch from 32768 Hz oscillator to internal RC by setting the bit OSCSEL to 0
• Wait 5 slow clock cycles for internal resynchronization
• Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0
29.4.4
Name:
Slow Clock Configuration Register
SCKCR
Address:
0xFFFFFD50
Access:
Read-write
Reset:
0x0000_0001
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
OSCSEL
OSC32BYP
OSC32EN
RCEN
• RCEN: Internal RC
0: RC is disabled.
1: RC is enabled.
• OSC32EN: 32768Hz Oscillator
0: 32768Hz oscillator is disabled.
1: 32768Hz oscillator is enabled.
• OSC32BYP: 32768Hz Oscillator Bypass
0: 32768Hz oscillator is not bypassed
1: 32768Hz oscillator is bypassed, accept an external slow clock on XIN32
• OSCSEL: Slow Clock Selector
0: Slow clock is internal RC.
1: Slow clock is 32768Hz oscillator.
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6264C–CAP–24-Mar-09
29.5
Main Oscillator
The Main Oscillator is designed for a 12 MHz fundamental crystal but supports 8 to 16 MHz crystals. The 12 MHz is also used to generate the 480 MHz USB High Speed Clock (UDPHSCK)
thanks to the UTMI PLL (UPLL).
Figure 29-3 shows the Main Oscillator block diagram.
Figure 29-3. Main Oscillator Block Diagram
MOSCEN
XIN
UTMI
Main
Oscillator
MAINCK
Main Clock
XOUT
UPLL
UDPHSCK
480MHz
OSCOUNT
SLCK
Slow Clock
Main
Oscillator
Counter
MOSCS
MAINF
Main Clock
Frequency
Counter
29.5.1
MAINRDY
Main Oscillator Connections
The Clock Generator integrates a Main Oscillator that is designed for a 8 to 16 MHz fundamental
crystal. The typical crystal connection is illustrated in Figure 29-4. For further details on the electrical characteristics of the Main Oscillator, see the section “DC Characteristics” of the product
datasheet.
Figure 29-4. Typical Crystal Connection
AT91 Microcontroller
XIN
XOUT
GND
1K
29.5.2
390
Main Oscillator Startup Time
The startup time of the Main Oscillator is given in the DC Characteristics section of the product
datasheet. The startup time depends on the crystal frequency and decreases when the frequency rises.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
29.5.3
Main Oscillator Control
To minimize the power required to start up the system, the main oscillator is disabled after reset
and slow clock is selected.
The software enables or disables the main oscillator so as to reduce power consumption by
clearing the MOSCEN bit in the Main Oscillator Register (CKGR_MOR).
When disabling the main oscillator by clearing the MOSCEN bit in CKGR_MOR, the MOSCS bit
in PMC_SR is automatically cleared, indicating the main clock is off.
When enabling the main oscillator, the user must initiate the main oscillator counter with a value
corresponding to the startup time of the oscillator. This startup time depends on the crystal frequency connected to the main oscillator.
When the MOSCEN bit and the OSCOUNT are written in CKGR_MOR to enable the main oscillator, the MOSCS bit in PMC_SR (Status Register) is cleared and the counter starts counting
down on the slow clock divided by 8 from the OSCOUNT value. Since the OSCOUNT value is
coded with 8 bits, the maximum startup time is about 62 ms.
When the counter reaches 0, the MOSCS bit is set, indicating that the main clock is valid. Setting the MOSCS bit in PMC_IMR can trigger an interrupt to the processor.
29.5.4
Main Clock Frequency Counter
The Main Oscillator features a Main Clock frequency counter that provides the quartz frequency
connected to the Main Oscillator. Generally, this value is known by the system designer; however, it is useful for the boot program to configure the device with the correct clock speed,
independently of the application.
The Main Clock frequency counter starts incrementing at the Main Clock speed after the next rising edge of the Slow Clock as soon as the Main Oscillator is stable, i.e., as soon as the MOSCS
bit is set. Then, at the 16th falling edge of Slow Clock, the MAINRDY bit in CKGR_MCFR (Main
Clock Frequency Register) is set and the counter stops counting. Its value can be read in the
MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of
Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can be
determined.
29.5.5
Main Oscillator Bypass
The user can input a clock on the device instead of connecting a crystal. In this case, the user
has to provide the external clock signal on the XIN pin. The input characteristics of the XIN pin
under these conditions are given in the product electrical characteristics section. The programmer has to be sure to set the OSCBYPASS bit to 1 and the MOSCEN bit to 0 in the Main OSC
register (CKGR_MOR) for the external clock to operate properly.
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6264C–CAP–24-Mar-09
29.6
Divider and PLL Block
The PLL embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must respect the PLL minimum input frequency when programming the divider.
Figure 29-5 shows the block diagram of the divider and PLL blocks.
Figure 29-5. Divider and PLL Block Diagram
DIVB
MULB
Divider B
MAINCK
OUTB
PLL B
PLLBCK
PLLRCB
DIVA
MULA
OUTA
PLL A
Divider A
PLLACK
PLLRCA
PLLBCOUNT
PLL B
Counter
LOCKB
PLLACOUNT
PLL A
Counter
SLCK
29.6.1
LOCKA
PLL Filter
The PLL requires connection to an external second-order filter through the PLLRCA and/or PLLRCB pin. Figure 29-6 shows a schematic of these filters.
Figure 29-6. PLL Capacitors and Resistors
PLLRC
PLL
R
C2
C1
GND
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Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of
the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be
found between output signal overshoot and startup time.
29.6.2
Divider and Phase Lock Loop Programming
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the
output of the corresponding divider and the PLL output is a continuous signal at level 0. On
reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.
The PLL allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that
depends on the respective source signal frequency and on the parameters DIV and MUL. The
factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0, the
corresponding PLL is disabled and its power consumption is saved. Re-enabling the PLL can be
performed by writing a value higher than 0 in the MUL field.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit (LOCKA or
LOCKB) in PMC_SR is automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT or PLLBCOUNT) in CKGR_PLLR (CKGR_PLLAR or CKGR_PLLBR), are loaded in the
PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it reaches 0.
At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The
user has to load the number of Slow Clock cycles required to cover the PLL transient time into
the PLLCOUNT field. The transient time depends on the PLL filter. The initial state of the PLL
and its target frequency can be calculated using a specific tool provided by Atmel.
29.6.3
UTMI Phase Lock Loop Programming
The multiplier is hard-wired to 40 to obtain the USB High Speed 480 MHz.
Figure 29-7. UTMI PLL
UPLLEN
MAINCK
PLL
UDPHSCK
PLLCOUNT
SLCK
PLL
Counter
LOCKU
Whenever the PLL is enabled by writing UPLLEN in CKGR_UCKR, the LOCKU bit in PMC_SR
is automatically cleared, the BIAS is enabled by writing BIASEN in CKGR_UCKR in the same
time. The values written in the PLLCOUNT field in CKGR_UCKR are loaded in the PLL counter.
The PLL counter then decrements at the speed of the Slow Clock divided by 8 until it reaches 0.
At this time, the LOCKU bit is set in PMC_SR and can trigger an interrupt to the processor. The
user has to load the number of Slow Clock cycles required to cover the PLL transient time into
the PLLCOUNT field.
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30. Power Management Controller (PMC)
30.1
Overview
The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the
peripherals and the ARM Processor.
The Power Management Controller provides the following clocks:
• MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating
frequency of the device. It is available to the modules running permanently, such as the AIC
and the Memory Controller.
• Processor Clock (PCK), switched off when entering processor in idle mode.
• Application Clock (APCK), programmable from a few hundred Hz to the maximum operating
frequency of the device, switched off when entering processor idle mode.
• DDRCK, the Double Data Rate Clock, provided to peripherals using double data rate transfer
(e.g., DDR SDR Controller)
• Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC, SPI,
TWI, TC, MCI, etc.) and independently controllable. In order to reduce the number of clock
names in a product, the Peripheral Clocks are named MCK in the product datasheet.
• UHP Clock (UHPCK), required by USB Host Port operations.
• Programmable Clock Outputs can be selected from the clocks provided by the clock
generator and driven on the PCKx pins.
30.2
Master Clock Controller
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is
the clock provided to all the peripherals and the memory controller.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting
the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock
saves power consumption of the PLLs.
The Master Clock Controller is made up of a clock selector and a prescaler. It also contains a
Master Clock divider which allows the processor clock to be faster than the Master Clock.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in
PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the
selected clock between 1 and 64. The PRES field in PMC_MCKR programs the prescaler. The
Master Clock divider can be programmed through the MDIV field in PMC_MCKR.
A Double Data Rate Clock (DDRCK) is created after the clock selector and before the clock
prescaler. The software must ensure that the DDRCK clock rate is twice the MCK clock rate.
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in
PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can
trigger an interrupt to the processor. This feature is useful when switching from a high-speed
clock to a lower one to inform the software when the change is actually done.
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Figure 30-1. Master Clock Controller
PMC_MCKR
PLLADIV2
PMC_MCKR
PMC_MCKR
CSS
PMC_MCKR
MDIV
PRES
DIV
/1-/2
PLLACK
PLLBCK
Master
Clock
&
DDRCock
Divider
Master Clock
Prescaler
MAINCK
SLCK
MCK
To the Double Data Rate
Peripherals
(DDRCK)
To the Processor
Clock Controller (PCK)
30.3
Processor Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle
Mode. The Processor Clock can be disabled by writing the System Clock Disable Register
(PMC_SCDR). The status of this clock (at least for debug purpose) can be read in the System
Clock Status Register (PMC_SCSR).
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any
enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock and
entering processor specific “Wait for Interrupt” mode. The processor clock is automatically reenabled by any enabled fast or normal interrupt, or by the reset of the product.
Note:
30.4
The ARM “Wait for Interrupt” mode is enterred with CP15 coprocessor operation.
USB Clock Controller
The USB Source Clock is always generated from the PLL B output. If using the USB, the user
must program the PLL to generate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of
± 0.25% depending on the USBDIV bit in CKGR_PLLBR (see Figure 29-5).
When the PLL B output is stable, i.e., the LOCKB is set:
• The USB host clock can be enabled by setting the UHP bit in PMC_SCER. To save power on
this peripheral when it is not used, the user can set the UHP bit in PMC_SCDR. The UHP bit
in PMC_SCSR gives the activity of this clock. The USB host port require both the 12/48 MHz
signal and the Master Clock. The Master Clock may be controlled via the Master Clock
Controller.
Figure 30-2. USB Clock Controller
USBDIV
USB
Source
Clock
Divider
/1,/2,/4
UHP Clock (UHPCK)
UHP
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30.5
Peripheral Clock Controller
The Power Management Controller controls the clocks of each embedded peripheral by the way
of the Peripheral Clock Controller. The user can individually enable and disable the Master
Clock on the peripherals by writing into the Peripheral Clock Enable (PMC_PCER) and Peripheral Clock Disable (PMC_PCDR) registers. The status of the peripheral clock activity can be
read in the Peripheral Clock Status Register (PMC_PCSR).
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are
automatically disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral
has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system.
The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and
PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number
corresponds to the interrupt source number assigned to the peripheral.
30.6
Programmable Clock Output Controller
The PMC controls 4 signals to be output on external pins PCKx. Each signal can be independently programmed via the PMC_PCKx registers.
PCKx can be independently selected between the Slow clock, the PLL A output, the PLL B output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be
divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx.
Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of
PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks
are given in the PCKx bits of PMC_SCSR (System Clock Status Register).
Moreover, like the PCK, a status bit in PMC_SR indicates that the programmable clock is actually what has been programmed in the Programmable Clock registers.
As the Programmable Clock Controller does not manage with glitch prevention when switching
clocks, it is strongly recommended to disable the programmable clock before any configuration
change and to re-enable it after the change is actually performed.
30.7
Programming Sequence
1. Enabling the Main Oscillator:
The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In
some cases it may be advantageous to define a start-up time. This can be achieved by writing a value in the OSCOUNT field in the CKGR_MOR register.
Once this register has been correctly configured, the user must wait for MOSCS field in the
PMC_SR register to be set. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to MOSCS has been enabled in
the PMC_IER register.
Code Example:
write_register(CKGR_MOR,0x00000701)
Start Up Time = 8 * OSCOUNT / SLCK = 56 Slow Clock Cycles.
So, the main oscillator will be enabled (MOSCS bit set) after 56 Slow Clock Cycles.
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2. Checking the Main Oscillator Frequency (Optional):
In some situations the user may need an accurate measure of the main oscillator frequency.
This measure can be accomplished via the CKGR_MCFR register.
Once the MAINRDY field is set in CKGR_MCFR register, the user may read the MAINF field
in CKGR_MCFR register. This provides the number of main clock cycles within sixteen slow
clock cycles.
3. Setting PLL A and divider A:
All parameters necessary to configure PLL A and divider A are located in the CKGR_PLLAR
register.
It is important to note that Bit 29 must always be set to 1 when programming the
CKGR_PLLAR register.
The DIVA field is used to control the divider A itself. The user can program a value between
0 and 255. Divider A output is divider A input divided by DIVA. By default, DIVA parameter is
set to 0 which means that divider A is turned off.
The OUTA field is used to select the PLL A output frequency range.
The MULA field is the PLL A multiplier factor. This parameter can be programmed between
0 and 2047. If MULA is set to 0, PLL A will be turned off. Otherwise PLL A output frequency
is PLL A input frequency multiplied by (MULA + 1).
The PLLACOUNT field specifies the number of slow clock cycles before LOCKA bit is set in
the PMC_SR register after CKGR_PLLAR register has been written.
Once CKGR_PLLAR register has been written, the user is obliged to wait for the LOCKA bit
to be set in the PMC_SR register. This can be done either by polling the status register or by
waiting the interrupt line to be raised if the associated interrupt to LOCKA has been enabled
in the PMC_IER register.
All parameters in CKGR_PLLAR can be programmed in a single write operation. If at some
stage one of the following parameters, SRCA, MULA, DIVA is modified, LOCKA bit will go
low to indicate that PLL A is not ready yet. When PLL A is locked, LOCKA will be set again.
User has to wait for LOCKA bit to be set before using the PLL A output clock.
Code Example:
write_register(CKGR_PLLAR,0x20030605)
PLL A and divider A are enabled. PLL A input clock is main clock divided by 5. PLL An output clock is PLL A input clock multiplied by 4. Once CKGR_PLLAR has been written,
LOCKA bit will be set after six slow clock cycles.
4. Setting PLL B and divider B:
All parameters needed to configure PLL B and divider B are located in the CKGR_PLLBR
register.
The DIVB field is used to control divider B itself. A value between 0 and 255 can be programmed. Divider B output is divider B input divided by DIVB parameter. By default DIVB
parameter is set to 0 which means that divider B is turned off.
The OUTB field is used to select the PLL B output frequency range.
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The MULB field is the PLL B multiplier factor. This parameter can be programmed between
0 and 2047. If MULB is set to 0, PLL B will be turned off, otherwise the PLL B output frequency is PLL B input frequency multiplied by (MULB + 1).
The PLLBCOUNT field specifies the number of slow clock cycles before LOCKB bit is set in
the PMC_SR register after CKGR_PLLBR register has been written.
Once the PMC_PLLB register has been written, the user must wait for the LOCKB bit to be
set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to LOCKB has been enabled in
the PMC_IER register. All parameters in CKGR_PLLBR can be programmed in a single
write operation. If at some stage one of the following parameters, MULB, DIVB is modified,
LOCKB bit will go low to indicate that PLL B is not ready yet. When PLL B is locked, LOCKB
will be set again. The user is constrained to wait for LOCKB bit to be set before using the
PLL A output clock.
The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the
USB clock(s).
Code Example:
write_register(CKGR_PLLBR,0x00040805)
If PLL B and divider B are enabled, the PLL B input clock is the main clock. PLL B output
clock is PLL B input clock multiplied by 5. Once CKGR_PLLBR has been written, LOCKB bit
will be set after eight slow clock cycles.
5. Selection of Master Clock and Processor Clock
The Master Clock and the Processor Clock are configurable via the PMC_MCKR register.
The CSS field is used to select the Master Clock divider source. By default, the selected
clock source is slow clock.
The PRES field is used to control the Master Clock prescaler. The user can choose between
different values (1, 2, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by
PRES parameter. By default, PRES parameter is set to 1 which means that master clock is
equal to slow clock.
The MDIV field is used to control the Master Clock prescaler. It is possible to choose
between different values (0, 1, 2). The Master Clock output is Processor Clock divided by 1,
2 or 4, depending on the value programmed in MDIV. By default, MDIV is set to 0, which
indicates that the Processor Clock is equal to the Master Clock.
Once the PMC_MCKR register has been written, the user must wait for the MCKRDY bit to
be set in the PMC_SR register. This can be done either by polling the status register or by
waiting for the interrupt line to be raised if the associated interrupt to MCKRDY has been
enabled in the PMC_IER register.
The PMC_MCKR register must not be programmed in a single write operation. The preferred programming sequence for the PMC_MCKR register is as follows:
• If a new value for CSS field corresponds to PLL Clock,
– Program the PRES field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the CSS field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
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• If a new value for CSS field corresponds to Main Clock or Slow Clock,
– Program the CSS field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the PRES field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY
bit will go low to indicate that the Master Clock and the Processor Clock are not ready yet.
The user must wait for MCKRDY bit to be set again before using the Master and Processor
Clocks.
Note:
IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in
CKGR_PLLR (CKGR_PLLAR or CKGR_PLLBR), the MCKRDY flag will go low while PLL is
unlocked. Once PLL is locked again, LOCK (LOCKA or LOCKB) goes high and MCKRDY is set.
While PLLA is unlocked, the Master Clock selection is automatically changed to Slow Clock. While
PLLB is unlocked, the Master Clock selection is automatically changed to Main Clock. For further
information, see Section 30.8.2. “Clock Switching Waveforms” on page 402.
Code Example:
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011)
wait (MCKRDY=1)
The Master Clock is main clock divided by 16.
The Processor Clock is the Master Clock.
6. Selection of programmable clocks
Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and
PMC_SCSR.
Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR
registers. Depending on the system used, 4 programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indication as to which programmable clock is
enabled. By default all programmable clocks are disabled.
PMC_PCKx registers are used to configure programmable clocks.
The CSS field is used to select the programmable clock divider source. Four clock options
are available: main clock, slow clock, PLLACK, PLLBCK. By default, the clock source
selected is slow clock.
The PRES field is used to control the programmable clock prescaler. It is possible to choose
between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler
input divided by PRES parameter. By default, the PRES parameter is set to 1 which means
that master clock is equal to slow clock.
Once the PMC_PCKx register has been programmed, The corresponding programmable
clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in
the PMC_SR register. This can be done either by polling the status register or by waiting the
interrupt line to be raised if the associated interrupt to PCKRDYx has been enabled in the
PMC_IER register. All parameters in PMC_PCKx can be programmed in a single write
operation.
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If the CSS and PRES parameters are to be modified, the corresponding programmable
clock must be disabled first. The parameters can then be modified. Once this has been
done, the user must re-enable the programmable clock and wait for the PCKRDYx bit to be
set.
Code Example:
write_register(PMC_PCK0,0x00000015)
Programmable clock 0 is main clock divided by 32.
7. Enabling Peripheral Clocks
Once all of the previous steps have been completed, the peripheral clocks can be enabled
and/or disabled via registers PMC_PCER and PMC_PCDR.
Depending on the system used, 23 peripheral clocks can be enabled or disabled. The
PMC_PCSR provides a clear view as to which peripheral clock is enabled.
Note:
Each enabled peripheral clock corresponds to Master Clock.
Code Examples:
write_register(PMC_PCER,0x00000110)
Peripheral clocks 4 and 8 are enabled.
write_register(PMC_PCDR,0x00000010)
Peripheral clock 4 is disabled.
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30.8
30.8.1
Clock Switching Details
Master Clock Switching Timings
Table 30-1 and Table 30-2 give the worst case timings required for the Master Clock to switch
from one selected clock to another one. This is in the event that the prescaler is de-activated.
When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock
has to be added.
Table 30-1.
Clock Switching Timings (Worst Case)
From
Main Clock
SLCK
PLL Clock
–
4 x SLCK +
2.5 x Main Clock
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
0.5 x Main Clock +
4.5 x SLCK
–
3 x PLL Clock +
5 x SLCK
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLLx Clock
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK
To
Main Clock
SLCK
PLL Clock
Notes:
1. PLL designates either the PLL A or the PLL B Clock.
2. PLLCOUNT designates either PLLACOUNT or PLLBCOUNT.
Table 30-2.
Clock Switching Timings Between Two PLLs (Worst Case)
From
PLLA Clock
PLLB Clock
PLLA Clock
2.5 x PLLA Clock +
4 x SLCK +
PLLACOUNT x SLCK
3 x PLLA Clock +
4 x SLCK +
1.5 x PLLA Clock
PLLB Clock
3 x PLLB Clock +
4 x SLCK +
1.5 x PLLB Clock
2.5 x PLLB Clock +
4 x SLCK +
PLLBCOUNT x SLCK
To
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6264C–CAP–24-Mar-09
30.8.2
Clock Switching Waveforms
Figure 30-3. Switch Master Clock from Slow Clock to PLL Clock
Slow Clock
PLL Clock
LOCK
MCKRDY
Master Clock
Write PMC_MCKR
Figure 30-4. Switch Master Clock from Main Clock to Slow Clock
Slow Clock
Main Clock
MCKRDY
Master Clock
Write PMC_MCKR
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Figure 30-5. Change PLLA Programming
Slow Clock
PLLA Clock
LOCK
MCKRDY
Master Clock
Slow Clock
Write CKGR_PLLAR
Figure 30-6. Change PLLB Programming
Main Clock
PLLB Clock
LOCK
MCKRDY
Master Clock
Main Clock
Write CKGR_PLLBR
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6264C–CAP–24-Mar-09
Figure 30-7. Programmable Clock Output Programming
PLL Clock
PCKRDY
PCKx Output
Write PMC_PCKx
PLL Clock is selected
Write PMC_SCER
Write PMC_SCDR
404
PCKx is enabled
PCKx is disabled
AT91CAP9S500A/AT91CAP9S250A
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AT91CAP9S500A/AT91CAP9S250A
30.9
Power Management Controller (PMC) User Interface
Table 30-3.
Register Mapping
Offset
Register
Name
Access
Reset
0x0000
System Clock Enable Register
PMC_SCER
Write-only
–
0x0004
System Clock Disable Register
PMC_SCDR
Write-only
–
0x0008
System Clock Status Register
PMC _SCSR
Read-only
0x03
0x000C
Reserved
–
–
–
0x0010
Peripheral Clock Enable Register
PMC _PCER
Write-only
–
0x0014
Peripheral Clock Disable Register
PMC_PCDR
Write-only
–
0x0018
Peripheral Clock Status Register
PMC_PCSR
Read-only
0x0
0x001C
UTMI Clock Register
CKGR_UCKR
Read-write
0x1020_0800
0x0020
Main Oscillator Register
CKGR_MOR
Read-write
0x0
0x0024
Main Clock Frequency Register
CKGR_MCFR
Read-only
0x0
0x0028
PLL A Register
CKGR_PLLAR
Read-write
0x3F00
0x002C
PLL B Register
CKGR_PLLBR
Read-write
0x3F00
0x0030
Master Clock Register
PMC_MCKR
Read-write
0x0
0x0038
Reserved
–
–
–
0x003C
Reserved
–
–
–
0x0040
Programmable Clock 0 Register
PMC_PCK0
Read-write
0x0
0x0044
Programmable Clock 1 Register
PMC_PCK1
Read-write
0x0
...
...
...
...
...
0x0060
Interrupt Enable Register
PMC_IER
Write-only
--
0x0064
Interrupt Disable Register
PMC_IDR
Write-only
--
0x0068
Status Register
PMC_SR
Read-only
0x08
0x006C
Interrupt Mask Register
PMC_IMR
Read-only
0x0
–
–
–
0x0070 - 0x007C
Reserved
0x00E4
Write Protect Mode Register
PMC_WPMR
Read-write
0x0
0x00E8
Write Protect Status Register
PMC_WPSR
Read-only
0x0
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30.9.1
Name:
PMC System Clock Enable Register
PMC_SCER
Address:
0xFFFFFC00
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
PCK3
PCK2
PCK1
PCK0
7
6
5
4
3
2
1
0
–
UHP
–
–
–
DCKE
–
PCK
• PCK: Processor Clock Enable
0 = No effect.
1 = Enables the Processor clock.
• DCKE: DDR Clock Enable
0 = No effect.
1 = Enables the DDR clock.
• UHP: USB Host Port Clock Enable
0 = No effect.
1 = Enables the 12 and 48 MHz clock of the USB Host Port.
• PCKx: Programmable Clock x Output Enable
0 = No effect.
1 = Enables the corresponding programmable Clock output.
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30.9.2
Name:
PMC System Clock Disable Register
PMC_SCDR
Address:
0xFFFFFC04
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
PCK3
PCK2
PCK1
PCK0
7
6
5
4
3
2
1
0
–
UHP
–
–
–
DCKD
–
PCK
• PCK: Processor Clock Disable
0 = No effect.
1 = Disables the Processor clock. This is used to enter the processor in Idle Mode.
Note:
PCK disable action will only take effect if processor enters “Wat for Interrupt” mode.
• DCKD: DDR Clock Disable
0 = No effect.
1 = Disables the DDR Clock.
• UHP: USB Host Port Clock Disable
0 = No effect.
1 = Disables the 12 and 48 MHz clock of the USB Host Port.
• PCKx: Programmable Clock x Output Disable
0 = No effect.
1 = Disables the corresponding programmable clock output.
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30.9.3
Name:
PMC System Clock Status Register
PMC_SCSR
Address:
0xFFFFFC08
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
PCK3
PCK2
PCK1
PCK0
7
6
5
4
3
2
1
0
–
UHP
–
–
–
DCKS
–
PCK
• PCK: Processor Clock Status
0 = The Processor clock is disabled.
1 = The Processor clock is enabled.
• DCKS: DDR Clock Status
0 = The DDR Clock is disabled.
1 = The DDR Clock is enabled.
• UHP: USB Host Port Clock Status
0 = The 12 and 48 MHz clock (UHPCK) of the USB Host Port is disabled.
1 = The 12 and 48 MHz clock (UHPCK) of the USB Host Port is enabled.
• PCKx: Programmable Clock x Output Status
0 = The corresponding programmable clock output is disabled.
1 = The corresponding programmable clock output is enabled
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30.9.4
Name:
PMC Peripheral Clock Enable Register
PMC_PCER
Address:
0xFFFFFC10
Access:
Write-only
31
30
29
28
27
26
25
24
PID31
PID30
PID29
PID28
PID27
PID26
PID25
PID24
23
22
21
20
19
18
17
16
PID23
PID22
PID21
PID20
PID19
PID18
PID17
PID16
15
14
13
12
11
10
9
8
PID15
PID14
PID13
PID12
PID11
PID10
PID9
PID8
7
6
5
4
3
2
1
0
PID7
PID6
PID5
PID4
PID3
PID2
–
–
• PIDx: Peripheral Clock x Enable
0 = No effect.
1 = Enables the corresponding peripheral clock.
Note:
PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
Note:
Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.
409
6264C–CAP–24-Mar-09
30.9.5
Name:
PMC Peripheral Clock Disable Register
PMC_PCDR
Address:
0xFFFFFC14
Access:
Write-only
31
30
29
28
27
26
25
24
PID31
PID30
PID29
PID28
PID27
PID26
PID25
PID24
23
22
21
20
19
18
17
16
PID23
PID22
PID21
PID20
PID19
PID18
PID17
PID16
15
14
13
12
11
10
9
8
PID15
PID14
PID13
PID12
PID11
PID10
PID9
PID8
7
6
5
4
3
2
1
0
PID7
PID6
PID5
PID4
PID3
PID2
–
–
• PIDx: Peripheral Clock x Disable
0 = No effect.
1 = Disables the corresponding peripheral clock.
Note:
410
PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
30.9.6
Name:
PMC Peripheral Clock Status Register
PMC_PCSR
Address:
0xFFFFFC18
Access:
Read-only
31
30
29
28
27
26
25
24
PID31
PID30
PID29
PID28
PID27
PID26
PID25
PID24
23
22
21
20
19
18
17
16
PID23
PID22
PID21
PID20
PID19
PID18
PID17
PID16
15
14
13
12
11
10
9
8
PID15
PID14
PID13
PID12
PID11
PID10
PID9
PID8
7
6
5
4
3
2
1
0
PID7
PID6
PID5
PID4
PID3
PID2
–
–
• PIDx: Peripheral Clock x Status
0 = The corresponding peripheral clock is disabled.
1 = The corresponding peripheral clock is enabled.
Note:
PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
411
6264C–CAP–24-Mar-09
30.9.7
Name:
PMC UTMI Clock Configuration Register
CKGR_UCKR
Address:
0xFFFFFC1C
Access:
Read-write
31
30
29
28
BIASCOUNT
23
22
21
20
PLLCOUNT
27
26
25
24
–
–
–
BIASEN
19
18
17
16
–
–
–
UPLLEN
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
• UPLLEN: UTMI PLL Enable
0 = The UTMI PLL is disabled.
1 = The UTMI PLL is enabled.
When UPLLEN is set, the LOCKU flag is set once the UTMI PLL startup time is achieved.
• PLLCOUNT: UTMI PLL Start-up Time
Specifies the number of Slow Clock cycles multiplied by 8 for the UTMI PLL start-up time. Should be set to 2.
• BIASEN: UTMI BIAS Enable
0 = The UTMI BIAS is disabled.
1 = The UTMI BIAS is enabled.
• BIASCOUNT: UTMI BIAS Start-up Time
Specifies the number of Slow Clock cycles for the UTMI BIAS start-up time. Should be set to 2.
412
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
30.9.8
Name:
PMC Clock Generator Main Oscillator Register
CKGR_MOR
Address:
0xFFFFFC20
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
OSCOUNT
7
6
5
4
3
2
1
0
–
–
–
–
–
–
OSCBYPASS
MOSCEN
• MOSCEN: Main Oscillator Enable
A crystal must be connected between XIN and XOUT.
0 = The Main Oscillator is disabled.
1 = The Main Oscillator is enabled. OSCBYPASS must be set to 0.
When MOSCEN is set, the MOSCS flag is set once the Main Oscillator startup time is achieved.
• OSCBYPASS: Oscillator Bypass
0 = No effect.
1 = The Main Oscillator is bypassed. MOSCEN must be set to 0. An external clock must be connected on XIN.
When OSCBYPASS is set, the MOSCS flag in PMC_SR is automatically set.
Clearing MOSCEN and OSCBYPASS bits allows resetting the MOSCS flag.
• OSCOUNT: Main Oscillator Start-up Time
Specifies the number of Slow Clock cycles multiplied by 8 for the Main Oscillator start-up time.
413
6264C–CAP–24-Mar-09
30.9.9
Name:
PMC Clock Generator Main Clock Frequency Register
CKGR_MCFR
Address:
0xFFFFFC24
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
MAINRDY
15
14
13
12
11
10
9
8
3
2
1
0
MAINF
7
6
5
4
MAINF
• MAINF: Main Clock Frequency
Gives the number of Main Clock cycles within 16 Slow Clock periods.
• MAINRDY: Main Clock Ready
0 = MAINF value is not valid or the Main Oscillator is disabled.
1 = The Main Oscillator has been enabled previously and MAINF value is available.
414
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
30.9.10
Name:
PMC Clock Generator PLL A Register
CKGR_PLLAR
Address:
0xFFFFFC28
Access:
Read-write
31
30
29
28
27
–
–
–
–
–
23
22
21
20
26
25
24
MULA
19
18
17
16
10
9
8
2
1
0
MULA
15
14
13
12
11
OUTA
7
PLLACOUNT
6
5
4
3
DIVA
Possible limitations on PLL A input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
• DIVA: Divider A
DIVA
Divider Selected
0
Divider output is 0
1
Divider is bypassed
2 - 255
Divider output is the Main Clock divided by DIVA.
• PLLACOUNT: PLL A Counter
Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• OUTA: PLL A Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Characteristics section of the product datasheet.
• MULA: PLL A Multiplier
0 = The PLL A is deactivated.
1 up to 2047 = The PLL A Clock frequency is the PLL A input frequency multiplied by MULA + 1.
415
6264C–CAP–24-Mar-09
30.9.11
Name:
PMC Clock Generator PLL B Register
CKGR_PLLBR
Address:
0xFFFFFC2C
Access:
Read-write
31
30
29
28
27
USBDIV
23
22
26
–
21
20
25
24
MULB
19
18
17
16
10
9
8
2
1
0
MULB
15
14
13
12
11
OUTB
7
PLLBCOUNT
6
5
4
3
DIVB
Possible limitations on PLL B input frequencies and multiplier factors should be checked before using the PMC.
• DIVB: Divider B
DIVB
Divider Selected
0
Divider output is 0
1
Divider is bypassed
2 - 255
Divider output is the selected clock divided by DIVB.
• PLLBCOUNT: PLL B Counter
Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• OUTB: PLLB Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Characteristics section of the product datasheet.
• MULB: PLL B Multiplier
0 = The PLL B is deactivated.
1 up to 2047 = The PLL B Clock frequency is the PLL B input frequency multiplied by MULB + 1.
• USBDIV: Divider for USB Clock
The division ratio is: USBDIV +1
USBDIV
416
Divider for USB Clock(s)
0
0
0
0
Divider output is PLL B clock output.
0
0
0
1
Divider output is PLL B clock output divided by 2.
0
0
1
0
Divider output is PLL B clock output divided by 3.
0
0
1
1
Divider output is PLL B clock output divided by 4.
0
1
0
0
Divider output is PLL B clock output divided by 5
0
1
0
1
Divider output is PLL B clock output divided by 6
0
1
1
0
Divider output is PLL B clock output divided by 7
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
USBDIV
Divider for USB Clock(s)
0
1
1
1
Divider output is PLL B clock output divided by 8
1
0
0
0
Divider output is PLL B clock output divided by 9
1
0
0
1
Divider output is PLL B clock output divided by 10
1
0
1
0
Divider output is PLL B clock output divided by 11
1
0
1
1
Divider output is PLL B clock output divided by 12
1
1
0
0
Divider output is PLL B clock output divided by 13
1
1
0
1
Divider output is PLL B clock output divided by 14
1
1
1
0
Divider output is PLL B clock output divided by 15
1
1
1
1
Divider output is PLL B clock output divided by 16
417
6264C–CAP–24-Mar-09
30.9.12
Name:
PMC Master Clock Register
PMC_MCKR
Address:
0xFFFFFC30
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
–
–
–
PLLADIV2
–
–
4
3
2
7
6
5
–
–
–
8
MDIV
1
PRES
0
CSS
• CSS: Master Clock Selection
CSS
Clock Source Selection
0
0
Slow Clock is selected
0
1
Main Clock is selected
1
0
PLL A Clock is selected
1
1
PLL B Clock is selected
• PRES: Processor Clock Prescaler
PRES
Processor Clock
0
0
0
Selected clock
0
0
1
Selected clock divided by 2
0
1
0
Selected clock divided by 4
0
1
1
Selected clock divided by 8
1
0
0
Selected clock divided by 16
1
0
1
Selected clock divided by 32
1
1
0
Selected clock divided by 64
1
1
1
Reserved
• PLLADIV2: PLL A Divided by 2
PLLADIV2
PLL A Division
0
PLL A Frequency is divided by 1.
1
PLL A Frequency is divided by 2.
• PDIV Processor Clock Division
0 = Processor Clock is Prescaler Output Clock divided by 1.
1 = Processor Clock is Prescaler Output Clock divided by 2.
418
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• MDIV: Master Clock Division
MDIV
Master Clock Division
0
0
Master Clock is Processor Clock.
DDRCK is unusable
0
1
Master Clock is Processor Clock divided by 2.
DDRCK is 2xMCK
1
0
Master Clock is Processor Clock divided by 4.
DDRCK is 2xMCK
1
1
Reserved.
419
6264C–CAP–24-Mar-09
30.9.13
Name:
PMC Programmable Clock Register
PMC_PCKx
Address:
0xFFFFFC40
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
4
3
2
1
7
6
5
–
–
–
PRES
0
CSS
• CSS: Master Clock Selection
CSS
Clock Source Selection
0
0
Slow Clock is selected
0
1
Main Clock is selected
1
0
PLL A Clock is selected
1
1
PLL B Clock is selected
• PRES: Programmable Clock Prescaler
PRES
420
Programmable Clock
0
0
0
Selected clock
0
0
1
Selected clock divided by 2
0
1
0
Selected clock divided by 4
0
1
1
Selected clock divided by 8
1
0
0
Selected clock divided by 16
1
0
1
Selected clock divided by 32
1
1
0
Selected clock divided by 64
1
1
1
Reserved
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
30.9.14
Name:
PMC Interrupt Enable Register
PMC_IER
Address:
0xFFFFFC60
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
PCKRDY3
PCKRDY2
PCKRDY1
PCKRDY0
7
6
5
4
3
2
1
0
–
LOCKU
–
ACKRDY
MCKRDY
LOCKB
LOCKA
MOSCS
• MOSCS: Main Oscillator Status Interrupt Enable
• LOCKA: PLL A Lock Interrupt Enable
• LOCKB: PLL B Lock Interrupt Enable
• MCKRDY: Master Clock Ready Interrupt Enable
• ACKRDY: Application Clock Ready Interrupt Enable
• PCKRDYx: Programmable Clock Ready x Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
• LOCKU: UTMI PLL Lock Interrupt Enable
421
6264C–CAP–24-Mar-09
30.9.15
Name:
PMC Interrupt Disable Register
PMC_IDR
Address:
0xFFFFFC64
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
PCKRDY3
PCKRDY2
PCKRDY1
PCKRDY0
7
6
5
4
3
2
1
0
–
LOCKU
–
ACKRDY
MCKRDY
LOCKB
LOCKA
MOSCS
• MOSCS: Main Oscillator Status Interrupt Disable
• LOCKA: PLL A Lock Interrupt Disable
• LOCKB: PLL B Lock Interrupt Disable
• MCKRDY: Master Clock Ready Interrupt Disable
• ACKRDY: Application Clock Ready Interrupt Disable
• PCKRDYx: Programmable Clock Ready x Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
• LOCKU: UTMI PLL Lock Interrupt Disable
422
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
30.9.16
Name:
PMC Status Register
PMC_SR
Address:
0xFFFFFC68
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
PCKRDY3
PCKRDY2
PCKRDY1
PCKRDY0
7
6
5
4
3
2
1
0
–
LOCKU
–
ACKRDY
MCKRDY
LOCKB
LOCKA
MOSCS
• MOSCS: MOSCS Flag Status
0 = Main oscillator is not stabilized.
1 = Main oscillator is stabilized.
• LOCKA: PLL A Lock Status
0 = PLL A is not locked
1 = PLL A is locked.
• LOCKB: PLL B Lock Status
0 = PLL B is not locked.
1 = PLL B is locked.
• MCKRDY: Master Clock Status
0 = Master Clock is not ready.
1 = Master Clock is ready.
• ACKRDY: Application Clock Status
0 = Application Clock is not ready.
1 = Application Clock is ready.
• PCKRDYx: Programmable Clock Ready Status
0 = Programmable Clock x is not ready.
1 = Programmable Clock x is ready.
• LOCKU: UTMI PLL Lock Interrupt Disable
423
6264C–CAP–24-Mar-09
30.9.17
Name:
PMC Interrupt Mask Register
PMC_IMR
Address:
0xFFFFFC6C
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
PCKRDY3
PCKRDY2
PCKRDY1
PCKRDY0
7
6
5
4
3
2
1
0
–
LOCKU
–
ACKRDY
MCKRDY
LOCKB
LOCKA
MOSCS
• MOSCS: Main Oscillator Status Interrupt Mask
• LOCKA: PLL A Lock Interrupt Mask
• LOCKB: PLL B Lock Interrupt Mask
• MCKRDY: Master Clock Ready Interrupt Mask
• ACKRDY: Application Clock Ready Interrupt Mask
• PCKRDYx: Programmable Clock Ready x Interrupt Mask
0 = The corresponding interrupt is enabled.
1 = The corresponding interrupt is disabled.
• LOCKU: UTMI PLL Lock Interrupt Mask
424
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
30.9.18
Name:
Write Protect Mode Register
PMC_WPMR
Address:
0xFFFFFCE4
Access:
Read-write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
WPKEY
23
22
21
20
WPKEY
15
14
13
12
WPKEY
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
WPEN
• WPEN: Write Protect Enable
0: Disables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
1: Disables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
Protects the registers:
• “PMC System Clock Enable Register” on page 406
• “PMC System Clock Disable Register” on page 407
• “PMC Peripheral Clock Enable Register” on page 409
• “PMC Peripheral Clock Disable Register” on page 410
• “PMC UTMI Clock Configuration Register” on page 412
• “PMC Clock Generator Main Oscillator Register” on page 413
• “PMC Clock Generator PLL A Register” on page 415
• “PMC Clock Generator PLL B Register” on page 416
• “PMC Master Clock Register” on page 418
• “PMC Programmable Clock Register” on page 420
• WPKEY: Write Protect KEY
Should be written at value 0x504D43 (“PMC” in ASCII). Writting any other value in this field aborts the write operation of the
WPEN bit. Always reads at 0.
425
6264C–CAP–24-Mar-09
30.9.19
Name:
Write Protect Status Register
PMC_WPSR
Address:
0xFFFFFCE8
Access:
Read-only
31
30
29
28
27
26
25
24
—
—
—
—
—
—
—
—
23
22
21
20
19
18
17
16
11
10
9
8
WPVSRC
15
14
13
12
WPVSRC
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
WPVS
• WPVS: Write Protect Violation Status
0 = No Write Protect Violation has occurred since the last read of the PMC_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the PMC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write
access has been attempted.
Note: Reading PMC_WPSR automatically clears all fields.
426
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
31. Advanced Interrupt Controller (AIC)
31.1
Description
The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored
interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external
interrupts.
The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs
of an ARM processor. Inputs of the AIC are either internal peripheral interrupts or external interrupts coming from the product's pins.
The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus
permitting higher priority interrupts to be serviced even if a lower priority interrupt is being
treated.
Internal interrupt sources can be programmed to be level sensitive or edge triggered. External
interrupt sources can be programmed to be positive-edge or negative-edge triggered or highlevel or low-level sensitive.
The fast forcing feature redirects any internal or external interrupt source to provide a fast interrupt rather than a normal interrupt.
427
6264C–CAP–24-Mar-09
31.2
Block Diagram
Figure 31-1. Block Diagram
FIQ
AIC
ARM
Processor
IRQ0-IRQn
Up to
Thirty-two
Sources
Embedded
PeripheralEE
Embedded
nFIQ
nIRQ
Peripheral
Embedded
Peripheral
APB
31.3
Application Block Diagram
Figure 31-2. Description of the Application Block
OS-based Applications
Standalone
Applications
OS Drivers
RTOS Drivers
Hard Real Time Tasks
General OS Interrupt Handler
Advanced Interrupt Controller
External Peripherals
(External Interrupts)
Embedded Peripherals
31.4
AIC Detailed Block Diagram
Figure 31-3. AIC Detailed Block Diagram
Advanced Interrupt Controller
FIQ
PIO
Controller
Fast
Interrupt
Controller
External
Source
Input
Stage
ARM
Processor
nFIQ
nIRQ
IRQ0-IRQn
Embedded
Peripherals
Interrupt
Priority
Controller
Fast
Forcing
PIOIRQ
Internal
Source
Input
Stage
Processor
Clock
Power
Management
Controller
User Interface
Wake Up
APB
428
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
31.5
I/O Line Description
Table 31-1.
I/O Line Description
Pin Name
Pin Description
Type
FIQ
Fast Interrupt
Input
IRQ0 - IRQn
Interrupt 0 - Interrupt n
Input
31.6
31.6.1
Product Dependencies
I/O Lines
The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be
programmed in accordance with their assigned interrupt function. This is not applicable when
the PIO controller used in the product is transparent on the input path.
Table 31-2.
31.6.2
I/O Lines
Instance
Signal
I/O Line
Peripheral
AIC
FIQ
PD4
A
AIC
IRQ0
PA10
A
AIC
IRQ1
PA14
B
Power Management
The Advanced Interrupt Controller is continuously clocked. The Power Management Controller
has no effect on the Advanced Interrupt Controller behavior.
The assertion of the Advanced Interrupt Controller outputs, either nIRQ or nFIQ, wakes up the
ARM processor while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to
wake up the processor without asserting the interrupt line of the processor, thus providing synchronization of the processor on an event.
31.6.3
Interrupt Sources
The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the
Interrupt Source 0 cannot be used.
The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring
of the system peripheral interrupt lines. When a system interrupt occurs, the service routine
must first distinguish the cause of the interrupt. This is performed by reading successively the
status registers of the above mentioned system peripherals.
The interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded
user peripheral or to external interrupt lines. The external interrupt lines can be connected
directly, or through the PIO Controller.
The PIO Controllers are considered as user peripherals in the scope of interrupt handling.
Accordingly, the PIO Controller interrupt lines are connected to the Interrupt Sources 2 to 31.
The peripheral identification defined at the product level corresponds to the interrupt source
number (as well as the bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are
named FIQ, SYS, and PID2 to PID31.
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31.7
Functional Description
31.7.1
31.7.1.1
Interrupt Source Control
Interrupt Source Mode
The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt
condition of each source.
The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be
programmed either in level-sensitive mode or in edge-triggered mode. The active level of the
internal interrupts is not important for the user.
The external interrupt sources can be programmed either in high level-sensitive or low level-sensitive modes, or in positive edge-triggered or negative edge-triggered modes.
31.7.1.2
Interrupt Source Enabling
Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the
command registers; AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt
Disable Command Register). This set of registers conducts enabling or disabling in one instruction. The interrupt mask can be read in the AIC_IMR register. A disabled interrupt does not affect
servicing of other interrupts.
31.7.1.3
Interrupt Clearing and Setting
All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be
individually set or cleared by writing respectively the AIC_ISCR and AIC_ICCR registers. Clearing or setting interrupt sources programmed in level-sensitive mode has no effect.
The clear operation is perfunctory, as the software must perform an action to reinitialize the
“memorization” circuitry activated when the source is programmed in edge-triggered mode.
However, the set operation is available for auto-test or software debug purposes. It can also be
used to execute an AIC-implementation of a software interrupt.
The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector
Register) is read. Only the interrupt source being detected by the AIC as the current interrupt is
affected by this operation. (See “Priority Controller” on page 433.) The automatic clear reduces
the operations required by the interrupt service routine entry code to reading the AIC_IVR. Note
that the automatic interrupt clear is disabled if the interrupt source has the Fast Forcing feature
enabled as it is considered uniquely as a FIQ source. (For further details, See “Fast Forcing” on
page 437.)
The automatic clear of the interrupt source 0 is performed when AIC_FVR is read.
31.7.1.4
Interrupt Status
For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and its
mask in AIC_IMR (Interrupt Mask Register). AIC_IPR enables the actual activity of the sources,
whether masked or not.
The AIC_ISR register reads the number of the current interrupt (see “Priority Controller” on page
433) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the
processor.
Each status referred to above can be used to optimize the interrupt handling of the systems.
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31.7.1.5
Internal Interrupt Source Input Stage
Figure 31-4.
Internal Interrupt Source Input Stage
AIC_SMRI
(SRCTYPE)
Level/
Edge
Source i
AIC_IPR
AIC_IMR
Fast Interrupt Controller
or
Priority Controller
Edge
AIC_IECR
Detector
Set Clear
FF
AIC_ISCR
AIC_ICCR
AIC_IDCR
31.7.1.6
External Interrupt Source Input Stage
Figure 31-5. External Interrupt Source Input Stage
High/Low
AIC_SMRi
SRCTYPE
Level/
Edge
AIC_IPR
AIC_IMR
Source i
Fast Interrupt Controller
or
Priority Controller
AIC_IECR
Pos./Neg.
Edge
Detector
Set
AIC_ISCR
FF
Clear
AIC_IDCR
AIC_ICCR
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31.7.2
Interrupt Latencies
Global interrupt latencies depend on several parameters, including:
• The time the software masks the interrupts.
• Occurrence, either at the processor level or at the AIC level.
• The execution time of the instruction in progress when the interrupt occurs.
• The treatment of higher priority interrupts and the resynchronization of the hardware signals.
This section addresses only the hardware resynchronization. It gives details of the latency times
between the event on an external interrupt leading in a valid interrupt (edge or level) or the
assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the processor. The resynchronization time depends on the programming of the interrupt source and on
its type (internal or external). For the standard interrupt, resynchronization times are given
assuming there is no higher priority in progress.
The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt
sources.
31.7.2.1
External Interrupt Edge Triggered Source
Figure 31-6.
External Interrupt Edge Triggered Source
MCK
IRQ or FIQ
(Positive Edge)
IRQ or FIQ
(Negative Edge)
nIRQ
Maximum IRQ Latency = 4 Cycles
nFIQ
Maximum FIQ Latency = 4 Cycles
31.7.2.2
External Interrupt Level Sensitive Source
Figure 31-7.
External Interrupt Level Sensitive Source
MCK
IRQ or FIQ
(High Level)
IRQ or FIQ
(Low Level)
nIRQ
Maximum IRQ
Latency = 3 Cycles
nFIQ
Maximum FIQ
Latency = 3 cycles
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31.7.2.3
Internal Interrupt Edge Triggered Source
Figure 31-8.
Internal Interrupt Edge Triggered Source
MCK
nIRQ
Maximum IRQ Latency = 4.5 Cycles
Peripheral Interrupt
Becomes Active
31.7.2.4
Internal Interrupt Level Sensitive Source
Figure 31-9.
Internal Interrupt Level Sensitive Source
MCK
nIRQ
Maximum IRQ Latency = 3.5 Cycles
Peripheral Interrupt
Becomes Active
31.7.3
31.7.3.1
Normal Interrupt
Priority Controller
An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt
conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast
Forcing).
Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the PRIOR field of the corresponding AIC_SMR (Source Mode Register). Level 7 is the
highest priority and level 0 the lowest.
As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SMR
(Source Mode Register), the nIRQ line is asserted. As a new interrupt condition might have happened on other interrupt sources since the nIRQ has been asserted, the priority controller
determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register) is read. The
read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider
that the interrupt has been taken into account by the software.
The current priority level is defined as the priority level of the current interrupt.
If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read,
the interrupt with the lowest interrupt source number is serviced first.
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The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a
higher priority. If an interrupt condition happens (or is pending) during the interrupt treatment in
progress, it is delayed until the software indicates to the AIC the end of the current service by
writing the AIC_EOICR (End of Interrupt Command Register). The write of AIC_EOICR is the
exit point of the interrupt handling.
31.7.3.2
Interrupt Nesting
The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled
during the service of lower priority interrupts. This requires the interrupt service routines of the
lower interrupts to re-enable the interrupt at the processor level.
When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is re-asserted. If the interrupt is enabled at the core level, the current
execution is interrupted and the new interrupt service routine should read the AIC_IVR. At this
time, the current interrupt number and its priority level are pushed into an embedded hardware
stack, so that they are saved and restored when the higher priority interrupt servicing is finished
and the AIC_EOICR is written.
The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt
nestings pursuant to having eight priority levels.
31.7.3.3
Interrupt Vectoring
The interrupt handler addresses corresponding to each interrupt source can be stored in the registers AIC_SVR1 to AIC_SVR31 (Source Vector Register 1 to 31). When the processor reads
AIC_IVR (Interrupt Vector Register), the value written into AIC_SVR corresponding to the current interrupt is returned.
This feature offers a way to branch in one single instruction to the handler corresponding to the
current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus accessible from the ARM interrupt vector at address 0x0000 0018 through the following instruction:
LDR
PC,[PC,# -&F20]
When the processor executes this instruction, it loads the read value in AIC_IVR in its program
counter, thus branching the execution on the correct interrupt handler.
This feature is often not used when the application is based on an operating system (either real
time or not). Operating systems often have a single entry point for all the interrupts and the first
task performed is to discern the source of the interrupt.
However, it is strongly recommended to port the operating system on AT91 products by supporting the interrupt vectoring. This can be performed by defining all the AIC_SVR of the interrupt
source to be handled by the operating system at the address of its interrupt handler. When doing
so, the interrupt vectoring permits a critical interrupt to transfer the execution on a specific very
fast handler and not onto the operating system’s general interrupt handler. This facilitates the
support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral handling) to be handled efficiently and independently of the application running under an operating
system.
31.7.3.4
434
Interrupt Handlers
This section gives an overview of the fast interrupt handling sequence when using the AIC. It is
assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and the associated status bits.
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It is assumed that:
1. The Advanced Interrupt Controller has been programmed, AIC_SVR registers are
loaded with corresponding interrupt service routine addresses and interrupts are
enabled.
2. The instruction at the ARM interrupt exception vector address is required to work with
the vectoring
LDR PC, [PC, # -&F20]
When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows:
1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in
the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with 0x18.
In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_irq, decrementing it by four.
2. The ARM core enters Interrupt mode, if it has not already done so.
3. When the instruction loaded at address 0x18 is executed, the program counter is
loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects:
– Sets the current interrupt to be the pending and enabled interrupt with the highest
priority. The current level is the priority level of the current interrupt.
– De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR
must be read in order to de-assert nIRQ.
– Automatically clears the interrupt, if it has been programmed to be edge-triggered.
– Pushes the current level and the current interrupt number on to the stack.
– Returns the value written in the AIC_SVR corresponding to the current interrupt.
4. The previous step has the effect of branching to the corresponding interrupt service
routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link
register must be decremented by four when it is saved if it is to be restored directly into
the program counter at the end of the interrupt. For example, the instruction SUB PC,
LR, #4 may be used.
5. Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing reassertion of the nIRQ to be taken into account by the core. This can happen if an interrupt with a higher priority than the current interrupt occurs.
6. The interrupt handler can then proceed as required, saving the registers that will be
used and restoring them at the end. During this phase, an interrupt of higher priority
than the current level will restart the sequence from step 1.
Note:
If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase.
7. The “I” bit in CPSR must be set in order to mask interrupts before exiting to ensure that
the interrupt is completed in an orderly manner.
8. The End of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the current interrupt is finished. This causes the current level to be
popped from the stack, restoring the previous current level if one exists on the stack. If
another interrupt is pending, with lower or equal priority than the old current level but
with higher priority than the new current level, the nIRQ line is re-asserted, but the interrupt sequence does not immediately start because the “I” bit is set in the core.
SPSR_irq is restored. Finally, the saved value of the link register is restored directly into
the PC. This has the effect of returning from the interrupt to whatever was being executed before, and of loading the CPSR with the stored SPSR, masking or unmasking
the interrupts depending on the state saved in SPSR_irq.
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Note:
31.7.4
The “I” bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of
masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored,
the mask instruction is completed (interrupt is masked).
Fast Interrupt
31.7.4.1
Fast Interrupt Source
The interrupt source 0 is the only source which can raise a fast interrupt request to the processor
except if fast forcing is used. The interrupt source 0 is generally connected to a FIQ pin of the
product, either directly or through a PIO Controller.
31.7.4.2
Fast Interrupt Control
The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is
programmed with the AIC_SMR0 and the field PRIOR of this register is not used even if it reads
what has been written. The field SRCTYPE of AIC_SMR0 enables programming the fast interrupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or
low-level sensitive
Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt
Disable Command Register) respectively enables and disables the fast interrupt. The bit 0 of
AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is enabled or disabled.
31.7.4.3
Fast Interrupt Vectoring
The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0). The
value written into this register is returned when the processor reads AIC_FVR (Fast Vector Register). This offers a way to branch in one single instruction to the interrupt handler, as AIC_FVR
is mapped at the absolute address 0xFFFF F104 and thus accessible from the ARM fast interrupt vector at address 0x0000 001C through the following instruction:
LDR
PC,[PC,# -&F20]
When the processor executes this instruction it loads the value read in AIC_FVR in its program
counter, thus branching the execution on the fast interrupt handler. It also automatically performs the clear of the fast interrupt source if it is programmed in edge-triggered mode.
31.7.4.4
Fast Interrupt Handlers
This section gives an overview of the fast interrupt handling sequence when using the AIC. It is
assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and associated status bits.
Assuming that:
1. The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with
the fast interrupt service routine address, and the interrupt source 0 is enabled.
2. The Instruction at address 0x1C (FIQ exception vector address) is required to vector
the fast interrupt:
LDR PC, [PC, # -&F20]
3. The user does not need nested fast interrupts.
When nFIQ is asserted, if the bit “F” of CPSR is 0, the sequence is:
1. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in
the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In
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the following cycle, during fetch at address 0x20, the ARM core adjusts R14_fiq, decrementing it by four.
2. The ARM core enters FIQ mode.
3. When the instruction loaded at address 0x1C is executed, the program counter is
loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automatically clearing the fast interrupt, if it has been programmed to be edge triggered. In this
case only, it de-asserts the nFIQ line on the processor.
4. The previous step enables branching to the corresponding interrupt service routine. It is
not necessary to save the link register R14_fiq and SPSR_fiq if nested fast interrupts
are not needed.
5. The Interrupt Handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to
R13 are banked. The other registers, R0 to R7, must be saved before being used, and
restored at the end (before the next step). Note that if the fast interrupt is programmed
to be level sensitive, the source of the interrupt must be cleared during this phase in
order to de-assert the interrupt source 0.
6. Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four
(with instruction SUB PC, LR, #4 for example). This has the effect of returning from
the interrupt to whatever was being executed before, loading the CPSR with the SPSR
and masking or unmasking the fast interrupt depending on the state saved in the
SPSR.
Note:
The “F” bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to mask
FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the
interrupted instruction is completed (FIQ is masked).
Another way to handle the fast interrupt is to map the interrupt service routine at the address of
the ARM vector 0x1C. This method does not use the vectoring, so that reading AIC_FVR must
be performed at the very beginning of the handler operation. However, this method saves the
execution of a branch instruction.
31.7.4.5
Fast Forcing
The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal
Interrupt source on the fast interrupt controller.
Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER)
and the Fast Forcing Disable Register (AIC_FFDR). Writing to these registers results in an
update of the Fast Forcing Status Register (AIC_FFSR) that controls the feature for each internal or external interrupt source.
When Fast Forcing is disabled, the interrupt sources are handled as described in the previous
pages.
When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detection of the interrupt source is still active but the source cannot trigger a normal interrupt to the
processor and is not seen by the priority handler.
If the interrupt source is programmed in level-sensitive mode and an active level is sampled,
Fast Forcing results in the assertion of the nFIQ line to the core.
If the interrupt source is programmed in edge-triggered mode and an active edge is detected,
Fast Forcing results in the assertion of the nFIQ line to the core.
The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Register (AIC_IPR).
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The FIQ Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0
(AIC_SVR0), whatever the source of the fast interrupt may be. The read of the FVR does not
clear the Source 0 when the fast forcing feature is used and the interrupt source should be
cleared by writing to the Interrupt Clear Command Register (AIC_ICCR).
All enabled and pending interrupt sources that have the fast forcing feature enabled and that are
programmed in edge-triggered mode must be cleared by writing to the Interrupt Clear Command
Register. In doing so, they are cleared independently and thus lost interrupts are prevented.
The read of AIC_IVR does not clear the source that has the fast forcing feature enabled.
The source 0, reserved to the fast interrupt, continues operating normally and becomes one of
the Fast Interrupt sources.
Figure 31-10. Fast Forcing
Source 0 _ FIQ
AIC_IPR
Input Stage
Automatic Clear
AIC_IMR
nFIQ
Read FVR if Fast Forcing is
disabled on Sources 1 to 31.
AIC_FFSR
Source n
AIC_IPR
Input Stage
Priority
Manager
Automatic Clear
AIC_IMR
nIRQ
Read IVR if Source n is the current interrupt
and if Fast Forcing is disabled on Source n.
31.7.5
Protect Mode
The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a
debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the IVR.
This has undesirable consequences:
• If an enabled interrupt with a higher priority than the current one is pending, it is stacked.
• If there is no enabled pending interrupt, the spurious vector is returned.
In either case, an End of Interrupt command is necessary to acknowledge and to restore the
context of the AIC. This operation is generally not performed by the debug system as the debug
system would become strongly intrusive and cause the application to enter an undesired state.
This is avoided by using the Protect Mode. Writing PROT in AIC_DCR (Debug Control Register)
at 0x1 enables the Protect Mode.
When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access
is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary
data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the
Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is
written.
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An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the
AIC_ISR. Extra AIC_IVR reads perform the same operations. However, it is recommended to
not stop the processor between the read and the write of AIC_IVR of the interrupt service routine
to make sure the debugger does not modify the AIC context.
To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC:
1. Calculates active interrupt (higher than current or spurious).
2. Determines and returns the vector of the active interrupt.
3. Memorizes the interrupt.
4. Pushes the current priority level onto the internal stack.
5. Acknowledges the interrupt.
However, while the Protect Mode is activated, only operations 1 to 3 are performed when
AIC_IVR is read. Operations 4 and 5 are only performed by the AIC when AIC_IVR is written.
Software that has been written and debugged using the Protect Mode runs correctly in Normal
Mode without modification. However, in Normal Mode the AIC_IVR write has no effect and can
be removed to optimize the code.
31.7.6
Spurious Interrupt
The Advanced Interrupt Controller features protection against spurious interrupts. A spurious
interrupt is defined as being the assertion of an interrupt source long enough for the AIC to
assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when:
• An external interrupt source is programmed in level-sensitive mode and an active level occurs
for only a short time.
• An internal interrupt source is programmed in level sensitive and the output signal of the
corresponding embedded peripheral is activated for a short time. (As in the case for the
Watchdog.)
• An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a
pulse on the interrupt source.
The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt
source is pending. When this happens, the AIC returns the value stored by the programmer in
AIC_SPU (Spurious Vector Register). The programmer must store the address of a spurious
interrupt handler in AIC_SPU as part of the application, to enable an as fast as possible return to
the normal execution flow. This handler writes in AIC_EOICR and performs a return from
interrupt.
31.7.7
General Interrupt Mask
The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor.
Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR
(Debug Control Register) is set. However, this mask does not prevent waking up the processor if
it has entered Idle Mode. This function facilitates synchronizing the processor on a next event
and, as soon as the event occurs, performs subsequent operations without having to handle an
interrupt. It is strongly recommended to use this mask with caution.
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31.8
Advanced Interrupt Controller (AIC) User Interface
31.8.1
Base Address
The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only a ± 4-Kbyte offset.
Table 31-3.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
0x04
Source Mode Register 0
AIC_SMR0
Read-write
0x0
Source Mode Register 1
AIC_SMR1
Read-write
0x0
---
---
---
---
---
0x7C
Source Mode Register 31
AIC_SMR31
Read-write
0x0
0x80
Source Vector Register 0
AIC_SVR0
Read-write
0x0
0x84
Source Vector Register 1
AIC_SVR1
Read-write
0x0
---
---
---
---
---
0xFC
Source Vector Register 31
AIC_SVR31
Read-write
0x0
0x100
Interrupt Vector Register
AIC_IVR
Read-only
0x0
0x104
FIQ Interrupt Vector Register
AIC_FVR
Read-only
0x0
0x108
Interrupt Status Register
AIC_ISR
Read-only
0x0
AIC_IPR
Read-only
0x0(1)
(2)
0x10C
Interrupt Pending Register
0x110
Interrupt Mask Register(2)
AIC_IMR
Read-only
0x0
0x114
Core Interrupt Status Register
AIC_CISR
Read-only
0x0
0x118 - 0x11C
Reserved
---
---
---
AIC_IECR
Write-only
---
AIC_IDCR
Write-only
---
AIC_ICCR
Write-only
---
AIC_ISCR
Write-only
---
AIC_EOICR
Write-only
---
0x120
Interrupt Enable Command Register
(2)
0x124
Interrupt Disable Command Register
0x128
Interrupt Clear Command Register(2)
(2)
(2)
0x12C
Interrupt Set Command Register
0x130
End of Interrupt Command Register
0x134
Spurious Interrupt Vector Register
AIC_SPU
Read-write
0x0
0x138
Debug Control Register
AIC_DCR
Read-write
0x0
0x13C
Reserved
---
---
---
AIC_FFER
Write-only
---
(2)
0x140
Fast Forcing Enable Register
(2)
AIC_FFDR
Write-only
---
AIC_FFSR
Read-only
0x0
---
---
---
Write Protect Mode Register
AIC_WPMR
Read-write
0x0
0x1E8
Write Protect Status Register
AIC_WPSR
Read-only
0x0
0x1EC - 0x1FC
Reserved
0x144
Fast Forcing Disable Register
0x148
Fast Forcing Status Register(2)
0x14C - 0x1E0
Reserved
0x1E4
Notes:
1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset,
thus not pending.
2. PID2...PID31 bit fields refer to the identifiers as defined in the Peripheral Identifiers Section of the product datasheet.
3. Values in the Version Register vary with the version of the IP block implementation.
440
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
31.8.2
Name:
AIC Source Mode Register
AIC_SMR0..AIC_SMR31
Address:
0xFFFFF000
Access:
Read-write
Reset:
0x0
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
SRCTYPE
PRIOR
• PRIOR: Priority Level
Programs the priority level for all sources except FIQ source (source 0).
The priority level can be between 0 (lowest) and 7 (highest).
The priority level is not used for the FIQ in the related SMR register AIC_SMRx.
• SRCTYPE: Interrupt Source Type
The active level or edge is not programmable for the internal interrupt sources.
SRCTYPE
Internal Interrupt Sources
External Interrupt Sources
0
0
High level Sensitive
Low level Sensitive
0
1
Positive edge triggered
Negative edge triggered
1
0
High level Sensitive
High level Sensitive
1
1
Positive edge triggered
Positive edge triggered
441
6264C–CAP–24-Mar-09
31.8.3
Name:
AIC Source Vector Register
AIC_SVR0..AIC_SVR31
Address:
0xFFFFF080
Access:
Read-write
Reset:
0x0
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
VECTOR
23
22
21
20
VECTOR
15
14
13
12
VECTOR
7
6
5
4
VECTOR
• VECTOR: Source Vector
The user may store in these registers the addresses of the corresponding handler for each interrupt source.
31.8.4
Name:
AIC Interrupt Vector Register
AIC_IVR
Address:
0xFFFFF100
Access:
Read-only
Reset:
0x0
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
IRQV
23
22
21
20
IRQV
15
14
13
12
IRQV
7
6
5
4
IRQV
• IRQV: Interrupt Vector Register
The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to
the current interrupt.
The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read.
When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU.
442
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
31.8.5
Name:
AIC FIQ Vector Register
AIC_FVR
Address:
0xFFFFF104
Access:
Read-only
Reset:
0x0
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
FIQV
23
22
21
20
FIQV
15
14
13
12
FIQV
7
6
5
4
FIQV
• FIQV: FIQ Vector Register
The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no
fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU.
31.8.6
Name:
AIC Interrupt Status Register
AIC_ISR
Address:
0xFFFFF108
Access:
Read-only
Reset:
0x0
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
IRQID
• IRQID: Current Interrupt Identifier
The Interrupt Status Register returns the current interrupt source number.
443
6264C–CAP–24-Mar-09
31.8.7
Name:
AIC Interrupt Pending Register
AIC_IPR
Address:
0xFFFFF10C
Access:
Read-only
Reset:
0x0
31
30
29
28
27
26
25
24
PID31
PID30
PID29
PID28
PID27
PID26
PID25
PID24
23
22
21
20
19
18
17
16
PID23
PID22
PID21
PID20
PID19
PID18
PID17
PID16
15
14
13
12
11
10
9
8
PID15
PID14
PID13
PID12
PID11
PID10
PID9
PID8
7
6
5
4
3
2
1
0
PID7
PID6
PID5
PID4
PID3
PID2
SYS
FIQ
• FIQ, SYS, PID2-PID31: Interrupt Pending
0 = Corresponding interrupt is not pending.
1 = Corresponding interrupt is pending.
31.8.8
Name:
AIC Interrupt Mask Register
AIC_IMR
Address:
0xFFFFF110
Access:
Read-only
Reset:
0x0
31
30
29
28
27
26
25
24
PID31
PID30
PID29
PID28
PID27
PID26
PID25
PID24
23
22
21
20
19
18
17
16
PID23
PID22
PID21
PID20
PID19
PID18
PID17
PID16
15
14
13
12
11
10
9
8
PID15
PID14
PID13
PID12
PID11
PID10
PID9
PID8
7
6
5
4
3
2
1
0
PID7
PID6
PID5
PID4
PID3
PID2
SYS
FIQ
• FIQ, SYS, PID2-PID31: Interrupt Mask
0 = Corresponding interrupt is disabled.
1 = Corresponding interrupt is enabled.
444
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
31.8.9
Name:
AIC Core Interrupt Status Register
AIC_CISR
Address:
0xFFFFF114
Access:
Read-only
Reset:
0x0
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
–
NIRQ
NFIQ
• NFIQ: NFIQ Status
0 = nFIQ line is deactivated.
1 = nFIQ line is active.
• NIRQ: NIRQ Status
0 = nIRQ line is deactivated.
1 = nIRQ line is active.
31.8.10
Name:
AIC Interrupt Enable Command Register
AIC_IECR
Address:
0xFFFFF120
Access:
Write-only
31
30
29
28
27
26
25
24
PID31
PID30
PID29
PID28
PID27
PID26
PID25
PID24
23
22
21
20
19
18
17
16
PID23
PID22
PID21
PID20
PID19
PID18
PID17
PID16
15
14
13
12
11
10
9
8
PID15
PID14
PID13
PID12
PID11
PID10
PID9
PID8
7
6
5
4
3
2
1
0
PID7
PID6
PID5
PID4
PID3
PID2
SYS
FIQ
• FIQ, SYS, PID2-PID31: Interrupt Enable
0 = No effect.
1 = Enables corresponding interrupt.
445
6264C–CAP–24-Mar-09
31.8.11
Name:
AIC Interrupt Disable Command Register
AIC_IDCR
Address:
0xFFFFF124
Access:
Write-only
31
30
29
28
27
26
25
24
PID31
PID30
PID29
PID28
PID27
PID26
PID25
PID24
23
22
21
20
19
18
17
16
PID23
PID22
PID21
PID20
PID19
PID18
PID17
PID16
15
14
13
12
11
10
9
8
PID15
PID14
PID13
PID12
PID11
PID10
PID9
PID8
7
6
5
4
3
2
1
0
PID7
PID6
PID5
PID4
PID3
PID2
SYS
FIQ
• FIQ, SYS, PID2-PID31: Interrupt Disable
0 = No effect.
1 = Disables corresponding interrupt.
31.8.12
Name:
AIC Interrupt Clear Command Register
AIC_ICCR
Address:
0xFFFFF128
Access:
Write-only
31
30
29
28
27
26
25
24
PID31
PID30
PID29
PID28
PID27
PID26
PID25
PID24
23
22
21
20
19
18
17
16
PID23
PID22
PID21
PID20
PID19
PID18
PID17
PID16
15
14
13
12
11
10
9
8
PID15
PID14
PID13
PID12
PID11
PID10
PID9
PID8
7
6
5
4
3
2
1
0
PID7
PID6
PID5
PID4
PID3
PID2
SYS
FIQ
• FIQ, SYS, PID2-PID31: Interrupt Clear
0 = No effect.
1 = Clears corresponding interrupt.
446
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
31.8.13
Name:
AIC Interrupt Set Command Register
AIC_ISCR
Address:
0xFFFFF12C
Access:
Write-only
31
30
29
28
27
26
25
24
PID31
PID30
PID29
PID28
PID27
PID26
PID25
PID24
23
22
21
20
19
18
17
16
PID23
PID22
PID21
PID20
PID19
PID18
PID17
PID16
15
14
13
12
11
10
9
8
PID15
PID14
PID13
PID12
PID11
PID10
PID9
PID8
7
6
5
4
3
2
1
0
PID7
PID6
PID5
PID4
PID3
PID2
SYS
FIQ
• FIQ, SYS, PID2-PID31: Interrupt Set
0 = No effect.
1 = Sets corresponding interrupt.
31.8.14
Name:
AIC End of Interrupt Command Register
AIC_EOICR
Address:
0xFFFFF130
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete.
Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt
treatment.
447
6264C–CAP–24-Mar-09
31.8.15
Name:
AIC Spurious Interrupt Vector Register
AIC_SPU
Address:
0xFFFFF134
Access:
Read-write
Reset:
0x0
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
SIVR
23
22
21
20
SIVR
15
14
13
12
SIVR
7
6
5
4
SIVR
• SIVR: Spurious Interrupt Vector Register
The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in
case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt.
31.8.16
Name:
AIC Debug Control Register
AIC_DCR
Address:
0xFFFFF138
Access:
Read-write
Reset:
0x0
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
–
GMSK
PROT
• PROT: Protection Mode
0 = The Protection Mode is disabled.
1 = The Protection Mode is enabled.
• GMSK: General Mask
0 = The nIRQ and nFIQ lines are normally controlled by the AIC.
1 = The nIRQ and nFIQ lines are tied to their inactive state.
448
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
31.8.17
Name:
AIC Fast Forcing Enable Register
AIC_FFER
Address:
0xFFFFF140
Access:
Write-only
31
30
29
28
27
26
25
24
PID31
PID30
PID29
PID28
PID27
PID26
PID25
PID24
23
22
21
20
19
18
17
16
PID23
PID22
PID21
PID20
PID19
PID18
PID17
PID16
15
14
13
12
11
10
9
8
PID15
PID14
PID13
PID12
PID11
PID10
PID9
PID8
7
6
5
4
3
2
1
0
PID7
PID6
PID5
PID4
PID3
PID2
SYS
–
• SYS, PID2-PID31: Fast Forcing Enable
0 = No effect.
1 = Enables the fast forcing feature on the corresponding interrupt.
31.8.18
Name:
AIC Fast Forcing Disable Register
AIC_FFDR
Address:
0xFFFFF144
Access:
Write-only
31
30
29
28
27
26
25
24
PID31
PID30
PID29
PID28
PID27
PID26
PID25
PID24
23
22
21
20
19
18
17
16
PID23
PID22
PID21
PID20
PID19
PID18
PID17
PID16
15
14
13
12
11
10
9
8
PID15
PID14
PID13
PID12
PID11
PID10
PID9
PID8
7
6
5
4
3
2
1
0
PID7
PID6
PID5
PID4
PID3
PID2
SYS
–
• SYS, PID2-PID31: Fast Forcing Disable
0 = No effect.
1 = Disables the Fast Forcing feature on the corresponding interrupt.
449
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
31.8.19
Name:
AIC Fast Forcing Status Register
AIC_FFSR
Address:
0xFFFFF148
Access:
Read-only
31
30
29
28
27
26
25
24
PID31
PID30
PID29
PID28
PID27
PID26
PID25
PID24
23
22
21
20
19
18
17
16
PID23
PID22
PID21
PID20
PID19
PID18
PID17
PID16
15
14
13
12
11
10
9
8
PID15
PID14
PID13
PID12
PID11
PID10
PID9
PID8
7
6
5
4
3
2
1
0
PID7
PID6
PID5
PID4
PID3
PID2
SYS
–
• SYS, PID2-PID31: Fast Forcing Status
0 = The Fast Forcing feature is disabled on the corresponding interrupt.
1 = The Fast Forcing feature is enabled on the corresponding interrupt.
450
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
31.8.20
Name:
AIC Write Protect Mode Register
AIC_WPMR
Address:
0xFFFFF1E4
Access:
Read-write
Reset:
See Table 31-3
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
WPKEY
23
22
21
20
WPKEY
15
14
13
12
WPKEY
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
WPEN
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x414943 (“AIC” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x414943 (“AIC” in ASCII).
Protects the registers:
• “AIC Source Mode Register” on page 441
• “AIC Source Vector Register” on page 442
• “AIC Spurious Interrupt Vector Register” on page 448
• “AIC Debug Control Register” on page 448
• WPKEY: Write Protect KEY
Should be written at value 0x414943 (“AIC” in ASCII). Writing any other value in this field aborts the write operation of the
WPEN bit. Always reads as 0.
451
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
31.8.21
Name:
AIC Write Protect Status Register
AIC_WPSR
Address:
0xFFFFF1E8
Access:
Read-only
Reset:
See Table 31-3
31
30
29
28
27
26
25
24
—
—
—
—
—
—
—
—
23
22
21
20
19
18
17
16
11
10
9
8
WPVSRC
15
14
13
12
WPVSRC
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
WPVS
• WPVS: Write Protect Violation Status
0 = No Write Protect Violation has occurred since the last read of the AIC_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the AIC_WPSR register. If this violation is an unauthorized
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write
access has been attempted.
Note:
Reading AIC_WPSR automatically clears all fields.
452
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
32. Debug Unit (DBGU)
32.1
Description
The Debug Unit provides a single entry point from the processor for access to all the debug
capabilities of Atmel’s ARM-based systems.
The Debug Unit features a two-pin UART that can be used for several debug and trace purposes
and offers an ideal medium for in-situ programming solutions and debug monitor communications. The Debug Unit two-pin UART can be used stand-alone for general purpose serial
communication. Moreover, the association with two peripheral data controller channels permits
packet handling for these tasks with processor time reduced to a minimum.
The Debug Unit also makes the Debug Communication Channel (DCC) signals provided by the
In-circuit Emulator of the ARM processor visible to the software. These signals indicate the status of the DCC read and write registers and generate an interrupt to the ARM processor, making
possible the handling of the DCC under interrupt control.
Chip Identifier registers permit recognition of the device and its revision. These registers inform
as to the sizes and types of the on-chip memories, as well as the set of embedded peripherals.
Finally, the Debug Unit features a Force NTRST capability that enables the software to decide
whether to prevent access to the system via the In-circuit Emulator. This permits protection of
the code, stored in ROM.
453
6264C–CAP–24-Mar-09
32.2
Block Diagram
Figure 32-1. Debug Unit Functional Block Diagram
Peripheral
Bridge
Peripheral DMA Controller
APB
Debug Unit
DTXD
Transmit
Power
Management
Controller
MCK
Parallel
Input/
Output
Baud Rate
Generator
Receive
DRXD
COMMRX
ARM
Processor
COMMTX
DCC
Handler
Chip ID
nTRST
ICE
Access
Handler
Interrupt
Control
dbgu_irq
Power-on
Reset
force_ntrst
Table 32-1.
Debug Unit Pin Description
Pin Name
Description
Type
DRXD
Debug Receive Data
Input
DTXD
Debug Transmit Data
Output
Figure 32-2. Debug Unit Application Example
Boot Program
Debug Monitor
Trace Manager
Debug Unit
RS232 Drivers
Programming Tool
454
Debug Console
Trace Console
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
32.3
32.3.1
Product Dependencies
I/O Lines
Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this
case, the programmer must first configure the corresponding PIO Controller to enable I/O lines
operations of the Debug Unit.
Table 32-2.
I/O Lines
Instance
Signal
I/O Line
Peripheral
DBGU
DRXD
PC30
A
DBGU
DTXD
PC31
A
32.3.2
Power Management
Depending on product integration, the Debug Unit clock may be controllable through the Power
Management Controller. In this case, the programmer must first configure the PMC to enable the
Debug Unit clock. Usually, the peripheral identifier used for this purpose is 1.
32.3.3
Interrupt Source
Depending on product integration, the Debug Unit interrupt line is connected to one of the interrupt sources of the Advanced Interrupt Controller. Interrupt handling requires programming of
the AIC before configuring the Debug Unit. Usually, the Debug Unit interrupt line connects to the
interrupt source 1 of the AIC, which may be shared with the real-time clock, the system timer
interrupt lines and other system peripheral interrupts, as shown in Figure 32-1. This sharing
requires the programmer to determine the source of the interrupt when the source 1 is triggered.
32.4
UART Operations
The Debug Unit operates as a UART, (asynchronous mode only) and supports only 8-bit character handling (with parity). It has no clock pin.
The Debug Unit's UART is made up of a receiver and a transmitter that operate independently,
and a common baud rate generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are compatible with those of a standard USART.
32.4.1
Baud Rate Generator
The baud rate generator provides the bit period clock named baud rate clock to both the receiver
and the transmitter.
The baud rate clock is the master clock divided by 16 times the value (CD) written in
DBGU_BRGR (Baud Rate Generator Register). If DBGU_BRGR is set to 0, the baud rate clock
is disabled and the Debug Unit's UART remains inactive. The maximum allowable baud rate is
Master Clock divided by 16. The minimum allowable baud rate is Master Clock divided by (16 x
65536).
MCK
Baud Rate = ---------------------16 × CD
455
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 32-3. Baud Rate Generator
CD
CD
MCK
16-bit Counter
OUT
>1
1
0
Divide
by 16
Baud Rate
Clock
0
Receiver
Sampling Clock
32.4.2
32.4.2.1
Receiver
Receiver Reset, Enable and Disable
After device reset, the Debug Unit receiver is disabled and must be enabled before being used.
The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At
this command, the receiver starts looking for a start bit.
The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the
receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already
detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its
operation.
The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit
RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled,
whatever its current state. If RSTRX is applied when data is being processed, this data is lost.
32.4.2.2
Start Detection and Data Sampling
The Debug Unit only supports asynchronous operations, and this affects only its receiver. The
Debug Unit receiver detects the start of a received character by sampling the DRXD signal until
it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is
detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a
space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is
7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit.
When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period)
so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling
point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected.
Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
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Figure 32-4. Start Bit Detection
Sampling Clock
DRXD
True Start
Detection
D0
Baud Rate
Clock
Figure 32-5. Character Reception
Example: 8-bit, parity enabled 1 stop
0.5 bit
period
1 bit
period
DRXD
Sampling
32.4.2.3
D0
D1
True Start Detection
D2
D3
D4
D5
D6
Stop Bit
D7
Parity Bit
Receiver Ready
When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the
receive holding register DBGU_RHR is read.
Figure 32-6. Receiver Ready
DRXD
S
D0
D1
D2
D3
D4
D5
D6
D7
S
P
D0
D1
D2
D3
D4
D5
D6
D7
P
RXRDY
Read DBGU_RHR
32.4.2.4
Receiver Overrun
If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the
last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in
DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with
the bit RSTSTA (Reset Status) at 1.
Figure 32-7. Receiver Overrun
DRXD
S
D0
D1
D2
D3
D4
D5
D6
D7
P
stop
S
D0
D1
D2
D3
D4
D5
D6
D7
P
stop
RXRDY
OVRE
RSTSTA
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32.4.2.5
Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits, in
accordance with the field PAR in DBGU_MR. It then compares the result with the received parity
bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set.
The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA
(Reset Status) at 1. If a new character is received before the reset status command is written,
the PARE bit remains at 1.
Figure 32-8. Parity Error
DRXD
S
D0
D1
D2
D3
D4
D5
D6
D7
P
stop
RXRDY
PARE
Wrong Parity Bit
32.4.2.6
RSTSTA
Receiver Framing Error
When a start bit is detected, it generates a character reception when all the data bits have been
sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error)
bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until
the control register DBGU_CR is written with the bit RSTSTA at 1.
Figure 32-9. Receiver Framing Error
DRXD
S
D0
D1
D2
D3
D4
D5
D6
D7
P
stop
RXRDY
FRAME
Stop Bit
Detected at 0
32.4.3
32.4.3.1
RSTSTA
Transmitter
Transmitter Reset, Enable and Disable
After device reset, the Debug Unit transmitter is disabled and it must be enabled before being
used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1.
From this command, the transmitter waits for a character to be written in the Transmit Holding
Register DBGU_THR before actually starting the transmission.
The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the
transmitter is not operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Holding
Register, the characters are completed before the transmitter is actually stopped.
The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the
bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing
characters.
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32.4.3.2
Transmit Format
The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven
depending on the format defined in the Mode Register and the data stored in the Shift Register.
One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity
bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. The field
PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a
parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or
mark bit.
Figure 32-10. Character Transmission
Example: Parity enabled
Baud Rate
Clock
DTXD
Start
Bit
32.4.3.3
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
Transmitter Control
When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register
DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift
Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As
soon as the first character is completed, the last character written in DBGU_THR is transferred
into the shift register and TXRDY rises again, showing that the holding register is empty.
When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in
DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been
completed.
Figure 32-11. Transmitter Control
DBGU_THR
Data 0
Data 1
Shift Register
DTXD
Data 0
S
Data 0
Data 1
P
stop
S
Data 1
P
stop
TXRDY
TXEMPTY
Write Data 0
in DBGU_THR
Write Data 1
in DBGU_THR
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32.4.4
Peripheral Data Controller
Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a
Peripheral Data Controller (PDC) channel.
The peripheral data controller channels are programmed via registers that are mapped within
the Debug Unit user interface from the offset 0x100. The status bits are reported in the Debug
Unit status register DBGU_SR and can generate an interrupt.
The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of
the data in DBGU_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of a data in DBGU_THR.
32.4.5
Test Modes
The Debug Unit supports three tests modes. These modes of operation are programmed by
using the field CHMODE (Channel Mode) in the mode register DBGU_MR.
The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD
line, it is sent to the DTXD line. The transmitter operates normally, but has no effect on the
DTXD line.
The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD
pins are not used and the output of the transmitter is internally connected to the input of the
receiver. The DRXD pin level has no effect and the DTXD line is held high, as in idle state.
The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter
and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission.
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AT91CAP9S500A/AT91CAP9S250A
Figure 32-12. Test Modes
Automatic Echo
RXD
Receiver
Transmitter
Disabled
TXD
Local Loopback
Disabled
Receiver
RXD
VDD
Disabled
Transmitter
Remote Loopback
Receiver
Transmitter
32.4.6
TXD
VDD
Disabled
Disabled
RXD
TXD
Debug Communication Channel Support
The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator.
The Debug Communication Channel contains two registers that are accessible through the ICE
Breaker on the JTAG side and through the coprocessor 0 on the ARM Processor side.
As a reminder, the following instructions are used to read and write the Debug Communication
Channel:
MRC
p14, 0, Rd, c1, c0, 0
Returns the debug communication data read register into Rd
MCR
p14, 0, Rd, c1, c0, 0
Writes the value in Rd to the debug communication data write register.
The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been
written by the debugger but not yet read by the processor, and that the write register has been
written by the processor and not yet read by the debugger, are wired on the two highest bits of
the status register DBGU_SR. These bits can generate an interrupt. This feature permits handling under interrupt a debug link between a debug monitor running on the target system and a
debugger.
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6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
32.4.7
Chip Identifier
The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and
DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only. The first
register contains the following fields:
• EXT - shows the use of the extension identifier register
• NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size
• ARCH - identifies the set of embedded peripherals
• SRAMSIZ - indicates the size of the embedded SRAM
• EPROC - indicates the embedded ARM processor
• VERSION - gives the revision of the silicon
The second register is device-dependent and reads 0 if the bit EXT is 0.
32.4.8
ICE Access Prevention
The Debug Unit allows blockage of access to the system through the ARM processor's ICE
interface. This feature is implemented via the register Force NTRST (DBGU_FNR), that allows
assertion of the NTRST signal of the ICE Interface. Writing the bit FNTRST (Force NTRST) to 1
in this register prevents any activity on the TAP controller.
On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access.
This feature is especially useful on custom ROM devices for customers who do not want their
on-chip code to be visible.
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32.5
Debug Unit (DBGU) User Interface
Table 32-3.
Register Mapping
Offset
Register
Name
Access
Reset
0x0000
Control Register
DBGU_CR
Write-only
–
0x0004
Mode Register
DBGU_MR
Read-write
0x0
0x0008
Interrupt Enable Register
DBGU_IER
Write-only
–
0x000C
Interrupt Disable Register
DBGU_IDR
Write-only
–
0x0010
Interrupt Mask Register
DBGU_IMR
Read-only
0x0
0x0014
Status Register
DBGU_SR
Read-only
–
0x0018
Receive Holding Register
DBGU_RHR
Read-only
0x0
0x001C
Transmit Holding Register
DBGU_THR
Write-only
–
0x0020
Baud Rate Generator Register
DBGU_BRGR
Read-write
0x0
–
–
–
0x0024 - 0x003C
Reserved
0x0040
Chip ID Register
DBGU_CIDR
Read-only
–
0x0044
Chip ID Extension Register
DBGU_EXID
Read-only
–
0x0048
Force NTRST Register
DBGU_FNR
Read-write
0x0
–
–
–
0x0100 - 0x0124
PDC Area
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32.5.1
Name:
Debug Unit Control Register
DBGU_CR
Address:
0xFFFFEE00
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
RSTSTA
7
6
5
4
3
2
1
0
TXDIS
TXEN
RXDIS
RXEN
RSTTX
RSTRX
–
–
• RSTRX: Reset Receiver
0 = No effect.
1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
• RSTTX: Reset Transmitter
0 = No effect.
1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted.
• RXEN: Receiver Enable
0 = No effect.
1 = The receiver is enabled if RXDIS is 0.
• RXDIS: Receiver Disable
0 = No effect.
1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the
receiver is stopped.
• TXEN: Transmitter Enable
0 = No effect.
1 = The transmitter is enabled if TXDIS is 0.
• TXDIS: Transmitter Disable
0 = No effect.
1 = The transmitter is disabled. If a character is being processed and a character has been written the DBGU_THR and
RSTTX is not set, both characters are completed before the transmitter is stopped.
• RSTSTA: Reset Status Bits
0 = No effect.
1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR.
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32.5.2
Name:
Debug Unit Mode Register
DBGU_MR
Address:
0xFFFFEE04
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
14
13
12
11
10
9
–
–
15
CHMODE
8
–
PAR
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
• PAR: Parity Type
PAR
Parity Type
0
0
0
Even parity
0
0
1
Odd parity
0
1
0
Space: parity forced to 0
0
1
1
Mark: parity forced to 1
1
x
x
No parity
• CHMODE: Channel Mode
CHMODE
Mode Description
0
0
Normal Mode
0
1
Automatic Echo
1
0
Local Loopback
1
1
Remote Loopback
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AT91CAP9S500A/AT91CAP9S250A
32.5.3
Name:
Debug Unit Interrupt Enable Register
DBGU_IER
Address:
0xFFFFEE08
Access:
Write-only
31
30
29
28
27
26
25
24
COMMRX
COMMTX
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
RXBUFF
TXBUFE
–
TXEMPTY
–
7
6
5
4
3
2
1
0
PARE
FRAME
OVRE
ENDTX
ENDRX
–
TXRDY
RXRDY
• RXRDY: Enable RXRDY Interrupt
• TXRDY: Enable TXRDY Interrupt
• ENDRX: Enable End of Receive Transfer Interrupt
• ENDTX: Enable End of Transmit Interrupt
• OVRE: Enable Overrun Error Interrupt
• FRAME: Enable Framing Error Interrupt
• PARE: Enable Parity Error Interrupt
• TXEMPTY: Enable TXEMPTY Interrupt
• TXBUFE: Enable Buffer Empty Interrupt
• RXBUFF: Enable Buffer Full Interrupt
• COMMTX: Enable COMMTX (from ARM) Interrupt
• COMMRX: Enable COMMRX (from ARM) Interrupt
0 = No effect.
1 = Enables the corresponding interrupt.
466
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
32.5.4
Name:
Debug Unit Interrupt Disable Register
DBGU_IDR
Address:
0xFFFFEE0C
Access:
Write-only
31
30
29
28
27
26
25
24
COMMRX
COMMTX
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
RXBUFF
TXBUFE
–
TXEMPTY
–
7
6
5
4
3
2
1
0
PARE
FRAME
OVRE
ENDTX
ENDRX
–
TXRDY
RXRDY
• RXRDY: Disable RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Disable End of Receive Transfer Interrupt
• ENDTX: Disable End of Transmit Interrupt
• OVRE: Disable Overrun Error Interrupt
• FRAME: Disable Framing Error Interrupt
• PARE: Disable Parity Error Interrupt
• TXEMPTY: Disable TXEMPTY Interrupt
• TXBUFE: Disable Buffer Empty Interrupt
• RXBUFF: Disable Buffer Full Interrupt
• COMMTX: Disable COMMTX (from ARM) Interrupt
• COMMRX: Disable COMMRX (from ARM) Interrupt
0 = No effect.
1 = Disables the corresponding interrupt.
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AT91CAP9S500A/AT91CAP9S250A
32.5.5
Name:
Debug Unit Interrupt Mask Register
DBGU_IMR
Address:
0xFFFFEE10
Access:
Read-only
31
30
29
28
27
26
25
24
COMMRX
COMMTX
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
RXBUFF
TXBUFE
–
TXEMPTY
–
7
6
5
4
3
2
1
0
PARE
FRAME
OVRE
ENDTX
ENDRX
–
TXRDY
RXRDY
• RXRDY: Mask RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Mask End of Receive Transfer Interrupt
• ENDTX: Mask End of Transmit Interrupt
• OVRE: Mask Overrun Error Interrupt
• FRAME: Mask Framing Error Interrupt
• PARE: Mask Parity Error Interrupt
• TXEMPTY: Mask TXEMPTY Interrupt
• TXBUFE: Mask TXBUFE Interrupt
• RXBUFF: Mask RXBUFF Interrupt
• COMMTX: Mask COMMTX Interrupt
• COMMRX: Mask COMMRX Interrupt
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
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6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
32.5.6
Name:
Debug Unit Status Register
DBGU_SR
Address:
0xFFFFEE14
Access:
Read-only
31
30
29
28
27
26
25
24
COMMRX
COMMTX
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
RXBUFF
TXBUFE
–
TXEMPTY
–
7
6
5
4
3
2
1
0
PARE
FRAME
OVRE
ENDTX
ENDRX
–
TXRDY
RXRDY
• RXRDY: Receiver Ready
0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled.
1 = At least one complete character has been received, transferred to DBGU_RHR and not yet read.
• TXRDY: Transmitter Ready
0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled.
1 = There is no character written to DBGU_THR not yet transferred to the Shift Register.
• ENDRX: End of Receiver Transfer
0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive.
1 = The End of Transfer signal from the receiver Peripheral Data Controller channel is active.
• ENDTX: End of Transmitter Transfer
0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive.
1 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is active.
• OVRE: Overrun Error
0 = No overrun error has occurred since the last RSTSTA.
1 = At least one overrun error has occurred since the last RSTSTA.
• FRAME: Framing Error
0 = No framing error has occurred since the last RSTSTA.
1 = At least one framing error has occurred since the last RSTSTA.
• PARE: Parity Error
0 = No parity error has occurred since the last RSTSTA.
1 = At least one parity error has occurred since the last RSTSTA.
• TXEMPTY: Transmitter Empty
0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled.
1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter.
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AT91CAP9S500A/AT91CAP9S250A
• TXBUFE: Transmission Buffer Empty
0 = The buffer empty signal from the transmitter PDC channel is inactive.
1 = The buffer empty signal from the transmitter PDC channel is active.
• RXBUFF: Receive Buffer Full
0 = The buffer full signal from the receiver PDC channel is inactive.
1 = The buffer full signal from the receiver PDC channel is active.
• COMMTX: Debug Communication Channel Write Status
0 = COMMTX from the ARM processor is inactive.
1 = COMMTX from the ARM processor is active.
• COMMRX: Debug Communication Channel Read Status
0 = COMMRX from the ARM processor is inactive.
1 = COMMRX from the ARM processor is active.
470
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AT91CAP9S500A/AT91CAP9S250A
32.5.7
Name:
Debug Unit Receiver Holding Register
DBGU_RHR
Address:
0xFFFFEE18
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
RXCHR
• RXCHR: Received Character
Last received character if RXRDY is set.
32.5.8
Name:
Debug Unit Transmit Holding Register
DBGU_THR
Address:
0xFFFFEE1C
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
TXCHR
• TXCHR: Character to be Transmitted
Next character to be transmitted after the current character if TXRDY is not set.
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AT91CAP9S500A/AT91CAP9S250A
32.5.9
Name:
Debug Unit Baud Rate Generator Register
DBGU_BRGR
Address:
0xFFFFEE20
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
3
2
1
0
CD
7
6
5
4
CD
• CD: Clock Divisor
CD
Baud Rate Clock
0
Disabled
1
MCK
2 to 65535
MCK / (CD x 16)
472
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
32.5.10
Name:
Debug Unit Chip ID Register
DBGU_CIDR
Address:
0xFFFFEE40
Access:
Read-only
31
30
29
EXT
23
28
27
26
NVPTYP
22
21
20
19
18
ARCH
15
14
13
6
24
17
16
9
8
1
0
SRAMSIZ
12
11
10
NVPSIZ2
7
25
ARCH
NVPSIZ
5
4
3
EPROC
2
VERSION
• VERSION: Version of the Device
Values depend upon the version of the device.
• EPROC: Embedded Processor
EPROC
Processor
0
0
1
ARM946ES
0
1
0
ARM7TDMI
1
0
0
ARM920T
1
0
1
ARM926EJS
• NVPSIZ: Nonvolatile Program Memory Size
NVPSIZ
Size
0
0
0
0
None
0
0
0
1
8K bytes
0
0
1
0
16K bytes
0
0
1
1
32K bytes
0
1
0
0
Reserved
0
1
0
1
64K bytes
0
1
1
0
Reserved
0
1
1
1
128K bytes
1
0
0
0
Reserved
1
0
0
1
256K bytes
1
0
1
0
512K bytes
1
0
1
1
Reserved
1
1
0
0
1024K bytes
1
1
0
1
Reserved
1
1
1
0
2048K bytes
1
1
1
1
Reserved
473
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• NVPSIZ2 Second Nonvolatile Program Memory Size
NVPSIZ2
Size
0
0
0
0
None
0
0
0
1
8K bytes
0
0
1
0
16K bytes
0
0
1
1
32K bytes
0
1
0
0
Reserved
0
1
0
1
64K bytes
0
1
1
0
Reserved
0
1
1
1
128K bytes
1
0
0
0
Reserved
1
0
0
1
256K bytes
1
0
1
0
512K bytes
1
0
1
1
Reserved
1
1
0
0
1024K bytes
1
1
0
1
Reserved
1
1
1
0
2048K bytes
1
1
1
1
Reserved
• SRAMSIZ: Internal SRAM Size
SRAMSIZ
Size
0
0
0
0
Reserved
0
0
0
1
1K bytes
0
0
1
0
2K bytes
0
0
1
1
6K bytes
0
1
0
0
112K bytes
0
1
0
1
4K bytes
0
1
1
0
80K bytes
0
1
1
1
160K bytes
1
0
0
0
8K bytes
1
0
0
1
16K bytes
1
0
1
0
32K bytes
1
0
1
1
64K bytes
1
1
0
0
128K bytes
1
1
0
1
256K bytes
1
1
1
0
96K bytes
1
1
1
1
512K bytes
474
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• ARCH: Architecture Identifier
ARCH
Hex
Bin
Architecture
0x19
0001 1001
AT91SAM9xx Series
0x29
0010 1001
AT91SAM9XExx Series
0x34
0011 0100
AT91x34 Series
0x37
0011 0111
CAP7 Series
0x39
0011 1001
CAP9 Series
0x3B
0011 1011
CAP11 Series
0x40
0100 0000
AT91x40 Series
0x42
0100 0010
AT91x42 Series
0x55
0101 0101
AT91x55 Series
0x60
0110 0000
AT91SAM7Axx Series
0x61
0110 0001
AT91SAM7AQxx Series
0x63
0110 0011
AT91x63 Series
0x70
0111 0000
AT91SAM7Sxx Series
0x71
0111 0001
AT91SAM7XCxx Series
0x72
0111 0010
AT91SAM7SExx Series
0x73
0111 0011
AT91SAM7Lxx Series
0x75
0111 0101
AT91SAM7Xxx Series
0x92
1001 0010
AT91x92 Series
0xF0
1111 0000
AT75Cxx Series
• NVPTYP: Nonvolatile Program Memory Type
NVPTYP
Memory
0
0
0
ROM
0
0
1
ROMless or on-chip Flash
1
0
0
SRAM emulating ROM
0
1
0
Embedded Flash Memory
0
1
1
ROM and Embedded Flash Memory
NVPSIZ is ROM size
NVPSIZ2 is Flash size
• EXT: Extension Flag
0 = Chip ID has a single register definition without extension
1 = An extended Chip ID exists.
475
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
32.5.11
Name:
Debug Unit Chip ID Extension Register
DBGU_EXID
Address:
0xFFFFEE44
Access:
Read-only
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
EXID
23
22
21
20
EXID
15
14
13
12
EXID
7
6
5
4
EXID
• EXID: Chip ID Extension
Reads 0 if the bit EXT in DBGU_CIDR is 0.
32.5.12
Name:
Debug Unit Force NTRST Register
DBGU_FNR
Address:
0xFFFFEE48
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
FNTRST
• FNTRST: Force NTRST
0 = NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal.
1 = NTRST of the ARM processor’s TAP controller is held low.
476
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
33. Parallel Input/Output Controller (PIO)
33.1
Description
The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output
lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of
an embedded peripheral. This assures effective optimization of the pins of a product.
Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User
Interface.
Each I/O line of the PIO Controller features:
• An input change interrupt enabling level change detection on any I/O line.
• A glitch filter providing rejection of pulses lower than one-half of clock cycle.
• Multi-drive capability similar to an open drain I/O line.
• Control of the pull-up of the I/O line.
• Input visibility and output control.
The PIO Controller also features a synchronous output providing up to 32 bits of data output in a
single write operation.
477
6264C–CAP–24-Mar-09
33.2
Block Diagram
Figure 33-1. Block Diagram
PIO Controller
AIC
PMC
PIO Interrupt
PIO Clock
Data, Enable
Up to 32
peripheral IOs
Embedded
Peripheral
PIN 0
Data, Enable
PIN 1
Up to 32 pins
Embedded
Peripheral
Up to 32
peripheral IOs
PIN 31
APB
Figure 33-2. Application Block Diagram
On-Chip Peripheral Drivers
Keyboard Driver
Control & Command
Driver
On-Chip Peripherals
PIO Controller
Keyboard Driver
478
General Purpose I/Os
External Devices
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
33.3
Product Dependencies
33.3.1
Pin Multiplexing
Each pin is configurable, according to product definition as either a general-purpose I/O line
only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must
carefully determine the configuration of the PIO controllers required by their application. When
an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of
the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product.
33.3.2
External Interrupt Lines
The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO
Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the
PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as
inputs.
33.3.3
Power Management
The Power Management Controller controls the PIO Controller clock in order to save power.
Writing any of the registers of the user interface does not require the PIO Controller clock to be
enabled. This means that the configuration of the I/O lines does not require the PIO Controller
clock to be enabled.
However, when the clock is disabled, not all of the features of the PIO Controller are available.
Note that the Input Change Interrupt and the read of the pin level require the clock to be
validated.
After a hardware reset, the PIO clock is disabled by default.
The user must configure the Power Management Controller before any access to the input line
information.
33.3.4
Interrupt Generation
For interrupt handling, the PIO Controllers are considered as user peripherals. This means that
the PIO Controller interrupt lines are connected among the interrupt sources 2 to 31. Refer to the
PIO Controller peripheral identifier in the product description to identify the interrupt sources
dedicated to the PIO Controllers.
The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled.
479
6264C–CAP–24-Mar-09
33.4
Functional Description
The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 33-3. In this description each signal shown
represents but one of up to 32 possible indexes.
Figure 33-3. I/O Line Control Logic
PIO_OER[0]
PIO_OSR[0]
PIO_PUER[0]
PIO_ODR[0]
PIO_PUSR[0]
PIO_PUDR[0]
1
Peripheral A
Output Enable
0
0
Peripheral B
Output Enable
0
1
PIO_ASR[0]
PIO_PER[0]
PIO_ABSR[0]
1
PIO_PSR[0]
PIO_BSR[0]
PIO_PDR[0]
Peripheral A
Output
0
Peripheral B
Output
1
PIO_MDER[0]
PIO_MDSR[0]
PIO_MDDR[0]
0
0
PIO_SODR[0]
PIO_ODSR[0]
1
Pad
PIO_CODR[0]
1
Peripheral A
Input
PIO_PDSR[0]
PIO_ISR[0]
0
Edge
Detector
Glitch
Filter
Peripheral B
Input
(Up to 32 possible inputs)
PIO Interrupt
1
PIO_IFER[0]
PIO_IFSR[0]
PIO_IFDR[0]
PIO_IER[0]
PIO_IMR[0]
PIO_IDR[0]
PIO_ISR[31]
PIO_IER[31]
PIO_IMR[31]
PIO_IDR[31]
480
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
33.4.1
Pull-up Resistor Control
Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled
or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pullup Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit
in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled.
Control of the pull-up resistor is possible regardless of the configuration of the I/O line.
After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0.
33.4.2
I/O Line or Peripheral Function Selection
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with
the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates
whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of
0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the
PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO
controller.
If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral),
PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit.
After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR
resets at 1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for
address lines that must be driven low for booting out of an external memory). Thus, the reset
value of PIO_PSR is defined at the product level, depending on the multiplexing of the device.
33.4.3
Peripheral A or B Selection
The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The
selection is performed by writing PIO_ASR (A Select Register) and PIO_BSR (Select B Register). PIO_ABSR (AB Select Status Register) indicates which peripheral line is currently selected.
For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corresponding bit at level 1 indicates that peripheral B is selected.
Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral
input lines are always connected to the pin input.
After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A.
However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line
mode.
Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the
pin. However, assignment of a pin to a peripheral function requires a write in the corresponding
peripheral selection register (PIO_ASR or PIO_BSR) in addition to a write in PIO_PDR.
33.4.4
Output Control
When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at
0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B, depending on the
value in PIO_ABSR, determines whether the pin is driven or not.
When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This
is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register).
481
6264C–CAP–24-Mar-09
The results of these write operations are detected in PIO_OSR (Output Status Register). When
a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at
1, the corresponding I/O line is driven by the PIO controller.
The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data
Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set
and clear PIO_ODSR (Output Data Status Register), which represents the data driven on the I/O
lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to
be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller.
Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it
defines the first level driven on the I/O line.
33.4.5
Synchronous Data Output
Controlling all parallel busses using several PIOs requires two successive write operations in the
PIO_SODR and PIO_CODR registers. This may lead to unexpected transient values. The PIO
controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output
Data Status Register). Only bits unmasked by PIO_OWSR (Output Write Status Register) are
written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Output Write Enable
Register) and cleared by writing to PIO_OWDR (Output Write Disable Register).
After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at
0x0.
33.4.6
Multi Drive Control (Open Drain)
Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This
feature permits several drivers to be connected on the I/O line which is driven low only by each
device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line.
The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and
PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line
is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multi-driver
Status Register) indicates the pins that are configured to support external drivers.
After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.
33.4.7
482
Output Line Timings
Figure 33-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by
directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is
set. Figure 33-4 also shows when the feedback in PIO_PDSR is available.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 33-4. Output Line Timings
MCK
Write PIO_SODR
Write PIO_ODSR at 1
APB Access
Write PIO_CODR
Write PIO_ODSR at 0
APB Access
PIO_ODSR
2 cycles
2 cycles
PIO_PDSR
33.4.8
Inputs
The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an
input or driven by the PIO controller or driven by a peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise
PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
33.4.9
Input Glitch Filtering
Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically
rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse
durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not
be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be
visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its
duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle
latency if the pin level change occurs before a rising edge. However, this latency does not
appear if the pin level change occurs before a falling edge. This is illustrated in Figure 33-5.
The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register),
PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing
PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register
enables the glitch filter on the I/O lines.
When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals.
It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The
glitch filters require that the PIO Controller clock is enabled.
483
6264C–CAP–24-Mar-09
Figure 33-5. Input Glitch Filter Timing
MCK
up to 1.5 cycles
Pin Level
1 cycle
1 cycle
1 cycle
1 cycle
PIO_PDSR
if PIO_IFSR = 0
2 cycles
PIO_PDSR
if PIO_IFSR = 1
33.4.10
up to 2.5 cycles
1 cycle
up to 2 cycles
Input Change Interrupt
The PIO Controller can be programmed to generate an interrupt when it detects an input change
on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable
Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the
input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask
Register). As Input change detection is possible only by comparing two successive samplings of
the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is
available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function.
When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt
Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt
line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the Advanced Interrupt Controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that
all the interrupts that are pending when PIO_ISR is read must be handled.
Figure 33-6. Input Change Interrupt Timings
MCK
Pin Level
PIO_ISR
Read PIO_ISR
484
APB Access
APB Access
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
33.5
I/O Lines Programming Example
The programing example as shown in Table 33-1 below is used to define the following
configuration.
• 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain,
with pull-up resistor
• Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no
pull-up resistor
• Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up
resistors, glitch filters and input change interrupts
• Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input
change interrupt), no pull-up resistor, no glitch filter
• I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor
• I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor
• I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor
Table 33-1.
Programming Example
Register
Value to be Written
PIO_PER
0x0000 FFFF
PIO_PDR
0x0FFF 0000
PIO_OER
0x0000 00FF
PIO_ODR
0x0FFF FF00
PIO_IFER
0x0000 0F00
PIO_IFDR
0x0FFF F0FF
PIO_SODR
0x0000 0000
PIO_CODR
0x0FFF FFFF
PIO_IER
0x0F00 0F00
PIO_IDR
0x00FF F0FF
PIO_MDER
0x0000 000F
PIO_MDDR
0x0FFF FFF0
PIO_PUDR
0x00F0 00F0
PIO_PUER
0x0F0F FF0F
PIO_ASR
0x0F0F 0000
PIO_BSR
0x00F0 0000
PIO_OWER
0x0000 000F
PIO_OWDR
0x0FFF FFF0
485
6264C–CAP–24-Mar-09
33.6
Parallel Input/Output Controller (PIO) User Interface
Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined,
writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns
1 systematically.
Table 33-2.
Register Mapping
Offset
Register
Name
Access
Reset
0x0000
PIO Enable Register
PIO_PER
Write-only
–
0x0004
PIO Disable Register
PIO_PDR
Write-only
–
PIO_PSR
Read-only
(1)
0x0008
PIO Status Register
0x000C
Reserved
0x0010
Output Enable Register
PIO_OER
Write-only
–
0x0014
Output Disable Register
PIO_ODR
Write-only
–
0x0018
Output Status Register
PIO_OSR
Read-only
0x0000 0000
0x001C
Reserved
0x0020
Glitch Input Filter Enable Register
PIO_IFER
Write-only
–
0x0024
Glitch Input Filter Disable Register
PIO_IFDR
Write-only
–
0x0028
Glitch Input Filter Status Register
PIO_IFSR
Read-only
0x0000 0000
0x002C
Reserved
0x0030
Set Output Data Register
PIO_SODR
Write-only
–
0x0034
Clear Output Data Register
PIO_CODR
Write-only
0x0038
Output Data Status Register
PIO_ODSR
Read-only
or(2)
Read/Write
–
0x003C
Pin Data Status Register
PIO_PDSR
Read-only
(3)
0x0040
Interrupt Enable Register
PIO_IER
Write-only
–
0x0044
Interrupt Disable Register
PIO_IDR
Write-only
–
0x0048
Interrupt Mask Register
PIO_IMR
Read-only
0x00000000
0x004C
Interrupt Status Register(4)
PIO_ISR
Read-only
0x00000000
0x0050
Multi-driver Enable Register
PIO_MDER
Write-only
–
0x0054
Multi-driver Disable Register
PIO_MDDR
Write-only
–
0x0058
Multi-driver Status Register
PIO_MDSR
Read-only
0x00000000
0x005C
Reserved
0x0060
Pull-up Disable Register
PIO_PUDR
Write-only
–
0x0064
Pull-up Enable Register
PIO_PUER
Write-only
–
0x0068
Pad Pull-up Status Register
PIO_PUSR
Read-only
0x00000000
0x006C
Reserved
486
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Table 33-2.
Register Mapping (Continued)
Offset
Register
0x0070
0x0074
Name
Peripheral A Select Register
(5)
Peripheral B Select Register
(5)
(5)
Access
Reset
PIO_ASR
Write-only
–
PIO_BSR
Write-only
–
PIO_ABSR
Read-only
0x00000000
0x0078
AB Status Register
0x007C
to
0x009C
Reserved
0x00A0
Output Write Enable
PIO_OWER
Write-only
–
0x00A4
Output Write Disable
PIO_OWDR
Write-only
–
0x00A8
Output Write Status Register
PIO_OWSR
Read-only
0x00000000
0x00AC
Reserved
Notes:
1. Reset value of PIO_PSR depends on the product implementation.
2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO
Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have
occurred.
5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second
register.
487
6264C–CAP–24-Mar-09
33.6.1
Name:
PIO Controller PIO Enable Register
PIO_PER
Addresses: 0xFFFFF200 (PIOA), 0xFFFFF400 (PIOB), 0xFFFFF600 (PIOC), 0xFFFFF800 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: PIO Enable
0 = No effect.
1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin).
33.6.2
Name:
PIO Controller PIO Disable Register
PIO_PDR
Addresses: 0xFFFFF204 (PIOA), 0xFFFFF404 (PIOB), 0xFFFFF604 (PIOC), 0xFFFFF804 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: PIO Disable
0 = No effect.
1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).
488
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
33.6.3
Name:
PIO Controller PIO Status Register
PIO_PSR
Addresses: 0xFFFFF208 (PIOA), 0xFFFFF408 (PIOB), 0xFFFFF608 (PIOC), 0xFFFFF808 (PIOD)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: PIO Status
0 = PIO is inactive on the corresponding I/O line (peripheral is active).
1 = PIO is active on the corresponding I/O line (peripheral is inactive).
33.6.4
Name:
PIO Controller Output Enable Register
PIO_OER
Addresses: 0xFFFFF210 (PIOA), 0xFFFFF410 (PIOB), 0xFFFFF610 (PIOC), 0xFFFFF810 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Output Enable
0 = No effect.
1 = Enables the output on the I/O line.
489
6264C–CAP–24-Mar-09
33.6.5
Name:
PIO Controller Output Disable Register
PIO_ODR
Addresses: 0xFFFFF214 (PIOA), 0xFFFFF414 (PIOB), 0xFFFFF614 (PIOC), 0xFFFFF814 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Output Disable
0 = No effect.
1 = Disables the output on the I/O line.
33.6.6
Name:
PIO Controller Output Status Register
PIO_OSR
Addresses: 0xFFFFF218 (PIOA), 0xFFFFF418 (PIOB), 0xFFFFF618 (PIOC), 0xFFFFF818 (PIOD)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Output Status
0 = The I/O line is a pure input.
1 = The I/O line is enabled in output.
490
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
33.6.7
Name:
PIO Controller Input Filter Enable Register
PIO_IFER
Addresses: 0xFFFFF220 (PIOA), 0xFFFFF420 (PIOB), 0xFFFFF620 (PIOC), 0xFFFFF820 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Input Filter Enable
0 = No effect.
1 = Enables the input glitch filter on the I/O line.
33.6.8
Name:
PIO Controller Input Filter Disable Register
PIO_IFDR
Addresses: 0xFFFFF224 (PIOA), 0xFFFFF424 (PIOB), 0xFFFFF624 (PIOC), 0xFFFFF824 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Input Filter Disable
0 = No effect.
1 = Disables the input glitch filter on the I/O line.
491
6264C–CAP–24-Mar-09
33.6.9
Name:
PIO Controller Input Filter Status Register
PIO_IFSR
Addresses: 0xFFFFF228 (PIOA), 0xFFFFF428 (PIOB), 0xFFFFF628 (PIOC), 0xFFFFF828 (PIOD)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Input Filer Status
0 = The input glitch filter is disabled on the I/O line.
1 = The input glitch filter is enabled on the I/O line.
33.6.10
Name:
PIO Controller Set Output Data Register
PIO_SODR
Addresses: 0xFFFFF230 (PIOA), 0xFFFFF430 (PIOB), 0xFFFFF630 (PIOC), 0xFFFFF830 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Set Output Data
0 = No effect.
1 = Sets the data to be driven on the I/O line.
492
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
33.6.11
Name:
PIO Controller Clear Output Data Register
PIO_CODR
Addresses: 0xFFFFF234 (PIOA), 0xFFFFF434 (PIOB), 0xFFFFF634 (PIOC), 0xFFFFF834 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Set Output Data
0 = No effect.
1 = Clears the data to be driven on the I/O line.
33.6.12
Name:
PIO Controller Output Data Status Register
PIO_ODSR
Addresses: 0xFFFFF238 (PIOA), 0xFFFFF438 (PIOB), 0xFFFFF638 (PIOC), 0xFFFFF838 (PIOD)
Access:
Read-only or Read-write
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Output Data Status
0 = The data to be driven on the I/O line is 0.
1 = The data to be driven on the I/O line is 1.
493
6264C–CAP–24-Mar-09
33.6.13
Name:
PIO Controller Pin Data Status Register
PIO_PDSR
Addresses: 0xFFFFF23C (PIOA), 0xFFFFF43C (PIOB), 0xFFFFF63C (PIOC), 0xFFFFF83C (PIOD)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Output Data Status
0 = The I/O line is at level 0.
1 = The I/O line is at level 1.
33.6.14
Name:
PIO Controller Interrupt Enable Register
PIO_IER
Addresses: 0xFFFFF240 (PIOA), 0xFFFFF440 (PIOB), 0xFFFFF640 (PIOC), 0xFFFFF840 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Input Change Interrupt Enable
0 = No effect.
1 = Enables the Input Change Interrupt on the I/O line.
494
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
33.6.15
Name:
PIO Controller Interrupt Disable Register
PIO_IDR
Addresses: 0xFFFFF244 (PIOA), 0xFFFFF444 (PIOB), 0xFFFFF644 (PIOC), 0xFFFFF844 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Input Change Interrupt Disable
0 = No effect.
1 = Disables the Input Change Interrupt on the I/O line.
33.6.16
Name:
PIO Controller Interrupt Mask Register
PIO_IMR
Addresses: 0xFFFFF248 (PIOA), 0xFFFFF448 (PIOB), 0xFFFFF648 (PIOC), 0xFFFFF848 (PIOD)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Input Change Interrupt Mask
0 = Input Change Interrupt is disabled on the I/O line.
1 = Input Change Interrupt is enabled on the I/O line.
495
6264C–CAP–24-Mar-09
33.6.17
Name:
PIO Controller Interrupt Status Register
PIO_ISR
Addresses: 0xFFFFF24C (PIOA), 0xFFFFF44C (PIOB), 0xFFFFF64C (PIOC), 0xFFFFF84C (PIOD)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Input Change Interrupt Status
0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
33.6.18
Name:
PIO Multi-driver Enable Register
PIO_MDER
Addresses: 0xFFFFF250 (PIOA), 0xFFFFF450 (PIOB), 0xFFFFF650 (PIOC), 0xFFFFF850 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Multi Drive Enable.
0 = No effect.
1 = Enables Multi Drive on the I/O line.
496
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
33.6.19
Name:
PIO Multi-driver Disable Register
PIO_MDDR
Addresses: 0xFFFFF254 (PIOA), 0xFFFFF454 (PIOB), 0xFFFFF654 (PIOC), 0xFFFFF854 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Multi Drive Disable.
0 = No effect.
1 = Disables Multi Drive on the I/O line.
33.6.20
Name:
PIO Multi-driver Status Register
PIO_MDSR
Addresses: 0xFFFFF258 (PIOA), 0xFFFFF458 (PIOB), 0xFFFFF658 (PIOC), 0xFFFFF858 (PIOD)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Multi Drive Status.
0 = The Multi Drive is disabled on the I/O line. The pin is driven at high and low level.
1 = The Multi Drive is enabled on the I/O line. The pin is driven at low level only.
497
6264C–CAP–24-Mar-09
33.6.21
Name:
PIO Pull Up Disable Register
PIO_PUDR
Addresses: 0xFFFFF260 (PIOA), 0xFFFFF460 (PIOB), 0xFFFFF660 (PIOC), 0xFFFFF860 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Pull Up Disable.
0 = No effect.
1 = Disables the pull up resistor on the I/O line.
33.6.22
Name:
PIO Pull Up Enable Register
PIO_PUER
Addresses: 0xFFFFF264 (PIOA), 0xFFFFF464 (PIOB), 0xFFFFF664 (PIOC), 0xFFFFF864 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Pull Up Enable.
0 = No effect.
1 = Enables the pull up resistor on the I/O line.
498
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
33.6.23
Name:
PIO Pull Up Status Register
PIO_PUSR
Addresses: 0xFFFFF268 (PIOA), 0xFFFFF468 (PIOB), 0xFFFFF668 (PIOC), 0xFFFFF868 (PIOD)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Pull Up Status.
0 = Pull Up resistor is enabled on the I/O line.
1 = Pull Up resistor is disabled on the I/O line.
33.6.24
Name:
PIO Peripheral A Select Register
PIO_ASR
Addresses: 0xFFFFF270 (PIOA), 0xFFFFF470 (PIOB), 0xFFFFF670 (PIOC), 0xFFFFF870 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Peripheral A Select.
0 = No effect.
1 = Assigns the I/O line to the Peripheral A function.
499
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
33.6.25
Name:
PIO Peripheral B Select Register
PIO_BSR
Addresses: 0xFFFFF274 (PIOA), 0xFFFFF474 (PIOB), 0xFFFFF674 (PIOC), 0xFFFFF874 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Peripheral B Select.
0 = No effect.
1 = Assigns the I/O line to the peripheral B function.
33.6.26
Name:
PIO Peripheral A B Status Register
PIO_ABSR
Addresses: 0xFFFFF278 (PIOA), 0xFFFFF478 (PIOB), 0xFFFFF678 (PIOC), 0xFFFFF878 (PIOD)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Peripheral A B Status.
0 = The I/O line is assigned to the Peripheral A.
1 = The I/O line is assigned to the Peripheral B.
500
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
33.6.27
Name:
PIO Output Write Enable Register
PIO_OWER
Addresses: 0xFFFFF2A0 (PIOA), 0xFFFFF4A0 (PIOB), 0xFFFFF6A0 (PIOC), 0xFFFFF8A0 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Output Write Enable.
0 = No effect.
1 = Enables writing PIO_ODSR for the I/O line.
33.6.28
Name:
PIO Output Write Disable Register
PIO_OWDR
Addresses: 0xFFFFF2A4 (PIOA), 0xFFFFF4A4 (PIOB), 0xFFFFF6A4 (PIOC), 0xFFFFF8A4 (PIOD)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Output Write Disable.
0 = No effect.
1 = Disables writing PIO_ODSR for the I/O line.
501
6264C–CAP–24-Mar-09
33.6.29
Name:
PIO Output Write Status Register
PIO_OWSR
Addresses:
0xFFFFF2A8 (PIOA), 0xFFFFF4A8 (PIOB), 0xFFFFF6A8 (PIOC), 0xFFFFF8A8 (PIOD)
Access Type:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Output Write Status.
0 = Writing PIO_ODSR does not affect the I/O line.
1 = Writing PIO_ODSR affects the I/O line.
502
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
34. Serial Peripheral Interface (SPI)
34.1
Description
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication
between processors if an external processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to
other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data
flow, while the other devices act as “slaves'' which have data shifted into and out by the master.
Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master
Protocol where one CPU is always the master while all of the others are always slaves) and one
master may simultaneously shift data into multiple slaves. However, only one slave may drive its
output to write data back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices
exist, the master generates a separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted
into the input(s) of the slave(s).
• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input
of the master. There may be no more than one slave transmitting data during any particular
transfer.
• Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the
data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once
for each bit that is transmitted.
• Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.
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6264C–CAP–24-Mar-09
34.2
Block Diagram
Figure 34-1. Block Diagram
PDC
APB
SPCK
MISO
PMC
MOSI
MCK
SPI Interface
PIO
NPCS0/NSS
NPCS1
NPCS2
Interrupt Control
NPCS3
SPI Interrupt
34.3
Application Block Diagram
Figure 34-2. Application Block Diagram: Single Master/Multiple Slave Implementation
SPI Master
SPCK
SPCK
MISO
MISO
MOSI
MOSI
NPCS0
NSS
Slave 0
SPCK
NPCS1
NPCS2
NC
NPCS3
MISO
Slave 1
MOSI
NSS
SPCK
MISO
Slave 2
MOSI
NSS
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AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
34.4
Signal Description
Table 34-1.
Signal Description
Type
Pin Name
Pin Description
Master
Slave
MISO
Master In Slave Out
Input
Output
MOSI
Master Out Slave In
Output
Input
SPCK
Serial Clock
Output
Input
NPCS1-NPCS3
Peripheral Chip Selects
Output
Unused
NPCS0/NSS
Peripheral Chip Select/Slave Select
Output
Input
34.5
34.5.1
Product Dependencies
I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
The programmer must first program the PIO controllers to assign the SPI pins to their peripheral
functions.
Table 34-2.
I/O Lines
Instance
Signal
I/O Line
Peripheral
SPI0
SPI0_MISO
PA0
B
SPI0
SPI0_MOSI
PA1
B
SPI0
SPI0_NPCS0
PA5
B
SPI0
SPI0_NPCS1
PA3
B
SPI0
SPI0_NPCS2
PA4
B
SPI0
SPI0_NPCS2
PD0
B
SPI0
SPI0_NPCS3
PA28
A
SPI0
SPI0_NPCS3
PD1
B
SPI0
SPI0_SPCK
PA2
B
SPI1
SPI1_MISO
PB12
A
SPI1
SPI1_MOSI
PB13
A
SPI1
SPI1_NPCS0
PB15
A
SPI1
SPI1_NPCS1
PB16
A
SPI1
SPI1_NPCS2
PB17
A
SPI1
SPI1_NPCS2
PD2
B
SPI1
SPI1_NPCS3
PB18
A
SPI1
SPI1_NPCS3
PD3
B
SPI1
SPI1_SPCK
PB14
A
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6264C–CAP–24-Mar-09
34.5.2
Power Management
The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock.
34.5.3
Interrupt
The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling the SPI interrupt requires programming the AIC before configuring the SPI.
Table 34-3.
506
Peripheral IDs
Instance
ID
SPI0
15
SPI1
16
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
34.6
34.6.1
Functional Description
Modes of Operation
The SPI operates in Master Mode or in Slave Mode.
Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register.
The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line
is wired on the receiver input and the MOSI line driven as an output by the transmitter.
If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the
transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the
transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a
Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other
purposes.
The data transfers are identically programmable for both modes of operations. The baud rate
generator is activated only in Master Mode.
34.6.2
Data Transfer
Four combinations of polarity and phase are available for data transfers. The clock polarity is
programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with
the NCPHA bit. These two parameters determine the edges of the clock signal on which data is
driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the
same parameter pair values to communicate. If multiple slaves are used and fixed in different
configurations, the master must reconfigure itself each time it needs to communicate with a different slave.
Table 34-4 shows the four modes and corresponding parameter settings.
Table 34-4.
SPI Bus Protocol Mode
SPI Mode
CPOL
NCPHA
0
0
1
1
0
0
2
1
1
3
1
0
Figure 34-3 and Figure 34-4 show examples of data transfers.
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6264C–CAP–24-Mar-09
Figure 34-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
1
SPCK cycle (for reference)
2
3
4
6
5
7
8
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
MOSI
(from master)
MSB
MISO
(from slave)
MSB
6
5
4
3
2
1
LSB
6
5
4
3
2
1
LSB
*
NSS
(to slave)
* Not defined, but normally MSB of previous character received.
Figure 34-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
1
SPCK cycle (for reference)
2
3
4
5
7
6
8
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
MOSI
(from master)
MISO
(from slave)
*
MSB
6
5
4
3
2
1
MSB
6
5
4
3
2
1
LSB
LSB
NSS
(to slave)
* Not defined but normally LSB of previous character transmitted.
508
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
34.6.3
Master Mode Operations
When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s)
connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock
signal (SPCK).
The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register. The holding registers maintain the data flow at a constant rate.
After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The written data is immediately transferred in the Shift Register and transfer
on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO
line is sampled and shifted in the Shift Register. Transmission cannot occur without reception.
Before writing the TDR, the PCS field must be set in order to select a slave.
If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is
completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data
in SPI_TDR is loaded in the Shift Register and a new transfer starts.
The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit
(Transmit Data Register Empty) in the Status Register (SPI_SR). When new data is written in
SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit PDC channel.
The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay
(DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said
delay. The master clock (MCK) can be switched off at this time.
The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit
(Receive Data Register Full) in the Status Register (SPI_SR). When the received data is read,
the RDRF bit is cleared.
If the SPI_RDR (Receive Data Register) has not been read before new data is received, the
Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in
SPI_RDR. The user has to read the status register to clear the OVRES bit.
Figure 34-5, shows a block diagram of the SPI when operating in Master Mode. Figure 34-6 on
page 511 shows a flow chart describing how transfers are handled.
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6264C–CAP–24-Mar-09
34.6.3.1
Master Mode Block Diagram
Figure 34-5. Master Mode Block Diagram
SPI_CSR0..3
SCBR
Baud Rate Generator
MCK
SPCK
SPI
Clock
SPI_CSR0..3
BITS
NCPHA
CPOL
LSB
MISO
SPI_RDR
RDRF
OVRES
RD
MSB
Shift Register
MOSI
SPI_TDR
TD
TDRE
SPI_CSR0..3
SPI_RDR
CSAAT
PCS
PS
NPCS3
PCSDEC
SPI_MR
PCS
0
NPCS2
Current
Peripheral
NPCS1
SPI_TDR
NPCS0
PCS
1
MSTR
MODF
NPCS0
MODFDIS
510
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
34.6.3.2
Master Mode Flow Diagram
Figure 34-6. Master Mode Flow Diagram
SPI Enable
- NPCS defines the current Chip Select
- CSAAT, DLYBS, DLYBCT refer to the fields of the
Chip Select Register corresponding to the Current Chip Select
- When NPCS is 0xF, CSAAT is 0.
1
TDRE ?
0
1
CSAAT ?
PS ?
0
1
0
Fixed
peripheral
PS ?
1
Fixed
peripheral
0
Variable
peripheral
Variable
peripheral
SPI_TDR(PCS)
= NPCS ?
no
NPCS = SPI_TDR(PCS)
NPCS = SPI_MR(PCS)
yes
SPI_MR(PCS)
= NPCS ?
no
NPCS = 0xF
NPCS = 0xF
Delay DLYBCS
Delay DLYBCS
NPCS = SPI_TDR(PCS)
NPCS = SPI_MR(PCS),
SPI_TDR(PCS)
Delay DLYBS
Serializer = SPI_TDR(TD)
TDRE = 1
Data Transfer
SPI_RDR(RD) = Serializer
RDRF = 1
Delay DLYBCT
0
TDRE ?
1
1
CSAAT ?
0
NPCS = 0xF
Delay DLYBCS
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6264C–CAP–24-Mar-09
34.6.3.3
Clock Generation
The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1
and 255.
This allows a maximum operating baud rate at up to Master Clock and a minimum operating
baud rate of MCK divided by 255.
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead
to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first
transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in the
SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud
rate for each interfaced peripheral without reprogramming.
34.6.3.4
Transfer Delays
Figure 34-7 shows a chip select transfer change and consecutive transfers on the same chip
select. Three delays can be programmed to modify the transfer waveforms:
• The delay between chip selects, programmable only once for all the chip selects by writing
the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one
chip select and before assertion of a new one.
• The delay before SPCK, independently programmable for each chip select by writing the field
DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted.
• The delay between consecutive transfers, independently programmable for each chip select
by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on
the same chip select
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus
release time.
Figure 34-7. Programmable Delays
Chip Select 1
Chip Select 2
SPCK
DLYBCS
34.6.3.5
DLYBS
DLYBCT
DLYBCT
Peripheral Selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By
default, all the NPCS signals are high before and after each transfer.
The peripheral selection can be performed in two different ways:
• Fixed Peripheral Select: SPI exchanges data with only one peripheral
512
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• Variable Peripheral Select: Data can be exchanged with more than one peripheral
Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In
this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the
SPI_TDR has no effect.
Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is
used to select the current peripheral. This means that the peripheral selection can be defined for
each new data.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is
an optimal means, as the size of the data transfer between the memory and the SPI is either 8
bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be
reprogrammed.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data
to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit
wide buffers, with the data in the Lisps and the PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI
lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several
peripherals without any intervention of the processor.
34.6.3.6
Peripheral Chip Select Decoding
The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip
Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing the PCSDEC bit at 1 in the Mode Register (SPI_MR).
When operating without decoding, the SPI makes sure that in any case only one chip select line
is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest
numbered chip select is driven low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field of
either the Mode Register or the Transmit Data Register (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when
not processing any transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated,
each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0
defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the
PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on
the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
34.6.3.7
Peripheral Deselection
When operating normally, as soon as the transfer of the last data written in SPI_TDR is completed, the NPCS lines all rise. This might lead to runtime error if the processor is too long in
responding to an interrupt, and thus might lead to difficulties for interfacing with some serial
peripherals requiring the chip select line to remain active during a full set of transfers.
To facilitate interfacing with such devices, the Chip Select Register can be programmed with the
CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in
their current state (low = active) until transfer to another peripheral is required.
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6264C–CAP–24-Mar-09
Figure 34-8 shows different peripheral deselection cases and the effect of the CSAAT bit.
Figure 34-8. Peripheral Deselection
CSAAT = 0
TDRE
NPCS[0..3]
CSAAT = 1
DLYBCT
DLYBCT
A
A
A
A
DLYBCS
A
DLYBCS
PCS = A
PCS = A
Write SPI_TDR
TDRE
NPCS[0..3]
DLYBCT
DLYBCT
A
A
A
A
DLYBCS
A
DLYBCS
PCS=A
PCS = A
Write SPI_TDR
TDRE
NPCS[0..3]
DLYBCT
DLYBCT
A
B
A
B
DLYBCS
PCS = B
DLYBCS
PCS = B
Write SPI_TDR
34.6.3.8
Mode Fault Detection
A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven
by an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be configured in open drain through the PIO controller, so that external pull up resistors are needed to
guarantee high level.
When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and
the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Control Register) at 1.
By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault
detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR).
34.6.4
514
SPI Slave Mode
When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI
clock pin (SPCK).
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
The SPI waits for NSS to go active before receiving the serial clock from an external master.
When NSS falls, the clock is validated on the serializer, which processes the number of bits
defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed
following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the
SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no
effect when the SPI is programmed in Slave Mode.
The bits are shifted out on the MISO line and sampled on the MOSI line.
(For more information on BITS field, see also, the
“SPI Chip Select Register” on page 527.)
(Note:)
below the register table; Section 34.7.9
When all the bits are processed, the received data is transferred in the Receive Data Register
and the RDRF bit rises. If the SPI_RDR (Receive Data Register) has not been read before new
data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data
is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit.
When a transfer starts, the data shifted out is the data present in the Shift Register. If no data
has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred.
If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets at 0.
When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the
TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls
and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in
SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent
updates of critical variables with single transfers.
Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no
character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last
load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received
character is retransmitted.
Figure 34-9 shows a block diagram of the SPI when operating in Slave Mode.
Figure 34-9. Slave Mode Functional Bloc Diagram
SPCK
NSS
SPI
Clock
SPIEN
SPIENS
SPIDIS
SPI_CSR0
BITS
NCPHA
CPOL
MOSI
LSB
SPI_RDR
RDRF
OVRES
RD
MSB
Shift Register
MISO
SPI_TDR
TD
TDRE
515
6264C–CAP–24-Mar-09
34.7
Serial Peripheral Interface (SPI) User Interface
Table 34-5.
Register Mapping
Offset
Name
Access
Reset
0x00
Control Register
SPI_CR
Write-only
---
0x04
Mode Register
SPI_MR
Read-write
0x0
0x08
Receive Data Register
SPI_RDR
Read-only
0x0
0x0C
Transmit Data Register
SPI_TDR
Write-only
---
0x10
Status Register
SPI_SR
Read-only
0x000000F0
0x14
Interrupt Enable Register
SPI_IER
Write-only
---
0x18
Interrupt Disable Register
SPI_IDR
Write-only
---
0x1C
Interrupt Mask Register
SPI_IMR
Read-only
0x0
0x20 - 0x2C
Reserved
0x30
Chip Select Register 0
SPI_CSR0
Read-write
0x0
0x34
Chip Select Register 1
SPI_CSR1
Read-write
0x0
0x38
Chip Select Register 2
SPI_CSR2
Read-write
0x0
0x3C
Chip Select Register 3
SPI_CSR3
Read-write
0x0
–
–
–
0x004C - 0x00F8
0x100 - 0x124
516
Register
Reserved
Reserved for the PDC
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
34.7.1
Name:
SPI Control Register
SPI_CR
Addresses: 0xFFFA4000 (0), 0xFFFA8000 (1)
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
LASTXFER
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
SWRST
–
–
–
–
–
SPIDIS
SPIEN
• SPIEN: SPI Enable
0 = No effect.
1 = Enables the SPI to transfer and receive data.
• SPIDIS: SPI Disable
0 = No effect.
1 = Disables the SPI.
As soon as SPIDIS is set, SPI finishes its transfer.
All pins are set in input mode and no data is received or transmitted.
If a transfer is in progress, the transfer is finished before the SPI is disabled.
If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.
• SWRST: SPI Software Reset
0 = No effect.
1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed.
The SPI is in slave mode after software reset.
PDC channels are not affected by software reset.
• LASTXFER: Last Transfer
0 = No effect.
1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this
allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD
transfer has completed.
517
6264C–CAP–24-Mar-09
34.7.2
Name:
SPI Mode Register
SPI_MR
Addresses: 0xFFFA4004 (0), 0xFFFA8004 (1)
Access:
31
Read/Write
30
29
28
27
26
19
18
25
24
17
16
DLYBCS
23
22
21
20
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
PCS
7
6
5
4
3
2
1
0
LLB
–
–
MODFDIS
–
PCSDEC
PS
MSTR
• MSTR: Master/Slave Mode
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
• PS: Peripheral Select
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
• PCSDEC: Chip Select Decode
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules:
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 14.
• MODFDIS: Mode Fault Detection
0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.
• LLB: Local Loopback Enable
0 = Local loopback path disabled.
1 = Local loopback path enabled
LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on
MOSI.)
518
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• PCS: Peripheral Chip Select
This field is only used if Fixed Peripheral Select is active (PS = 0).
If PCSDEC = 0:
PCS = xxx0NPCS[3:0] = 1110
PCS = xx01NPCS[3:0] = 1101
PCS = x011NPCS[3:0] = 1011
PCS = 0111NPCS[3:0] = 0111
PCS = 1111forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS.
• DLYBCS: Delay Between Chip Selects
This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times.
If DLYBCS is less than or equal to six, six MCK periods will be inserted by default.
Otherwise, the following equation determines the delay:
DLYBCS
Delay Between Chip Selects = ----------------------MCK
519
6264C–CAP–24-Mar-09
34.7.3
Name:
SPI Receive Data Register
SPI_RDR
Addresses: 0xFFFA4008 (0), 0xFFFA8008 (1)
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
15
14
13
12
PCS
11
10
9
8
3
2
1
0
RD
7
6
5
4
RD
• RD: Receive Data
Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
• PCS: Peripheral Chip Select
In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read
zero.
520
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
34.7.4
Name:
SPI Transmit Data Register
SPI_TDR
Addresses: 0xFFFA400C (0), 0xFFFA800C (1)
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
LASTXFER
23
22
21
20
19
18
17
16
–
–
–
–
15
14
13
12
PCS
11
10
9
8
3
2
1
0
TD
7
6
5
4
TD
• TD: Transmit Data
Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the
transmit data register in a right-justified format.
• PCS: Peripheral Chip Select
This field is only used if Variable Peripheral Select is active (PS = 1).
If PCSDEC = 0:
PCS = xxx0NPCS[3:0] = 1110
PCS = xx01NPCS[3:0] = 1101
PCS = x011NPCS[3:0] = 1011
PCS = 0111NPCS[3:0] = 0111
PCS = 1111forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS
• LASTXFER: Last Transfer
0 = No effect.
1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this
allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD
transfer has completed.
This field is only used if Variable Peripheral Select is active (PS = 1).
521
6264C–CAP–24-Mar-09
34.7.5
Name:
SPI Status Register
SPI_SR
Addresses: 0xFFFA4010 (0), 0xFFFA8010 (1)
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
SPIENS
15
14
13
12
11
10
9
8
–
–
–
–
–
–
TXEMPTY
NSSR
7
6
5
4
3
2
1
0
TXBUFE
RXBUFF
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
• RDRF: Receive Data Register Full
0 = No data has been received since the last read of SPI_RDR
1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read
of SPI_RDR.
• TDRE: Transmit Data Register Empty
0 = Data has been written to SPI_TDR and not yet transferred to the serializer.
1 = The last data written in the Transmit Data Register has been transferred to the serializer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
• MODF: Mode Fault Error
0 = No Mode Fault has been detected since the last read of SPI_SR.
1 = A Mode Fault occurred since the last read of the SPI_SR.
• OVRES: Overrun Error Status
0 = No overrun has been detected since the last read of SPI_SR.
1 = An overrun has occurred since the last read of SPI_SR.
An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.
• ENDRX: End of RX buffer
0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1).
1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1).
• ENDTX: End of TX buffer
0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1).
1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1).
• RXBUFF: RX Buffer Full
0 = SPI_RCR(1) or SPI_RNCR(1) has a value other than 0.
1 = Both SPI_RCR(1) and SPI_RNCR(1) have a value of 0.
522
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• TXBUFE: TX Buffer Empty
0 = SPI_TCR(1) or SPI_TNCR(1) has a value other than 0.
1 = Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0.
• NSSR: NSS Rising
0 = No rising edge detected on NSS pin since last read.
1 = A rising edge occurred on NSS pin since last read.
• TXEMPTY: Transmission Registers Empty
0 = As soon as data is written in SPI_TDR.
1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of
such delay.
• SPIENS: SPI Enable Status
0 = SPI is disabled.
1 = SPI is enabled.
Note:
1. SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR are physically located in the PDC.
523
6264C–CAP–24-Mar-09
34.7.6
Name:
SPI Interrupt Enable Register
SPI_IER
Addresses: 0xFFFA4014 (0), 0xFFFA8014 (1)
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
TXEMPTY
NSSR
7
6
5
4
3
2
1
0
TXBUFE
RXBUFF
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
0 = No effect.
1 = Enables the corresponding interrupt.
• RDRF: Receive Data Register Full Interrupt Enable
• TDRE: SPI Transmit Data Register Empty Interrupt Enable
• MODF: Mode Fault Error Interrupt Enable
• OVRES: Overrun Error Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
• NSSR: NSS Rising Interrupt Enable
• TXEMPTY: Transmission Registers Empty Enable
524
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
34.7.7
Name:
SPI Interrupt Disable Register
SPI_IDR
Addresses: 0xFFFA4018 (0), 0xFFFA8018 (1)
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
TXEMPTY
NSSR
7
6
5
4
3
2
1
0
TXBUFE
RXBUFF
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
0 = No effect.
1 = Disables the corresponding interrupt.
• RDRF: Receive Data Register Full Interrupt Disable
• TDRE: SPI Transmit Data Register Empty Interrupt Disable
• MODF: Mode Fault Error Interrupt Disable
• OVRES: Overrun Error Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
• NSSR: NSS Rising Interrupt Disable
• TXEMPTY: Transmission Registers Empty Disable
525
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
34.7.8
Name:
SPI Interrupt Mask Register
SPI_IMR
Addresses: 0xFFFA401C (0), 0xFFFA801C (1)
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
TXEMPTY
NSSR
7
6
5
4
3
2
1
0
TXBUFE
RXBUFF
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.
• RDRF: Receive Data Register Full Interrupt Mask
• TDRE: SPI Transmit Data Register Empty Interrupt Mask
• MODF: Mode Fault Error Interrupt Mask
• OVRES: Overrun Error Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
• NSSR: NSS Rising Interrupt Mask
• TXEMPTY: Transmission Registers Empty Mask
526
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
34.7.9
Name:
SPI Chip Select Register
SPI_CSR0... SPI_CSR3
Addresses: 0xFFFA4030 (0), 0xFFFA8030 (1)
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
DLYBCT
23
22
21
20
DLYBS
15
14
13
12
SCBR
7
6
5
4
BITS
Note:
3
2
1
0
CSAAT
–
NCPHA
CPOL
SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the translated value unless the register is written.
• CPOL: Clock Polarity
0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the
required clock/data relationship between master and slave devices.
• NCPHA: Clock Phase
0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is
used with CPOL to produce the required clock/data relationship between master and slave devices.
• CSAAT: Chip Select Active After Transfer
0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is
requested on a different chip select.
• BITS: Bits Per Transfer (See the (Note:) below the register table; Section 34.7.9 “SPI Chip Select Register” on page 527.)
The BITS field determines the number of data bits transferred. Reserved values should not be used.
BITS
0000
0001
0010
0011
0100
0101
0110
0111
Bits Per Transfer
8
9
10
11
12
13
14
15
527
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
BITS
1000
1001
1010
1011
1100
1101
1110
1111
Bits Per Transfer
16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The
Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud
rate:
MCKSPCK Baudrate = -------------SCBR
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
Delay Before SPCK = DLYBS
------------------MCK
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
32 × DLYBCT
Delay Between Consecutive Transfers = ------------------------------------MCK
528
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
35. Two-wire Interface (TWI)
35.1
Description
The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made
up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a
byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial
EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD
Controllers and Temperature Sensor, to name but a few. The TWI is programmable as a master
or a slave with sequential or single-byte access. Multiple master capability is supported. 20
Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the
bus arbitration is lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range of
core clock frequencies.
Below, Table 35-1 lists the compatibility level of the Atmel Two-wire Interface in Master Mode and
a full I2C compatible device.
Table 35-1.
Atmel TWI compatibility with i2C Standard
I2C Standard
Atmel TWI
Standard Mode Speed (100 KHz)
Supported
Fast Mode Speed (400 KHz)
Supported
7 or 10 bits Slave Addressing
Supported
(1)
START BYTE
Not Supported
Repeated Start (Sr) Condition
Supported
ACK and NACK Management
Supported
Slope control and input filtering (Fast mode)
Not Supported
Clock stretching
Supported
Multi Master Capability
Supported
Note:
35.2
1. START + b000000001 + Ack + Sr
List of Abbreviations
Table 35-2.
Abbreviations
Abbreviation
Description
TWI
Two-wire Interface
A
Acknowledge
NA
Non Acknowledge
P
Stop
S
Start
Sr
Repeated Start
SADR
Slave Address
529
6264C–CAP–24-Mar-09
Table 35-2.
35.3
Abbreviations
Abbreviation
Description
ADR
Any address except SADR
R
Read
W
Write
Block Diagram
Figure 35-1. Block Diagram
APB Bridge
TWCK
PIO
PMC
MCK
TWD
Two-wire
Interface
TWI
Interrupt
35.4
AIC
Application Block Diagram
Figure 35-2. Application Block Diagram
VDD
Rp
Host with
TWI
Interface
Rp
TWD
TWCK
Atmel TWI
Serial EEPROM
Slave 1
I²C RTC
I²C LCD
Controller
I²C Temp.
Sensor
Slave 2
Slave 3
Slave 4
Rp: Pull up value as given by the I²C Standard
530
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.5
I/O Lines Description
I/O Lines Description
Pin Name
Pin Description
TWD
Two-wire Serial Data
Input/Output
TWCK
Two-wire Serial Clock
Input/Output
35.6
35.6.1
Type
Product Dependencies
I/O Lines
Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current
source or pull-up resistor (see Figure 35-2 on page 530). When the bus is free, both lines are
high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function.
TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer
must perform the following step:
• Program the PIO controller to dedicate TWD and TWCK as peripheral lines.
The user must not program TWD and TWCK as open-drain. It is already done by the hardware.
Table 35-3.
35.6.2
I/O Lines
Instance
Signal
I/O Line
Peripheral
TWI
TWCK
PB5
B
TWI
TWD
PB4
B
Power Management
• Enable the peripheral clock.
The TWI interface may be clocked through the Power Management Controller (PMC), thus the
programmer must first configure the PMC to enable the TWI clock.
35.6.3
Interrupt
The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In
order to handle interrupts, the AIC must be programmed before configuring the TWI.
Table 35-4.
531
Peripheral IDs
Instance
ID
TWI
14
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.7
35.7.1
Functional Description
Transfer Format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must
be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure
35-4).
Each transfer begins with a START condition and terminates with a STOP condition (see Figure
35-3).
• A high-to-low transition on the TWD line while TWCK is high defines the START condition.
• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 35-3.
START and STOP Conditions
TWD
TWCK
Start
Stop
Figure 35-4. Transfer Format
TWD
TWCK
Start
35.7.2
Address
R/W
Ack
Data
Ack
Data
Ack
Stop
Modes of Operation
The TWI has six modes of operations:
• Master transmitter mode
• Master receiver mode
• Multi-master transmitter mode
• Multi-master receiver mode
• Slave transmitter mode
• Slave receiver mode
These modes are described in the following chapters.
532
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.8
Master Mode
35.8.1
Definition
The Master is the device that starts a transfer, generates a clock and stops it.
35.8.2
Application Block Diagram
Figure 35-5. Master Mode Typical Application Block Diagram
VDD
Rp
Host with
TWI
Interface
Rp
TWD
TWCK
Atmel TWI
Serial EEPROM
Slave 1
I²C RTC
I²C LCD
Controller
I²C Temp.
Sensor
Slave 2
Slave 3
Slave 4
Rp: Pull up value as given by the I²C Standard
35.8.3
Programming Master Mode
The following registers have to be programmed before entering Master mode:
1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used
to access slave devices in read or write mode.
2. CKDIV + CHDIV + CLDIV: Clock Waveform.
3. SVDIS: Disable the slave mode.
4. MSEN: Enable the master mode.
35.8.4
Master Transmitter Mode
After the master initiates a Start condition when writing into the Transmit Holding Register,
TWI_THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in
TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer
direction, 0 in this case (MREAD = 0 in TWI_MMR).
The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the Not Acknowledge bit (NACK) in the status register if the slave does not
acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in
the interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data written in
the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is
detected, the TXRDY bit is set until a new write in the TWI_THR.
533
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
While no new data is written in the TWI_THR, the Serial Clock Line is tied low. When new data is
written in the TWI_THR, the SCL is released and the data is sent. To generate a STOP event,
the STOP command must be performed by writing in the STOP field of TWI_CR.
After a Master Write transfer, the Serial Clock line is stretched (tied low) while no new data is
written in the TWI_THR or until a STOP command is performed.
See Figure 35-6, Figure 35-7, and Figure 35-8.
Figure 35-6. Master Write with One Data Byte
STOP Command sent (write in TWI_CR)
S
TWD
DADR
W
A
DATA
A
P
TXCOMP
TXRDY
Write THR (DATA)
Figure 35-7. Master Write with Multiple Data Bytes
STOP command performed
(by writing in the TWI_CR)
TWD
S
DADR
W
A
DATA n
A
DATA n+1
A
DATA n+2
A
P
TWCK
TXCOMP
TXRDY
Write THR (Data n)
Write THR (Data n+1)
534
Write THR (Data n+2)
Last data sent
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 35-8. Master Write with One Byte Internal Address and Multiple Data Bytes
STOP command performed
(by writing in the TWI_CR)
TWD
S
DADR
W
A
IADR
A
DATA n
A
DATA n+1
A
DATA n+2
A
P
TWCK
TXCOMP
TXRDY
Write THR (Data n)
Write THR (Data n+1)
Write THR (Data n+2)
Last data sent
TXRDY is used as Transmit Ready for the PDC transmit channel.
35.8.5
Master Receiver Mode
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data
has been received, the master sends an acknowledge condition to notify the slave that the data
has been received except for the last data, after the stop condition. See Figure 35-9. When the
RXRDY bit is set in the status register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See Figure 35-9. When a multiple data byte read is
performed, with or without internal address (IADR), the STOP bit must be set after the next-tolast data received. See Figure 35-10. For Internal Address usage see Section 35.8.6.
Figure 35-9. Master Read with One Data Byte
TWD
S
DADR
R
A
DATA
N
P
TXCOMP
Write START &
STOP Bit
RXRDY
Read RHR
535
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 35-10. Master Read with Multiple Data Bytes
TWD
S
DADR
R
A
DATA n
A
DATA (n+1)
A
DATA (n+m)-1
A
DATA (n+m)
N
P
TXCOMP
Write START Bit
RXRDY
Read RHR
DATA n
Read RHR
DATA (n+1)
Read RHR
DATA (n+m)-1
Read RHR
DATA (n+m)
Write STOP Bit
after next-to-last data read
RXRDY is used as Receive Ready for the PDC receive channel.
35.8.6
35.8.6.1
Internal Address
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address
devices and 10-bit slave address devices.
7-bit Slave Addressing
When Addressing 7-bit slave devices, the internal address bytes are used to perform random
address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example. When performing read operations with an internal address,
the TWI performs a write operation to set the internal address into the slave device, and then
switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is
sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See Figure 35-12. See
Figure 35-11 and Figure 35-13 for Master Write operation with internal address.
The three internal address bytes are configurable through the Master Mode register
(TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to
0.
In the figures below the following abbreviations are used:
536
•S
Start
• Sr
Repeated Start
•P
Stop
•W
Write
•R
Read
•A
Acknowledge
•N
Not Acknowledge
• DADR
Device Address
• IADR
Internal Address
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 35-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Three bytes internal address
S
TWD
DADR
W
A
IADR(23:16)
A
IADR(15:8)
A
IADR(7:0)
A
W
A
IADR(15:8)
A
IADR(7:0)
A
DATA
A
W
A
IADR(7:0)
A
DATA
A
DATA
A
P
Two bytes internal address
S
TWD
DADR
P
One byte internal address
S
TWD
DADR
P
Figure 35-12. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
Three bytes internal address
S
TWD
DADR
W
A
IADR(23:16)
A
A
IADR(15:8)
IADR(7:0)
A
Sr
DADR
R
A
DATA
N
P
Two bytes internal address
S
TWD
DADR
W
A
IADR(15:8)
A
IADR(7:0)
A
Sr
W
A
IADR(7:0)
A
Sr
R
A
DADR
R
A
DATA
N
P
One byte internal address
TWD
35.8.6.2
S
DADR
DADR
DATA
N
P
10-bit Slave Addressing
For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and
set the other slave address bits in the internal address register (TWI_IADR). The two remaining
Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave
Addressing.
Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)
1. Program IADRSZ = 1,
2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)
3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit
address)
Figure 35-13 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates
the use of internal addresses to access the device.
Figure 35-13. Internal Address Usage
S
T
A
R
T
Device
Address
W
R
I
T
E
FIRST
WORD ADDRESS
SECOND
WORD ADDRESS
S
T
O
P
DATA
0
M
S
B
537
LR A
S / C
BW K
M
S
B
A
C
K
LA
SC
BK
A
C
K
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.8.7
Using the Peripheral DMA Controller (PDC)
The use of the PDC significantly reduces the CPU load.
To assure correct implementation, respect the following programming sequences:
35.8.7.1
Data Transmit with the PDC
1. Initialize the transmit PDC (memory pointers, size, etc.).
2. Configure the master mode (DADR, CKDIV, etc.).
3. Start the transfer by setting the PDC TXTEN bit.
4. Wait for the PDC end TX flag.
5. Disable the PDC by setting the PDC TXDIS bit.
35.8.7.2
Data Receive with the PDC
1. Initialize the receive PDC (memory pointers, size - 1, etc.).
2. Configure the master mode (DADR, CKDIV, etc.).
3. Start the transfer by setting the PDC RXTEN bit.
4. Wait for the PDC end RX flag.
5. Disable the PDC by setting the PDC RXDIS bit.
35.8.8
SMBUS Quick Command (Master Mode Only)
The TWI interface can perform a Quick Command:
1. Configure the master mode (DADR, CKDIV, etc.).
2. Write the MREAD bit in the TWI_MMR register at the value of the one-bit command to
be sent.
3. Start the transfer by setting the QUICK bit in the TWI_CR.
Figure 35-14. SMBUS Quick Command
TWD
S
DADR
R/W
A
P
TXCOMP
TXRDY
Write QUICK command in TWI_CR
35.8.9
538
Read-write Flowcharts
The following flowcharts shown in Figure 35-16 on page 540, Figure 35-17 on page 541, Figure
35-18 on page 542, Figure 35-19 on page 543 and Figure 35-20 on page 544 give examples for
read and write operations. A polling or interrupt method can be used to check the status bits.
The interrupt method requires that the interrupt enable register (TWI_IER) be configured first.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 35-15. TWI Write Operation with Single Data Byte without Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address (DADR)
- Transfer direction bit
Write ==> bit MREAD = 0
Load Transmit register
TWI_THR = Data to send
Write STOP Command
TWI_CR = STOP
Read Status register
No
TXRDY = 1?
Yes
Read Status register
No
TXCOMP = 1?
Yes
Transfer finished
539
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 35-16. TWI Write Operation with Single Data Byte and Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address (DADR)
- Internal address size (IADRSZ)
- Transfer direction bit
Write ==> bit MREAD = 0
Set the internal address
TWI_IADR = address
Load transmit register
TWI_THR = Data to send
Write STOP command
TWI_CR = STOP
Read Status register
No
TXRDY = 1?
Yes
Read Status register
TXCOMP = 1?
No
Yes
Transfer finished
540
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 35-17. TWI Write Operation with Multiple Data Bytes with or without Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Write ==> bit MREAD = 0
No
Internal address size = 0?
Set the internal address
TWI_IADR = address
Yes
Load Transmit register
TWI_THR = Data to send
Read Status register
TWI_THR = data to send
No
TXRDY = 1?
Yes
Data to send?
Yes
Write STOP Command
TWI_CR = STOP
Read Status register
Yes
No
TXCOMP = 1?
END
541
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 35-18. TWI Read Operation with Single Data Byte without Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Transfer direction bit
Read ==> bit MREAD = 1
Start the transfer
TWI_CR = START | STOP
Read status register
RXRDY = 1?
No
Yes
Read Receive Holding Register
Read Status register
No
TXCOMP = 1?
Yes
END
542
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 35-19. TWI Read Operation with Single Data Byte and Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (IADRSZ)
- Transfer direction bit
Read ==> bit MREAD = 1
Set the internal address
TWI_IADR = address
Start the transfer
TWI_CR = START | STOP
Read Status register
No
RXRDY = 1?
Yes
Read Receive Holding register
Read Status register
No
TXCOMP = 1?
Yes
END
543
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 35-20. TWI Read Operation with Multiple Data Bytes with or without Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Read ==> bit MREAD = 1
Internal address size = 0?
Set the internal address
TWI_IADR = address
Yes
Start the transfer
TWI_CR = START
Read Status register
RXRDY = 1?
No
Yes
Read Receive Holding register (TWI_RHR)
No
Last data to read
but one?
Yes
Stop the transfer
TWI_CR = STOP
Read Status register
No
RXRDY = 1?
Yes
Read Receive Holding register (TWI_RHR)
Read status register
TXCOMP = 1?
No
Yes
END
544
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.9
Multi-master Mode
35.9.1
Definition
More than one master may handle the bus at the same time without data corruption by using
arbitration.
Arbitration starts as soon as two or more masters place information on the bus at the same time,
and stops (arbitration is lost) for the master that intends to send a logical one while the other
master sends a logical zero.
As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to
detect a stop. When the stop is detected, the master who has lost arbitration may put its data on
the bus by respecting arbitration.
Arbitration is illustrated in Figure 35-22 on page 546.
35.9.2
Different Multi-master Modes
Two multi-master modes may be distinguished:
1. TWI is considered as a Master only and will never be addressed.
2. TWI may be either a Master or a Slave and may be addressed.
Note:
35.9.2.1
In both Multi-master modes arbitration is supported.
TWI as Master Only
In this mode, TWI is considered as a Master only (MSEN is always at one) and must be driven
like a Master with the ARBLST (ARBitration Lost) flag in addition.
If arbitration is lost (ARBLST = 1), the programmer must reinitiate the data transfer.
If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the
TWI automatically waits for a STOP condition on the bus to initiate the transfer (see Figure 3521 on page 546).
Note:
35.9.2.2
The state of the bus (busy or free) is not indicated in the user interface.
TWI as Master or Slave
The automatic reversal from Master to Slave is not supported in case of a lost arbitration.
Then, in the case where TWI may be either a Master or a Slave, the programmer must manage
the pseudo Multi-master mode described in the steps below.
1. Program TWI in Slave mode (SADR + MSDIS + SVEN) and perform Slave Access (if
TWI is addressed).
2. If TWI has to be set in Master mode, wait until TXCOMP flag is at 1.
3. Program Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START +
Write in THR).
4. As soon as the Master mode is enabled, TWI scans the bus in order to detect if it is
busy or free. When the bus is considered as free, TWI initiates the transfer.
5. As soon as the transfer is initiated and until a STOP condition is sent, the arbitration
becomes relevant and the user must monitor the ARBLST flag.
6. If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave
mode in the case where the Master that won the arbitration wanted to access the TWI.
7. If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the
Slave mode.
545
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Note:
In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it
is programmed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat
SADR.
Figure 35-21. Programmer Sends Data While the Bus is Busy
TWCK
START sent by the TWI
STOP sent by the master
DATA sent by a master
TWD
DATA sent by the TWI
Bus is busy
Bus is free
Transfer is kept
TWI DATA transfer
A transfer is programmed
(DADR + W + START + Write THR)
Bus is considered as free
Transfer is initiated
Figure 35-22. Arbitration Cases
TWCK
TWD
TWCK
Data from a Master
S
1
0 0 1 1
Data from TWI
S
1
0
TWD
S
1
0 0
1
P
Arbitration is lost
TWI stops sending data
1 1
Data from the master
P
Arbitration is lost
S
1
0
S
1
0 0 1
1
S
1
0
1
1
The master stops sending data
0 1
Data from the TWI
ARBLST
Bus is busy
Bus is free
Transfer is kept
TWI DATA transfer
A transfer is programmed
(DADR + W + START + Write THR)
Transfer is stopped
Transfer is programmed again
(DADR + W + START + Write THR)
Bus is considered as free
Transfer is initiated
The flowchart shown in Figure 35-23 on page 547 gives an example of read and write operations
in Multi-master mode.
546
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 35-23. Multi-master Flowchart
START
Programm the SLAVE mode:
SADR + MSDIS + SVEN
Read Status Register
SVACC = 1 ?
Yes
GACC = 1 ?
No
No
No
No
SVREAD = 0 ?
EOSACC = 1 ?
Yes
Yes
No
Write in TWI_THR
TXCOMP = 1 ?
No
RXRDY= 0 ?
Yes
No
No
TXRDY= 1 ?
Yes
Yes
Read TWI_RHR
Need to perform
a master access ?
GENERAL CALL TREATMENT
Yes
Decoding of the
programming sequence
No
Prog seq
OK ?
Change SADR
Program the Master mode
DADR + SVDIS + MSEN + CLK + R / W
Read Status Register
Yes
No
ARBLST = 1 ?
Yes
Yes
No
MREAD = 1 ?
RXRDY= 0 ?
TXRDY= 0 ?
No
No
Read TWI_RHR
Yes
Yes
Data to read?
Data to send ?
Yes
Write in TWI_THR
No
No
Stop Transfer
TWI_CR = STOP
Read Status Register
Yes
547
TXCOMP = 0 ?
No
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.10 Slave Mode
35.10.1
Definition
The Slave Mode is defined as a mode where the device receives the clock and the address from
another device called the master.
In this mode, the device never initiates and never completes the transmission (START,
REPEATED_START and STOP conditions are always provided by the master).
35.10.2
Application Block Diagram
Figure 35-24. Slave Mode Typical Application Block Diagram
VDD
R
Master
Host with
TWI
Interface
35.10.3
R
TWD
TWCK
Host with TWI
Interface
Host with TWI
Interface
LCD Controller
Slave 1
Slave 2
Slave 3
Programming Slave Mode
The following fields must be programmed before entering Slave mode:
1. SADR (TWI_SMR): The slave device address is used in order to be accessed by master devices in read or write mode.
2. MSDIS (TWI_CR): Disable the master mode.
3. SVEN (TWI_CR): Enable the slave mode.
As the device receives the clock, values written in TWI_CWGR are not taken into account.
35.10.4
Receiving Data
After a Start or Repeated Start condition is detected and if the address sent by the Master
matches with the Slave address programmed in the SADR (Slave ADdress) field, SVACC (Slave
ACCess) flag is set and SVREAD (Slave READ) indicates the direction of the transfer.
SVACC remains high until a STOP condition or a repeated START is detected. When such a
condition is detected, EOSACC (End Of Slave ACCess) flag is set.
35.10.4.1
Read Sequence
In the case of a Read sequence (SVREAD is high), TWI transfers data written in the TWI_THR
(TWI Transmit Holding Register) until a STOP condition or a REPEATED_START + an address
different from SADR is detected. Note that at the end of the read sequence TXCOMP (Transmission Complete) flag is set and SVACC reset.
As soon as data is written in the TWI_THR, TXRDY (Transmit Holding Register Ready) flag is
reset, and it is set when the shift register is empty and the sent data acknowledged or not. If the
data is not acknowledged, the NACK flag is set.
548
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Note that a STOP or a repeated START always follows a NACK.
See Figure 35-25 on page 550.
35.10.4.2
Write Sequence
In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register
Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive
Holding Register). RXRDY is reset when reading the TWI_RHR.
TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set
and SVACC reset.
See Figure 35-26 on page 550.
35.10.4.3
Clock Synchronization Sequence
In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock
synchronization.
Clock stretching information is given by the SCLWS (Clock Wait state) bit.
See Figure 35-28 on page 552 and Figure 35-29 on page 553.
35.10.4.4
General Call
In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set.
After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL
and to decode the new address programming sequence.
See Figure 35-27 on page 551.
35.10.4.5
PDC
As it is impossible to know the exact number of data to receive/send, the use of PDC is NOT recommended in SLAVE mode.
35.10.5
35.10.5.1
Data Transfer
Read Operation
The read mode is defined as a data requirement from the master.
After a START or a REPEATED START condition is detected, the decoding of the address
starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer.
Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded
in the TWI_THR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected,
SVACC is reset.
Figure 35-25 on page 550 describes the write operation.
549
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 35-25. Read Access Ordered by a MASTER
SADR matches,
TWI answers with an ACK
SADR does not match,
TWI answers with a NACK
TWD
S
ADR
R
NA
DATA
NA
P/S/Sr
SADR R
A
DATA
A
ACK/NACK from the Master
A
DATA
NA
S/Sr
TXRDY
Read RHR
Write THR
NACK
SVACC
SVREAD
SVREAD has to be taken into account only while SVACC is active
EOSVACC
Notes:
1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been
acknowledged or non acknowledged.
35.10.5.2
Write Operation
The write mode is defined as a data transmission from the master.
After a START or a REPEATED START, the decoding of the address starts. If the slave address
is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in
this case).
Until a STOP or REPEATED START condition is detected, TWI stores the received data in the
TWI_RHR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected,
SVACC is reset.
Figure 35-26 on page 550 describes the Write operation.
Figure 35-26. Write Access Ordered by a Master
SADR does not match,
TWI answers with a NACK
TWD
S
ADR
W
NA
DATA
NA
SADR matches,
TWI answers with an ACK
P/S/Sr
SADR W
A
DATA
A
Read RHR
A
DATA
NA
S/Sr
RXRDY
SVACC
SVREAD
SVREAD has to be taken into account only while SVACC is active
EOSVACC
Notes:
1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read.
550
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.10.5.3
General Call
The general call is performed in order to change the address of the slave.
If a GENERAL CALL is detected, GACC is set.
After the detection of General Call, it is up to the programmer to decode the commands which
come afterwards.
In case of a WRITE command, the programmer has to decode the programming sequence and
program a new SADR if the programming sequence matches.
Figure 35-27 on page 551 describes the General Call access.
Figure 35-27. Master Performs a General Call
0000000 + W
TXD
S
GENERAL CALL
RESET command = 00000110X
WRITE command = 00000100X
A
Reset or write DADD
A
DATA1
A
DATA2
A
New SADR
A
P
New SADR
Programming sequence
GCACC
Reset after read
SVACC
Note:
551
This method allows the user to create an own programming sequence by choosing the programming bytes and the number of them. The programming sequence has to be provided to the
master.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.10.5.4
Clock Synchronization
In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving
undesired data, a clock stretching mechanism is implemented.
35.10.5.5
Clock Synchronization in Read Mode
The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition
was not detected. It is tied low until the shift register is loaded.
Figure 35-28 on page 552 describes the clock synchronization in Read mode.
Figure 35-28. Clock Synchronization in Read Mode
TWI_THR
DATA0
S
SADR
R
DATA1
1
A
DATA0
A
DATA1
DATA2
A
XXXXXXX
DATA2
NA
S
2
TWCK
Write THR
CLOCK is tied low by the TWI
as long as THR is empty
SCLWS
TXRDY
SVACC
SVREAD
As soon as a START is detected
TXCOMP
TWI_THR is transmitted to the shift register
Notes:
Ack or Nack from the master
1
The data is memorized in TWI_THR until a new value is written
2
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
1. TXRDY is reset when data has been written in the TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged.
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
3. SCLWS is automatically set when the clock synchronization mechanism is started.
552
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.10.5.6
Clock Synchronization in Write Mode
The c lock is tied lo w if the shift register and the TWI_RHR is full. If a STOP or
REPEATED_START condition was not detected, it is tied low until TWI_RHR is read.
Figure 35-29 on page 553 describes the clock synchronization in Read mode.
Figure 35-29. Clock Synchronization in Write Mode
TWCK
CLOCK is tied low by the TWI as long as RHR is full
TWD
S
SADR
W
A
DATA0
TWI_RHR
A
DATA1
A
DATA0 is not read in the RHR
DATA2
DATA1
NA
S
ADR
DATA2
SCLWS
SCL is stretched on the last bit of DATA1
RXRDY
Rd DATA0
Rd DATA1
Rd DATA2
SVACC
SVREAD
TXCOMP
Notes:
As soon as a START is detected
1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mechanism is finished.
553
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.10.5.7
Reversal after a Repeated Start
35.10.5.8
Reversal of Read to Write
The master initiates the communication by a read command and finishes it by a write command.
Figure 35-30 on page 554 describes the repeated start + reversal from Read to Write mode.
Figure 35-30. Repeated Start + Reversal from Read to Write Mode
TWI_THR
TWD
DATA0
S
SADR
R
A
DATA0
DATA1
A
DATA1
NA
Sr
SADR
W
A
DATA2
TWI_RHR
A
DATA3
DATA2
A
P
DATA3
SVACC
SVREAD
TXRDY
RXRDY
EOSACC
Cleared after read
As soon as a START is detected
TXCOMP
1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
35.10.5.9
Reversal of Write to Read
The master initiates the communication by a write command and finishes it by a read command.Figure 35-31 on page 554 describes the repeated start + reversal from Write to Read
mode.
Figure 35-31. Repeated Start + Reversal from Write to Read Mode
DATA2
TWI_THR
TWD
S
SADR
W
A
DATA0
TWI_RHR
A
DATA1
DATA0
A
Sr
SADR
R
A
DATA3
DATA2
A
DATA3
NA
P
DATA1
SVACC
SVREAD
TXRDY
RXRDY
EOSACC
TXCOMP
Notes:
Read TWI_RHR
Cleared after read
As soon as a START is detected
1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before
the ACK.
2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
554
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.10.6
Read Write Flowcharts
The flowchart shown in Figure 35-32 on page 555 gives an example of read and write operations
in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt
method requires that the interrupt enable register (TWI_IER) be configured first.
Figure 35-32. Read Write Flowchart in Slave Mode
Set the SLAVE mode:
SADR + MSDIS + SVEN
Read Status Register
SVACC = 1 ?
No
No
No
EOSACC = 1 ?
GACC = 1 ?
No
SVREAD = 0 ?
No
TXRDY= 1 ?
No
Write in TWI_THR
TXCOMP = 1 ?
RXRDY= 0 ?
No
END
Read TWI_RHR
GENERAL CALL TREATMENT
Decoding of the
programming sequence
Prog seq
OK ?
No
Change SADR
555
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.11 Two-wire Interface (TWI) User Interface
Table 35-5.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
Control Register
TWI_CR
Write-only
N/A
0x04
Master Mode Register
TWI_MMR
Read-write
0x00000000
0x08
Slave Mode Register
TWI_SMR
Read-write
0x00000000
0x0C
Internal Address Register
TWI_IADR
Read-write
0x00000000
0x10
Clock Waveform Generator Register
TWI_CWGR
Read-write
0x00000000
0x20
Status Register
TWI_SR
Read-only
0x0000F009
0x24
Interrupt Enable Register
TWI_IER
Write-only
N/A
0x28
Interrupt Disable Register
TWI_IDR
Write-only
N/A
0x2C
Interrupt Mask Register
TWI_IMR
Read-only
0x00000000
0x30
Receive Holding Register
TWI_RHR
Read-only
0x00000000
0x34
Transmit Holding Register
TWI_THR
Write-only
0x00000000
0x38 - 0xFC
Reserved
–
–
–
0x100 - 0x124
Reserved for the PDC
–
–
–
556
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.11.1
Name:
TWI Control Register
TWI_CR
Address:
0xFFF88000
Access:
Write-only
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
SWRST
6
QUICK
5
SVDIS
4
SVEN
3
MSDIS
2
MSEN
1
STOP
0
START
• START: Send a START Condition
0 = No effect.
1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a
write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR).
• STOP: Send a STOP Condition
0 = No effect.
1 = STOP Condition is sent just after completing the current byte transmission in master read mode.
– In single data byte master read, the START and STOP must both be set.
– In multiple data bytes master read, the STOP must be set after the last data received but one.
– In master read mode, if a NACK bit is received, the STOP is automatically performed.
– In master data write operation, a STOP condition will be sent after the transmission of the current data is
finished.
• MSEN: TWI Master Mode Enabled
0 = No effect.
1 = If MSDIS = 0, the master mode is enabled.
Note:
Switching from Slave to Master mode is only permitted when TXCOMP = 1.
• MSDIS: TWI Master Mode Disabled
0 = No effect.
1 = The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are
transmitted in case of write operation. In read operation, the character being transferred must be completely received
before disabling.
557
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
• SVEN: TWI Slave Mode Enabled
0 = No effect.
1 = If SVDIS = 0, the slave mode is enabled.
Note:
Switching from Master to Slave mode is only permitted when TXCOMP = 1.
• SVDIS: TWI Slave Mode Disabled
0 = No effect.
1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling.
• QUICK: SMBUS Quick Command
0 = No effect.
1 = If Master mode is enabled, a SMBUS Quick Command is sent.
• SWRST: Software Reset
0 = No effect.
1 = Equivalent to a system reset.
558
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.11.2
Name:
TWI Master Mode Register
TWI_MMR
Address:
0xFFF88004
Access:
Read-write
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
21
20
19
DADR
18
17
16
15
–
14
–
13
–
12
MREAD
11
–
10
–
9
7
–
6
–
5
–
4
–
3
–
2
–
1
–
8
IADRSZ
0
–
• IADRSZ: Internal Device Address Size
IADRSZ[9:8]
0
0
No internal device address
0
1
One-byte internal device address
1
0
Two-byte internal device address
1
1
Three-byte internal device address
• MREAD: Master Read Direction
0 = Master write direction.
1 = Master read direction.
• DADR: Device Address
The device address is used to access slave devices in read or write mode. Those bits are only used in Master mode.
559
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.11.3
Name:
TWI Slave Mode Register
TWI_SMR
Address:
0xFFF88008
Access:
Read-write
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
21
20
19
SADR
18
17
16
15
–
14
–
13
–
12
–
11
–
10
–
9
8
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
–
• SADR: Slave Address
The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode.
SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect.
560
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.11.4
Name:
TWI Internal Address Register
TWI_IADR
Address:
0xFFF8800C
Access:
Read-write
Reset:
0x00000000
31
–
30
–
29
–
28
–
23
22
21
20
27
–
26
–
25
–
24
–
19
18
17
16
11
10
9
8
3
2
1
0
IADR
15
14
13
12
IADR
7
6
5
4
IADR
• IADR: Internal Address
0, 1, 2 or 3 bytes depending on IADRSZ.
561
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.11.5
Name:
TWI Clock Waveform Generator Register
TWI_CWGR
Address:
0xFFF88010
Access:
Read-write
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
22
21
20
19
18
17
CKDIV
16
15
14
13
12
11
10
9
8
3
2
1
0
CHDIV
7
6
5
4
CLDIV
TWI_CWGR is only used in Master mode.
• CLDIV: Clock Low Divider
The SCL low period is defined as follows:
T low = ( ( CLDIV × 2
CKDIV
) + 4 ) × T MCK
• CHDIV: Clock High Divider
The SCL high period is defined as follows:
T high = ( ( CHDIV × 2
CKDIV
) + 4 ) × T MCK
• CKDIV: Clock Divider
The CKDIV is used to increase both SCL high and low periods.
562
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.11.6
Name
TWI Status Register
TWI_SR
Address:
0xFFF88020
Access:
Read-only
Reset:
0x0000F009
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
TXBUFE
14
RXBUFF
13
ENDTX
12
ENDRX
11
EOSACC
10
SCLWS
9
ARBLST
8
NACK
7
–
6
OVRE
5
GACC
4
SVACC
3
SVREAD
2
TXRDY
1
RXRDY
0
TXCOMP
• TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0 = During the length of the current frame.
1 = When both holding and shifter registers are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in Figure 35-8 on page 535 and in Figure 35-10 on page 536.
TXCOMP used in Slave mode:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in Figure 35-28 on page 552, Figure 35-29 on page 553, Figure 35-30 on
page 554 and Figure 35-31 on page 554.
• RXRDY: Receive Holding Register Ready (automatically set / reset)
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in Figure 35-10 on page 536.
RXRDY behavior in Slave mode can be seen in Figure 35-26 on page 550, Figure 35-29 on page 553, Figure 35-30 on
page 554 and Figure 35-31 on page 554.
• TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in Figure 35-8 on page 535.
563
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
TXRDY used in Slave mode:
0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK).
1 = It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged.
If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the
programmer must not fill TWI_THR to avoid losing it.
TXRDY behavior in Slave mode can be seen in Figure 35-25 on page 550, Figure 35-28 on page 552, Figure 35-30 on
page 554 and Figure 35-31 on page 554.
• SVREAD: Slave Read (automatically set / reset)
This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant.
0 = Indicates that a write access is performed by a Master.
1 = Indicates that a read access is performed by a Master.
SVREAD behavior can be seen in Figure 35-25 on page 550, Figure 35-26 on page 550, Figure 35-30 on page 554 and
Figure 35-31 on page 554.
• SVACC: Slave Access (automatically set / reset)
This bit is only used in Slave mode.
0 = TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected.
1 = Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a
NACK or a STOP condition is detected.
SVACC behavior can be seen in Figure 35-25 on page 550, Figure 35-26 on page 550, Figure 35-30 on page 554 and Figure 35-31 on page 554.
• GACC: General Call Access (clear on read)
This bit is only used in Slave mode.
0 = No General Call has been detected.
1 = A General Call has been detected. After the detection of General Call, if need be, the programmer may acknowledge
this access and decode the following bytes and respond according to the value of the bytes.
GACC behavior can be seen in Figure 35-27 on page 551.
• OVRE: Overrun Error (clear on read)
This bit is only used in Master mode.
0 = TWI_RHR has not been loaded while RXRDY was set
1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.
• NACK: Not Acknowledged (clear on read)
NACK used in Master mode:
0 = Each data byte has been correctly received by the far-end side TWI slave component.
1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP.
564
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
NACK used in Slave Read mode:
0 = Each data byte has been correctly received by the Master.
1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill
TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it.
Note that in Slave Write mode all data are acknowledged by the TWI.
• ARBLST: Arbitration Lost (clear on read)
This bit is only used in Master mode.
0: Arbitration won.
1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time.
• SCLWS: Clock Wait State (automatically set / reset)
This bit is only used in Slave mode.
0 = The clock is not stretched.
1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new
character.
SCLWS behavior can be seen in Figure 35-28 on page 552 and Figure 35-29 on page 553.
• EOSACC: End Of Slave Access (clear on read)
This bit is only used in Slave mode.
0 = A slave access is being performing.
1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset.
EOSACC behavior can be seen in Figure 35-30 on page 554 and Figure 35-31 on page 554
• ENDRX: End of RX buffer
This bit is only used in Master mode.
0 = The Receive Counter Register has not reached 0 since the last write in TWI_RCR or TWI_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in TWI_RCR or TWI_RNCR.
• ENDTX: End of TX buffer
This bit is only used in Master mode.
0 = The Transmit Counter Register has not reached 0 since the last write in TWI_TCR or TWI_TNCR.
1 = The Transmit Counter Register has reached 0 since the last write in TWI_TCR or TWI_TNCR.
• RXBUFF: RX Buffer Full
This bit is only used in Master mode.
0 = TWI_RCR or TWI_RNCR have a value other than 0.
1 = Both TWI_RCR and TWI_RNCR have a value of 0.
565
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
• TXBUFE: TX Buffer Empty
This bit is only used in Master mode.
0 = TWI_TCR or TWI_TNCR have a value other than 0.
1 = Both TWI_TCR and TWI_TNCR have a value of 0.
566
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
35.11.7
Name:
TWI Interrupt Enable Register
TWI_IER
Address:
0xFFF88024
Access:
Write-only
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
TXBUFE
14
RXBUFF
13
ENDTX
12
ENDRX
11
EOSACC
10
SCL_WS
9
ARBLST
8
NACK
7
–
6
OVRE
5
GACC
4
SVACC
3
–
2
TXRDY
1
RXRDY
0
TXCOMP
• TXCOMP: Transmission Completed Interrupt Enable
• RXRDY: Receive Holding Register Ready Interrupt Enable
• TXRDY: Transmit Holding Register Ready Interrupt Enable
• SVACC: Slave Access Interrupt Enable
• GACC: General Call Access Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• NACK: Not Acknowledge Interrupt Enable
• ARBLST: Arbitration Lost Interrupt Enable
• SCL_WS: Clock Wait State Interrupt Enable
• EOSACC: End Of Slave Access Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
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35.11.8
Name:
TWI Interrupt Disable Register
TWI_IDR
Address:
0xFFF88028
Access:
Write-only
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
TXBUFE
14
RXBUFF
13
ENDTX
12
ENDRX
11
EOSACC
10
SCL_WS
9
ARBLST
8
NACK
7
–
6
OVRE
5
GACC
4
SVACC
3
–
2
TXRDY
1
RXRDY
0
TXCOMP
• TXCOMP: Transmission Completed Interrupt Disable
• RXRDY: Receive Holding Register Ready Interrupt Disable
• TXRDY: Transmit Holding Register Ready Interrupt Disable
• SVACC: Slave Access Interrupt Disable
• GACC: General Call Access Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• NACK: Not Acknowledge Interrupt Disable
• ARBLST: Arbitration Lost Interrupt Disable
• SCL_WS: Clock Wait State Interrupt Disable
• EOSACC: End Of Slave Access Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
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AT91CAP9S500A/AT91CAP9S250A
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35.11.9
Name:
TWI Interrupt Mask Register
TWI_IMR
Address:
0xFFF8802C
Access:
Read-only
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
TXBUFE
14
RXBUFF
13
ENDTX
12
ENDRX
11
EOSACC
10
SCL_WS
9
ARBLST
8
NACK
7
–
6
OVRE
5
GACC
4
SVACC
3
–
2
TXRDY
1
RXRDY
0
TXCOMP
• TXCOMP: Transmission Completed Interrupt Mask
• RXRDY: Receive Holding Register Ready Interrupt Mask
• TXRDY: Transmit Holding Register Ready Interrupt Mask
• SVACC: Slave Access Interrupt Mask
• GACC: General Call Access Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• NACK: Not Acknowledge Interrupt Mask
• ARBLST: Arbitration Lost Interrupt Mask
• SCL_WS: Clock Wait State Interrupt Mask
• EOSACC: End Of Slave Access Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
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35.11.10 TWI Receive Holding Register
Name:
TWI_RHR
Address:
0xFFF88030
Access:
Read-only
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
6
5
4
3
2
1
0
RXDATA
• RXDATA: Master or Slave Receive Holding Data
35.11.11 TWI Transmit Holding Register
Name:
TWI_THR
Address:
0xFFF88034
Access:
Read-write
Reset:
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
6
5
4
3
2
1
0
TXDATA
• TXDATA: Master or Slave Transmit Holding Data
570
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AT91CAP9S500A/AT91CAP9S250A
36. Universal Synchronous Asynchronous Receiver Transceiver (USART)
36.1
Description
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full
duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver
implements parity error, framing error and overrun error detection. The receiver time-out enables
handling variable-length frames and the transmitter timeguard facilitates communications with
slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission.
The USART features three test modes: remote loopback, local loopback and automatic echo.
The USART supports specific operating modes providing interfaces on RS485 buses, with
ISO7816 T = 0 or T = 1 smart card slots and infrared transceivers. The hardware handshaking
feature enables an out-of-band flow control by automatic management of the pins RTS and
CTS.
The USART supports the connection to the Peripheral DMA Controller, which enables data
transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor.
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6264C–CAP–24-Mar-09
36.2
Block Diagram
Figure 36-1. USART Block Diagram
Peripheral DMA
Controller
Channel
Channel
PIO
Controller
USART
RXD
Receiver
RTS
AIC
USART
Interrupt
TXD
Transmitter
CTS
DTR
PMC
Modem
Signals
Control
MCK
DIV
DSR
DCD
MCK/DIV
RI
SLCK
Baud Rate
Generator
SCK
User Interface
APB
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AT91CAP9S500A/AT91CAP9S250A
36.3
Application Block Diagram
Figure 36-2. Application Block Diagram
IrLAP
PPP
Modem
Driver
Serial
Driver
Field Bus
Driver
EMV
Driver
IrDA
Driver
USART
RS232
Drivers
RS232
Drivers
RS485
Drivers
Serial
Port
Differential
Bus
Smart
Card
Slot
IrDA
Transceivers
Modem
PSTN
36.4
I/O Lines Description
Table 36-1.
I/O Line Description
Name
Description
Type
Active Level
SCK
Serial Clock
I/O
TXD
Transmit Serial Data
I/O
RXD
Receive Serial Data
Input
CTS
Clear to Send
Input
Low
RTS
Request to Send
Output
Low
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36.5
36.5.1
Product Dependencies
I/O Lines
The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral
function. If I/O lines of the USART are not used by the application, they can be used for other
purposes by the PIO Controller.
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up
is mandatory. If the hardware handshaking feature is used, the internal pull up on TXD must also
be enabled.
Only USART0 is fully equipped with all the modem signals.
36.5.2
Power Management
The USART is not continuously clocked. The programmer must first enable the USART Clock in
the Power Management Controller (PMC) before using the USART. However, if the application
does not require USART operations, the USART clock can be stopped when not needed and be
restarted later. In this case, the USART will resume its operations where it left off.
Configuring the USART does not require the USART clock to be enabled.
36.5.3
Interrupt
The USART interrupt line is connected on one of the internal sources of the Advanced Inter-rupt
Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not
recommended to use the USART interrupt line in edge sensitive mode.
Table 36-2.
Peripheral IDs
Instance
ID
USART0
8
USART1
9
USART2
10
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36.6
Functional Description
The USART is capable of managing several types of serial synchronous or asynchronous
communications.
It supports the following communication modes:
• 5- to 9-bit full-duplex asynchronous serial communication
– MSB- or LSB-first
– 1, 1.5 or 2 stop bits
– Parity even, odd, marked, space or none
– By 8 or by 16 over-sampling receiver frequency
– Optional hardware handshaking
– Optional break management
– Optional multidrop serial communication
• High-speed 5- to 9-bit full-duplex synchronous serial communication
– MSB- or LSB-first
– 1 or 2 stop bits
– Parity even, odd, marked, space or none
– By 8 or by 16 over-sampling frequency
– Optional hardware handshaking
– Optional break management
– Optional multidrop serial communication
• RS485 with driver control signal
• ISO7816, T0 or T1 protocols for interfacing with smart cards
– NACK handling, error counter with repetition and iteration limit
• InfraRed IrDA Modulation and Demodulation
• Test modes
– Remote loopback, local loopback, automatic echo
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AT91CAP9S500A/AT91CAP9S250A
36.6.1
Baud Rate Generator
The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the
receiver and the transmitter.
The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode
Register (US_MR) between:
• the Master Clock MCK
• a division of the Master Clock, the divider being product dependent, but generally set to 8
• the external clock, available on the SCK pin
The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field
of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate
Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and
becomes inactive.
If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the
signal provided on SCK must be at least 4.5 times lower than MCK.
Figure 36-3. Baud Rate Generator
USCLKS
MCK
MCK/DIV
SCK
Reserved
CD
CD
SCK
0
1
2
16-bit Counter
FIDI
>1
3
1
0
0
0
SYNC
OVER
Sampling
Divider
0
Baud Rate
Clock
1
1
SYNC
USCLKS = 3
36.6.1.1
Sampling
Clock
Baud Rate in Asynchronous Mode
If the USART is programmed to operate in asynchronous mode, the selected clock is first
divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR).
The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8,
depending on the programming of the OVER bit in US_MR.
If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is
cleared, the sampling is performed at 16 times the baud rate clock.
The following formula performs the calculation of the Baud Rate.
SelectedClock
Baudrate = -------------------------------------------( 8 ( 2 – Over )CD )
This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed at 1.
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36.6.1.2
Baud Rate Calculation Example
Table 36-3 shows calculations of CD to obtain a baud rate at 38400 bauds for different source
clock frequencies. This table also shows the actual resulting baud rate and the error.
Table 36-3.
Baud Rate Example (OVER = 0)
Source Clock
Expected Baud
Rate
MHz
Bit/s
3 686 400
38 400
6.00
6
38 400.00
0.00%
4 915 200
38 400
8.00
8
38 400.00
0.00%
5 000 000
38 400
8.14
8
39 062.50
1.70%
7 372 800
38 400
12.00
12
38 400.00
0.00%
8 000 000
38 400
13.02
13
38 461.54
0.16%
12 000 000
38 400
19.53
20
37 500.00
2.40%
12 288 000
38 400
20.00
20
38 400.00
0.00%
14 318 180
38 400
23.30
23
38 908.10
1.31%
14 745 600
38 400
24.00
24
38 400.00
0.00%
18 432 000
38 400
30.00
30
38 400.00
0.00%
24 000 000
38 400
39.06
39
38 461.54
0.16%
24 576 000
38 400
40.00
40
38 400.00
0.00%
25 000 000
38 400
40.69
40
38 109.76
0.76%
32 000 000
38 400
52.08
52
38 461.54
0.16%
32 768 000
38 400
53.33
53
38 641.51
0.63%
33 000 000
38 400
53.71
54
38 194.44
0.54%
40 000 000
38 400
65.10
65
38 461.54
0.16%
50 000 000
38 400
81.38
81
38 580.25
0.47%
60 000 000
38 400
97.66
98
38 265.31
0.35%
70 000 000
38 400
113.93
114
38 377.19
0.06%
Calculation Result
CD
Actual Baud Rate
Error
Bit/s
The baud rate is calculated with the following formula:
BaudRate = MCK ⁄ CD × 16
The baud rate error is calculated with the following formula. It is not recommended to work with
an error higher than 5%.
ExpectedBaudRate
Error = 1 – ⎛ ---------------------------------------------------⎞
⎝ ActualBaudRate ⎠
36.6.1.3
Fractional Baud Rate in Asynchronous Mode
The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this
problem is to integrate a fractional N clock generator that has a high resolution. The generator
architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock.
577
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AT91CAP9S500A/AT91CAP9S250A
This fractional part is programmed with the FP field in the Baud Rate Generator Register
(US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the
clock divider. This feature is only available when using USART normal mode. The fractional
Baud Rate is calculated using the following formula:
SelectedClock
Baudrate = ---------------------------------------------------------------⎛ 8 ( 2 – Over ) ⎛ CD + FP
⎞
⎞
------⎝
⎝
8 ⎠⎠
The modified architecture is presented below:
Figure 36-4. Fractional Baud Rate Generator
FP
USCLKS
CD
Modulus
Control
FP
MCK
MCK/DIV
SCK
Reserved
CD
SCK
0
1
2
3
16-bit Counter
glitch-free
logic
1
0
FIDI
>1
0
0
SYNC
OVER
Sampling
Divider
0
Baud Rate
Clock
1
1
SYNC
USCLKS = 3
36.6.1.4
Sampling
Clock
Baud Rate in Synchronous Mode
If the USART is programmed to operate in synchronous mode, the selected clock is simply
divided by the field CD in US_BRGR.
BaudRate = SelectedClock
-------------------------------------CD
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided
directly by the signal on the USART SCK pin. No division is active. The value written in
US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the
system clock.
When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the
value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the
SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty
cycle on the SCK pin, even if the value programmed in CD is odd.
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36.6.1.5
Baud Rate in ISO 7816 Mode
The ISO7816 specification defines the bit rate with the following formula:
Di
B = ------ × f
Fi
where:
• B is the bit rate
• Di is the bit-rate adjustment factor
• Fi is the clock frequency division factor
• f is the ISO7816 clock frequency (Hz)
Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 36-4.
Table 36-4.
Binary and Decimal Values for Di
DI field
0001
0010
0011
0100
0101
0110
1000
1001
1
2
4
8
16
32
12
20
Di (decimal)
Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 36-5.
Table 36-5.
Binary and Decimal Values for Fi
FI field
0000
0001
0010
0011
0100
0101
0110
1001
1010
1011
1100
1101
Fi (decimal
372
372
558
744
1116
1488
1860
512
768
1024
1536
2048
Table 36-6 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the
baud rate clock.
Table 36-6.
Possible Values for the Fi/Di Ratio
Fi/Di
372
558
774
1116
1488
1806
512
768
1024
1536
2048
1
372
558
744
1116
1488
1860
512
768
1024
1536
2048
2
186
279
372
558
744
930
256
384
512
768
1024
4
93
139.5
186
279
372
465
128
192
256
384
512
8
46.5
69.75
93
139.5
186
232.5
64
96
128
192
256
16
23.25
34.87
46.5
69.75
93
116.2
32
48
64
96
128
32
11.62
17.43
23.25
34.87
46.5
58.13
16
24
32
48
64
12
31
46.5
62
93
124
155
42.66
64
85.33
128
170.6
20
18.6
27.9
37.2
55.8
74.4
93
25.6
38.4
51.2
76.8
102.4
If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the
Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud
Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to
feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR.
This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio
register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up
to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the
user must program the FI_DI_RATIO field to a value as close as possible to the expected value.
The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common
divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1).
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AT91CAP9S500A/AT91CAP9S250A
Figure 36-5 shows the relation between the Elementary Time Unit, corresponding to a bit time,
and the ISO 7816 clock.
Figure 36-5. Elementary Time Unit (ETU)
FI_DI_RATIO
ISO7816 Clock Cycles
ISO7816 Clock
on SCK
ISO7816 I/O Line
on TXD
1 ETU
36.6.2
Receiver and Transmitter Control
After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit
in the Control Register (US_CR). However, the receiver registers can be programmed before the
receiver clock is enabled.
After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the
Control Register (US_CR). However, the transmitter registers can be programmed before being
enabled.
The Receiver and the Transmitter can be enabled together or independently.
At any time, the software can perform a reset on the receiver or the transmitter of the USART by
setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register
(US_CR). The software resets clear the status flag and reset internal state machines but the
user interface configuration registers hold the value configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately
stopped.
The user can also independently disable the receiver or the transmitter by setting RXDIS and
TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the
USART waits until the end of reception of the current character, then the reception is stopped. If
the transmitter is disabled while it is operating, the USART waits the end of transmission of both
the current character and character being stored in the Transmit Holding Register (US_THR). If
a timeguard is programmed, it is handled normally.
36.6.3
36.6.3.1
Synchronous and Asynchronous Modes
Transmitter Operations
The transmitter performs the same in both synchronous and asynchronous operating modes
(SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two
stop bits are successively shifted out on the TXD pin at each falling edge of the programmed
serial clock.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register
(US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The
parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none
parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If
written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The num580
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
ber of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in
asynchronous mode only.
Figure 36-6. Character Transmit
Example: 8-bit, Parity Enabled One Stop
Baud Rate
Clock
TXD
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter
reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready),
which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters
written in US_THR have been processed. When the current character processing is completed,
the last character written in US_THR is transferred into the Shift Register of the transmitter and
US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in
US_THR while TXRDY is low has no effect and the written character is lost.
Figure 36-7. Transmitter Status
Baud Rate
Clock
TXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop Start
D0
Bit Bit Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
Write
US_THR
TXRDY
TXEMPTY
36.6.3.2
Manchester Encoder
When the Manchester encoder is in use, characters transmitted through the USART are
encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the
US_MR register to 1. Depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the
midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the
receiver has more error control since the expected input must show a change at the center of a
bit cell. An example of Manchester encoded sequence is: the byte 0xB1 or 10110001 encodes
to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. Figure 36-8 illustrates
this coding scheme.
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AT91CAP9S500A/AT91CAP9S250A
Figure 36-8. NRZ to Manchester Encoding
NRZ
encoded
data
Manchester
encoded
data
1
0
1
1
0
0
0
1
Txd
The Manchester encoded character can also be encapsulated by adding both a configurable
preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a
training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15
bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any
character. The preamble pattern is chosen among the following sequences: ALL_ONE,
ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the US_MAN register, the
field TX_PL is used to configure the preamble length. Figure 36-9 illustrates and defines the
valid patterns. To improve flexibility, the encoding scheme can be configured using the
TX_MPOL field in the US_MAN register. If the TX_MPOL field is set to zero (default), a logic
zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. If the TX_MPOL field is set to one, a logic one is encoded with a one-to-zero transition
and a logic zero is encoded with a zero-to-one transition.
Figure 36-9. Preamble Patterns, Default Polarity Assumed
Manchester
encoded
data
Txd
SFD
DATA
SFD
DATA
SFD
DATA
SFD
DATA
8 bit width "ALL_ONE" Preamble
Manchester
encoded
data
Txd
8 bit width "ALL_ZERO" Preamble
Manchester
encoded
data
Txd
8 bit width "ZERO_ONE" Preamble
Manchester
encoded
data
Txd
8 bit width "ONE_ZERO" Preamble
A start frame delimiter is to be configured using the ONEBIT field in the US_MR register. It consists of a user-defined pattern that indicates the beginning of a valid data. Figure 36-10
illustrates these patterns. If the start frame delimiter, also known as start bit, is one bit, (ONEBIT
at 1), a logic zero is Manchester encoded and indicates that a new character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as sync
(ONEBIT at 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new
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character. The sync waveform is in itself an invalid Manchester waveform as the transition
occurs at the middle of the second bit time. Two distinct sync patterns are used: the command
sync and the data sync. The command sync has a logic one level for one and a half bit times,
then a transition to logic zero for the second one and a half bit times. If the MODSYNC field in
the US_MR register is set to 1, the next character is a command. If it is set to 0, the next character is a data. When direct memory access is used, the MODSYNC field can be immediately
updated with a modified character located in memory. To enable this mode, VAR_SYNC field in
US_MR register must be set to 1. In this case, the MODSYNC field in US_MR is bypassed and
the sync configuration is held in the TXSYNH in the US_THR register. The USART character format is modified and includes sync information.
Figure 36-10. Start Frame Delimiter
Preamble Length
is set to 0
SFD
Manchester
encoded
data
DATA
Txd
One bit start frame delimiter
SFD
Manchester
encoded
data
DATA
Txd
SFD
Manchester
encoded
data
Txd
Command Sync
start frame delimiter
DATA
Data Sync
start frame delimiter
36.6.3.3
Drift Compensation
Drift compensation is available only in 16X oversampling mode. An hardware recovery system
allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register
must be set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered
as normal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock
cycles before the expected edge, then the current period is shortened by one clock cycle. If the
RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is
lengthened by one clock cycle. These intervals are considered to be drift and so corrective
actions are automatically taken.
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Figure 36-11. Bit Resynchronization
Oversampling
16x Clock
RXD
Sampling
point
Expected edge
Synchro.
Error
36.6.3.4
Synchro.
Jump
Tolerance
Sync
Jump
Synchro.
Error
Asynchronous Receiver
If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock,
depending on the OVER bit in the Mode Register (US_MR).
The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start
bit is detected and data, parity and stop bits are successively sampled on the bit rate clock.
If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data
bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8
(OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop
bit are sampled on each 8 sampling clock cycle.
The number of data bits, first bit sent and parity mode are selected by the same fields and bits
as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization
mechanism only, the number of stop bits has no effect on the receiver as it considers only one
stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the
transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking
for a new start bit so that resynchronization can also be accomplished when the transmitter is
operating with one stop bit.
Figure 36-12 and Figure 36-13 illustrate start detection and character reception when USART
operates in asynchronous mode.
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Figure 36-12. Asynchronous Start Detection
Baud Rate
Clock
Sampling
Clock (x16)
RXD
Sampling
1
2
3
4
5
6
7
8
1
2
3
4
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
D0
Sampling
Start
Detection
RXD
Sampling
1
2
3
4
5
6
7
0 1
Start
Rejection
Figure 36-13. Asynchronous Character Reception
Example: 8-bit, Parity Enabled
Baud Rate
Clock
RXD
Start
Detection
16
16
16
16
16
16
16
16
16
16
samples samples samples samples samples samples samples samples samples samples
D0
36.6.3.5
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
Manchester Decoder
When the MAN field in US_MR register is set to 1, the Manchester decoder is enabled. The
decoder performs both preamble and start frame delimiter detection. One input line is dedicated
to Manchester encoded input data.
An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in US_MAN register to configure the length of the preamble
sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addition, the polarity of the input stream is programmable with RX_MPOL field in US_MAN register.
Depending on the desired application the preamble pattern matching is to be defined via the
RX_PP field in US_MAN. See Figure 36-9 for available preamble patterns.
Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder.
So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start
frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame
delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled during one quarter of a bit time at zero, a start bit is detected. See Figure 36-14. The sample pulse
rejection mechanism applies.
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Figure 36-14. Asynchronous Start Bit Detection
Sampling
Clock
(16 x)
Manchester
encoded
data
Txd
Start
Detection
1
2
3
4
The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data
at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is
detected, the receiver continues decoding with the same synchronization. If the stream does not
match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next
valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time.
If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming
stream is decoded into NRZ data and passed to USART for processing. Figure 36-15 illustrates
Manchester pattern mismatch. When incoming data stream is passed to the USART, the
receiver is also able to detect Manchester code violation. A code violation is a lack of transition
in the middle of a bit cell. In this case, MANE flag in US_CSR register is raised. It is cleared by
writing the Control Register (US_CR) with the RSTSTA bit at 1. See Figure 36-16 for an example of Manchester error detection during data phase.
Figure 36-15. Preamble Pattern Mismatch
Preamble Mismatch
Manchester coding error
Manchester
encoded
data
Preamble Mismatch
invalid pattern
SFD
Txd
DATA
Preamble Length is set to 8
Figure 36-16. Manchester Error Flag
Preamble Length
is set to 4
Elementary character bit time
SFD
Manchester
encoded
data
Txd
Entering USART character area
sampling points
Preamble subpacket
and Start Frame Delimiter
were successfully
decoded
Manchester
Coding Error
detected
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When the start frame delimiter is a sync pattern (ONEBIT field at 0), both command and data
delimiter are supported. If a valid sync is detected, the received character is written as RXCHR
field in the US_RHR register and the RXSYNH is updated. RXCHR is set to 1 when the received
character is a command, and it is set to 0 if the received character is a data. This mechanism
alleviates and simplifies the direct memory access as the character contains its own sync field in
the same register.
As the decoder is setup to be used in unipolar mode, the first bit of the frame has to be a zero-toone transition.
36.6.3.6
Radio Interface: Manchester Encoded USART Application
This section describes low data rate RF transmission systems and their integration with a Manchester encoded USART. These systems are based on transmitter and receiver ICs that support
ASK and FSK modulation schemes.
The goal is to perform full duplex radio transmission of characters using two different frequency
carriers. See the configuration in Figure 36-17.
Figure 36-17. Manchester Encoded Characters RF Transmission
Fup frequency Carrier
ASK/FSK
Upstream Receiver
Upstream
Emitter
LNA
VCO
RF filter
Demod
Serial
Configuration
Interface
control
Fdown frequency Carrier
bi-dir
line
Manchester
decoder
USART
Receiver
Manchester
encoder
USART
Emitter
ASK/FSK
downstream transmitter
Downstream
Receiver
PA
RF filter
Mod
VCO
control
The USART module is configured as a Manchester encoder/decoder. Looking at the downstream communication channel, Manchester encoded characters are serially sent to the RF
emitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and
signals due to noise. The Manchester stream is then modulated. See Figure 36-18 for an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power
amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency.
When a logic zero is transmitted, the RF signal is turned off. If the FSK modulator is activated,
two different frequencies are used to transmit data. When a logic 1 is sent, the modulator outputs an RF signal at frequency F0 and switches to F1 if the data sent is a 0. See Figure 36-19.
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From the receiver side, another carrier frequency is used. The RF receiver performs a bit check
operation examining demodulated data stream. If a valid pattern is detected, the receiver
switches to receiving mode. The demodulated stream is sent to the Manchester decoder.
Because of bit checking inside RF IC, the data transferred to the microcontroller is reduced by a
user-defined number of bits. The Manchester preamble length is to be defined in accordance
with the RF IC configuration.
Figure 36-18. ASK Modulator Output
1
0
0
1
0
0
1
NRZ stream
Manchester
encoded
data
default polarity
unipolar output
Txd
ASK Modulator
Output
Uptstream Frequency F0
Figure 36-19. FSK Modulator Output
1
NRZ stream
Manchester
encoded
data
default polarity
unipolar output
Txd
FSK Modulator
Output
Uptstream Frequencies
[F0, F0+offset]
36.6.3.7
Synchronous Receiver
In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of
the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity
bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode
operations provide a high speed transfer capability.
Configuration fields and bits are the same as in asynchronous mode.
Figure 36-20 illustrates a character reception in synchronous mode.
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Figure 36-20. Synchronous Mode Character Reception
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Clock
RXD
Sampling
Start
D0
D1
D2
D3
D4
D5
D6
Stop Bit
D7
Parity Bit
36.6.3.8
Receiver Operations
When a character reception is completed, it is transferred to the Receive Holding Register
(US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is
transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing
the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1.
Figure 36-21. Receiver Status
Baud Rate
Clock
RXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop Start
D0
Bit Bit Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
RSTSTA = 1
Write
US_CR
Read
US_RHR
RXRDY
OVRE
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36.6.3.9
Parity
The USART supports five parity modes selected by programming the PAR field in the Mode
Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on
page 591. Even and odd parity bit generation and error detection are supported.
If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the
receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the
transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if
the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received
1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is
used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The
receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is
used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The
receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the
transmitter does not generate any parity bit and the receiver does not report any parity error.
Table 36-7 shows an example of the parity bit for the character 0x41 (character ASCII “A”)
depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added
when a parity is odd, or 0 is added when a parity is even.
Table 36-7.
Parity Bit Examples
Character
Hexa
Binary
Parity Bit
Parity Mode
A
0x41
0100 0001
1
Odd
A
0x41
0100 0001
0
Even
A
0x41
0100 0001
1
Mark
A
0x41
0100 0001
0
Space
A
0x41
0100 0001
None
None
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status
Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with
the RSTSTA bit at 1. Figure 36-22 illustrates the parity bit status setting and clearing.
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Figure 36-22. Parity Error
Baud Rate
Clock
RXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Bad Stop
Parity Bit
Bit
RSTSTA = 1
Write
US_CR
PARE
RXRDY
36.6.3.10
Multidrop Mode
If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the
USART runs in Multidrop Mode. This mode differentiates the data characters and the address
characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the
parity bit at 1.
If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when
the parity bit is high and the transmitter is able to send a character with the parity bit high when
the Control Register is written with the SENDA bit at 1.
To handle parity error, the PARE bit is cleared when the Control Register is written with the bit
RSTSTA at 1.
The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this
case, the next byte written to US_THR is transmitted as an address. Any character written in
US_THR without having written the command SENDA is transmitted normally with the parity at
0.
36.6.3.11
Transmitter Timeguard
The timeguard feature enables the USART interface with slow remote devices.
The timeguard function enables the transmitter to insert an idle state on the TXD line between
two characters. This idle state actually acts as a long stop bit.
The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed at zero no timeguard is generated. Otherwise,
the transmitter holds a high level on TXD after each transmitted byte during the number of bit
periods programmed in TG in addition to the number of stop bits.
As illustrated in Figure 36-23, the behavior of TXRDY and TXEMPTY status bits is modified by
the programming of a timeguard. TXRDY rises only when the start bit of the next character is
sent, and thus remains at 0 during the timeguard transmission if a character has been written in
US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted.
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Figure 36-23. Timeguard Operations
TG = 4
TG = 4
Baud Rate
Clock
TXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
Write
US_THR
TXRDY
TXEMPTY
Table 36-8 indicates the maximum length of a timeguard period that the transmitter can handle
in relation to the function of the Baud Rate.
Table 36-8.
36.6.3.12
Maximum Timeguard Length Depending on Baud Rate
Baud Rate
Bit time
Timeguard
Bit/sec
µs
ms
1 200
833
212.50
9 600
104
26.56
14400
69.4
17.71
19200
52.1
13.28
28800
34.7
8.85
33400
29.9
7.63
56000
17.9
4.55
57600
17.4
4.43
115200
8.7
2.21
Receiver Time-out
The Receiver Time-out provides support in handling variable-length frames. This feature detects
an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel
Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an
end of frame.
The time-out delay period (during which the receiver waits for a new character) is programmed
in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at
0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR
remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO.
This counter is decremented at each bit period and reloaded each time a new character is
received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user
can either:
• Stop the counter clock until a new character is received. This is performed by writing the
Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state
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on RXD before a new character is received will not provide a time-out. This prevents having
to handle an interrupt before a character is received and allows waiting for the next idle state
on RXD after a frame is received.
• Obtain an interrupt while no character is received. This is performed by writing US_CR with
the RETTO (Reload and Start Time-out) bit at 1. If RETTO is performed, the counter starts
counting down immediately from the value TO. This enables generation of a periodic interrupt
so that a user time-out can be handled, for example when no key is pressed on a keyboard.
If STTTO is performed, the counter clock is stopped until a first character is received. The idle
state on RXD before the start of the frame does not provide a time-out. This prevents having to
obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is
detected.
If RETTO is performed, the counter starts counting down immediately from the value TO. This
enables generation of a periodic interrupt so that a user time-out can be handled, for example
when no key is pressed on a keyboard.
Figure 36-24 shows the block diagram of the Receiver Time-out feature.
Figure 36-24. Receiver Time-out Block Diagram
TO
Baud Rate
Clock
1
D
Q
Clock
16-bit Time-out
Counter
16-bit
Value
=
STTTO
Character
Received
Load
Clear
TIMEOUT
0
RETTO
Table 36-9 gives the maximum time-out period for some standard baud rates.
Table 36-9.
Maximum Time-out Period
Baud Rate
Bit Time
Time-out
bit/sec
µs
ms
600
1 667
109 225
1 200
833
54 613
2 400
417
27 306
4 800
208
13 653
9 600
104
6 827
14400
69
4 551
19200
52
3 413
28800
35
2 276
33400
30
1 962
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Table 36-9.
36.6.3.13
Maximum Time-out Period (Continued)
Baud Rate
Bit Time
Time-out
56000
18
1 170
57600
17
1 138
200000
5
328
Framing Error
The receiver is capable of detecting framing errors. A framing error happens when the stop bit of
a received character is detected at level 0. This can occur if the receiver and the transmitter are
fully desynchronized.
A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The
FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is
cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1.
Figure 36-25. Framing Error Status
Baud Rate
Clock
RXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
RSTSTA = 1
Write
US_CR
FRAME
RXRDY
36.6.3.14
Transmit Break
The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a
0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the
TXD line at least during one character until the user requests the break condition to be removed.
A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This
can be performed at any time, either while the transmitter is empty (no character in either the
Shift Register or in US_THR) or when a character is being transmitted. If a break is requested
while a character is being shifted out, the character is first completed before the TXD line is held
low.
Once STTBRK command is requested further STTBRK commands are ignored until the end of
the break is completed.
The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is
requested before the end of the minimum break duration (one character, including start, data,
parity and stop bits), the transmitter ensures that the break condition completes.
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The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK
commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the
break condition clears the TXRDY and TXEMPTY bits as if a character is processed.
Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable
result. All STPBRK commands requested without a previous STTBRK command are ignored. A
byte written into the Transmit Holding Register while a break is pending, but not started, is
ignored.
After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times.
Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the
start of the next character. If the timeguard is programmed with a value higher than 12, the TXD
line is held high for the timeguard period.
After holding the TXD line for this period, the transmitter resumes normal operations.
Figure 36-26 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK)
commands on the TXD line.
Figure 36-26. Break Transmission
Baud Rate
Clock
TXD
Start
D0
Bit
D1
D2
D3
D4
D5
STTBRK = 1
D6
D7
Parity Stop
Bit Bit
Break Transmission
End of Break
STPBRK = 1
Write
US_CR
TXRDY
TXEMPTY
36.6.3.15
Receive Break
The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low.
When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may
be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1.
An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of
break detection also asserts the RXBRK bit.
36.6.3.16
Hardware Handshaking
The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins
are used to connect with the remote device, as shown in Figure 36-27.
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Figure 36-27. Connection with a Remote Device for Hardware Handshaking
USART
Remote
Device
TXD
RXD
RXD
TXD
CTS
RTS
RTS
CTS
Setting the USART to operate with hardware handshaking is performed by writing the
USART_MODE field in the Mode Register (US_MR) to the value 0x2.
The USART behavior when hardware handshaking is enabled is the same as the behavior in
standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as
described below and the level on the CTS pin modifies the behavior of the transmitter as
described below. Using this mode requires using the PDC channel for reception. The transmitter
can handle hardware handshaking in any case.
Figure 36-28 shows how the receiver operates if hardware handshaking is enabled. The RTS
pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while
its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating
to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the
status bit RXBUFF and, as a result, asserts the pin RTS low.
Figure 36-28. Receiver Behavior when Operating with Hardware Handshaking
RXD
RXEN = 1
RXDIS = 1
Write
US_CR
RTS
RXBUFF
Figure 36-29 shows how the transmitter operates if hardware handshaking is enabled. The CTS
pin disables the transmitter. If a character is being processing, the transmitter is disabled only
after the completion of the current character and transmission of the next character happens as
soon as the pin CTS falls.
Figure 36-29. Transmitter Behavior when Operating with Hardware Handshaking
CTS
TXD
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36.6.4
ISO7816 Mode
The USART features an ISO7816-compatible operating mode. This mode permits interfacing
with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link.
Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported.
Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the
Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T =
1.
36.6.4.1
ISO7816 Mode Overview
The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is
determined by a division of the clock provided to the remote device (see “Baud Rate Generator”
on page 576).
The USART connects to a smart card as shown in Figure 36-30. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin
becomes bidirectional, its output remains driven by the output of the transmitter but only when
the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock.
Figure 36-30. Connection of a Smart Card to the USART
USART
SCK
TXD
CLK
I/O
Smart
Card
When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The
configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB
or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to
“USART Mode Register” on page 608 and “PAR: Parity Type” on page 609.
The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by
enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver
and the transmitter at the same time in ISO7816 mode may lead to unpredictable results.
The ISO7816 specification defines an inverse transmission format. Data bits of the character
must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit
Holding Register (US_THR) or after reading it in the Receive Holding Register (US_RHR).
36.6.4.2
Protocol T = 0
In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one
guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the
I/O line during the guard time.
If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter
can continue with the transmission of the next character, as shown in Figure 36-31.
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If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as
shown in Figure 36-32. This error bit is also named NACK, for Non Acknowledge. In this case,
the character lasts 1 bit time more, as the guard time length is the same and is added to the
error bit time which lasts 1 bit time.
When the USART is the receiver and it detects an error, it does not load the erroneous character
in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle the error.
Figure 36-31. T = 0 Protocol without Parity Error
Baud Rate
Clock
RXD
Start
Bit
D0
D2
D1
D4
D3
D5
D6
D7
Parity Guard Guard Next
Bit Time 1 Time 2 Start
Bit
Figure 36-32. T = 0 Protocol with Parity Error
Baud Rate
Clock
Error
I/O
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Guard
Bit Time 1
Guard Start
Time 2 Bit
D0
D1
Repetition
36.6.4.3
Receive Error Counter
The USART receiver also records the total number of errors. This can be read in the Number of
Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER
automatically clears the NB_ERRORS field.
36.6.4.4
Receive NACK Inhibit
The USART can also be configured to inhibit an error. This can be achieved by setting the
INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O
line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR). The
INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1.
Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding
Register, as if no error occurred. However, the RXRDY bit does not raise.
36.6.4.5
Transmit Character Repetition
When the USART is transmitting a character and gets a NACK, it can automatically repeat the
character before moving on to the next one. Repetition is enabled by writing the
MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character
can be transmitted up to eight times; the first transmission plus seven repetitions.
If MAX_ITERATION does not equal zero, the USART repeats the character as many times as
the value loaded in MAX_ITERATION.
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When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the
Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the
receiver, the repetitions are stopped and the iteration counter is cleared.
The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit
at 1.
36.6.4.6
Disable Successive Receive NACK
The receiver can limit the number of successive NACKs sent back to the remote transmitter.
This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum
number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as
MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on
the line and the ITERATION bit in the Channel Status Register is set.
36.6.4.7
Protocol T = 1
When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when
receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR).
36.6.5
IrDA Mode
The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the
infrared transceivers, as shown in Figure 36-33. The modulator and demodulator are compliant
with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to
115.2 Kb/s.
The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register
(US_MR) to the value 0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator
filter. The USART transmitter and receiver operate in a normal asynchronous mode and all
parameters are accessible. Note that the modulator and the demodulator are activated.
Figure 36-33. Connection to IrDA Transceivers
USART
IrDA
Transceivers
Receiver
Demodulator
RXD
Transmitter
Modulator
TXD
RX
TX
The receiver and the transmitter must be enabled or disabled according to the direction of the
transmission to be managed.
To receive IrDA signals, the following needs to be done:
• Disable TX and Enable RX
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• Configure the TXD pin as PIO and set it as an output at 0 (to avoid LED emission). Disable
the internal pull-up (better for power consumption).
• Receive data
36.6.5.1
IrDA Modulation
For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is
represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are
shown in Table 36-10.
Table 36-10. IrDA Pulse Duration
Baud Rate
Pulse Duration (3/16)
2.4 Kb/s
78.13 µs
9.6 Kb/s
19.53 µs
19.2 Kb/s
9.77 µs
38.4 Kb/s
4.88 µs
57.6 Kb/s
3.26 µs
115.2 Kb/s
1.63 µs
Figure 36-34 shows an example of character transmission.
Figure 36-34. IrDA Modulation
Start
Bit
Transmitter
Output
0
Stop
Bit
Data Bits
1
0
1
0
0
1
1
0
1
TXD
3
16 Bit Period
Bit Period
36.6.5.2
IrDA Baud Rate
Table 36-11 gives some examples of CD values, baud rate error and pulse duration. Note that
the requirement on the maximum acceptable error of ±1.87% must be met.
Table 36-11. IrDA Baud Rate Error
Peripheral Clock
Baud Rate
CD
Baud Rate Error
Pulse Time
3 686 400
115 200
2
0.00%
1.63
20 000 000
115 200
11
1.38%
1.63
32 768 000
115 200
18
1.25%
1.63
40 000 000
115 200
22
1.38%
1.63
3 686 400
57 600
4
0.00%
3.26
20 000 000
57 600
22
1.38%
3.26
32 768 000
57 600
36
1.25%
3.26
600
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Table 36-11. IrDA Baud Rate Error (Continued)
Peripheral Clock
36.6.5.3
Baud Rate
CD
Baud Rate Error
Pulse Time
40 000 000
57 600
43
0.93%
3.26
3 686 400
38 400
6
0.00%
4.88
20 000 000
38 400
33
1.38%
4.88
32 768 000
38 400
53
0.63%
4.88
40 000 000
38 400
65
0.16%
4.88
3 686 400
19 200
12
0.00%
9.77
20 000 000
19 200
65
0.16%
9.77
32 768 000
19 200
107
0.31%
9.77
40 000 000
19 200
130
0.16%
9.77
3 686 400
9 600
24
0.00%
19.53
20 000 000
9 600
130
0.16%
19.53
32 768 000
9 600
213
0.16%
19.53
40 000 000
9 600
260
0.16%
19.53
3 686 400
2 400
96
0.00%
78.13
20 000 000
2 400
521
0.03%
78.13
32 768 000
2 400
853
0.04%
78.13
IrDA Demodulator
The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is
loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin,
the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is
detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is
detected when the counter reaches 0, the input of the receiver is driven low during one bit time.
Figure 36-35 illustrates the operations of the IrDA demodulator.
Figure 36-35. IrDA Demodulator Operations
MCK
RXD
Counter
Value
Receiver
Input
6
5
4 3
Pulse
Rejected
2
6
6
5
4
3
2
1
0
Pulse
Accepted
As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in
US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate
correctly.
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36.6.6
RS485 Mode
The USART features the RS485 mode to enable line driver control. While operating in RS485
mode, the USART behaves as though in asynchronous or synchronous mode and configuration
of all the parameters is possible. The difference is that the RTS pin is driven high when the
transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical
connection of the USART to a RS485 bus is shown in Figure 36-36.
Figure 36-36. Typical Connection to a RS485 Bus
USART
RXD
Differential
Bus
TXD
RTS
The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the value 0x1.
The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high
when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 36-37 gives an example of the RTS waveform during a character transmission
when the timeguard is enabled.
Figure 36-37. Example of RTS Drive with Timeguard
TG = 4
Baud Rate
Clock
TXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
Write
US_THR
TXRDY
TXEMPTY
RTS
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AT91CAP9S500A/AT91CAP9S250A
36.6.7
Test Modes
The USART can be programmed to operate in three different test modes. The internal loopback
capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally.
36.6.7.1
Normal Mode
Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD
pin.
Figure 36-38. Normal Mode Configuration
RXD
Receiver
TXD
Transmitter
36.6.7.2
Automatic Echo Mode
Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it
is sent to the TXD pin, as shown in Figure 36-39. Programming the transmitter has no effect on
the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains
active.
Figure 36-39. Automatic Echo Mode Configuration
RXD
Receiver
TXD
Transmitter
36.6.7.3
Local Loopback Mode
Local loopback mode connects the output of the transmitter directly to the input of the receiver,
as shown in Figure 36-40. The TXD and RXD pins are not used. The RXD pin has no effect on
the receiver and the TXD pin is continuously driven high, as in idle state.
Figure 36-40. Local Loopback Mode Configuration
RXD
Receiver
Transmitter
1
TXD
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6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
36.6.7.4
Remote Loopback Mode
Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 36-41.
The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit
retransmission.
Figure 36-41. Remote Loopback Mode Configuration
Receiver
1
RXD
TXD
Transmitter
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AT91CAP9S500A/AT91CAP9S250A
36.7
Universal Synchronous Asynchronous Receiver Transmitter
(USART) User Interface
Table 36-13.
Register Mapping
Offset
Register
Name
Access
Reset
0x0000
Control Register
US_CR
Write-only
–
0x0004
Mode Register
US_MR
Read-write
–
0x0008
Interrupt Enable Register
US_IER
Write-only
–
0x000C
Interrupt Disable Register
US_IDR
Write-only
–
0x0010
Interrupt Mask Register
US_IMR
Read-only
0x0
0x0014
Channel Status Register
US_CSR
Read-only
–
0x0018
Receiver Holding Register
US_RHR
Read-only
0x0
0x001C
Transmitter Holding Register
US_THR
Write-only
–
0x0020
Baud Rate Generator Register
US_BRGR
Read-write
0x0
0x0024
Receiver Time-out Register
US_RTOR
Read-write
0x0
0x0028
Transmitter Timeguard Register
US_TTGR
Read-write
0x0
–
–
–
0x2C - 0x3C
Reserved
0x0040
FI DI Ratio Register
US_FIDI
Read-write
0x174
0x0044
Number of Errors Register
US_NER
Read-only
–
0x0048
Reserved
–
–
–
0x004C
IrDA Filter Register
US_IF
Read-write
0x0
0x0050
Manchester Encoder Decoder Register
US_MAN
Read-write
0x30011004
Reserved
–
–
–
Reserved for PDC Registers
–
–
–
0x5C - 0xFC
0x100 - 0x128
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36.7.1
Name:
USART Control Register
US_CR
Addresses:
0xFFF8C000 (0), 0xFFF90000 (1), 0xFFF94000 (2)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
RTSDIS
18
RTSEN
17
–
16
–
15
RETTO
14
RSTNACK
13
RSTIT
12
SENDA
11
STTTO
10
STPBRK
9
STTBRK
8
RSTSTA
7
TXDIS
6
TXEN
5
RXDIS
4
RXEN
3
RSTTX
2
RSTRX
1
–
0
–
• RSTRX: Reset Receiver
0: No effect.
1: Resets the receiver.
• RSTTX: Reset Transmitter
0: No effect.
1: Resets the transmitter.
• RXEN: Receiver Enable
0: No effect.
1: Enables the receiver, if RXDIS is 0.
• RXDIS: Receiver Disable
0: No effect.
1: Disables the receiver.
• TXEN: Transmitter Enable
0: No effect.
1: Enables the transmitter if TXDIS is 0.
• TXDIS: Transmitter Disable
0: No effect.
1: Disables the transmitter.
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AT91CAP9S500A/AT91CAP9S250A
• RSTSTA: Reset Status Bits
0: No effect.
1: Resets the status bits PARE, FRAME, OVRE, MANERR and RXBRK in US_CSR.
• STTBRK: Start Break
0: No effect.
1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted.
• STPBRK: Stop Break
0: No effect.
1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.
No effect if no break is being transmitted.
• STTTO: Start Time-out
0: No effect.
1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR.
• SENDA: Send Address
0: No effect.
1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set.
• RSTIT: Reset Iterations
0: No effect.
1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled.
• RSTNACK: Reset Non Acknowledge
0: No effect
1: Resets NACK in US_CSR.
• RETTO: Rearm Time-out
0: No effect
1: Restart Time-out
• RTSEN: Request to Send Enable
0: No effect.
1: Drives the pin RTS to 0.
• RTSDIS: Request to Send Disable
0: No effect.
1: Drives the pin RTS to 1.
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36.7.2
Name:
USART Mode Register
US_MR
Addresses:
0xFFF8C004 (0), 0xFFF90004 (1), 0xFFF94004 (2)
Access:
Read-write
31
ONEBIT
30
MODSYNC
29
MAN
28
FILTER
27
–
26
25
MAX_ITERATION
24
23
–
22
VAR_SYNC
21
DSNACK
20
INACK
19
OVER
18
CLKO
17
MODE9
16
MSBF
14
13
12
11
10
PAR
9
8
SYNC
4
3
2
1
0
15
CHMODE
7
NBSTOP
6
5
CHRL
USCLKS
USART_MODE
• USART_MODE
USART_MODE
Mode of the USART
0
0
0
0
Normal
0
0
0
1
RS485
0
0
1
0
Hardware Handshaking
0
1
0
0
IS07816 Protocol: T = 0
0
1
1
0
IS07816 Protocol: T = 1
1
0
0
0
IrDA
Others
Reserved
• USCLKS: Clock Selection
USCLKS
Selected Clock
0
0
MCK
0
1
MCK/DIV (DIV = 8)
1
0
Reserved
1
1
SCK
• CHRL: Character Length.
CHRL
Character Length
0
0
5 bits
0
1
6 bits
1
0
7 bits
1
1
8 bits
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6264C–CAP–24-Mar-09
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• SYNC: Synchronous Mode Select
0: USART operates in Asynchronous Mode.
1: USART operates in Synchronous Mode.
• PAR: Parity Type
PAR
Parity Type
0
0
0
Even parity
0
0
1
Odd parity
0
1
0
Parity forced to 0 (Space)
0
1
1
Parity forced to 1 (Mark)
1
0
x
No parity
1
1
x
Multidrop mode
• NBSTOP: Number of Stop Bits
NBSTOP
Asynchronous (SYNC = 0)
Synchronous (SYNC = 1)
0
0
1 stop bit
1 stop bit
0
1
1.5 stop bits
Reserved
1
0
2 stop bits
2 stop bits
1
1
Reserved
Reserved
• CHMODE: Channel Mode
CHMODE
Mode Description
0
0
Normal Mode
0
1
Automatic Echo. Receiver input is connected to the TXD pin.
1
0
Local Loopback. Transmitter output is connected to the Receiver Input.
1
1
Remote Loopback. RXD pin is internally connected to the TXD pin.
• MSBF: Bit Order
0: Least Significant Bit is sent/received first.
1: Most Significant Bit is sent/received first.
• MODE9: 9-bit Character Length
0: CHRL defines character length.
1: 9-bit character length.
• CLKO: Clock Output Select
0: The USART does not drive the SCK pin.
1: The USART drives the SCK pin if USCLKS does not select the external clock SCK.
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6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• OVER: Oversampling Mode
0: 16x Oversampling.
1: 8x Oversampling.
• INACK: Inhibit Non Acknowledge
0: The NACK is generated.
1: The NACK is not generated.
• DSNACK: Disable Successive NACK
0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag
ITERATION is asserted.
• VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter
0: User defined configuration of command or data sync field depending on SYNC value.
1: The sync field is updated when a character is written into US_THR register.
• MAX_ITERATION
Defines the maximum number of iterations in mode ISO7816, protocol T= 0.
• FILTER: Infrared Receive Line Filter
0: The USART does not filter the receive line.
1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).
• MAN: Manchester Encoder/Decoder Enable
0: Manchester Encoder/Decoder are disabled.
1: Manchester Encoder/Decoder are enabled.
• MODSYNC: Manchester Synchronization Mode
0:The Manchester Start bit is a 0 to 1 transition
1: The Manchester Start bit is a 1 to 0 transition.
• ONEBIT: Start Frame Delimiter Selector
0: Start Frame delimiter is COMMAND or DATA SYNC.
1: Start Frame delimiter is One Bit.
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6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
36.7.3
Name:
USART Interrupt Enable Register
US_IER
Addresses:
0xFFF8C008 (0), 0xFFF90008 (1), 0xFFF94008 (2)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
MANE
19
CTSIC
18
–
17
–
16
–
15
–
14
–
13
NACK
12
RXBUFF
11
TXBUFE
10
ITER
9
TXEMPTY
8
TIMEOUT
7
PARE
6
FRAME
5
OVRE
4
ENDTX
3
ENDRX
2
RXBRK
1
TXRDY
0
RXRDY
• RXRDY: RXRDY Interrupt Enable
• TXRDY: TXRDY Interrupt Enable
• RXBRK: Receiver Break Interrupt Enable
• ENDRX: End of Receive Transfer Interrupt Enable
• ENDTX: End of Transmit Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• FRAME: Framing Error Interrupt Enable
• PARE: Parity Error Interrupt Enable
• TIMEOUT: Time-out Interrupt Enable
• TXEMPTY: TXEMPTY Interrupt Enable
• ITER: Iteration Interrupt Enable
• TXBUFE: Buffer Empty Interrupt Enable
• RXBUFF: Buffer Full Interrupt Enable
• NACK: Non Acknowledge Interrupt Enable
• CTSIC: Clear to Send Input Change Interrupt Enable
• MANE: Manchester Error Interrupt Enable
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6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
36.7.4
Name:
USART Interrupt Disable Register
US_IDR
Addresses:
0xFFF8C00C (0), 0xFFF9000C (1), 0xFFF9400C (2)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
MANE
19
CTSIC
18
–
17
–
16
–
15
–
14
–
13
NACK
12
RXBUFF
11
TXBUFE
10
ITER
9
TXEMPTY
8
TIMEOUT
7
PARE
6
FRAME
5
OVRE
4
ENDTX
3
ENDRX
2
RXBRK
1
TXRDY
0
RXRDY
• RXRDY: RXRDY Interrupt Disable
• TXRDY: TXRDY Interrupt Disable
• RXBRK: Receiver Break Interrupt Disable
• ENDRX: End of Receive Transfer Interrupt Disable
• ENDTX: End of Transmit Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• FRAME: Framing Error Interrupt Disable
• PARE: Parity Error Interrupt Disable
• TIMEOUT: Time-out Interrupt Disable
• TXEMPTY: TXEMPTY Interrupt Disable
• ITER: Iteration Interrupt Enable
• TXBUFE: Buffer Empty Interrupt Disable
• RXBUFF: Buffer Full Interrupt Disable
• NACK: Non Acknowledge Interrupt Disable
• CTSIC: Clear to Send Input Change Interrupt Disable
• MANE: Manchester Error Interrupt Disable
612
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
36.7.5
Name:
USART Interrupt Mask Register
US_IMR
Addresses:
0xFFF8C010 (0), 0xFFF90010 (1), 0xFFF94010 (2)
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
MANE
19
CTSIC
18
–
17
–
16
–
15
–
14
–
13
NACK
12
RXBUFF
11
TXBUFE
10
ITER
9
TXEMPTY
8
TIMEOUT
7
PARE
6
FRAME
5
OVRE
4
ENDTX
3
ENDRX
2
RXBRK
1
TXRDY
0
RXRDY
• RXRDY: RXRDY Interrupt Mask
• TXRDY: TXRDY Interrupt Mask
• RXBRK: Receiver Break Interrupt Mask
• ENDRX: End of Receive Transfer Interrupt Mask
• ENDTX: End of Transmit Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• FRAME: Framing Error Interrupt Mask
• PARE: Parity Error Interrupt Mask
• TIMEOUT: Time-out Interrupt Mask
• TXEMPTY: TXEMPTY Interrupt Mask
• ITER: Iteration Interrupt Enable
• TXBUFE: Buffer Empty Interrupt Mask
• RXBUFF: Buffer Full Interrupt Mask
• NACK: Non Acknowledge Interrupt Mask
• CTSIC: Clear to Send Input Change Interrupt Mask
• MANE: Manchester Error Interrupt Mask
613
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
36.7.6
Name:
USART Channel Status Register
US_CSR
Addresses:
0xFFF8C014 (0), 0xFFF90014 (1), 0xFFF94014 (2)
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
MANERR
23
CTS
22
–
21
–
20
–
19
CTSIC
18
–
17
–
16
–
15
–
14
–
13
NACK
12
RXBUFF
11
TXBUFE
10
ITER
9
TXEMPTY
8
TIMEOUT
7
PARE
6
FRAME
5
OVRE
4
ENDTX
3
ENDRX
2
RXBRK
1
TXRDY
0
RXRDY
• RXRDY: Receiver Ready
0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were
being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and US_RHR has not yet been read.
• TXRDY: Transmitter Ready
0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been
requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
1: There is no character in the US_THR.
• RXBRK: Break Received/End of Break
0: No Break received or End of Break detected since the last RSTSTA.
1: Break Received or End of Break detected since the last RSTSTA.
• ENDRX: End of Receiver Transfer
0: The End of Transfer signal from the Receive PDC channel is inactive.
1: The End of Transfer signal from the Receive PDC channel is active.
• ENDTX: End of Transmitter Transfer
0: The End of Transfer signal from the Transmit PDC channel is inactive.
1: The End of Transfer signal from the Transmit PDC channel is active.
• OVRE: Overrun Error
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
614
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• FRAME: Framing Error
0: No stop bit has been detected low since the last RSTSTA.
1: At least one stop bit has been detected low since the last RSTSTA.
• PARE: Parity Error
0: No parity error has been detected since the last RSTSTA.
1: At least one parity error has been detected since the last RSTSTA.
• TIMEOUT: Receiver Time-out
0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0.
1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
• TXEMPTY: Transmitter Empty
0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
1: There are no characters in US_THR, nor in the Transmit Shift Register.
• ITER: Max number of Repetitions Reached
0: Maximum number of repetitions has not been reached since the last RSTSTA.
1: Maximum number of repetitions has been reached since the last RSTSTA.
• TXBUFE: Transmission Buffer Empty
0: The signal Buffer Empty from the Transmit PDC channel is inactive.
1: The signal Buffer Empty from the Transmit PDC channel is active.
• RXBUFF: Reception Buffer Full
0: The signal Buffer Full from the Receive PDC channel is inactive.
1: The signal Buffer Full from the Receive PDC channel is active.
• NACK: Non Acknowledge
0: No Non Acknowledge has not been detected since the last RSTNACK.
1: At least one Non Acknowledge has been detected since the last RSTNACK.
• CTSIC: Clear to Send Input Change Flag
0: No input change has been detected on the CTS pin since the last read of US_CSR.
1: At least one input change has been detected on the CTS pin since the last read of US_CSR.
• CTS: Image of CTS Input
0: CTS is at 0.
1: CTS is at 1.
• MANERR: Manchester Error
0: No Manchester error has been detected since the last RSTSTA.
1: At least one Manchester error has been detected since the last RSTSTA.
615
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
36.7.7
Name:
USART Receive Holding Register
US_RHR
Addresses:
0xFFF8C018 (0), 0xFFF90018 (1), 0xFFF94018 (2)
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
RXSYNH
14
–
13
–
12
–
11
–
10
–
9
–
8
RXCHR
7
6
5
4
3
2
1
0
RXCHR
• RXCHR: Received Character
Last character received if RXRDY is set.
• RXSYNH: Received Sync
0: Last Character received is a Data.
1: Last Character received is a Command.
616
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
36.7.8
Name:
USART Transmit Holding Register
US_THR
Addresses:
0xFFF8C01C (0), 0xFFF9001C (1), 0xFFF9401C (2)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
TXSYNH
14
–
13
–
12
–
11
–
10
–
9
–
8
TXCHR
7
6
5
4
3
2
1
0
TXCHR
• TXCHR: Character to be Transmitted
Next character to be transmitted after the current character if TXRDY is not set.
• TXSYNH: Sync Field to be transmitted
0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC.
1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC.
617
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
36.7.9
Name:
USART Baud Rate Generator Register
US_BRGR
Addresses:
0xFFF8C020 (0), 0xFFF90020 (1), 0xFFF94020 (2)
Access:
Read-write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
17
FP
16
15
14
13
12
11
10
9
8
3
2
1
0
CD
7
6
5
4
CD
• CD: Clock Divider
USART_MODE ≠ ISO7816
SYNC = 0
CD
OVER = 0
0
1 to 65535
SYNC = 1
OVER = 1
USART_MODE =
ISO7816
Baud Rate Clock Disabled
Baud Rate =
Selected Clock/16/CD
Baud Rate =
Selected Clock/8/CD
Baud Rate =
Selected Clock /CD
Baud Rate = Selected
Clock/CD/FI_DI_RATIO
• FP: Fractional Part
0: Fractional divider is disabled.
1 - 7: Baudrate resolution, defined by FP x 1/8.
618
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
36.7.10
Name:
USART Receiver Time-out Register
US_RTOR
Addresses:
0xFFF8C024 (0), 0xFFF90024 (1), 0xFFF94024 (2)
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
3
2
1
0
TO
7
6
5
4
TO
• TO: Time-out Value
0: The Receiver Time-out is disabled.
1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.
619
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
36.7.11
Name:
USART Transmitter Timeguard Register
US_TTGR
Addresses:
0xFFF8C028 (0), 0xFFF90028 (1), 0xFFF94028 (2)
Access:
Read-write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
6
5
4
3
2
1
0
TG
• TG: Timeguard Value
0: The Transmitter Timeguard is disabled.
1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.
620
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
36.7.12
Name:
USART FI DI RATIO Register
US_FIDI
Addresses:
0xFFF8C040 (0), 0xFFF90040 (1), 0xFFF94040 (2)
Access:
Read-write
Reset Value:
0x174
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
9
FI_DI_RATIO
8
7
6
5
4
3
2
1
0
FI_DI_RATIO
• FI_DI_RATIO: FI Over DI Ratio Value
0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal.
1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO.
621
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
36.7.13
Name:
USART Number of Errors Register
US_NER
Addresses:
0xFFF8C044 (0), 0xFFF90044 (1), 0xFFF94044 (2)
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
6
5
4
3
2
1
0
NB_ERRORS
• NB_ERRORS: Number of Errors
Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
36.7.14
Name:
USART IrDA FILTER Register
US_IF
Addresses:
0xFFF8C04C (0), 0xFFF9004C (1), 0xFFF9404C (2)
Access:
Read-write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
6
5
4
3
2
1
0
IRDA_FILTER
• IRDA_FILTER: IrDA Filter
Sets the filter of the IrDA demodulator.
622
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
36.7.15
Name:
USART Manchester Configuration Register
US_MAN
Addresses:
0xFFF8C050 (0), 0xFFF90050 (1), 0xFFF94050 (2)
Access:
Read-write
31
–
30
DRIFT
29
1
28
RX_MPOL
27
–
26
–
25
23
–
22
–
21
–
20
–
19
18
15
–
14
–
13
–
12
TX_MPOL
11
–
10
–
9
7
–
6
–
5
–
4
–
3
2
1
24
RX_PP
17
16
RX_PL
8
TX_PP
0
TX_PL
This register can only be written if the WPEN bit is cleared in ”USART Write Protect Mode Register” on page 103.
• TX_PL: Transmitter Preamble Length
0: The Transmitter Preamble pattern generation is disabled
1 - 15: The Preamble Length is TX_PL x Bit Period
• TX_PP: Transmitter Preamble Pattern
TX_PP
Preamble Pattern default polarity assumed (TX_MPOL field not set)
0
0
ALL_ONE
0
1
ALL_ZERO
1
0
ZERO_ONE
1
1
ONE_ZERO
• TX_MPOL: Transmitter Manchester Polarity
0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
• RX_PL: Receiver Preamble Length
0: The receiver preamble pattern detection is disabled
1 - 15: The detected preamble length is RX_PL x Bit Period
• RX_PP: Receiver Preamble Pattern detected
RX_PP
0
Preamble Pattern default polarity assumed (RX_MPOL field not set)
0
ALL_ONE
623
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
0
1
ALL_ZERO
1
0
ZERO_ONE
1
1
ONE_ZERO
• RX_MPOL: Receiver Manchester Polarity
0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
• DRIFT: Drift compensation
0: The USART can not recover from an important clock drift
1: The USART can recover from clock drift. The 16X clock mode must be enabled.
624
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37. Synchronous Serial Controller (SSC)
37.1
Description
The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link
with external devices. It supports many serial synchronous communication protocols generally
used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc.
The SSC contains an independent receiver and transmitter and a common clock divider. The
receiver and the transmitter each interface with three signals: the TD/RD signal for data, the
TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal.
The SSC’s high-level of programmability and its two dedicated PDC channels of up to 32 bits
permit a continuous high bit rate data transfer without processor intervention.
Featuring connection to two PDC channels, the SSC permits interfacing with low processor
overhead to the following:
• CODEC’s in master or slave mode
• DAC through dedicated serial interface, particularly I2S
• Magnetic card reader
625
6264C–CAP–24-Mar-09
37.2
Block Diagram
Figure 37-1. Block Diagram
System
Bus
APB Bridge
PDC
Peripheral
Bus
TF
TK
PMC
TD
MCK
PIO
SSC Interface
RF
RK
Interrupt Control
RD
SSC Interrupt
37.3
Application Block Diagram
Figure 37-2. Application Block Diagram
OS or RTOS Driver
Power
Management
Interrupt
Management
Test
Management
SSC
Serial AUDIO
626
Codec
Time Slot
Management
Frame
Management
Line Interface
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.4
Pin Name List
Table 37-1.
I/O Lines Description
Pin Name
Pin Description
RF
Receiver Frame Synchro
Input/Output
RK
Receiver Clock
Input/Output
RD
Receiver Data
Input
TF
Transmitter Frame Synchro
Input/Output
TK
Transmitter Clock
Input/Output
TD
Transmitter Data
Output
37.5
37.5.1
Type
Product Dependencies
I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC
receiver I/O lines to the SSC peripheral mode.
Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC
transmitter I/O lines to the SSC peripheral mode.
Table 37-2.
I/O Lines
Instance
Signal
I/O Line
Peripheral
SSC0
RD0
PB3
A
SSC0
RF0
PB5
A
SSC0
RK0
PB4
A
SSC0
TD0
PB2
A
SSC0
TF0
PB0
A
SSC0
TK0
PB1
A
SSC1
RD1
PB9
A
SSC1
RF1
PB11
A
SSC1
RK1
PB10
A
SSC1
TD1
PB8
A
SSC1
TF1
PB6
A
SSC1
TK1
PB7
A
37.5.2
Power Management
The SSC is not continuously clocked. The SSC interface may be clocked through the Power
Management Controller (PMC), therefore the programmer must first configure the PMC to
enable the SSC clock.
37.5.3
Interrupt
The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling interrupts requires programming the AIC before configuring the SSC.
627
6264C–CAP–24-Mar-09
All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each
pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register.
Table 37-3.
37.6
Peripheral IDs
Instance
ID
SSC0
17
SSC1
18
Functional Description
This chapter contains the functional description of the following: SSC Functional Block, Clock
Management, Data format, Start, Transmitter, Receiver and Frame Sync.
The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission
starts. Alternatively, this can be done by programming the transmitter to use the receive clock
and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the
SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK
and RK pins is the master clock divided by 2.
628
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 37-3. SSC Functional Block Diagram
Transmitter
MCK
TK Input
Clock
Divider
Transmit Clock
Controller
RX clock
TF
RF
Start
Selector
TX clock
Clock Output
Controller
TK
Frame Sync
Controller
TF
Transmit Shift Register
TX PDC
APB
Transmit Holding
Register
TD
Transmit Sync
Holding Register
Load Shift
User
Interface
Receiver
RK Input
Receive Clock RX Clock
Controller
TX Clock
RF
TF
Start
Selector
Interrupt Control
RK
Frame Sync
Controller
RF
Receive Shift Register
RX PDC
PDC
Clock Output
Controller
Receive Holding
Register
RD
Receive Sync
Holding Register
Load Shift
AIC
37.6.1
Clock Management
The transmitter clock can be generated by:
• an external clock received on the TK I/O pad
• the receiver clock
• the internal clock divider
The receiver clock can be generated by:
• an external clock received on the RK I/O pad
• the transmitter clock
• the internal clock divider
Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the
receiver block can generate an external clock on the RK I/O pad.
This allows the SSC to support many Master and Slave Mode data transfers.
629
6264C–CAP–24-Mar-09
37.6.1.1
Clock Divider
Figure 37-4. Divided Clock Block Diagram
Clock Divider
SSC_CMR
MCK
12-bit Counter
/2
Divided Clock
The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its
maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division
by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this
field is programmed to 0, the Clock Divider is not used and remains inactive.
When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master
Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of
whether the DIV value is even or odd.
Figure 37-5.
Divided Clock Generation
Master Clock
Divided Clock
DIV = 1
Divided Clock Frequency = MCK/2
Master Clock
Divided Clock
DIV = 3
Divided Clock Frequency = MCK/6
Table 37-4.
37.6.1.2
630
Maximum
Minimum
MCK / 2
MCK / 8190
Transmitter Clock Management
The transmitter clock is generated from the receiver clock or the divider clock or an external
clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in
SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by
the CKI bits in SSC_TCMR.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion
(CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TK pin
(CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results.
Figure 37-6. Transmitter Clock Management
TK (pin)
Clock
Output
Tri_state
Controller
MUX
Receiver
Clock
Divider
Clock
Data Transfer
CKO
CKS
37.6.1.3
INV
MUX
Tri-state
Controller
CKI
CKG
Transmitter
Clock
Receiver Clock Management
The receiver clock is generated from the transmitter clock or the divider clock or an external
clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in
SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by
the CKI bits in SSC_RCMR.
The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer.
The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI)
bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS
field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable
results.
631
6264C–CAP–24-Mar-09
Figure 37-7. Receiver Clock Management
RK (pin)
Tri-state
Controller
MUX
Clock
Output
Transmitter
Clock
Divider
Clock
Data Transfer
CKO
CKS
37.6.1.4
INV
MUX
Tri-state
Controller
CKI
CKG
Receiver
Clock
Serial Clock Ratio Considerations
The Transmitter and the Receiver can be programmed to operate with the clock signals provided
on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In
this case, the maximum clock speed allowed on the RK pin is:
– Master Clock divided by 2 if Receiver Frame Synchro is input
– Master Clock divided by 3 if Receiver Frame Synchro is output
In addition, the maximum clock speed allowed on the TK pin is:
– Master Clock divided by 6 if Transmit Frame Synchro is input
– Master Clock divided by 2 if Transmit Frame Synchro is output
37.6.2
Transmitter Operations
A transmitted frame is triggered by a start event and can be followed by synchronization data
before data transmission.
The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See
“Start” on page 634.
The frame synchronization is configured setting the Transmit Frame Mode Register
(SSC_TFMR). See “Frame Sync” on page 636.
To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and
the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR
register then transferred to the shift register according to the data format selected.
When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is
set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register,
the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding
register.
632
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 37-8. Transmitter Block Diagram
SSC_CR.TXEN
SSC_SR.TXEN
SSC_CR.TXDIS
SSC_TFMR.DATDEF
1
RF
Transmitter Clock
TF
Start
Selector
37.6.3
TD
0
SSC_TFMR.MSBF
Transmit Shift Register
SSC_TFMR.FSDEN
SSC_TCMR.STTDLY
SSC_TFMR.DATLEN
SSC_TCMR.STTDLY
SSC_TFMR.FSDEN
SSC_TFMR.DATNB
0
SSC_THR
1
SSC_TSHR
SSC_TFMR.FSLEN
Receiver Operations
A received frame is triggered by a start event and can be followed by synchronization data
before data transmission.
The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See
“Start” on page 634.
The frame synchronization is configured setting the Receive Frame Mode Register
(SSC_RFMR). See “Frame Sync” on page 636.
The receiver uses a shift register clocked by the receiver clock signal and the start mode
selected in the SSC_RCMR. The data is transferred from the shift register depending on the
data format selected.
When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register. If
another transfer occurs before read of the RHR register, the status flag OVERUN is set in
SSC_SR and the receiver shift register is transferred in the RHR register.
633
6264C–CAP–24-Mar-09
Figure 37-9. Receiver Block Diagram
SSC_CR.RXEN
SSC_SR.RXEN
SSC_CR.RXDIS
RF
Receiver Clock
TF
Start
Selector
SSC_RFMR.MSBF
SSC_RFMR.DATNB
Receive Shift Register
SSC_RSHR
SSC_RHR
SSC_RFMR.FSLEN
SSC_RFMR.DATLEN
RD
SSC_RCMR.STTDLY
37.6.4
Start
The transmitter and receiver can both be programmed to start their operations when an event
occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the
Receive Start Selection (START) field of SSC_RCMR.
Under the following conditions the start event is independently programmable:
• Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR
and the reception starts as soon as the Receiver is enabled.
• Synchronously with the transmitter/receiver
• On detection of a falling/rising edge on TF/RF
• On detection of a low level/high level on TF/RF
• On detection of a level change or an edge on TF/RF
A start can be programmed in the same manner on either side of the Transmit/Receive Clock
Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive).
Moreover, the Receiver can start when data is detected in the bit stream with the Compare
Functions.
Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode
Register (TFMR/RFMR).
634
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 37-10. Transmit Start Mode
TK
TF
(Input)
Start = Low Level on TF
Start = Falling Edge on TF
Start = High Level on TF
Start = Rising Edge on TF
Start = Level Change on TF
Start = Any Edge on TF
TD
(Output)
TD
(Output)
X
BO
STTDLY
BO
X
B1
STTDLY
BO
X
TD
(Output)
B1
STTDLY
TD
(Output)
BO
X
B1
STTDLY
TD
(Output)
TD
(Output)
B1
BO
X
B1
BO
B1
STTDLY
X
B1
BO
BO
B1
STTDLY
Figure 37-11. Receive Pulse/Edge Start Modes
RK
RF
(Input)
Start = Low Level on RF
Start = Falling Edge on RF
Start = High Level on RF
Start = Rising Edge on RF
Start = Level Change on RF
Start = Any Edge on RF
RD
(Input)
RD
(Input)
X
BO
STTDLY
BO
X
B1
STTDLY
BO
X
RD
(Input)
B1
STTDLY
RD
(Input)
BO
X
B1
STTDLY
RD
(Input)
RD
(Input)
B1
BO
X
B1
BO
B1
STTDLY
X
BO
B1
BO
B1
STTDLY
635
6264C–CAP–24-Mar-09
37.6.5
Frame Sync
The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate
different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field
in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register
(SSC_TFMR) are used to select the required waveform.
• Programmable low or high levels during data transfer are supported.
• Programmable high levels before the start of data transfers or toggling are also supported.
If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and
SSC_TFMR programs the length of the pulse, from 1 bit time up to 16 bit time.
The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed
through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR.
37.6.5.1
Frame Sync Data
Frame Sync Data transmits or receives a specific tag during the Frame Sync signal.
During the Frame Sync signal, the Receiver can sample the RD line and store the data in the
Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register
in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal
is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and has a maximum value of 16.
Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or
lower than the delay between the start event and the actual data reception, the data sampling
operation is performed in the Receive Sync Holding Register through the Receive Shift Register.
The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync
Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than
the delay between the start event and the actual data transmission, the normal transmission has
priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register, then shifted out.
37.6.5.2
37.6.6
Frame Sync Edge Detection
The Frame Sync Edge detection is programmed by the FSEDGE field in
SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status
Register (SSC_SR) on frame synchro edge detection (signals RF/TF).
Receive Compare Modes
Figure 37-12. Receive Compare Modes
RK
RD
(Input)
CMP0
CMP1
CMP2
CMP3
Ignored
B0
B2
B1
Start
FSLEN
Up to 16 Bits
(4 in This Example)
636
STDLY
DATLEN
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.6.6.1
37.6.7
Compare Functions
Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they
are compared to is defined by FSLEN, but with a maximum value of 16 bits. Comparison is
always done by comparing the last bits received with the comparison pattern. Compare 0 can be
one start event of the Receiver. In this case, the receiver compares at each new sample the last
bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R).
When this start event is selected, the user can program the Receiver to start a new data transfer
either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This
selection is done with the bit (STOP) in SSC_RCMR.
Data Format
The data framing format of both the transmitter and the receiver are programmable through the
Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register
(SSC_RFMR). In either case, the user can independently select:
• the event that starts the data transfer (START)
• the delay in number of bit periods between the start event and the first data bit (STTDLY)
• the length of the data (DATLEN)
• the number of data to be transferred for each start event (DATNB).
• the length of synchronization transferred for each start event (FSLEN)
• the bit sense: most or lowest significant bit first (MSBF)
Additionally, the transmitter can be used to transfer synchronization and select the level driven
on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync
Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR.
Table 37-5.
Data Frame Registers
Transmitter
Receiver
Field
Length
Comment
SSC_TFMR
SSC_RFMR
DATLEN
Up to 32
Size of word
SSC_TFMR
SSC_RFMR
DATNB
Up to 16
Number of words transmitted in frame
SSC_TFMR
SSC_RFMR
MSBF
SSC_TFMR
SSC_RFMR
FSLEN
Up to 16
Size of Synchro data register
SSC_TFMR
DATDEF
0 or 1
Data default value ended
SSC_TFMR
FSDEN
Most significant bit first
Enable send SSC_TSHR
SSC_TCMR
SSC_RCMR
PERIOD
Up to 512
Frame size
SSC_TCMR
SSC_RCMR
STTDLY
Up to 255
Size of transmit start delay
637
6264C–CAP–24-Mar-09
Figure 37-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes
Start
Start
PERIOD
(1)
TF/RF
FSLEN
TD
(If FSDEN = 1)
TD
(If FSDEN = 0)
RD
Sync Data
Default
From SSC_TSHR FromDATDEF
Data
From SSC_THR
Default
Ignored
Sync Data
Default
From SSC_THR
Data
To SSC_RSHR
From DATDEF
Ignored
Data
To SSC_RHR
To SSC_RHR
DATLEN
DATLEN
STTDLY
Sync Data
FromDATDEF
Data
Data
From SSC_THR
From DATDEF
Default
Data
From SSC_THR
Sync Data
DATNB
Note:
1. Example of input on falling edge of TF/RF.
Figure 37-14. Transmit Frame Format in Continuous Mode
Start
Data
TD
Default
Data
From SSC_THR
From SSC_THR
DATLEN
DATLEN
Start: 1. TXEMPTY set to 1
2. Write into the SSC_THR
Note:
1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on
the transmission. SyncData cannot be output in continuous mode.
Figure 37-15. Receive Frame Format in Continuous Mode
Start = Enable Receiver
RD
Note:
638
Data
Data
To SSC_RHR
To SSC_RHR
DATLEN
DATLEN
1. STTDLY is set to 0.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.6.8
Loop Mode
The receiver can be programmed to receive transmissions from the transmitter. This is done by
setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is
connected to TF and RK is connected to TK.
37.6.9
Interrupt
Most bits in SSC_SR have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is
controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable and disable, respectively, the corresponding interrupt by setting
and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the
generation of interrupts by asserting the SSC interrupt line connected to the AIC.
Figure 37-16. Interrupt Block Diagram
SSC_IMR
SSC_IER
PDC
SSC_IDR
Set
Clear
TXBUFE
ENDTX
Transmitter
TXRDY
TXEMPTY
TXSYNC
Interrupt
Control
RXBUFF
ENDRX
SSC Interrupt
Receiver
RXRDY
OVRUN
RXSYNC
639
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.7
SSC Application Examples
The SSC can support several serial communication modes used in audio or high speed serial
links. Some standard applications are shown in the following figures. All serial link applications
supported by the SSC are not listed here.
Figure 37-17. Audio Application Block Diagram
Clock SCK
TK
Word Select WS
I2S
RECEIVER
TF
Data SD
SSC
TD
RD
Clock SCK
RF
Word Select WS
RK
MSB
Data SD
LSB
MSB
Right Channel
Left Channel
Figure 37-18. Codec Application Block Diagram
Serial Data Clock (SCLK)
TK
Frame sync (FSYNC)
TF
Serial Data Out
SSC
CODEC
TD
Serial Data In
RD
RF
RK
Serial Data Clock (SCLK)
Frame sync (FSYNC)
First Time Slot
Dstart
Dend
Serial Data Out
Serial Data In
640
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 37-19. Time Slot Application Block Diagram
SCLK
TK
FSYNC
TF
CODEC
First
Time Slot
Data Out
TD
SSC
RD
Data in
RF
RK
CODEC
Second
Time Slot
Serial Data Clock (SCLK)
Frame sync (FSYNC)
First Time Slot
Dstart
Second Time Slot
Dend
Serial Data Out
Serial Data in
641
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.8
Synchronous Serial Controller (SSC) User Interface
Table 37-6.
Register Mapping
Offset
Register
Name
Access
Reset
SSC_CR
Write-only
–
SSC_CMR
Read-write
0x0
0x0
Control Register
0x4
Clock Mode Register
0x8
Reserved
–
–
–
0xC
Reserved
–
–
–
0x10
Receive Clock Mode Register
SSC_RCMR
Read-write
0x0
0x14
Receive Frame Mode Register
SSC_RFMR
Read-write
0x0
0x18
Transmit Clock Mode Register
SSC_TCMR
Read-write
0x0
0x1C
Transmit Frame Mode Register
SSC_TFMR
Read-write
0x0
0x20
Receive Holding Register
SSC_RHR
Read-only
0x0
0x24
Transmit Holding Register
SSC_THR
Write-only
–
0x28
Reserved
–
–
–
0x2C
Reserved
–
–
–
0x30
Receive Sync. Holding Register
SSC_RSHR
Read-only
0x0
0x34
Transmit Sync. Holding Register
SSC_TSHR
Read-write
0x0
0x38
Receive Compare 0 Register
SSC_RC0R
Read-write
0x0
0x3C
Receive Compare 1 Register
SSC_RC1R
Read-write
0x0
0x40
Status Register
SSC_SR
Read-only
0x000000CC
0x44
Interrupt Enable Register
SSC_IER
Write-only
–
0x48
Interrupt Disable Register
SSC_IDR
Write-only
–
0x4C
Interrupt Mask Register
SSC_IMR
Read-only
0x0
Reserved
–
–
–
Reserved for Peripheral Data Controller (PDC)
–
–
–
0x50-0xFC
0x100- 0x124
642
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.8.1
Name:
SSC Control Register
SSC_CR
Addresses: 0xFFF98000 (0), 0xFFF9C000 (1)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
SWRST
14
–
13
–
12
–
11
–
10
–
9
TXDIS
8
TXEN
7
–
6
–
5
–
4
–
3
–
2
–
1
RXDIS
0
RXEN
• RXEN: Receive Enable
0 = No effect.
1 = Enables Receive if RXDIS is not set.
• RXDIS: Receive Disable
0 = No effect.
1 = Disables Receive. If a character is currently being received, disables at end of current character reception.
• TXEN: Transmit Enable
0 = No effect.
1 = Enables Transmit if TXDIS is not set.
• TXDIS: Transmit Disable
0 = No effect.
1 = Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission.
• SWRST: Software Reset
0 = No effect.
1 = Performs a software reset. Has priority on any other bit in SSC_CR.
643
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.8.2
Name:
SSC Clock Mode Register
SSC_CMR
Addresses: 0xFFF98004 (0), 0xFFF9C004 (1)
Access:
Read-write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
10
9
8
7
6
5
4
1
0
DIV
3
2
DIV
• DIV: Clock Divider
0 = The Clock Divider is not active.
Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The
minimum bit rate is MCK/2 x 4095 = MCK/8190.
644
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.8.3
Name:
SSC Receive Clock Mode Register
SSC_RCMR
Addresses: 0xFFF98010 (0), 0xFFF9C010 (1)
Access:
Read-write
31
30
29
28
27
26
25
24
19
18
17
16
10
9
8
PERIOD
23
22
21
20
STTDLY
15
–
7
14
–
13
–
12
STOP
11
6
5
CKI
4
3
CKO
CKG
START
2
1
0
CKS
• CKS: Receive Clock Selection
CKS
Selected Receive Clock
0x0
Divided Clock
0x1
TK Clock signal
0x2
RK pin
0x3
Reserved
• CKO: Receive Clock Output Mode Selection
CKO
Receive Clock Output Mode
0x0
None
0x1
Continuous Receive Clock
Output
0x2
Receive Clock only during data transfers
Output
0x3-0x7
RK pin
Input-only
Reserved
• CKI: Receive Clock Inversion
0 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal
output is shifted out on Receive Clock rising edge.
1 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out on Receive Clock falling edge.
CKI affects only the Receive Clock and not the output clock signal.
645
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• CKG: Receive Clock Gating Selection
CKG
Receive Clock Gating
0x0
None, continuous clock
0x1
Receive Clock enabled only if RF Low
0x2
Receive Clock enabled only if RF High
0x3
Reserved
• START: Receive Start Selection
START
Receive Start
0x0
Continuous, as soon as the receiver is enabled, and immediately after the end of
transfer of the previous data.
0x1
Transmit start
0x2
Detection of a low level on RF signal
0x3
Detection of a high level on RF signal
0x4
Detection of a falling edge on RF signal
0x5
Detection of a rising edge on RF signal
0x6
Detection of any level change on RF signal
0x7
Detection of any edge on RF signal
0x8
Compare 0
0x9-0xF
Reserved
• STOP: Receive Stop Selection
0 = After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a
new compare 0.
1 = After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
• STTDLY: Receive Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.
When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.
Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG
(Receive Sync Data) reception.
• PERIOD: Receive Period Divider Selection
This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no
PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.
646
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.8.4
Name:
SSC Receive Frame Mode Register
SSC_RFMR
Addresses: 0xFFF98014 (0), 0xFFF9C014 (1)
Access:
Read-write
31
FSLEN_EXT
30
FSLEN_EXT
29
FSLEN_EXT
23
–
22
15
–
7
MSBF
28
FSLEN_EXT
27
–
26
–
21
FSOS
20
19
18
14
–
13
–
12
–
11
6
–
5
LOOP
4
3
25
–
24
FSEDGE
17
16
9
8
1
0
FSLEN
10
DATNB
2
DATLEN
• DATLEN: Data Length
0 = Forbidden value (1-bit data length not supported).
Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the
PDC2 assigned to the Receiver. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and
15 (included), half-words are transferred, and for any other value, 32-bit words are transferred.
• LOOP: Loop Mode
0 = Normal operating mode.
1 = RD is driven by TD, RF is driven by TF and TK drives RK.
• MSBF: Most Significant Bit First
0 = The lowest significant bit of the data register is sampled first in the bit stream.
1 = The most significant bit of the data register is sampled first in the bit stream.
• DATNB: Data Number per Frame
This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).
• FSLEN: Receive Frame Sync Length
This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by
the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to
the Compare 0 or Compare 1 register.
This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal.
Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Receive Clock periods.
647
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• FSOS: Receive Frame Sync Output Selection
FSOS
Selected Receive Frame Sync Signal
RF Pin
0x0
None
0x1
Negative Pulse
Output
0x2
Positive Pulse
Output
0x3
Driven Low during data transfer
Output
0x4
Driven High during data transfer
Output
0x5
Toggling at each start of data transfer
Output
0x6-0x7
Input-only
Reserved
Undefined
• FSEDGE: Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
FSEDGE
Frame Sync Edge Detection
0x0
Positive Edge Detection
0x1
Negative Edge Detection
• FSLEN_EXT: FSLEN Field Extension
Extends FSLEN field. For details, refer to FSLEN bit description on page 647.
648
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.8.5
Name:
SSC Transmit Clock Mode Register
SSC_TCMR
Addresses: 0xFFF98018 (0), 0xFFF9C018 (1)
Access:
Read-write
31
30
29
28
27
26
25
24
19
18
17
16
10
9
8
PERIOD
23
22
21
20
STTDLY
15
–
7
14
–
13
–
12
–
11
6
5
CKI
4
3
CKO
CKG
START
2
1
0
CKS
• CKS: Transmit Clock Selection
CKS
Selected Transmit Clock
0x0
Divided Clock
0x1
RK Clock signal
0x2
TK Pin
0x3
Reserved
• CKO: Transmit Clock Output Mode Selection
CKO
Transmit Clock Output Mode
0x0
None
0x1
Continuous Transmit Clock
Output
0x2
Transmit Clock only during data transfers
Output
0x3-0x7
TK pin
Input-only
Reserved
• CKI: Transmit Clock Inversion
0 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal
input is sampled on Transmit clock rising edge.
1 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal
input is sampled on Transmit clock falling edge.
CKI affects only the Transmit Clock and not the output clock signal.
649
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• CKG: Transmit Clock Gating Selection
CKG
Transmit Clock Gating
0x0
None, continuous clock
0x1
Transmit Clock enabled only if TF Low
0x2
Transmit Clock enabled only if TF High
0x3
Reserved
• START: Transmit Start Selection
START
Transmit Start
0x0
Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and
immediately after the end of transfer of the previous data.
0x1
Receive start
0x2
Detection of a low level on TF signal
0x3
Detection of a high level on TF signal
0x4
Detection of a falling edge on TF signal
0x5
Detection of a rising edge on TF signal
0x6
Detection of any level change on TF signal
0x7
Detection of any edge on TF signal
0x8 - 0xF
Reserved
• STTDLY: Transmit Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission
of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied.
Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG.
• PERIOD: Transmit Period Divider Selection
This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period
signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock.
650
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.8.6
Name:
SSC Transmit Frame Mode Register
SSC_TFMR
Addresses: 0xFFF9801C (0), 0xFFF9C01C (1)
Access:
Read-write
31
FSLEN_EXT
30
FSLEN_EXT
29
FSLEN_EXT
23
FSDEN
22
15
–
7
MSBF
28
FSLEN_EXT
27
–
26
–
21
FSOS
20
19
18
14
–
13
–
12
–
11
6
–
5
DATDEF
4
3
25
–
24
FSEDGE
17
16
9
8
1
0
FSLEN
10
DATNB
2
DATLEN
• DATLEN: Data Length
0 = Forbidden value (1-bit data length not supported).
Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the
PDC2 assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15
(included), half-words are transferred, and for any other value, 32-bit words are transferred.
• DATDEF: Data Default Value
This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the
PIO Controller, the pin is enabled only if the SCC TD output is 1.
• MSBF: Most Significant Bit First
0 = The lowest significant bit of the data register is shifted out first in the bit stream.
1 = The most significant bit of the data register is shifted out first in the bit stream.
• DATNB: Data Number per frame
This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1).
• FSLEN: Transmit Frame Sync Length
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync
Data Register if FSDEN is 1.
This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal.
Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Transmit Clock period.
651
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• FSOS: Transmit Frame Sync Output Selection
FSOS
Selected Transmit Frame Sync Signal
TF Pin
0x0
None
0x1
Negative Pulse
Output
0x2
Positive Pulse
Output
0x3
Driven Low during data transfer
Output
0x4
Driven High during data transfer
Output
0x5
Toggling at each start of data transfer
Output
0x6-0x7
Reserved
Input-only
Undefined
• FSDEN: Frame Sync Data Enable
0 = The TD line is driven with the default value during the Transmit Frame Sync signal.
1 = SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
• FSEDGE: Frame Sync Edge Detection
Determines which edge on frame sync will generate the interrupt TXSYN (Status Register).
FSEDGE
Frame Sync Edge Detection
0x0
Positive Edge Detection
0x1
Negative Edge Detection
• FSLEN_EXT: FSLEN Field Extension
Extends FSLEN field. For details, refer to FSLEN bit description on page 651.
652
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.8.7
Name:
SSC Receive Holding Register
SSC_RHR
Addresses: 0xFFF98020 (0), 0xFFF9C020 (1)
Access:
Read-only
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
RDAT
23
22
21
20
RDAT
15
14
13
12
RDAT
7
6
5
4
RDAT
• RDAT: Receive Data
Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.
37.8.8
Name:
SSC Transmit Holding Register
SSC_THR
Addresses: 0xFFF98024 (0), 0xFFF9C024 (1)
Access:
Write-only
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
TDAT
23
22
21
20
TDAT
15
14
13
12
TDAT
7
6
5
4
TDAT
• TDAT: Transmit Data
Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.
653
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.8.9
Name:
SSC Receive Synchronization Holding Register
SSC_RSHR
Addresses: 0xFFF98030 (0), 0xFFF9C030 (1)
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
3
2
1
0
RSDAT
7
6
5
4
RSDAT
• RSDAT: Receive Synchronization Data
37.8.10
Name:
SSC Transmit Synchronization Holding Register
SSC_TSHR
Addresses: 0xFFF98034 (0), 0xFFF9C034 (1)
Access:
Read-write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
3
2
1
0
TSDAT
7
6
5
4
TSDAT
• TSDAT: Transmit Synchronization Data
654
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.8.11
Name:
SSC Receive Compare 0 Register
SSC_RC0R
Addresses: 0xFFF98038 (0), 0xFFF9C038 (1)
Access:
Read-write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
3
2
1
0
CP0
7
6
5
4
CP0
• CP0: Receive Compare Data 0
655
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.8.12
Name:
SSC Receive Compare 1 Register
SSC_RC1R
Addresses: 0xFFF9803C (0), 0xFFF9C03C (1)
Access:
Read-write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
3
2
1
0
CP1
7
6
5
4
CP1
• CP1: Receive Compare Data 1
656
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.8.13
Name:
SSC Status Register
SSC_SR
Addresses: 0xFFF98040 (0), 0xFFF9C040 (1)
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
RXEN
16
TXEN
15
–
14
–
13
–
12
–
11
RXSYN
10
TXSYN
9
CP1
8
CP0
7
RXBUFF
6
ENDRX
5
OVRUN
4
RXRDY
3
TXBUFE
2
ENDTX
1
TXEMPTY
0
TXRDY
• TXRDY: Transmit Ready
0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).
1 = SSC_THR is empty.
• TXEMPTY: Transmit Empty
0 = Data remains in SSC_THR or is currently transmitted from TSR.
1 = Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.
• ENDTX: End of Transmission
0 = The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.
1 = The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.
• TXBUFE: Transmit Buffer Empty
0 = SSC_TCR or SSC_TNCR have a value other than 0.
1 = Both SSC_TCR and SSC_TNCR have a value of 0.
• RXRDY: Receive Ready
0 = SSC_RHR is empty.
1 = Data has been received and loaded in SSC_RHR.
• OVRUN: Receive Overrun
0 = No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status
Register.
1 = Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status
Register.
• ENDRX: End of Reception
0 = Data is written on the Receive Counter Register or Receive Next Counter Register.
1 = End of PDC transfer when Receive Counter Register has arrived at zero.
657
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• RXBUFF: Receive Buffer Full
0 = SSC_RCR or SSC_RNCR have a value other than 0.
1 = Both SSC_RCR and SSC_RNCR have a value of 0.
• CP0: Compare 0
0 = A compare 0 has not occurred since the last read of the Status Register.
1 = A compare 0 has occurred since the last read of the Status Register.
• CP1: Compare 1
0 = A compare 1 has not occurred since the last read of the Status Register.
1 = A compare 1 has occurred since the last read of the Status Register.
• TXSYN: Transmit Sync
0 = A Tx Sync has not occurred since the last read of the Status Register.
1 = A Tx Sync has occurred since the last read of the Status Register.
• RXSYN: Receive Sync
0 = An Rx Sync has not occurred since the last read of the Status Register.
1 = An Rx Sync has occurred since the last read of the Status Register.
• TXEN: Transmit Enable
0 = Transmit is disabled.
1 = Transmit is enabled.
• RXEN: Receive Enable
0 = Receive is disabled.
1 = Receive is enabled.
658
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.8.14
Name:
SSC Interrupt Enable Register
SSC_IER
Addresses: 0xFFF98044 (0), 0xFFF9C044 (1)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
RXSYN
10
TXSYN
9
CP1
8
CP0
7
RXBUFF
6
ENDRX
5
OVRUN
4
RXRDY
3
TXBUFE
2
ENDTX
1
TXEMPTY
0
TXRDY
• TXRDY: Transmit Ready Interrupt Enable
0 = 0 = No effect.
1 = Enables the Transmit Ready Interrupt.
• TXEMPTY: Transmit Empty Interrupt Enable
0 = No effect.
1 = Enables the Transmit Empty Interrupt.
• ENDTX: End of Transmission Interrupt Enable
0 = No effect.
1 = Enables the End of Transmission Interrupt.
• TXBUFE: Transmit Buffer Empty Interrupt Enable
0 = No effect.
1 = Enables the Transmit Buffer Empty Interrupt
• RXRDY: Receive Ready Interrupt Enable
0 = No effect.
1 = Enables the Receive Ready Interrupt.
• OVRUN: Receive Overrun Interrupt Enable
0 = No effect.
1 = Enables the Receive Overrun Interrupt.
• ENDRX: End of Reception Interrupt Enable
0 = No effect.
1 = Enables the End of Reception Interrupt.
659
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• RXBUFF: Receive Buffer Full Interrupt Enable
0 = No effect.
1 = Enables the Receive Buffer Full Interrupt.
• CP0: Compare 0 Interrupt Enable
0 = No effect.
1 = Enables the Compare 0 Interrupt.
• CP1: Compare 1 Interrupt Enable
0 = No effect.
1 = Enables the Compare 1 Interrupt.
• TXSYN: Tx Sync Interrupt Enable
0 = No effect.
1 = Enables the Tx Sync Interrupt.
• RXSYN: Rx Sync Interrupt Enable
0 = No effect.
1 = Enables the Rx Sync Interrupt.
660
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.8.15
Name:
SSC Interrupt Disable Register
SSC_IDR
Addresses: 0xFFF98048 (0), 0xFFF9C048 (1)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
RXSYN
10
TXSYN
9
CP1
8
CP0
7
RXBUFF
6
ENDRX
5
OVRUN
4
RXRDY
3
TXBUFE
2
ENDTX
1
TXEMPTY
0
TXRDY
• TXRDY: Transmit Ready Interrupt Disable
0 = No effect.
1 = Disables the Transmit Ready Interrupt.
• TXEMPTY: Transmit Empty Interrupt Disable
0 = No effect.
1 = Disables the Transmit Empty Interrupt.
• ENDTX: End of Transmission Interrupt Disable
0 = No effect.
1 = Disables the End of Transmission Interrupt.
• TXBUFE: Transmit Buffer Empty Interrupt Disable
0 = No effect.
1 = Disables the Transmit Buffer Empty Interrupt.
• RXRDY: Receive Ready Interrupt Disable
0 = No effect.
1 = Disables the Receive Ready Interrupt.
• OVRUN: Receive Overrun Interrupt Disable
0 = No effect.
1 = Disables the Receive Overrun Interrupt.
• ENDRX: End of Reception Interrupt Disable
0 = No effect.
1 = Disables the End of Reception Interrupt.
661
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• RXBUFF: Receive Buffer Full Interrupt Disable
0 = No effect.
1 = Disables the Receive Buffer Full Interrupt.
• CP0: Compare 0 Interrupt Disable
0 = No effect.
1 = Disables the Compare 0 Interrupt.
• CP1: Compare 1 Interrupt Disable
0 = No effect.
1 = Disables the Compare 1 Interrupt.
• TXSYN: Tx Sync Interrupt Enable
0 = No effect.
1 = Disables the Tx Sync Interrupt.
• RXSYN: Rx Sync Interrupt Enable
0 = No effect.
1 = Disables the Rx Sync Interrupt.
662
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
37.8.16
Name:
SSC Interrupt Mask Register
SSC_IMR
Addresses: 0xFFF9804C (0), 0xFFF9C04C (1)
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
RXSYN
10
TXSYN
9
CP1
8
CP0
7
RXBUFF
6
ENDRX
5
OVRUN
4
RXRDY
3
TXBUFE
2
ENDTX
1
TXEMPTY
0
TXRDY
• TXRDY: Transmit Ready Interrupt Mask
0 = The Transmit Ready Interrupt is disabled.
1 = The Transmit Ready Interrupt is enabled.
• TXEMPTY: Transmit Empty Interrupt Mask
0 = The Transmit Empty Interrupt is disabled.
1 = The Transmit Empty Interrupt is enabled.
• ENDTX: End of Transmission Interrupt Mask
0 = The End of Transmission Interrupt is disabled.
1 = The End of Transmission Interrupt is enabled.
• TXBUFE: Transmit Buffer Empty Interrupt Mask
0 = The Transmit Buffer Empty Interrupt is disabled.
1 = The Transmit Buffer Empty Interrupt is enabled.
• RXRDY: Receive Ready Interrupt Mask
0 = The Receive Ready Interrupt is disabled.
1 = The Receive Ready Interrupt is enabled.
• OVRUN: Receive Overrun Interrupt Mask
0 = The Receive Overrun Interrupt is disabled.
1 = The Receive Overrun Interrupt is enabled.
• ENDRX: End of Reception Interrupt Mask
0 = The End of Reception Interrupt is disabled.
1 = The End of Reception Interrupt is enabled.
663
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
• RXBUFF: Receive Buffer Full Interrupt Mask
0 = The Receive Buffer Full Interrupt is disabled.
1 = The Receive Buffer Full Interrupt is enabled.
• CP0: Compare 0 Interrupt Mask
0 = The Compare 0 Interrupt is disabled.
1 = The Compare 0 Interrupt is enabled.
• CP1: Compare 1 Interrupt Mask
0 = The Compare 1 Interrupt is disabled.
1 = The Compare 1 Interrupt is enabled.
• TXSYN: Tx Sync Interrupt Mask
0 = The Tx Sync Interrupt is disabled.
1 = The Tx Sync Interrupt is enabled.
• RXSYN: Rx Sync Interrupt Mask
0 = The Rx Sync Interrupt is disabled.
1 = The Rx Sync Interrupt is enabled.
664
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
38. AC97 Controller (AC97C)
38.1
Overview
The AC97 Controller is the hardware implementation of the AC97 digital controller (DC’97) compliant with AC97 Component Specification 2.2. The AC97 Controller communicates with an
audio codec (AC97) or a modem codec (MC’97) via the AC-link digital serial interface. All digital
audio, modem and handset data streams, as well as control (command/status) informations are
transferred in accordance to the AC-link protocol.
The AC97 Controller features a Peripheral DMA Controller (PDC) for audio streaming transfers.
It also supports variable sampling rate and four Pulse Code Modulation (PCM) sample resolutions of 10, 16, 18 and 20 bits.
38.2
Block Diagram
Figure 38-1. Functional Block Diagram
MCK Clock Domain
Slot Number
SYNC
AC97 Slot Controller
Slot Number
16/20 bits
Slot #0
Transmit Shift Register
M
AC97 Tag Controller
SDATA_OUT
Receive Shift Register
Slot #0,1
U
AC97 CODEC Channel
AC97C_COTHR
AC97C_CORHR
AC97C Interrupt
X
Slot #1,2
Transmit Shift Register
SDATA_IN
Slot #2
Receive Shift Register
E
AC97 Channel A
AC97C_CATHR
MCK
AC97C_CARHR
D
Transmit Shift Register
M
Receive Shift Register
U
Slot #3...12
BITCLK
X
User Interface
Bit Clock Domain
APB Interface
665
6264C–CAP–24-Mar-09
38.3
Pin Name List
Table 38-1.
I/O Lines Description
Pin Name
Pin Description
Type
AC97CK
12.288-MHz bit-rate clock
Input
AC97RX
Receiver Data (Referred as SDATA_IN in AC-link spec)
Input
AC97FS
48-KHz frame indicator and synchronizer
Output
AC97TX
Transmitter Data (Referred as SDATA_OUT in AC-link spec)
Output
The AC97 reset signal provided to the primary codec can be generated by a PIO.
38.4
Application Block Diagram
Figure 38-2. Application Block diagram
AC-link
AC 97 Controller
PIOx
AC'97 Primary Codec
AC97_RESET
AC97_SYNC
AC97FS
AC97_BITCLK
AC97CK
AC97TX
AC97_SDATA_OUT
AC97_SDATA_IN
AC97RX
666
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.5
38.5.1
Product Dependencies
I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
Before using the AC97 Controller receiver, the PIO controller must be configured in order for the
AC97C receiver I/O lines to be in AC97 Controller peripheral mode.
Before using the AC97 Controller transmitter, the PIO controller must be configured in order for
the AC97C transmitter I/O lines to be in AC97 Controller peripheral mode.
Table 38-2.
38.5.2
I/O Lines
Instance
Signal
I/O Line
Peripheral
AC97C
AC97CK
PA7
A
AC97C
AC97FS
PA6
A
AC97C
AC97RX
PA9
A
AC97C
AC97TX
PA8
A
Power Management
The AC97 Controller is not continuously clocked. Its interface may be clocked through the Power
Management Controller (PMC), therefore the programmer must first configure the PMC to
enable the AC97 Controller clock.
The AC97 Controller has two clock domains. The first one is supplied by PMC and is equal to
MCK. The second one is AC97CK which is sent by the AC97 Codec (Bit clock).
Signals that cross the two clock domains are re-synchronized. MCK clock frequency must be
higher than the AC97CK (Bit Clock) clock frequency.
38.5.3
Interrupt
The AC97 Controller interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AIC before configuring the AC97C.
All AC97 Controller interrupts can be enabled/disabled by writing to the AC97 Controller Interrupt Enable/Disable Registers. Each pending and unmasked AC97 Controller interrupt will
assert the interrupt line. The AC97 Controller interrupt service routine can get the interrupt
source in two steps:
• Reading and ANDing AC97 Controller Interrupt Mask Register (AC97C_IMR) and AC97
Controller Status Register (AC97C_SR).
• Reading AC97 Controller Channel x Status Register (AC97C_CxSR).
Table 38-3.
667
Peripheral IDs
Instance
ID
AC97C
19
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.6
Functional Description
38.6.1
Protocol overview
AC-link protocol is a bidirectional, fixed clock rate, serial digital stream. AC-link handles multiple
input and output Pulse Code Modulation PCM audio streams, as well as control register
accesses employing a Time Division Multiplexed (TDM) scheme that divides each audio frame
in 12 outgoing and 12 incoming 20-bit wide data slots.
Figure 38-3. Bidirectional AC-link Frame with Slot Assignment
Slot #
0
1
2
3
4
5
6
7
8
9
10
11
12
PCM
L SURR
PCM
R SURR
PCM
LFE
LINE 2
DAC
HSET
DAC
IO
CTRL
RSVED
RSVED
LINE 2
ADC
HSET
ADC
IO
STATUS
AC97FS
AC97TX
(Controller Output)
TAG
CMD
ADDR
CMD
DATA
PCM
L Front
PCM
R Front
LINE 1
DAC
PCM
Center
AC97RX
(Codec output)
TAG
STATUS
ADDR
STATUS
DATA
PCM
LEFT
PCM
RIGHT
LINE 1
DAC
PCM
MIC
Table 38-4.
AC-link Output Slots Transmitted from the AC97C Controller
Slot #
Pin Description
0
TAG
1
Command Address Port
2
Command Data Port
3,4
PCM playback Left/Right Channel
5
Modem Line 1 Output Channel
6, 7, 8
PCM Center/Left Surround/Right Surround
9
PCM LFE DAC
10
Modem Line 2 Output Channel
11
Modem Handset Output Channel
12
Modem GPIO Control Channel
Table 38-5.
668
RSVED
AC-link Input Slots Transmitted from the AC97C Controller
Slot #
Pin Description
0
TAG
1
Status Address Port
2
Status Data Port
3,4
PCM playback Left/Right Channel
5
Modem Line 1 ADC
6
Dedicated Microphone ADC
7, 8, 9
Vendor Reserved
10
Modem Line 2 ADC
11
Modem Handset Input ADC
12
Modem IO Status
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.6.1.1
Slot Description
38.6.1.2
Tag Slot
The tag slot, or slot 0, is a 16-bit wide slot that always goes at the beginning of an outgoing or
incoming frame. Within tag slot, the first bit is a global bit that flags the entire frame validity. The
next 12 bit positions sampled by the AC97 Controller indicate which of the corresponding 12
time slots contain valid data. The slot’s last two bits (combined) called Codec ID, are used to distinguish primary and secondary codec.
The 16-bit wide tag slot of the output frame is automatically generated by the AC97 Controller
according to the transmit request of each channel and to the SLOTREQ from the previous input
frame, sent by the AC97 Codec, in Variable Sample Rate mode.
38.6.1.3
Codec Slot 1
The command/status slot is a 20-bit wide slot used to control features, and monitors status for
AC97 Codec functions.
The control interface architecture supports up to sixty-four 16-bit wide read-write registers. Only
the even registers are currently defined and addressed.
Slot 1’s bitmap is the following:
• Bit 19 is for read-write command, 1= read, 0 = write.
• Bits [18:12] are for control register index.
• Bits [11:0] are reserved.
38.6.1.4
Codec Slot 2
Slot 2 is a 20-bit wide slot used to carry 16-bit wide AC97 Codec control register data. If the current command port operation is a read, the entire slot time is stuffed with zeros. Its bitmap is the
following:
• Bits [19:4] are the control register data
• Bits [3:0] are reserved and stuffed with zeros.
38.6.1.5
669
Data Slots [3:12]
Slots [3:12] are 20-bit wide data slots, they usually carry audio PCM or/and modem I/O data.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.6.2
AC97 Controller Channel Organization
The AC97 Controller features a Codec channel and 2 logical channels: Channel A.
The Codec channel controls AC97 Codec registers, it enables write and read configuration values in order to bring the AC97 Codec to an operating state. The Codec channel always runs slot
1 and slot 2 exclusively, in both input and output directions.
Channel A transfer data to/from AC97 codec. All audio samples and modem data must transit by
these 2 channels. However, Channel A is connected to PDC channels thus making it suitable
for audio streaming applications.
Each slot of the input or the output frame that belongs to this range [3 to 12] can be operated by
Channel A. The slot to channel assignment is configured by two registers:
• AC97 Controller Input Channel Assignment Register (AC97C_ICA)
• AC97 Controller Output Channel Assignment Register (AC97C_OCA)
The AC97 Controller Input Channel Assignment Register (AC97C_ICA) configures the input slot
to channel assignment. The AC97 Controller Output Channel Assignment Register
(AC97C_OCA) configures the output slot to channel assignment.
A slot can be left unassigned to a channel by the AC97 Controller. Slots 0, 1,and 2 cannot be
assigned to Channel A through the AC97C_OCA and AC97C_ICA Registers.
The width of sample data, that transit via the Channel varies and can take one of these values;
10, 16, 18 or 20 bits.
Figure 38-4. Logical Channel Assignment
Slot #
0
1
2
3
4
5
6
7
PCM
L Front
PCM
R Front
LINE 1
DAC
PCM
Center
PCM
L SURR
LINE 1
DAC
PCM
MIC
RSVED
8
9
10
11
12
PCM
R SURR
PCM
LFE
LINE 2
DAC
HSET
DAC
IO
CTRL
RSVED
RSVED
LINE 2
ADC
HSET
ADC
IO
STATUS
AC97FS
AC97TX
(Controller Output)
TAG
CMD
ADDR
CMD
DATA
Codec Channel
Channel A
AC97C_OCA = 0x0000_0209
AC97RX
(Codec output)
TAG
STATUS
ADDR
STATUS
DATA
Codec Channel
PCM
LEFT
PCM
RIGHT
Channel A
AC97C_ICA = 0x0000_0009
670
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.6.2.1
AC97 Controller Setup
The following operations must be performed in order to bring the AC97 Controller into an operating state:
1. Enable the AC97 Controller clock in the PMC controller.
2. Turn on AC97 function by enabling the ENA bit in AC97 Controller Mode Register
(AC97C_MR).
3. Configure the input channel assignment by controlling the AC97 Controller Input
Assignment Register (AC97C_ICA).
4. Configure the output channel assignment by controlling the AC97 Controller Input
Assignment Register (AC97C_OCA).
5. Configure sample width for Channel A by writing the SIZE bit field in AC97C Channel x
Mode Register (AC97C_CAMR). The application can write 10, 16, 18,or 20-bit wide
PCM samples through the AC97 interface and they will be transferred into 20-bit wide
slots.
6. Configure data Endianness for Channel A by writing CEM bit field in (AC97C_CAMR)
register. Data on the AC-link are shifted MSB first. The application can write little- or
big-endian data to the AC97 Controller interface.
7. Configure the PIO controller to drive the RESET signal of the external Codec. The
RESET signal must fulfill external AC97 Codec timing requirements.
8. Enable Channel A by writing CEN bit field in AC97C_CxMR register.
38.6.2.2
Transmit Operation
The application must perform the following steps in order to send data via a channel to the AC97
Codec:
• Check if previous data has been sent by polling TXRDY flag in the AC97C Channel x Status
Register (AC97_CxSR). x being one of the 2 channels.
• Write data to the AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR).
Once data has been transferred to the Channel x Shift Register, the TXRDY flag is automatically
set by the AC97 Controller which allows the application to start a new write action. The application can also wait for an interrupt notice associated with TXRDY in order to send data. The
interrupt remains active until TXRDY flag is cleared.
671
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 38-5. Audio Transfer (PCM L Front, PCM R Front) on Channel x
Slot #
0
1
2
CMD
ADDR
CMD
DATA
3
4
5
6
7
8
9
10
11
12
AC97FS
AC97TX
(Controller Output)
TAG
PCM
L Front
PCM
R Front
LINE 1
DAC
PCM
Center
PCM
L SURR
PCM
R SURR
PCM
LFE
LINE 2
DAC
HSET
DAC
IO
CTRL
TXRDYCx
(AC97C_SR)
TXEMPTY
(AC97C_SR)
Write access to
AC97C_THRx
PCM L Front
transfered to the shift register
PCM R Front
transfered to the shift register
The TXEMPTY flag in the AC97 Controller Channel x Status Register (AC97C_CxSR) is set
when all requested transmissions for a channel have been shifted on the AC-link. The application can either poll TXEMPTY flag in AC97C_CxSR or wait for an interrupt notice associated
with the same flag.
In most cases, the AC97 Controller is embedded in chips that target audio player devices. In
such cases, the AC97 Controller is exposed to heavy audio transfers. Using the polling technique increases processor overhead and may fail to keep the required pace under an operating
system. In order to avoid these polling drawbacks, the application can perform audio streams by
using PDC connected to channel A, which reduces processor overhead and increases performance especially under an operating system.
The PDC transmit counter values must be equal to the number of PCM samples to be transmitted, each sample goes in one slot.
38.6.2.3
AC97 Output Frame
The AC97 Controller outputs a thirteen-slot frame on the AC-Link. The first slot (tag slot or slot 0)
flags the validity of the entire frame and the validity of each slot; whether a slot carries valid data
or not. Slots 1 and 2 are used if the application performs control and status monitoring actions
on AC97 Codec control/status registers. Slots [3:12] are used according to the content of the
AC97 Controller Output Channel Assignment Register (AC97C_OCA). If the application performs many transmit requests on a channel, some of the slots associated to this channel or all of
them will carry valid data.
38.6.2.4
Receive Operation
The AC97 Controller can also receive data from AC97 Codec. Data is received in the channel’s
shift register and then transferred to the AC97 Controller Channel x Read Holding Register. To
read the newly received data, the application must perform the following steps:
• Poll RXRDY flag in AC97 Controller Channel x Status Register (AC97C_CxSR). x being one
of the 2 channels.
• Read data from AC97 Controller Channel x Read Holding Register.
672
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
The application can also wait for an interrupt notice in order to read data from AC97C_CxRHR.
The interrupt remains active until RXRDY is cleared by reading AC97C_CxSR.
The RXRDY flag in AC97C_CxSR is set automatically when data is received in the Channel x
shift register. Data is then shifted to AC97C_CxRHR.
Figure 38-6. Audio Transfer (PCM L Front, PCM R Front) on Channel x
Slot #
0
1
2
TAG
STATUS
ADDR
STATUS
DATA
3
4
5
6
7
8
9
RSVED
RSVED
10
11
12
AC97FS
AC97RX
(Codec output)
PCM
LEFT
PCM
RIGHT
LINE 1
DAC
PCM
MIC
RSVED
LINE 2
ADC
HSET
ADC
IO
STATUS
RXRDYCx
(AC97C_SR)
Read access to
AC97C_RHRx
If the previously received data has not been read by the application, the new data overwrites the
data already waiting in AC97C_CxRHR, therefore the OVRUN flag in AC97C_CxSR is raised.
The application can either poll the OVRUN flag in AC97C_CxSR or wait for an interrupt notice.
The interrupt remains active until the OVRUN flag in AC97C_CxSR is set.
The AC97 Controller can also be used in sound recording devices in association with an AC97
Codec. The AC97 Controller may also be exposed to heavy PCM transfers. The application can
use the PDC connected to channel A in order to reduce processor overhead and increase performance especially under an operating system.
The PDC receive counter values must be equal to the number of PCM samples to be received,
each sample goes in one slot.
38.6.2.5
AC97 Input Frame
The AC97 Controller receives a thirteen slot frame on the AC-Link sent by the AC97 Codec. The
first slot (tag slot or slot 0) flags the validity of the entire frame and the validity of each slot;
whether a slot carries valid data or not. Slots 1 and 2 are used if the application requires status
informations from AC97 Codec. Slots [3:12] are used according to AC97 Controller Output
Channel Assignment Register (AC97C_ICA) content. The AC97 Controller will not receive any
data from any slot if AC97C_ICA is not assigned to a channel in input.
38.6.2.6
Configuring and Using Interrupts
Instead of polling flags in AC97 Controller Global Status Register (AC97C_SR) and in AC97
Controller Channel x Status Register (AC97C_CxSR), the application can wait for an interrupt
notice. The following steps show how to configure and use interrupts correctly:
• Set the interruptible flag in AC97 Controller Channel x Mode Register (AC97C_CxMR).
• Set the interruptible event and channel event in AC97 Controller Interrupt Enable Register
(AC97C_IER).
The interrupt handler must read both AC97 Controller Global Status Register (AC97C_SR) and
AC97 Controller Interrupt Mask Register (AC97C_IMR) and AND them to get the real interrupt
source. Furthermore, to get which event was activated, the interrupt handler has to read AC97
Controller Channel x Status Register (AC97C_CxSR), x being the channel whose event triggers
the interrupt.
673
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
The application can disable event interrupts by writing in AC97 Controller Interrupt Disable Register (AC97C_IDR). The AC97 Controller Interrupt Mask Register (AC97C_IMR) shows which
event can trigger an interrupt and which one cannot.
38.6.2.7
Endianness
Endianness can be managed automatically for each channel, except for the Codec channel, by
writing to Channel Endianness Mode (CEM) in AC97C_CxMR. This enables transferring data on
AC-link in Big Endian format without any additional operation.
38.6.2.8
To Transmit a Word Stored in Big Endian Format on AC-link
Word to be written in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR)
(as it is stored in memory or microprocessor register).
31
24
23
16
Byte0[7:0]
15
Byte1[7:0]
8
7
0
Byte2[7:0]
Byte3[7:0]
Word stored in Channel x Transmit Holding Register (AC97C_CxTHR) (data to transmit).
31
24
23
–
20
19
16
Byte2[3:0]
–
15
8
7
0
Byte1[7:0]
Byte0[7:0]
Data transmitted on appropriate slot: data[19:0] = {Byte2[3:0], Byte1[7:0], Byte0[7:0]}.
38.6.2.9
To Transmit A Halfword Stored in Big Indian Format on AC-link
Halfw ord to be written in AC97 Controlle r Channel x Transmit Holding Register
(AC97C_CxTHR).
31
24
23
–
16
15
–
8
7
0
Byte0[7:0]
Byte1[7:0]
Halfword stored in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR) (data
to transmit).
31
24
23
–
16
15
–
8
7
0
Byte1[7:0]
Byte0[7:0]
Data emitted on related slot: data[19:0] = {0x0, Byte1[7:0], Byte0[7:0]}.
38.6.2.10
To Transmit a10-bit Sample Stored in Big Endian Format on AC-link
Halfw ord to be written in AC97 Controlle r Channel x Transmit Holding Register
(AC97C_CxTHR).
31
24
23
–
16
15
–
8
7
Byte0[7:0]
0
{0x00, Byte1[1:0]}
Halfword stored in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR) (data
to transmit).
31
24
–
23
16
–
15
10
–
9
8
Byte1
[1:0]
7
0
Byte0[7:0]
Data emitted on related slot: data[19:0] = {0x000, Byte1[1:0], Byte0[7:0]}.
674
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.6.2.11
To Receive Word transfers
Data received on appropriate slot: data[19:0] = {Byte2[3:0], Byte1[7:0], Byte0[7:0]}.
Word stored in AC97 Controller Channel x Receive Holding Register (AC97C_CxRHR)
(Received Data).
31
24
23
–
20
19
16
Byte2[3:0]
–
15
8
7
Byte1[7:0]
0
Byte0[7:0]
Data is read from AC97 Controller Channel x Receive Holding Register (AC97C_CxRHR) when
Channel x data size is greater than 16 bits and when big-endian mode is enabled (data written to
memory).
31
24
23
Byte0[7:0]
38.6.2.12
16
15
Byte1[7:0]
8
7
0
{0x0, Byte2[3:0]}
0x00
To Receive Halfword Transfers
Data received on appropriate slot: data[19:0] = {0x0, Byte1[7:0], Byte0[7:0]}.
Halfword stored in AC97 Controller Channel x Receive Holding Register (AC97C_CxRHR)
(Received Data).
31
24
23
–
16
15
–
8
7
Byte1[7:0]
0
Byte0[7:0]
Data is read from AC97 Controller Channel x Receive Holding Register (AC97C_CxRHR) when
data size is equal to 16 bits and when big-endian mode is enabled.
31
24
23
–
38.6.2.13
16
15
–
8
7
Byte0[7:0]
0
Byte1[7:0]
To Receive 10-bit Samples
Data received on appropriate slot: data[19:0] = {0x000, Byte1[1:0], Byte0[7:0]}.Halfword stored
in AC97 Controller Channel x Receive Holding Register (AC97C_CxRHR) (Received Data)
31
24
23
–
16
–
15
10
–
9
8
Byte1
[1:0]
7
0
Byte0[7:0]
Data read from AC97 Controller Channel x Receive Holding Register (AC97C_CxRHR) when
data size is equal to 10 bits and when big-endian mode is enabled.
31
24
–
38.6.3
675
23
16
–
15
Byte0[7:0]
8
7
3
0x00
1
0
Byte1
[1:0]
Variable Sample Rate
The problem of variable sample rate can be summarized by a simple example. When passing a
44.1 kHz stream across the AC-link, for every 480 audio output frames that are sent across, 441
of them must contain valid sample data. The new AC97 standard approach calls for the addition
of “on-demand” slot request flags. The AC97 Codec examines its sample rate control register,
the state of its FIFOs, and the incoming SDATA_OUT tag bits (slot 0) of each output frame and
then determines which SLOTREQ bits to set active (low). These bits are passed from the AC97
Codec to the AC97 Controller in slot 1/SLOTREQ in every audio input frame. Each time the
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AC97 controller sees one or more of the newly defined slot request flags set active (low) in a
given audio input frame, it must pass along the next PCM sample for the corresponding slot(s) in
the AC-link output frame that immediately follows.
The variable Sample Rate mode is enabled by performing the following steps:
• Setting the VRA bit in the AC97 Controller Mode Register (AC97C_MR).
• Enable Variable Rate mode in the AC97 Codec by performing a transfer on the Codec
channel.
Slot 1 of the input frame is automatically interpreted as SLOTREQ signaling bits. The AC97 Controller will automatically fill the active slots according to both SLOTREQ and AC97C_OCA
register in the next transmitted frame.
38.6.4
38.6.4.1
Power Management
Powering Down the AC-Link
The AC97 Codecs can be placed in low power mode. The application can bring AC97 Codec to
a power down state by performing sequential writes to AC97 Codec powerdown register. Both
the bit clock (clock delivered by AC97 Codec, AC97CK) and the input line (AC97RX) are held at
a logic low voltage level. This puts AC97 Codec in power down state while all its registers are
still holding current values. Without the bit clock, the AC-link is completely in a power down
state.
The AC97 Controller should not attempt to play or capture audio data until it has awakened
AC97 Codec.
To set the AC97 Codec in low power mode, the PR4 bit in the AC97 Codec powerdown register
(Codec address 0x26) must be set to 1. Then the primary Codec drives both AC97CK and
AC97RX to a low logic voltage level.
The following operations must be done to put AC97 Codec in low power mode:
• Disable Channel A clearing CEN field in the AC97C_CAMR register.
• Write 0x2680 value in the AC97C_COTHR register.
• Poll the TXEMPTY flag in AC97C_CxSR registers for the 2 channels.
At this point AC97 Codec is in low power mode.
38.6.4.2
Waking up the AC-link
There are two methods to bring the AC-link out of low power mode. Regardless of the method, it
is always the AC97 Controller that performs the wake-up.
38.6.4.3
Wake-up Triggered by the AC97 Controller
The AC97 Controller can wake up the AC97 Codec by issuing either a cold or a warm reset.
The AC97 Controller can also wake up the AC97 Codec by asserting AC97FS signal, however
this action should not be performed for a minimum period of four audio frames following the
frame in which the powerdown was issued.
38.6.4.4
676
Wake-up Triggered by the AC97 Codec
This feature is implemented in AC97 modem codecs that need to report events such as CallerID and wake-up on ring.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
The AC97 Codec can drive AC97RX signal from low to high level and holding it high until the
controller issues either a cold or a worm reset. The AC97RX rising edge is asynchronously
(regarding AC97FS) detected by the AC97 Controller. If WKUP bit is enabled in AC97C_IMR
register, an interrupt is triggered that wakes up the AC97 Controller which should then immediately issue a cold or a warm reset.
If the processor needs to be awakened by an external event, the AC97RX signal must be externally connected to the WAKEUP entry of the system controller.
Figure 38-7. AC97 Power-Down/Up Sequence
Wake Event
Power Down Frame
Sleep State
Warm Reset
New Audio Frame
AC97CK
AC97FS
AC97TX
TAG
Write to
0x26
Data
PR4
TAG
Slot1
Slot2
AC97RX
TAG
Write to
0x26
Data
PR4
TAG
Slot1
Slot2
38.6.4.5
AC97 Codec Reset
There are three ways to reset an AC97 Codec.
38.6.4.6
Cold AC97 Reset
A cold reset is generated by asserting the RESET signal low for the minimum specified time
(depending on the AC97 Codec) and then by de-asserting RESET high. AC97CK and AC97FS
is reactivated and all AC97 Codec registers are set to their default power-on values. Transfers
on AC-link can resume.
The RESET signal will be controlled via a PIO line. This is how an application should perform a
cold reset:
• Clear and set ENA flag in the AC97C_MR register to reset the AC97 Controller
• Clear PIO line output controlling the AC97 RESET signal
• Wait for the minimum specified time
• Set PIO line output controlling the AC97 RESET signal
AC97CK, the clock provided by AC97 Codec, is detected by the controller.
38.6.4.7
Warm AC97 Reset
A warm reset reactivates the AC-link without altering AC97 Codec registers. A warm reset is signaled by driving AC97FX signal high for a minimum of 1us in the absence of AC97CK. In the
absence of AC97CK, AC97FX is treated as an asynchronous (regarding AC97FX) input used to
signal a warm reset to AC97 Codec.
This is the right way to perform a warm reset:
• Set WRST in the AC97C_MR register.
• Wait for at least 1us
• Clear WRST in the AC97C_MR register.
677
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
The application can check that operations have resumed by checking SOF flag in the
AC97C_SR register or wait for an interrupt notice if SOF is enabled in AC97C_IMR.
678
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.7
AC97 Controller (AC97C) User Interface
Table 38-6.
Register Mapping
Offset
Register
Name
Access
Reset
0x0-0x4
Reserved
–
–
–
AC97C_MR
Read-write
0x0
–
–
–
0x8
Mode Register
0xC
Reserved
0x10
Input Channel Assignment Register
AC97C_ICA
Read-write
0x0
0x14
Output Channel Assignment Register
AC97C_OCA
Read-write
0x0
–
–
–
0x18-0x1C
0x20
Channel A Receive Holding Register
AC97C_CARHR
Read
0x0
0x24
Channel A Transmit Holding Register
AC97C_CATHR
Write
–
0x28
Channel A Status Register
AC97C_CASR
Read
0x0
0x2C
Channel A Mode Register
AC97C_CAMR
Read-write
0x0
0x40
Codec Channel Receive Holding Register
AC97C_CORHR
Read
0x0
0x44
Codec Channel Transmit Holding Register
AC97C_COTHR
Write
–
0x48
Codec Status Register
AC97C_COSR
Read
0x0
0x4C
Codec Mode Register
AC97C_COMR
Read-write
0x0
0x50
Status Register
AC97C_SR
Read
0x0
0x54
Interrupt Enable Register
AC97C_IER
Write
–
0x58
Interrupt Disable Register
AC97C_IDR
Write
–
0x5C
Interrupt Mask Register
AC97C_IMR
Read
0x0
Reserved
–
–
–
Reserved for Peripheral DMA Controller (PDC)
registers related to channel transfers
–
–
–
0x60-0xFB
0x100-0x124
679
Reserved
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.7.1
Name:
AC97 Controller Mode Register
AC97C_MR
Address:
0xFFFA0008
Access:
Read-Write
31
–
23
–
15
–
7
–
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
VRA
25
–
17
–
9
–
1
WRST
24
–
16
–
8
–
0
ENA
• VRA: Variable Rate (for Data Slots 3-12)
0: Variable Rate is inactive. (48 KHz only)
1: Variable Rate is active.
• WRST: Warm Reset
0: Warm Reset is inactive.
1: Warm Reset is active.
• ENA: AC97 Controller Global Enable
0: No effect. AC97 function as well as access to other AC97 Controller registers are disabled.
1: Activates the AC97 function.
680
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.7.2
Name:
AC97 Controller Input Channel Assignment Register
AC97C_ICA
Address:
0xFFFA0010
Access:
Read-write
31
–
23
30
–
22
CHID10
14
15
CHID8
7
6
29
21
13
CHID7
5
CHID5
• CHIDx: Channel ID
CHIDx
681
28
CHID12
20
12
4
CHID4
27
26
19
CHID9
11
18
3
25
CHID11
17
24
16
CHID8
10
CHID6
2
9
1
CHID3
8
CHID5
0
for the input slot x
Selected Receive Channel
0x0
None. No data will be received during this slot time
0x1
Channel A data will be received during this slot time.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.7.3
Name:
AC97 Controller Output Channel Assignment Register
AC97C_OCA
Address:
0xFFFA0014
Access:
Read-write
31
–
23
30
–
22
CHID10
14
15
CHID8
7
6
29
21
13
CHID7
5
CHID5
• CHIDx: Channel ID
CHIDx
682
28
CHID12
20
12
4
CHID4
27
26
19
CHID9
11
18
3
25
CHID11
17
24
16
CHID8
10
CHID6
2
9
1
CHID3
8
CHID5
0
for the output slot x
Selected Transmit Channel
0x0
None. No data will be transmitted during this slot time
0x1
Channel A data will be transferred during this slot time.
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.7.4
Name:
AC97 Controller Codec Channel Receive Holding Register
AC97C_CORHR
Address:
0xFFFA0040
Access:
Read-only
31
–
23
–
15
30
–
22
–
14
29
–
21
–
13
28
–
20
–
12
7
6
5
4
27
–
19
–
11
26
–
18
–
10
25
–
17
–
9
24
–
16
–
8
3
2
1
0
SDATA
SDATA
• SDATA: Status Data
Data sent by the CODEC in the third AC97 input frame slot (Slot 2).
683
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.7.5
Name:
AC97 Controller Codec Channel Transmit Holding Register
AC97C_COTHR
Address:
0xFFFA0044
Access:
Write-only
31
–
23
READ
15
30
–
22
29
–
21
28
–
20
14
13
12
7
6
5
4
27
–
19
CADDR
11
26
–
18
25
–
17
24
–
16
10
9
8
3
2
1
0
CDATA
CDATA
• READ: Read-write command
0: Write operation to the CODEC register indexed by the CADDR address.
1: Read operation to the CODEC register indexed by the CADDR address.
This flag is sent during the second AC97 frame slot
• CADDR: CODEC control register index
Data sent to the CODEC in the second AC97 frame slot.
• CDATA: Command Data
Data sent to the CODEC in the third AC97 frame slot (Slot 2).
684
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.7.6
Name:
AC97 Controller Channel A, Receive Holding Register
AC97C_CARHR
Address:
0xFFFA0020
Access:
Read-only
31
–
23
–
15
30
–
22
–
14
29
–
21
–
13
28
–
20
–
12
7
6
5
4
27
–
19
26
–
18
25
–
17
24
–
16
11
10
9
8
3
2
1
0
RDATA
RDATA
RDATA
• RDATA: Receive Data
Received Data on channel x.
685
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.7.7
Name:
AC97 Controller Channel A, Transmit Holding Register
AC97C_CATHR
Address:
0xFFFA0024
Access:
Write-only
31
–
23
–
15
30
–
22
–
14
29
–
21
–
13
28
–
20
–
12
7
6
5
4
27
–
19
26
–
18
25
–
17
24
–
16
11
10
9
8
3
2
1
0
TDATA
TDATA
TDATA
• TDATA: Transmit Data
Data to be sent on channel x.
686
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.7.8
Name:
AC97 Controller Channel A Status Register
AC97C_CASR
Address:
0xFFFA0028
Access:
Read-only
31
–
23
–
15
RXBUFF
7
–
30
–
22
–
14
ENDRX
6
–
29
–
21
–
13
–
5
OVRUN
28
–
20
–
12
–
4
RXRDY
27
–
19
–
11
TXBUFE
3
–
26
–
18
–
10
ENDTX
2
UNRUN
25
–
17
–
9
–
1
TXEMPTY
24
–
16
–
8
–
0
TXRDY
• TXRDY: Channel Transmit Ready
0: Data has been loaded in Channel Transmit Register and is waiting to be loaded in the Channel Transmit Shift Register.
1: Channel Transmit Register is empty.
• TXEMPTY: Channel Transmit Empty
0: Data remains in the Channel Transmit Register or is currently transmitted from the Channel Transmit Shift Register.
1: Data in the Channel Transmit Register have been loaded in the Channel Transmit Shift Register and sent to the codec.
• UNRUN: Transmit Underrun
Active only when Variable Rate Mode is enabled (VRA bit set in the AC97C_MR register). Automatically cleared by a processor read operation.
0: No data has been requested from the channel since the last read of the Status Register, or data has been available each
time the CODEC requested new data from the channel since the last read of the Status Register.
1: Data has been emitted while no valid data to send has been previously loaded into the Channel Transmit Shift Register
since the last read of the Status Register.
• RXRDY: Channel Receive Ready
0: Channel Receive Holding Register is empty.
1: Data has been received and loaded in Channel Receive Holding Register.
• OVRUN: Receive Overrun
Automatically cleared by a processor read operation.
0: No data has been loaded in the Channel Receive Holding Register while previous data has not been read since the last
read of the Status Register.
1: Data has been loaded in the Channel Receive Holding Register while previous data has not yet been read since the last
read of the Status Register.
• ENDTX: End of Transmission for Channel A
0: The register AC97C_CATCR has not reached 0 since the last write in AC97C_CATCR or AC97C_CANCR.
1: The register AC97C_CATCR has reached 0 since the last write in AC97C_CATCR or AC97C_CATNCR.
687
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
• TXBUFE: Transmit Buffer Empty for Channel A
0: AC97C_CATCR or AC97C_CATNCR have a value other than 0.
1: Both AC97C_CATCR and AC97C_CATNCR have a value of 0.
• ENDRX: End of Reception for Channel A
0: The register AC97C_CARCR has not reached 0 since the last write in AC97C_CARCR or AC97C_CARNCR.
1: The register AC97C_CARCR has reached 0 since the last write in AC97C_CARCR or AC97C_CARNCR.
• RXBUFF: Receive Buffer Full for Channel A
0: AC97C_CARCR or AC97C_CARNCR have a value other than 0.
1: Both AC97C_CARCR and AC97C_CARNCR have a value of 0.
688
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.7.9
Name:
AC97 Controller Codec Status Register
AC97C_COSR
Address:
0xFFFA0048
Access:
Read-only
31
–
23
–
15
–
7
–
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
OVRUN
28
–
20
–
12
–
4
RXRDY
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
UNRUN
25
–
17
–
9
–
1
TXEMPTY
24
–
16
–
8
–
0
TXRDY
• TXRDY: Channel Transmit Ready
0: Data has been loaded in Channel Transmit Register and is waiting to be loaded in the Channel Transmit Shift Register.
1: Channel Transmit Register is empty.
• TXEMPTY: Channel Transmit Empty
0: Data remains in the Channel Transmit Register or is currently transmitted from the Channel Transmit Shift Register.
1: Data in the Channel Transmit Register have been loaded in the Channel Transmit Shift Register and sent to the codec.
• UNRUN: Transmit Underrun
Active only when Variable Rate Mode is enabled (VRA bit set in the AC97C_MR register). Automatically cleared by a processor read operation.
0: No data has been requested from the channel since the last read of the Status Register, or data has been available each
time the CODEC requested new data from the channel since the last read of the Status Register.
1: Data has been emitted while no valid data to send has been previously loaded into the Channel Transmit Shift Register
since the last read of the Status Register.
• RXRDY: Channel Receive Ready
0: Channel Receive Holding Register is empty.
1: Data has been received and loaded in Channel Receive Holding Register.
• OVRUN: Receive Overrun
Automatically cleared by a processor read operation.
0: No data has been loaded in the Channel Receive Holding Register while previous data has not been read since the last
read of the Status Register.
1: Data has been loaded in the Channel Receive Holding Register while previous data has not yet been read since the last
read of the Status Register.
689
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.7.10
Name:
AC97 Controller Channel A Mode Register
AC97C_CAMR
Address:
0xFFFA002C
Access:
Read-write
31
–
23
–
15
RXBUFF
7
–
30
–
22
PDCEN
14
ENDRX
6
–
29
–
21
CEN
13
–
5
OVRUN
28
–
20
–
12
–
4
RXRDY
27
–
19
–
11
TXBUFE
3
–
26
–
18
CEM
10
ENDTX
2
UNRUN
25
–
17
24
–
16
SIZE
9
–
1
TXEMPTY
8
–
0
TXRDY
• TXRDY: Channel Transmit Ready Interrupt Enable
• TXEMPTY: Channel Transmit Empty Interrupt Enable
• UNRUN: Transmit Underrun Interrupt Enable
• RXRDY: Channel Receive Ready Interrupt Enable
• OVRUN: Receive Overrun Interrupt Enable
• ENDTX: End of Transmission for Channel A Interrupt Enable
• TXBUFE: Transmit Buffer Empty for Channel A Interrupt Enable
0: Read: the corresponding interrupt is disabled. Write: disables the corresponding interrupt.
1: Read: the corresponding interrupt is enabled. Write: enables the corresponding interrupt.
• ENDRX: End of Reception for Channel A Interrupt Enable
0: Read: the corresponding interrupt is disabled. Write: disables the corresponding interrupt.
1: Read: the corresponding interrupt is enabled. Write: enables the corresponding interrupt.
• RXBUFF: Receive Buffer Full for Channel A Interrupt Enable
0: Read: the corresponding interrupt is disabled. Write: disables the corresponding interrupt.
1: Read: the corresponding interrupt is enabled. Write: enables the corresponding interrupt.
• SIZE: Channel A Data Size
SIZE Encoding
SIZE
Note:
690
Selected Data Size
0x0
20 bits
0x1
18 bits
0x2
16 bits
0x3
10 bits
Each time slot in the data phase is 20 bit long. For example, if a 16-bit sample stream is being played to an AC 97 DAC, the first
16 bit positions are presented to the DAC MSB-justified. They are followed by the next four bit positions that the AC97 Controller
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
fills with zeroes. This process ensures that the least significant bits do not introduce any DC biasing, regardless of the implemented DAC’s resolution (16-, 18-, or 20-bit)
• CEM: Channel A Endian Mode
0: Transferring Data through Channel A is straight forward (Little-Endian).
1: Transferring Data through Channel A from/to a memory is performed with from/to Big-Endian format translation.
• CEN: Channel A Enable
0: Data transfer is disabled on Channel A.
1: Data transfer is enabled on Channel A.
• PDCEN: Peripheral Data Controller Channel Enable
0: Channel A is not transferred through a Peripheral Data Controller Channel. Related PDC flags are ignored or not
generated.
1: Channel A is transferred through a Peripheral Data Controller Channel. Related PDC flags are taken into account or
generated.
691
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.7.11
Name:
AC97 Controller Codec Mode Register
AC97C_COMR
Address:
0xFFFA004C
Access:
Read-write
31
–
23
–
15
–
7
–
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
OVRUN
28
–
20
–
12
–
4
RXRDY
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
UNRUN
25
–
17
–
9
–
1
TXEMPTY
24
–
16
–
8
–
0
TXRDY
• TXRDY: Channel Transmit Ready Interrupt Enable
• TXEMPTY: Channel Transmit Empty Interrupt Enable
• UNRUN: Transmit Underrun Interrupt Enable
• RXRDY: Channel Receive Ready Interrupt Enable
• OVRUN: Receive Overrun Interrupt Enable
692
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.7.12
Name:
AC97 Controller Status Register
AC97C_SR
Address:
0xFFFA0050
Access:
Read-only
31
–
23
–
15
–
7
–
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
CAEVT
26
–
18
–
10
–
2
COEVT
25
–
17
–
9
–
1
WKUP
24
–
16
–
8
–
0
SOF
WKUP and SOF flags in AC97C_SR register are automatically cleared by a processor read operation.
• SOF: Start Of Frame
0: No Start of Frame has been detected since the last read of the Status Register.
1: At least one Start of frame has been detected since the last read of the Status Register.
• WKUP: Wake Up detection
0: No Wake-up has been detected.
1: At least one rising edge on SDATA_IN has been asynchronously detected. That means AC97 Codec has notified a
wake-up.
• COEVT: CODEC Channel Event
A Codec channel event occurs when AC97C_COSR AND AC97C_COMR is not 0. COEVT flag is automatically cleared
when the channel event condition is cleared.
0: No event on the CODEC channel has been detected since the last read of the Status Register.
1: At least one event on the CODEC channel is active.
• CAEVT: Channel A Event
A channel A event occurs when AC97C_CASR AND AC97C_CAMR is not 0. CAEVT flag is automatically cleared when the
channel event condition is cleared.
0: No event on the channel A has been detected since the last read of the Status Register.
1: At least one event on the channel A is active.
693
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.7.13
Name:
AC97 Codec Controller Interrupt Enable Register
AC97C_IER
Address:
0xFFFA0054
Access:
Write-only
31
–
23
–
15
–
7
–
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
CAEVT
26
–
18
–
10
–
2
COEVT
25
–
17
–
9
–
1
WKUP
24
–
16
–
8
–
0
SOF
• SOF: Start Of Frame
• WKUP: Wake Up
• COEVT: Codec Event
• CAEVT: Channel A Event
0: No Effect.
1: Enables the corresponding interrupt.
694
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.7.14
Name:
AC97 Controller Interrupt Disable Register
AC97C_IDR
Address:
0xFFFA0058
Access:
Write-only
31
–
23
–
15
–
7
–
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
CAEVT
26
–
18
–
10
–
2
COEVT
25
–
17
–
9
–
1
WKUP
24
–
16
–
8
–
0
SOF
• SOF: Start Of Frame
• WKUP: Wake Up
• COEVT: Codec Event
• CAEVT: Channel A Event
0: No Effect.
1: Disables the corresponding interrupt.
695
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
38.7.15
Name:
AC97 Controller Interrupt Mask Register
AC97C_IMR
Address:
0xFFFA005C
Access:
Read-only
31
–
23
–
15
–
7
–
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
CAEVT
26
–
18
–
10
–
2
COEVT
25
–
17
–
9
–
1
WKUP
24
–
16
–
8
–
0
SOF
• SOF: Start Of Frame
• WKUP: Wake Up
• COEVT: Codec Event
• CAEVT: Channel A Event
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
696
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
39. Timer Counter (TC)
39.1
Description
The Timer Counter (TC) includes three identical 16-bit Timer Counter channels.
Each channel can be independently programmed to perform a wide range of functions including
frequency measurement, event counting, interval measurement, pulse generation, delay timing
and pulse width modulation.
Each channel has three external clock inputs, five internal clock inputs and two multi-purpose
input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts.
The Timer Counter block has two global registers which act upon all three TC channels.
The Block Control Register allows the three channels to be started simultaneously with the same
instruction.
The Block Mode Register defines the external clock inputs for each channel, allowing them to be
chained.
Table 39-1 gives the assignment of the device Timer Counter clock inputs common to Timer
Counter 0 to 2.
Table 39-1.
Timer Counter Clock Assignment
Name
Definition
TIMER_CLOCK1
MCK/2
TIMER_CLOCK2
MCK/8
TIMER_CLOCK3
MCK/32
TIMER_CLOCK4
MCK/128
TIMER_CLOCK5(1)
SLCK
Note:
1. When Slow Clock is selected for Master Clock (CSS = 0 in PMC Master CLock Register),
TIMER_CLOCK5 input is Master Clock, i.e., Slow CLock modified by PRES and MDIV fields.
697
6264C–CAP–24-Mar-09
39.2
Block Diagram
Figure 39-1. Timer Counter Block Diagram
Parallel I/O
Controller
TIMER_CLOCK1
TCLK0
TIMER_CLOCK2
TIOA1
XC0
TIOA2
TIMER_CLOCK3
XC1
TCLK1
TIMER_CLOCK4
Timer/Counter
Channel 0
TIOA
TIOA0
TIOB0
TIOA0
TIOB
XC2
TCLK2
TIMER_CLOCK5
TC0XC0S
TIOB0
SYNC
TCLK0
TCLK1
TCLK2
INT0
TCLK0
XC0
TCLK1
XC1
TIOA0
Timer/Counter
Channel 1
TIOA
TIOA1
TIOB1
TIOA1
TIOB
XC2
TIOA2
TCLK2
TC1XC1S
TCLK0
XC0
TCLK1
XC1
TCLK2
XC2
TIOB1
SYNC
Timer/Counter
Channel 2
INT1
TIOA
TIOA2
TIOB2
TIOA2
TIOB
TIOA0
TIOA1
TC2XC2S
TIOB2
SYNC
INT2
Timer Counter
Advanced
Interrupt
Controller
Table 39-2.
Signal Name Description
Block/Channel
Signal Name
XC0, XC1, XC2
Channel Signal
External Clock Inputs
TIOA
Capture Mode: Timer Counter Input
Waveform Mode: Timer Counter Output
TIOB
Capture Mode: Timer Counter Input
Waveform Mode: Timer Counter Input/Output
INT
SYNC
698
Description
Interrupt Signal Output
Synchronization Input Signal
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.3
Pin Name List
Table 39-3.
39.4
39.4.1
TC pin list
Pin Name
Description
Type
TCLK0-TCLK2
External Clock Input
Input
TIOA0-TIOA2
I/O Line A
I/O
TIOB0-TIOB2
I/O Line B
I/O
Product Dependencies
I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
The programmer must first program the PIO controllers to assign the TC pins to their peripheral
functions.
Table 39-4.
I/O Lines
Instance
Signal
I/O Line
Peripheral
TC0
TCLK0
PB28
B
TC0
TCLK1
PC28
B
TC0
TCLK2
PA14
A
TC0
TIOA0
PA29
A
TC0
TIOA1
PB6
B
TC0
TIOA2
PB21
B
TC0
TIOB0
PA30
A
TC0
TIOB1
PB7
B
TC0
TIOB2
PB22
B
39.4.2
Power Management
The TC is clocked through the Power Management Controller (PMC), thus the programmer must
first configure the PMC to enable the Timer Counter clock.
39.4.3
Interrupt
The TC has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the
TC interrupt requires programming the AIC before configuring the TC.
699
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.5
Functional Description
39.5.1
TC Description
The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Table 39-5 on page 713.
39.5.2
16-bit Counter
Each channel is organized around a 16-bit counter. The value of the counter is incremented at
each positive edge of the selected clock. When the counter has reached the value 0xFFFF and
passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set.
The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to
0x0000 on the next valid edge of the selected clock.
39.5.3
Clock Selection
At block level, input clock signals of each channel can either be connected to the external inputs
TCLK0, TCLK1 or TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2
for chaining by programming the TC_BMR (Block Mode). See Figure 39-2 on page 701.
Each channel can independently select an internal or external clock source for its counter:
•
Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3,
TIMER_CLOCK4, TIMER_CLOCK5
•
External clock signals: XC0, XC1 or XC2
This selection is made by the TCCLKS bits in the TC Channel Mode Register.
The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the
opposite edges of the clock.
The burst function allows the clock to be validated when an external signal is high. The BURST
parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). See Figure 39-3 on
page 701
Note:
700
In all cases, if an external clock is used, the duration of each of its levels must be longer than the
master clock period. The external clock frequency must be at least 2.5 times lower than the master clock
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 39-2. Clock Chaining Selection
TC0XC0S
Timer/Counter
Channel 0
TCLK0
TIOA1
XC0
TIOA2
TIOA0
XC1 = TCLK1
XC2 = TCLK2
TIOB0
SYNC
TC1XC1S
Timer/Counter
Channel 1
TCLK1
XC0 = TCLK2
TIOA0
TIOA1
XC1
TIOA2
XC2 = TCLK2
TIOB1
SYNC
Timer/Counter
Channel 2
TC2XC2S
XC0 = TCLK0
TCLK2
TIOA2
XC1 = TCLK1
TIOA0
XC2
TIOB2
TIOA1
SYNC
Figure 39-3. Clock Selection
TCCLKS
TIMER_CLOCK1
TIMER_CLOCK2
CLKI
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
Selected
Clock
XC0
XC1
XC2
BURST
1
701
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.5.4
Clock Control
The clock of each counter can be controlled in two different ways: it can be enabled/disabled
and started/stopped. See Figure 39-4.
•
The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS
commands in the Control Register. In Capture Mode it can be disabled by an RB load event
if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare
event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no
effect: only a CLKEN command in the Control Register can re-enable the clock. When the
clock is enabled, the CLKSTA bit is set in the Status Register.
•
The clock can also be started or stopped: a trigger (software, synchro, external or compare)
always starts the clock. The clock can be stopped by an RB load event in Capture Mode
(LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in
TC_CMR). The start and the stop commands have effect only if the clock is enabled.
Figure 39-4. Clock Control
Selected
Clock
Trigger
CLKSTA
CLKEN
Q
Q
S
CLKDIS
S
R
R
Counter
Clock
39.5.5
Stop
Event
Disable
Event
TC Operating Modes
Each channel can independently operate in two different modes:
•
Capture Mode provides measurement on signals.
•
Waveform Mode provides wave generation.
The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register.
In Capture Mode, TIOA and TIOB are configured as inputs.
In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not
selected to be the external trigger.
39.5.6
Trigger
A trigger resets the counter and starts the counter clock. Three types of triggers are common to
both modes, and a fourth external trigger is available to each mode.
702
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Regardless of the trigger used, it will be taken into account at the following active edge of the
selected clock. This means that the counter value can be read differently from zero just after a
trigger, especially when a low frequency signal is selected as the clock.
The following triggers are common to both modes:
•
Software Trigger: Each channel has a software trigger, available by setting SWTRG in
TC_CCR.
•
SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has
the same effect as a software trigger. The SYNC signals of all channels are asserted
simultaneously by writing TC_BCR (Block Control) with SYNC set.
•
Compare RC Trigger: RC is implemented in each channel and can provide a trigger when
the counter value matches the RC value if CPCTRG is set in TC_CMR.
The channel can also be configured to have an external trigger. In Capture Mode, the external
trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event
can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external
event can then be programmed to perform a trigger by setting ENETRG in TC_CMR.
If an external trigger is used, the duration of the pulses must be longer than the master clock
period in order to be detected.
39.5.7
Capture Operating Mode
This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register).
Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as
inputs.
Figure 39-5 shows the configuration of the TC channel when programmed in Capture Mode.
39.5.8
Capture Registers A and B
Registers A and B (RA and RB) are used as capture registers. This means that they can be
loaded with the counter value when a programmable event occurs on the signal TIOA.
The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A, and the
LDRB parameter defines the TIOA edge for the loading of Register B.
RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since
the last loading of RA.
RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS)
in TC_SR (Status Register). In this case, the old value is overwritten.
39.5.9
Trigger Conditions
In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined.
The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The
ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an external
trigger. If ETRGEDG = 0 (none), the external trigger is disabled.
703
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
704
MTIOA
MTIOB
1
If RA is not loaded
or RB is Loaded
Edge
Detector
ETRGEDG
SWTRG
Timer/Counter Channel
ABETRG
BURST
CLKI
S
R
OVF
LDRB
Edge
Detector
Edge
Detector
Capture
Register A
LDBSTOP
R
S
CLKEN
LDRA
If RA is Loaded
CPCTRG
16-bit Counter
RESET
Trig
CLK
Q
Q
CLKSTA
LDBDIS
Capture
Register B
CLKDIS
TC1_SR
TIOA
TIOB
SYNC
XC2
XC1
XC0
TIMER_CLOCK5
TIMER_CLOCK4
TIMER_CLOCK3
TIMER_CLOCK2
TIMER_CLOCK1
TCCLKS
Compare RC =
Register C
COVFS
INT
Figure 39-5. Capture Mode
CPCS
LOVRS
LDRBS
ETRGS
LDRAS
TC1_IMR
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.5.10
Waveform Operating Mode
Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel
Mode Register).
In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot
or repetitive pulses.
In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used
as an external event (EEVT parameter in TC_CMR).
Figure 39-6 shows the configuration of the TC channel when programmed in Waveform Operating Mode.
39.5.11
Waveform Selection
Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of
TC_CV varies.
With any selection, RA, RB and RC can all be used as compare registers.
RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output
(if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs.
705
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
706
TIOB
SYNC
XC2
XC1
XC0
TIMER_CLOCK5
TIMER_CLOCK4
TIMER_CLOCK3
TIMER_CLOCK2
TIMER_CLOCK1
1
EEVT
BURST
Timer/Counter Channel
Edge
Detector
EEVTEDG
SWTRG
ENETRG
CLKI
Trig
CLK
R
S
OVF
WAVSEL
RESET
16-bit Counter
WAVSEL
Q
Compare RA =
Register A
Q
CLKSTA
Compare RC =
Compare RB =
CPCSTOP
CPCDIS
Register C
CLKDIS
Register B
R
S
CLKEN
CPAS
INT
BSWTRG
BEEVT
BCPB
BCPC
ASWTRG
AEEVT
ACPA
ACPC
Output Controller
Output Controller
TCCLKS
TIOB
MTIOB
TIOA
MTIOA
Figure 39-6. Waveform Mode
CPCS
CPBS
COVFS
TC1_SR
ETRGS
TC1_IMR
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.5.11.1
WAVSEL = 00
When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has
been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle
continues. See Figure 39-7.
An external event trigger or a software trigger can reset the value of TC_CV. It is important to
note that the trigger may occur at any time. See Figure 39-8.
RC Compare cannot be programmed to generate a trigger in this configuration. At the same
time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the
counter clock (CPCDIS = 1 in TC_CMR).
Figure 39-7. WAVSEL= 00 without trigger
Counter Value
Counter cleared by compare match with 0xFFFF
0xFFFF
RC
RB
RA
Waveform Examples
Time
TIOB
TIOA
707
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 39-8. WAVSEL= 00 with trigger
Counter cleared by compare match with 0xFFFF
Counter Value
0xFFFF
Counter cleared by trigger
RC
RB
RA
Time
Waveform Examples
TIOB
TIOA
39.5.11.2
WAVSEL = 10
When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then
incremented and so on. See Figure 39-9.
It is important to note that TC_CV can be reset at any time by an external event or a software
trigger if both are programmed correctly. See Figure 39-10.
In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable
the counter clock (CPCDIS = 1 in TC_CMR).
Figure 39-9. WAVSEL = 10 Without Trigger
Counter Value
0xFFFF
Counter cleared by compare match with RC
RC
RB
RA
Waveform Examples
Time
TIOB
TIOA
708
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 39-10. WAVSEL = 10 With Trigger
Counter Value
0xFFFF
Counter cleared by compare match with RC
Counter cleared by trigger
RC
RB
RA
Time
Waveform Examples
TIOB
TIOA
39.5.11.3
WAVSEL = 01
When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is
reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on.
See Figure 39-11.
A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while
TC_CV is decrementing, TC_CV then increments. See Figure 39-12.
RC Compare cannot be programmed to generate a trigger in this configuration.
At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the
counter clock (CPCDIS = 1).
709
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 39-11. WAVSEL = 01 Without Trigger
Counter decremented by compare match with 0xFFFF
Counter Value
0xFFFF
RC
RB
RA
Time
Waveform Examples
TIOB
TIOA
Figure 39-12. WAVSEL = 01 With Trigger
Counter Value
Counter decremented by compare match with 0xFFFF
0xFFFF
Counter decremented
by trigger
RC
RB
Counter incremented
by trigger
RA
Time
Waveform Examples
TIOB
TIOA
39.5.11.4
WAVSEL = 11
When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the
value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 39-13.
A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while
TC_CV is decrementing, TC_CV then increments. See Figure 39-14.
RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock
(CPCDIS = 1).
710
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
Figure 39-13. WAVSEL = 11 Without Trigger
Counter Value
0xFFFF
Counter decremented by compare match with RC
RC
RB
RA
Time
Waveform Examples
TIOB
TIOA
Figure 39-14. WAVSEL = 11 With Trigger
Counter Value
0xFFFF
Counter decremented by compare match with RC
RC
RB
Counter decremented
by trigger
Counter incremented
by trigger
RA
Waveform Examples
Time
TIOB
TIOA
711
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.5.12
External Event/Trigger Conditions
An external event can be programmed to be detected on one of the clock sources (XC0, XC1,
XC2) or TIOB. The external event selected can then be used as a trigger.
The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines
the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is
cleared (none), no external event is defined.
If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output
and the compare register B is not used to generate waveforms and subsequently no IRQs. In
this case the TC channel can only generate a waveform on TIOA.
When an external event is defined, it can be used as a trigger by setting bit ENETRG in
TC_CMR.
As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC
Compare can also be used as a trigger depending on the parameter WAVSEL.
39.5.13
Output Controller
The output controller defines the output level changes on TIOA and TIOB following an event.
TIOB control is used only if TIOB is defined as output (not as an external event).
The following events control TIOA and TIOB: software trigger, external event and RC compare.
RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in
TC_CMR.
712
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.6
Timer Counter (TC) User Interface
Table 39-5.
Register Mapping
Offset(1)
Register
Name
Access
Reset
0x00 + channel * 0x40 + 0x00
Channel Control Register
TC_CCR
Write-only
–
0x00 + channel * 0x40 + 0x04
Channel Mode Register
TC_CMR
Read-write
0
0x00 + channel * 0x40 + 0x08
Reserved
0x00 + channel * 0x40 + 0x0C
Reserved
0x00 + channel * 0x40 + 0x10
Counter Value
TC_CV
Read-only
0
0x00 + channel * 0x40 + 0x14
Register A
TC_RA
Read-write
(2)
0
Read-write
(2)
0
0x00 + channel * 0x40 + 0x18
Register B
TC_RB
0x00 + channel * 0x40 + 0x1C
Register C
TC_RC
Read-write
0
0x00 + channel * 0x40 + 0x20
Status Register
TC_SR
Read-only
0
0x00 + channel * 0x40 + 0x24
Interrupt Enable Register
TC_IER
Write-only
–
0x00 + channel * 0x40 + 0x28
Interrupt Disable Register
TC_IDR
Write-only
–
0x00 + channel * 0x40 + 0x2C
Interrupt Mask Register
TC_IMR
Read-only
0
0xC0
Block Control Register
TC_BCR
Write-only
–
0xC4
Block Mode Register
TC_BMR
Read-write
0
0xFC
Reserved
–
–
–
Notes:
1. Channel index ranges from 0 to 2.
2. Read-only if WAVE = 0
713
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.6.1
Name:
TC Block Control Register
TC_BCR
Address:
0xFFF7C0C0
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
SYNC
• SYNC: Synchro Command
0 = No effect.
1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
714
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.6.2
Name:
TC Block Mode Register
TC_BMR
Address:
0xFFF7C0C4
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
–
–
TC2XC2S
TC1XC1S
0
TC0XC0S
• TC0XC0S: External Clock Signal 0 Selection
TC0XC0S
Signal Connected to XC0
0
0
TCLK0
0
1
none
1
0
TIOA1
1
1
TIOA2
• TC1XC1S: External Clock Signal 1 Selection
TC1XC1S
Signal Connected to XC1
0
0
TCLK1
0
1
none
1
0
TIOA0
1
1
TIOA2
• TC2XC2S: External Clock Signal 2 Selection
TC2XC2S
715
Signal Connected to XC2
0
0
TCLK2
0
1
none
1
0
TIOA0
1
1
TIOA1
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.6.3
Name:
TC Channel Control Register
TC_CCRx [x=0..2]
Addresses: 0xFFF7C000 (0)[0], 0xFFF7C040 (0)[1], 0xFFF7C080 (0)[2]
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
SWTRG
CLKDIS
CLKEN
• CLKEN: Counter Clock Enable Command
0 = No effect.
1 = Enables the clock if CLKDIS is not 1.
• CLKDIS: Counter Clock Disable Command
0 = No effect.
1 = Disables the clock.
• SWTRG: Software Trigger Command
0 = No effect.
1 = A software trigger is performed: the counter is reset and the clock is started.
716
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.6.4
Name:
TC Channel Mode Register: Capture Mode
TC_CMRx [x=0..2] (WAVE = 0)
Addresses: 0xFFF7C004 (0)[0], 0xFFF7C044 (0)[1], 0xFFF7C084 (0)[2]
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
–
–
–
–
15
14
13
12
11
10
WAVE
CPCTRG
–
–
–
ABETRG
7
6
5
3
2
LDBDIS
LDBSTOP
16
LDRB
4
BURST
CLKI
LDRA
9
8
ETRGEDG
1
0
TCCLKS
• TCCLKS: Clock Selection
TCCLKS
Clock Selected
0
0
0
TIMER_CLOCK1
0
0
1
TIMER_CLOCK2
0
1
0
TIMER_CLOCK3
0
1
1
TIMER_CLOCK4
1
0
0
TIMER_CLOCK5
1
0
1
XC0
1
1
0
XC1
1
1
1
XC2
• CLKI: Clock Invert
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
BURST
0
0
The clock is not gated by an external signal.
0
1
XC0 is ANDed with the selected clock.
1
0
XC1 is ANDed with the selected clock.
1
1
XC2 is ANDed with the selected clock.
• LDBSTOP: Counter Clock Stopped with RB Loading
0 = Counter clock is not stopped when RB loading occurs.
1 = Counter clock is stopped when RB loading occurs.
717
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
• LDBDIS: Counter Clock Disable with RB Loading
0 = Counter clock is not disabled when RB loading occurs.
1 = Counter clock is disabled when RB loading occurs.
• ETRGEDG: External Trigger Edge Selection
ETRGEDG
Edge
0
0
none
0
1
rising edge
1
0
falling edge
1
1
each edge
• ABETRG: TIOA or TIOB External Trigger Selection
0 = TIOB is used as an external trigger.
1 = TIOA is used as an external trigger.
• CPCTRG: RC Compare Trigger Enable
0 = RC Compare has no effect on the counter and its clock.
1 = RC Compare resets the counter and starts the counter clock.
• WAVE
0 = Capture Mode is enabled.
1 = Capture Mode is disabled (Waveform Mode is enabled).
• LDRA: RA Loading Selection
LDRA
Edge
0
0
none
0
1
rising edge of TIOA
1
0
falling edge of TIOA
1
1
each edge of TIOA
• LDRB: RB Loading Selection
LDRB
718
Edge
0
0
none
0
1
rising edge of TIOA
1
0
falling edge of TIOA
1
1
each edge of TIOA
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.6.5
Name:
TC Channel Mode Register: Waveform Mode
TC_CMRx [x=0..2] (WAVE = 1)
Addresses: 0xFFF7C004 (0)[0], 0xFFF7C044 (0)[1], 0xFFF7C084 (0)[2]
Access:
Read-write
31
30
29
BSWTRG
23
22
21
ASWTRG
15
28
27
BEEVT
20
19
AEEVT
14
WAVE
13
7
6
CPCDIS
CPCSTOP
24
BCPB
18
11
ENETRG
5
25
17
16
ACPC
12
WAVSEL
26
BCPC
ACPA
10
9
EEVT
4
3
BURST
CLKI
8
EEVTEDG
2
1
0
TCCLKS
• TCCLKS: Clock Selection
TCCLKS
Clock Selected
0
0
0
TIMER_CLOCK1
0
0
1
TIMER_CLOCK2
0
1
0
TIMER_CLOCK3
0
1
1
TIMER_CLOCK4
1
0
0
TIMER_CLOCK5
1
0
1
XC0
1
1
0
XC1
1
1
1
XC2
• CLKI: Clock Invert
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
BURST
0
0
The clock is not gated by an external signal.
0
1
XC0 is ANDed with the selected clock.
1
0
XC1 is ANDed with the selected clock.
1
1
XC2 is ANDed with the selected clock.
• CPCSTOP: Counter Clock Stopped with RC Compare
0 = Counter clock is not stopped when counter reaches RC.
1 = Counter clock is stopped when counter reaches RC.
719
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
• CPCDIS: Counter Clock Disable with RC Compare
0 = Counter clock is not disabled when counter reaches RC.
1 = Counter clock is disabled when counter reaches RC.
• EEVTEDG: External Event Edge Selection
EEVTEDG
Edge
0
0
none
0
1
rising edge
1
0
falling edge
1
1
each edge
• EEVT: External Event Selection
EEVT
Signal selected as external event
TIOB Direction
0
0
TIOB
input (1)
0
1
XC0
output
1
0
XC1
output
1
1
XC2
output
Note:
1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs.
• ENETRG: External Event Trigger Enable
0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the
TIOA output.
1 = The external event resets the counter and starts the counter clock.
• WAVSEL: Waveform Selection
WAVSEL
Effect
0
0
UP mode without automatic trigger on RC Compare
1
0
UP mode with automatic trigger on RC Compare
0
1
UPDOWN mode without automatic trigger on RC Compare
1
1
UPDOWN mode with automatic trigger on RC Compare
• WAVE
0 = Waveform Mode is disabled (Capture Mode is enabled).
1 = Waveform Mode is enabled.
720
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
• ACPA: RA Compare Effect on TIOA
ACPA
Effect
0
0
none
0
1
set
1
0
clear
1
1
toggle
• ACPC: RC Compare Effect on TIOA
ACPC
Effect
0
0
none
0
1
set
1
0
clear
1
1
toggle
• AEEVT: External Event Effect on TIOA
AEEVT
Effect
0
0
none
0
1
set
1
0
clear
1
1
toggle
• ASWTRG: Software Trigger Effect on TIOA
ASWTRG
Effect
0
0
none
0
1
set
1
0
clear
1
1
toggle
• BCPB: RB Compare Effect on TIOB
BCPB
721
Effect
0
0
none
0
1
set
1
0
clear
1
1
toggle
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
• BCPC: RC Compare Effect on TIOB
BCPC
Effect
0
0
none
0
1
set
1
0
clear
1
1
toggle
• BEEVT: External Event Effect on TIOB
BEEVT
Effect
0
0
none
0
1
set
1
0
clear
1
1
toggle
• BSWTRG: Software Trigger Effect on TIOB
BSWTRG
722
Effect
0
0
none
0
1
set
1
0
clear
1
1
toggle
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.6.6
Name:
TC Counter Value Register
TC_CVx [x=0..2]
Addresses: 0xFFF7C010 (0)[0], 0xFFF7C050 (0)[1], 0xFFF7C090 (0)[2]
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
3
2
1
0
CV
7
6
5
4
CV
• CV: Counter Value
CV contains the counter value in real time.
723
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.6.7
Name:
TC Register A
TC_RAx [x=0..2]
Addresses: 0xFFF7C014 (0)[0], 0xFFF7C054 (0)[1], 0xFFF7C094 (0)[2]
Access:
Read-only if WAVE = 0, Read-write if WAVE = 1
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
3
2
1
0
RA
7
6
5
4
RA
• RA: Register A
RA contains the Register A value in real time.
39.6.8
Name:
TC Register B
TC_RBx [x=0..2]
Addresses: 0xFFF7C018 (0)[0], 0xFFF7C058 (0)[1], 0xFFF7C098 (0)[2]
Access:
Read-only if WAVE = 0, Read-write if WAVE = 1
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
3
2
1
0
RB
7
6
5
4
RB
• RB: Register B
RB contains the Register B value in real time.
724
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.6.9
Name:
TC Register C
TC_RCx [x=0..2]
Addresses: 0xFFF7C01C (0)[0], 0xFFF7C05C (0)[1], 0xFFF7C09C (0)[2]
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
3
2
1
0
RC
7
6
5
4
RC
• RC: Register C
RC contains the Register C value in real time.
725
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.6.10
Name:
TC Status Register
TC_SRx [x=0..2]
Addresses: 0xFFF7C020 (0)[0], 0xFFF7C060 (0)[1], 0xFFF7C0A0 (0)[2]
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
MTIOB
MTIOA
CLKSTA
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
ETRGS
LDRBS
LDRAS
CPCS
CPBS
CPAS
LOVRS
COVFS
• COVFS: Counter Overflow Status
0 = No counter overflow has occurred since the last read of the Status Register.
1 = A counter overflow has occurred since the last read of the Status Register.
• LOVRS: Load Overrun Status
0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0.
• CPAS: RA Compare Status
0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.
• CPBS: RB Compare Status
0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.
• CPCS: RC Compare Status
0 = RC Compare has not occurred since the last read of the Status Register.
1 = RC Compare has occurred since the last read of the Status Register.
• LDRAS: RA Loading Status
0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.
• LDRBS: RB Loading Status
0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.
• ETRGS: External Trigger Status
0 = External trigger has not occurred since the last read of the Status Register.
1 = External trigger has occurred since the last read of the Status Register.
726
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
• CLKSTA: Clock Enabling Status
0 = Clock is disabled.
1 = Clock is enabled.
• MTIOA: TIOA Mirror
0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low.
1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.
• MTIOB: TIOB Mirror
0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low.
1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.
727
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.6.11
Name:
TC Interrupt Enable Register
TC_IERx [x=0..2]
Addresses: 0xFFF7C024 (0)[0], 0xFFF7C064 (0)[1], 0xFFF7C0A4 (0)[2]
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
ETRGS
LDRBS
LDRAS
CPCS
CPBS
CPAS
LOVRS
COVFS
• COVFS: Counter Overflow
0 = No effect.
1 = Enables the Counter Overflow Interrupt.
• LOVRS: Load Overrun
0 = No effect.
1 = Enables the Load Overrun Interrupt.
• CPAS: RA Compare
0 = No effect.
1 = Enables the RA Compare Interrupt.
• CPBS: RB Compare
0 = No effect.
1 = Enables the RB Compare Interrupt.
• CPCS: RC Compare
0 = No effect.
1 = Enables the RC Compare Interrupt.
• LDRAS: RA Loading
0 = No effect.
1 = Enables the RA Load Interrupt.
• LDRBS: RB Loading
0 = No effect.
1 = Enables the RB Load Interrupt.
• ETRGS: External Trigger
0 = No effect.
1 = Enables the External Trigger Interrupt.
728
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.6.12
Name:
TC Interrupt Disable Register
TC_IDRx [x=0..2]
Addresses: 0xFFF7C028 (0)[0], 0xFFF7C068 (0)[1], 0xFFF7C0A8 (0)[2]
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
ETRGS
LDRBS
LDRAS
CPCS
CPBS
CPAS
LOVRS
COVFS
• COVFS: Counter Overflow
0 = No effect.
1 = Disables the Counter Overflow Interrupt.
• LOVRS: Load Overrun
0 = No effect.
1 = Disables the Load Overrun Interrupt (if WAVE = 0).
• CPAS: RA Compare
0 = No effect.
1 = Disables the RA Compare Interrupt (if WAVE = 1).
• CPBS: RB Compare
0 = No effect.
1 = Disables the RB Compare Interrupt (if WAVE = 1).
• CPCS: RC Compare
0 = No effect.
1 = Disables the RC Compare Interrupt.
• LDRAS: RA Loading
0 = No effect.
1 = Disables the RA Load Interrupt (if WAVE = 0).
• LDRBS: RB Loading
0 = No effect.
1 = Disables the RB Load Interrupt (if WAVE = 0).
• ETRGS: External Trigger
0 = No effect.
1 = Disables the External Trigger Interrupt.
729
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
39.6.13
Name:
TC Interrupt Mask Register
TC_IMRx [x=0..2]
Addresses: 0xFFF7C02C (0)[0], 0xFFF7C06C (0)[1], 0xFFF7C0AC (0)[2]
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
ETRGS
LDRBS
LDRAS
CPCS
CPBS
CPAS
LOVRS
COVFS
• COVFS: Counter Overflow
0 = The Counter Overflow Interrupt is disabled.
1 = The Counter Overflow Interrupt is enabled.
• LOVRS: Load Overrun
0 = The Load Overrun Interrupt is disabled.
1 = The Load Overrun Interrupt is enabled.
• CPAS: RA Compare
0 = The RA Compare Interrupt is disabled.
1 = The RA Compare Interrupt is enabled.
• CPBS: RB Compare
0 = The RB Compare Interrupt is disabled.
1 = The RB Compare Interrupt is enabled.
• CPCS: RC Compare
0 = The RC Compare Interrupt is disabled.
1 = The RC Compare Interrupt is enabled.
• LDRAS: RA Loading
0 = The Load RA Interrupt is disabled.
1 = The Load RA Interrupt is enabled.
• LDRBS: RB Loading
0 = The Load RB Interrupt is disabled.
1 = The Load RB Interrupt is enabled.
• ETRGS: External Trigger
0 = The External Trigger Interrupt is disabled.
1 = The External Trigger Interrupt is enabled.
730
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
40. Controller Area Network (CAN)
40.1
Overview
The CAN controller provides all the features required to implement the serial communication
protocol CAN defined by Robert Bosch GmbH, the CAN specification as referred to by
ISO/11898A (2.0 Part A and 2.0 Part B) for high speeds and ISO/11519-2 for low speeds. The
CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and
achieves a bitrate of 1 Mbit/sec.
CAN controller accesses are made through configuration registers. 16 independent message
objects (mailboxes) are implemented.
Any mailbox can be programmed as a reception buffer block (even non-consecutive buffers).
For the reception of defined messages, one or several message objects can be masked without
participating in the buffer feature. An interrupt is generated when the buffer is full. According to
the mailbox configuration, the first message received can be locked in the CAN controller registers until the application acknowledges it, or this message can be discarded by new received
messages.
Any mailbox can be programmed for transmission. Several transmission mailboxes can be
enabled in the same time. A priority can be defined for each mailbox independently.
An internal 16-bit timer is used to stamp each received and sent message. This timer starts
counting as soon as the CAN controller is enabled. This counter can be reset by the application
or automatically after a reception in the last mailbox in Time Triggered Mode.
The CAN controller offers optimized features to support the Time Triggered Communication
(TTC) protocol.
731
6264C–CAP–24-Mar-09
40.2
Block Diagram
Figure 40-1. CAN Block Diagram
Controller Area Network
CANRX
CAN Protocol Controller
PIO
CANTX
Error Counter
Mailbox
Priority
Encoder
Control
&
Status
MB0
MB1
MCK
PMC
MBx
(x = number of mailboxes - 1)
CAN Interrupt
User Interface
Internal Bus
40.3
Application Block Diagram
Figure 40-2.
732
Application Block Diagram
Layers
Implementation
CAN-based Profiles
Software
CAN-based Application Layer
Software
CAN Data Link Layer
CAN Controller
CAN Physical Layer
Transceiver
AT91CAP9S500A/AT91CAP9S250A
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
40.4
I/O Lines Description
Table 40-1.
I/O Lines Description
Name
Description
Type
CANRX
CAN Receive Serial Data
Input
CANTX
CAN Transmit Serial Data
Output
40.5
40.5.1
Product Dependencies
I/O Lines
The pins used for interfacing the CAN may be multiplexed with the PIO lines. The programmer
must first program the PIO controller to assign the desired CAN pins to their peripheral function.
If I/O lines of the CAN are not used by the application, they can be used for other purposes by
the PIO Controller.
Table 40-2.
40.5.2
I/O Lines
Instance
Signal
I/O Line
Peripheral
CAN
CANRX
PA13
A
CAN
CANTX
PA12
A
Power Management
The programmer must first enable the CAN clock in the Power Management Controller (PMC)
before using the CAN.
A Low-power Mode is defined for the CAN controller: If the application does not require CAN
operations, the CAN clock can be stopped when not needed and be restarted later. Before stopping the clock, the CAN Controller must be in Low-power Mode to complete the current transfer.
After restarting the clock, the application must disable the Low-power Mode of the CAN
controller.
40.5.3
Interrupt
The CAN interrupt line is connected on one of the internal sources of the Advanced Interrupt
Controller. Using the CAN interrupt requires the AIC to be programmed first. Note that it is not
recommended to use the CAN interrupt line in edge-sensitive mode.
Table 40-3.
Peripheral IDs
Instance
ID
CAN
13
733
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
40.6
CAN Controller Features
40.6.1
CAN Protocol Overview
The Controller Area Network (CAN) is a multi-master serial communication protocol that efficiently supports real-time control with a very high level of security with bit rates up to 1 Mbit/s.
The CAN protocol supports four different frame types:
• Data frames: They carry data from a transmitter node to the receiver nodes. The overall
maximum data frame length is 108 bits for a standard frame and 128 bits for an extended
frame.
• Remote frames: A destination node can request data from the source by sending a remote
frame with an identifier that matches the identifier of the required data frame. The appropriate
data source node then sends a data frame as a response to this node request.
• Error frames: An error frame is generated by any node that detects a bus error.
• Overload frames: They provide an extra delay between the preceding and the successive
data frames or remote frames.
The Atmel CAN controller provides the CPU with full functionality of the CAN protocol V2.0 Part
A and V2.0 Part B. It minimizes the CPU load in communication overhead. The Data Link Layer
and part of the physical layer are automatically handled by the CAN controller itself.
The CPU reads or writes data or messages via the CAN controller mailboxes. An identifier is
assigned to each mailbox. The CAN controller encapsulates or decodes data messages to build
or to decode bus data frames. Remote frames, error frames and overload frames are automatically handled by the CAN controller under supervision of the software application.
40.6.2
Mailbox Organization
The CAN module has 16 buffers, also called channels or mailboxes. An identifier that corresponds to the CAN identifier is defined for each active mailbox. Message identifiers can match
the standard frame identifier or the extended frame identifier. This identifier is defined for the first
time during the CAN initialization, but can be dynamically reconfigured later so that the mailbox
can handle a new message family. Several mailboxes can be configured with the same ID.
Each mailbox can be configured in receive or in transmit mode independently. The mailbox
object type is defined in the MOT field of the CAN_MMRx register.
40.6.2.1
Message Acceptance Procedure
If the MIDE field in the CAN_MIDx register is set, the mailbox can handle the extended format
identifier; otherwise, the mailbox handles the standard format identifier. Once a new message is
received, its ID is masked with the CAN_MAMx value and compared with the CAN_MIDx value.
If accepted, the message ID is copied to the CAN_MIDx register.
734
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
Figure 40-3. Message Acceptance Procedure
CAN_MAMx
CAN_MIDx
&
Message Received
&
==
No
Message Refused
Yes
Message Accepted
CAN_MFIDx
If a mailbox is dedicated to receiving several messages (a family of messages) with different
IDs, the acceptance mask defined in the CAN_MAMx register must mask the variable part of the
ID family. Once a message is received, the application must decode the masked bits in the
CAN_MIDx. To speed up the decoding, masked bits are grouped in the family ID register
(CAN_MFIDx).
For example, if the following message IDs are handled by the same mailbox:
ID0 101000100100010010000100 0 11 00b
ID1 101000100100010010000100 0 11 01b
ID2 101000100100010010000100 0 11 10b
ID3 101000100100010010000100 0 11 11b
ID4 101000100100010010000100 1 11 00b
ID5 101000100100010010000100 1 11 01b
ID6 101000100100010010000100 1 11 10b
ID7 101000100100010010000100 1 11 11b
The CAN_MIDx and CAN_MAMx of Mailbox x must be initialized to the corresponding values:
CAN_MIDx = 001 101000100100010010000100 x 11 xxb
CAN_MAMx = 001 111111111111111111111111 0 11 00b
If Mailbox x receives a message with ID6, then CAN_MIDx and CAN_MFIDx are set:
CAN_MIDx = 001 101000100100010010000100 1 11 10b
CAN_MFIDx = 00000000000000000000000000000110b
If the application associates a handler for each message ID, it may define an array of pointers to
functions:
void (*pHandler[8])(void);
When a message is received, the corresponding handler can be invoked using CAN_MFIDx register and there is no need to check masked bits:
unsigned int MFID0_register;
MFID0_register = Get_CAN_MFID0_Register();
// Get_CAN_MFID0_Register() returns the value of the CAN_MFID0 register
pHandler[MFID0_register]();
735
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
40.6.2.2
Receive Mailbox
When the CAN module receives a message, it looks for the first available mailbox with the lowest number and compares the received message ID with the mailbox ID. If such a mailbox is
found, then the message is stored in its data registers. Depending on the configuration, the mailbox is disabled as long as the message has not been acknowledged by the application (Receive
only), or, if new messages with the same ID are received, then they overwrite the previous ones
(Receive with overwrite).
It is also possible to configure a mailbox in Consumer Mode. In this mode, after each transfer
request, a remote frame is automatically sent. The first answer received is stored in the corresponding mailbox data registers.
Several mailboxes can be chained to receive a buffer. They must be configured with the same
ID in Receive Mode, except for the last one, which can be configured in Receive with Overwrite
Mode. The last mailbox can be used to detect a buffer overflow.
Mailbox Object Type
The first message received is stored in mailbox data registers. Data remain available until the
next transfer request.
Receive
Receive with overwrite
The last message received is stored in mailbox data register. The next message always
overwrites the previous one. The application has to check whether a new message has not
overwritten the current one while reading the data registers.
A remote frame is sent by the mailbox. The answer received is stored in mailbox data register.
This extends Receive mailbox features. Data remain available until the next transfer request.
Consumer
40.6.2.3
Description
Transmit Mailbox
When transmitting a message, the message length and data are written to the transmit mailbox
with the correct identifier. For each transmit mailbox, a priority is assigned. The controller automatically sends the message with the highest priority first (set with the field PRIOR in
CAN_MMRx register).
It is also possible to configure a mailbox in Producer Mode. In this mode, when a remote frame
is received, the mailbox data are sent automatically. By enabling this mode, a producer can be
done using only one mailbox instead of two: one to detect the remote frame and one to send the
answer.
Mailbox Object Type
Description
Transmit
The message stored in the mailbox data registers will try to win the bus arbitration immediately
or later according to or not the Time Management Unit configuration (see Section 40.6.3).
The application is notified that the message has been sent or aborted.
Producer
The message prepared in the mailbox data registers will be sent after receiving the next remote
frame. This extends transmit mailbox features.
736
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
40.6.3
Time Management Unit
The CAN Controller integrates a free-running 16-bit internal timer. The counter is driven by the
bit clock of the CAN bus line. It is enabled when the CAN controller is enabled (CANEN set in the
CAN_MR register). It is automatically cleared in the following cases:
• after a reset
• when the CAN controller is in Low-power Mode is enabled (LPM bit set in the CAN_MR and
SLEEP bit set in the CAN_SR)
• after a reset of the CAN controller (CANEN bit in the CAN_MR register)
• in Time-triggered Mode, when a message is accepted by the last mailbox (rising edge of the
MRDY signal in the CAN_MSRlast_mailbox_number register).
The application can also reset the internal timer by setting TIMRST in the CAN_TCR register.
The current value of the internal timer is always accessible by reading the CAN_TIM register.
When the timer rolls-over from FFFFh to 0000h, TOVF (Timer Overflow) signal in the CAN_SR
register is set. TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register.
Depending on the corresponding interrupt mask in the CAN_IMR register, an interrupt is generated while TOVF is set.
In a CAN network, some CAN devices may have a larger counter. In this case, the application
can also decide to freeze the internal counter when the timer reaches FFFFh and to wait for a
restart condition from another device. This feature is enabled by setting TIMFRZ in the CAN_MR
register. The CAN_TIM register is frozen to the FFFFh value. A clear condition described above
restarts the timer. A timer overflow (TOVF) interrupt is triggered.
To monitor the CAN bus activity, the CAN_TIM register is copied to the CAN _TIMESTP register
after each start of frame or end of frame and a TSTP interrupt is triggered. If TEOF bit in the
CAN_MR register is set, the value is captured at each End Of Frame, else it is captured at each
Start Of Frame. Depending on the corresponding mask in the CAN_IMR register, an interrupt is
generated while TSTP is set in the CAN_SR. TSTP bit is cleared by reading the CAN_SR
register.
The time management unit can operate in one of the two following modes:
• Timestamping mode: The value of the internal timer is captured at each Start Of Frame or
each End Of Frame
• Time Triggered mode: A mailbox transfer operation is triggered when the internal timer
reaches the mailbox trigger.
Timestamping Mode is enabled by clearing TTM field in the CAN_MR register. Time Triggered
Mode is enabled by setting TTM field in the CAN_MR register.
737
6264C–CAP–24-Mar-09
AT91CAP9S500A/AT91CAP9S250A
40.6.4
40.6.4.1
CAN 2.0 Standard Features
CAN Bit Timing Configuration
All controllers on a CAN bus must have the same bit rate and bit length. At different clock frequencies of the individual controllers, the bit rate has to be adjusted by the time segments.
The CAN protocol specification partitions the nominal bit time into four different segments:
Figure 40-4. Partition of the CAN Bit Time
NOMINAL BIT TIME
SYNC_SEG
PROP_SEG
PHASE_SEG1
PHASE_SEG2
Sample Point
• TIME QUANTUM
The TIME QUANTUM (TQ) is a fixed unit of time derived from the MCK period. The total number
of TIME QUANTA in a bit time is programmable from 8 to 25.
SYNC SEG: SYNChronization Segment.
This part of the bit time is used to synchronize the various nodes on the bus. An edge is
expected to lie within this segment. It is 1 TQ long.
• PROP SEG: PROPagation Segment.
This part of the bit time is used to compensate for the physical delay times within the network. It
is twice the sum of the signal’s propagation time on the bus line, the input comparator delay, and
the output driver delay. It is programmable to be 1,2,..., 8 TQ long.
This parameter is defined in the PROPAG field of the ”CAN Baudrate Register”.
• PHASE SEG1, PHASE SEG2: PHASE Segment 1 and 2.
The Phase-Buffer-Segments are used to compensate for edge phase errors. These segments
can be lengthened (PHASE SEG1) or shortened (PHASE SEG2) by resynchronization.
Phase Segment 1 is programmable to be 1,2,..., 8 TQ long.
Phase Segment 2 length has to be at least as long as the Information Processing Time (IPT)
and may not be more than the length of Phase Segment 1.
These parameters are defined in the PHASE1 and PHASE2 fields of the ”CAN Baudrate
Register”.
• INFORMATION PROCESSING TIME:
The Information Processing Time (IPT) is the time required for the logic to determine the bit level
of a sampled bit. The IPT begins at the sample point, is measured in TQ and is fixed at 2 TQ for
the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, PHASE SEG2 shall not be less than the IPT.
• SAMPLE POINT:
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The SAMPLE POINT is the point in time at which the bus level is read and interpreted as the
value of that respective bit. Its location is at the end of PHASE_SEG1.
• SJW: ReSynchronization Jump Width.
The ReSynchronization Jump Width defines the limit to the amount of lengthening or shortening
of the Phase Segments.
SJW is programmable to be the minimum of PHASE SEG1 and 4 TQ.
If the SMP field in the CAN_BR register is set, then the incoming bit stream is sampled three
times with a period of half a CAN clock period, centered on sample point.
In the CAN controller, the length of a bit on the CAN bus is determined by the parameters (BRP,
PROPAG, PHASE1 and PHASE2).
t BIT = t CSC + t PRS + t PHS1 + t PHS2
The time quantum is calculated as follows:
t CSC = ( BRP + 1 ) ⁄ MCK
Note: The BRP field must be within the range [1, 0x7F], i.e., BRP = 0 is not authorized.
t PRS = t CSC × ( PROPAG + 1 )
t PHS1 = t CSC × ( PHASE1 + 1 )
t PHS2 = t CSC × ( PHASE2 + 1 )
To compensate for phase shifts between clock oscillators of different controllers on the bus, the
CAN controller must resynchronize on any relevant signal edge of the current transmission. The
resynchronization shortens or lengthens the bit time so that the position of the sample point is
shifted with regard to the detected edge. The resynchronization jump width (SJW) defines the
maximum of time by which a bit period may be shortened or lengthened by resynchronization.
t SJW = t CSC × ( SJW + 1 )
Figure 40-5. CAN Bit Timing
MCK
CAN Clock
tCSC
tPRS
tPHS1
tPHS2
NOMINAL BIT TIME
SYNC_
SEG
PROP_SEG
PHASE_SEG1
PHASE_SEG2
Sample Point
Transmission Point
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Example of bit timing determination for CAN baudrate of 500 Kbit/s:
MCK = 48MHz
CAN baudrate= 500kbit/s => bit time= 2us
Delay of the bus driver: 50 ns
Delay of the receiver: 30ns
Delay of the bus line (20m): 110ns
The total number of time quanta in a bit time must be comprised between 8
and 25. If we fix the bit time to 16 time quanta:
Tcsc = 1 time quanta = bit time / 16 = 125 ns
=> BRP = (Tcsc x MCK) - 1 = 5
The propagation segment time is equal to twice the sum of the signal’s
propagation time on the bus line, the receiver delay and the output driver
delay:
Tprs = 2 * (50+30+110) ns = 380 ns = 3 Tcsc
=> PROPAG = Tprs/Tcsc - 1 = 2
The remaining time for the two phase segments is:
Tphs1 + Tphs2 = bit time - Tcsc - Tprs = (16 - 1 - 3)Tcsc
Tphs1 + Tphs2 = 12 Tcsc
Because this number is even, we choose Tphs2 = Tphs1 (else we would choose
Tphs2 = Tphs1 + Tcsc)
Tphs1 = Tphs2 = (12/2) Tcsc = 6 Tcsc
=> PHASE1 = PHASE2 = Tphs1/Tcsc - 1 = 5
The resynchronization jump width must be comprised between 1 Tcsc and the
minimum of 4 Tcsc and Tphs1. We choose its maximum value:
Tsjw = Min(4 Tcsc,Tphs1) = 4 Tcsc
=> SJW = Tsjw/Tcsc - 1 = 3
Finally: CAN_BR = 0x00053255
40.6.4.2
CAN Bus Synchronization
Two types of synchronization are distinguished: “hard synchronization” at the start of a frame
and “resynchronization” inside a frame. After a hard synchronization, the bit time is restarted
with the end of the SYNC_SEG segment, regardless of the phase error. Resynchronization
causes a reduction or increase in the bit time so that the position of the sample point is shifted
with respect to the detected edge.
The effect of resynchronization is the same as that of hard synchronization when the magnitude
of the phase error of the edge causing the resynchronization is less than or equal to the programmed value of the resynchronization jump width (tSJW).
When the magnitude of the phase error is larger than the resynchronization jump width and
• the phase error is positive, then PHASE_SEG1 is lengthened by an amount equal to the
resynchronization jump width.
• the phase error is negative, then PHASE_SEG2 is shortened by an amount equal to the
resynchronization jump width.
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Figure 40-6. CAN Resynchronization
THE PHASE ERROR IS POSITIVE
(the transmitter is slower than the receiver)
Nominal
Sample point
Sample point
after resynchronization
Received
data bit
Nominal bit time
(before resynchronization)
SYNC_
SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
Phase error (max Tsjw)
Phase error
Bit time with
resynchronization
SYNC_
SEG
SYNC_
SEG
PROP_SEG
PHASE_SEG1
THE PHASE ERROR IS NEGATIVE
(the transmitter is faster than the receiver)
PHASE_SEG2
Sample point
after resynchronization
SYNC_
SEG
Nominal
Sample point
Received
data bit
Nominal bit time
(before resynchronization)
PHASE_SEG2
SYNC_
SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
SYNC_
SEG
Phase error
Bit time with
resynchronization
PHASE_ SYNC_
SEG2 SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
SYNC_
SEG
Phase error (max Tsjw)
40.6.4.3
Autobaud Mode
The autobaud feature is enabled by setting the ABM field in the CAN_MR register. In this mode,
the CAN controller is only listening to the line without acknowledging the received messages. It
can not send any message. The errors flags are updated. The bit timing can be adjusted until no
error occurs (good configuration found). In this mode, the error counters are frozen. To go back
to the standard mode, the ABM bit must be cleared in the CAN_MR register.
40.6.4.4
Error Detection
There are five different error types that are not mutually exclusive. Each error concerns only specific fields of the CAN data frame (refer to the Bosch CAN specification for their
correspondence):
• CRC error (CERR bit in the CAN_SR register): With the CRC, the transmitter calculates a
checksum for the CRC bit sequence from the Start of Frame bit until the end of the Data
Field. This CRC sequence is transmitted in the CRC field of the Data or Remote Frame.
• Bit-stuffing error (SERR bit in the CAN_SR register): If a node detects a sixth consecutive
equal bit level during the bit-stuffing area of a frame, it generates an Error Frame starting with
the next bit-time.
• Bit error (BERR bit in CAN_SR register): A bit error occurs if a transmitter sends a dominant
bit but detects a recessive bit on the bus line, or if it sends a recessive bit but detects a
dominant bit on the bus line. An error frame is generated and starts with the next bit time.
• Form Error (FERR bit in the CAN_SR register): If a transmitter detects a dominant bit in one
of the fix-formatted segments CRC Delimiter, ACK Delimiter or End of Frame, a form error
has occurred and an error frame is generated.
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• Acknowledgment error (AERR bit in the CAN_SR register): The transmitter checks the
Acknowledge Slot, which is transmitted by the transmitting node as a recessive bit, contains a
dominant bit. If this is the case, at least one other node has received the frame correctly. If
not, an Acknowledge Error has occurred and the transmitter will start in the next bit-time an
Error Frame transmission.
40.6.4.5
Fault Confinement
To distinguish between temporary and permanent failures, every CAN controller has two error
counters: REC (Receive Error Counter) and TEC (Transmit Error Counter). The two counters
are incremented upon detected errors and are decremented upon correct transmissions or
receptions, respectively. Depending on the counter values, the state of the node changes: the
initial state of the CAN controller is Error Active, meaning that the controller can send Error
Active flags. The controller changes to the Error Passive state if there is an accumulation of
errors. If the CAN controller fails or if there is an extreme accumulation of errors, there is a state
transition to Bus Off.
Figure 40-7. Line Error Mode
Init
TEC < 127
and
REC < 127
ERROR
PASSIVE
ERROR
ACTIVE
TEC > 127
or
REC > 127
128 occurences of 11 consecutive recessive bits
or
CAN controller reset
BUS OFF
TEC > 255
An error active unit takes part in bus communication and sends an active error frame when the
CAN controller detects an error.
An error passive unit cannot send an active error frame. It takes part in bus communication, but
when an error is detected, a passive error frame is sent. Also, after a transmission, an error passive unit waits before initiating further transmission.
A bus off unit is not allowed to have any influence on the bus.
For fault confinement, two errors counters (TEC and REC) are implemented. These counters are
accessible via the CAN_ECR register. The state of the CAN controller is automatically updated
according to these counter values. If the CAN controller is in Error Active state, then the ERRA
bit is set in the CAN_SR register. The corresponding interrupt is pending while the interrupt is
not masked in the CAN_IMR register. If the CAN controller is in Error Passive Mode, then the
ERRP bit is set in the CAN_SR register and an interrupt remains pending while the ERRP bit is
set in the CAN_IMR register. If the CAN is in Bus Off Mode, then the BOFF bit is set in the
CAN_SR register. As for ERRP and ERRA, an interrupt is pending while the BOFF bit is set in
the CAN_IMR register.
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When one of the error counters values exceeds 96, an increased error rate is indicated to the
controller through the WARN bit in CAN_SR register, but the node remains error active. The corresponding interrupt is pending while the interrupt is set in the CAN_IMR register.
Refer to the Bosch CAN specification v2.0 for details on fault confinement.
40.6.4.6
Error Interrupt Handler
WARN, BOFF, ERRA and ERRP (CAN_SR) represent the current status of the CAN bus and
are not latched. They reflect the current TEC and REC (CAN_ECR) values as described in Section 40.6.4.5 “Fault Confinement” on page 742.
Based on that, if these bits are used as an interrupt, the user can enter into an interrupt and not
see the corresponding status register if the TEC and REC counter have changed their state.
When entering Bus Off Mode, the only way to exit from this state is 128 occurrences of 11 consecutive recessive bits or a CAN controller reset.
In Error Active Mode, the user reads:
• ERRA =1
• ERRP = 0
• BOFF = 0
In Error Passive Mode, the user reads:
• ERRA = 0
• ERRP =1
• BOFF = 0
In Bus Off Mode, the user reads:
• ERRA = 0
• ERRP =1
• BOFF =1
The CAN interrupt handler should do the following:
• Only enable one error mode interrupt at a time.
• Look at and check the REC and TEC values in the interrupt handler to determine the current
state.
40.6.4.7
Overload
The overload frame is provided to request a delay of the next data or remote frame by the
receiver node (“Request overload frame”) or to signal certain error conditions (“Reactive overload frame”) related to the intermission field respectively.
Reactive overload frames are transmitted after detection of the following error conditions:
• Detection of a dominant bit during the first two bits of the intermission field
• Detection of a dominant bit in the last bit of EOF by a receiver, or detection of a dominant bit
by a receiver or a transmitter at the last bit of an error or overload frame delimiter
The CAN controller can generate a request overload frame automatically after each message
sent to one of the CAN controller mailboxes. This feature is enabled by setting the OVL bit in the
CAN_MR register.
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Reactive overload frames are automatically handled by the CAN controller even if the OVL bit in
the CAN_MR register is not set. An overload flag is generated in the same way as an error flag,
but error counters do not increment.
40.6.5
Low-power Mode
In Low-power Mode, the CAN controller cannot send or receive messages. All mailboxes are
inactive.
In Low-power Mode, the SLEEP signal in the CAN_SR register is set; otherwise, the WAKEUP
signal in the CAN_SR register is set. These two fields are exclusive except after a CAN controller reset (WAKEUP and SLEEP are stuck at 0 after a reset). After power-up reset, the Lowpower Mode is disabled and the WAKEUP bit is set in the CAN_SR register only after detection
of 11 consecutive recessive bits on the bus.
40.6.5.1
Enabling Low-power Mode
A software application can enable Low-power Mode by setting the LPM bit in the CAN_MR
global register. The CAN controller enters Low-power Mode once all pending transmit messages
are sent.
When the CAN controller enters Low-power Mode, the SLEEP signal in the CAN_SR register is
set. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated
while SLEEP is set.
The SLEEP signal in the CAN_SR register is automatically cleared once WAKEUP is set. The
WAKEUP signal is automatically cleared once SLEEP is set.
Reception is disabled while the SLEEP signal is set to one in the CAN_SR register. It is important to note that those messages with higher priority than the last message transmitted can be
received between the LPM command and entry in Low-power Mode.
Once in Low-power Mode, the CAN controller clock can be switched off by programming the
chip’s Power Management Controller (PMC). The CAN controller drains only the static current.
Error counters are disabled while the SLEEP signal is set to one.
Thus, to enter Low-power Mode, the software application must:
– Set LPM field in the CAN_MR register
– Wait for SLEEP signal rising
Now the CAN Controller clock can be disabled. This is done by programming the Power Management Controller (PMC).
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Figure 40-8. Enabling Low-power Mode
Arbitration lost
Mailbox 1
CAN BUS
Mailbox 3
LPEN= 1
LPM
(CAN_MR)
SLEEP
(CAN_SR)
WAKEUP
(CAN_SR)
MRDY
(CAN_MSR1)
MRDY
(CAN_MSR3)
CAN_TIM
40.6.5.2
0x0
Disabling Low-power Mode
The CAN controller can be awake after detecting a CAN bus activity. Bus activity detection is
done by an external module that may be embedded in the chip. When it is notified of a CAN bus
activity, the software application disables Low-power Mode by programming the CAN controller.
To disable Low-power Mode, the software application must:
– Enable the CAN Controller clock. This is done by programming the Power
Management Controller (PMC).
– Clear the LPM field in the CAN_MR register
The CAN controller synchronizes itself with the bus activity by checking for eleven consecutive
“recessive” bits. Once synchronized, the WAKEUP signal in the CAN_SR register is set.
Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while
WAKEUP is set. The SLEEP signal in the CAN_SR register is automatically cleared once
WAKEUP is set. WAKEUP signal is automatically cleared once SLEEP is set.
If no message is being sent on the bus, then the CAN controller is able to send a message
eleven bit times after disabling Low-power Mode.
If there is bus activity when Low-power mode is disabled, the CAN controller is synchronized
with the bus activity in the next interframe. The previous message is lost (see Figure 40-9).
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Figure 40-9. Disabling Low-power Mode
Bus Activity Detected
CAN BUS
LPM
(CAN_MR)
Message lost
Message x
Interframe synchronization
SLEEP
(CAN_SR)
WAKEUP
(CAN_SR)
MRDY
(CAN_MSRx)
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40.7
40.7.1
Functional Description
CAN Controller Initialization
After power-up reset, the CAN controller is disabled. The CAN controller clock must be activated
by the Power Management Controller (PMC) and the CAN controller interrupt line must be
enabled by the interrupt controller (AIC).
The CAN controller must be initialized with the CAN network parameters. The CAN_BR register
defines the sampling point in the bit time period. CAN_BR must be set before the CAN controller
is enabled by setting the CANEN field in the CAN_MR register.
The CAN controller is enabled by setting the CANEN flag in the CAN_MR register. At this stage,
the internal CAN controller state machine is reset, error counters are reset to 0, error flags are
reset to 0.
Once the CAN controller is enabled, bus synchronization is done automatically by scanning
eleven recessive bits. The WAKEUP bit in the CAN_SR register is automatically set to 1 when
the CAN controller is synchronized (WAKEUP and SLEEP are stuck at 0 after a reset).
The CAN controller can start listening to the network in Autobaud Mode. In this case, the error
counters are locked and a mailbox may be configured in Receive Mode. By scanning error flags,
the CAN_BR register values synchronized with the network. Once no error has been detected,
the application disables the Autobaud Mode, clearing the ABM field in the CAN_MR register.
Figure 40-10. Possible Initialization Procedure
Enable CAN Controller Clock
(PMC)
Enable CAN Controller Interrupt Line
(AIC)
Configure a Mailbox in Reception Mode
Change CAN_BR value
(ABM == 1 and CANEN == 1)
Errors ?
Yes
(CAN_SR or CAN_MSRx)
No
ABM = 0 and CANEN = 0
CANEN = 1 (ABM == 0)
End of Initialization
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40.7.2
CAN Controller Interrupt Handling
There are two different types of interrupts. One type of interrupt is a message-object related
interrupt, the other is a system interrupt that handles errors or system-related interrupt sources.
All interrupt sources can be masked by writing the corresponding field in the CAN_IDR register.
They can be unmasked by writing to the CAN_IER register. After a power-up reset, all interrupt
sources are disabled (masked). The current mask status can be checked by reading the
CAN_IMR register.
The CAN_SR register gives all interrupt source states.
The following events may initiate one of the two interrupts:
• Message object interrupt
– Data registers in the mailbox object are available to the application. In Receive
Mode, a new message was received. In Transmit Mode, a message was transmitted
successfully.
– A sent transmission was aborted.
• System interrupts
– Bus off interrupt: The CAN module enters the bus off state.
– Error passive interrupt: The CAN module enters Error Passive Mode.
– Error Active Mode: The CAN module is neither in Error Passive Mode nor in Bus Off
mode.
– Warn Limit interrupt: The CAN module is in Error-active Mode, but at least one of its
error counter value exceeds 96.
– Wake-up interrupt: This interrupt is generated after a wake-up and a bus
synchronization.
– Sleep interrupt: This interrupt is generated after a Low-power Mode enable once all
pending messages in transmission have been sent.
– Internal timer counter overflow interrupt: This interrupt is generated when the
internal timer rolls over.
– Timestamp interrupt: This interrupt is generated after the reception or the
transmission of a start of frame or an end of frame. The value of the internal counter
is copied in the CAN_TIMESTP register.
All interrupts are cleared by clearing the interrupt source except for the internal timer counter
overflow interrupt and the timestamp interrupt. These interrupts are cleared by reading the
CAN_SR register.
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40.7.3
CAN Controller Message Handling
40.7.3.1
Receive Handling
Two modes are available to configure a mailbox to receive messages. In Receive Mode, the
first message received is stored in the mailbox data register. In Receive with Overwrite Mode,
the last message received is stored in the mailbox.
40.7.3.2
Simple Receive Mailbox
A mailbox is in Receive Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance Mask must be set before the Receive Mode is
enabled.
After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically
cleared until the first message is received. When the first message has been accepted by the
mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set.
This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register.
Message data are stored in the mailbox data register until the software application notifies that
data processing has ended. This is done by asking for a new transfer command, setting the
MTCR flag in the CAN_MCRx register. This automatically clears the MRDY signal.
The MMI flag in the CAN_MSRx register notifies the software that a message has been lost by
the mailbox. This flag is set when messages are received while MRDY is set in the CAN_MSRx
register. This flag is cleared by reading the CAN_MSRs register. A receive mailbox prevents
from overwriting the first message by new ones while MRDY flag is set in the CAN_MSRx register. See Figure 40-11.
Figure 40-11. Receive Mailbox
Message ID = CAN_MIDx
CAN BUS
Message 1
Message 2 lost
Message 3
MRDY
(CAN_MSRx)
MMI
(CAN_MSRx)
(CAN_MDLx
CAN_MDHx)
Message 1
Message 3
MTCR
(CAN_MCRx)
Reading CAN_MSRx
Reading CAN_MDHx & CAN_MDLx
Writing CAN_MCRx
Note:
In the case of ARM architecture, CAN_MSRx, CAN_MDLx, CAN_MDHx can be read using an optimized ldm assembler
instruction.
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40.7.3.3
Receive with Overwrite Mailbox
A mailbox is in Receive with Overwrite Mode once the MOT field in the CAN_MMRx register has
been configured. Message ID and Message Acceptance masks must be set before Receive
Mode is enabled.
After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically
cleared until the first message is received. When the first message has been accepted by the
mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set.
This interrupt is masked depending on the mailbox flag in the CAN_IMR global register.
If a new message is received while the MRDY flag is set, this new message is stored in the mailbox data register, overwriting the previous message. The MMI flag in the CAN_MSRx register
notifies the software that a message has been dropped by the mailbox. This flag is cleared when
reading the CAN_MSRx register.
The CAN controller may store a new message in the CAN data registers while the application
reads them. To check that CAN_MDHx and CAN_MDLx do not belong to different messages,
the application must check the MMI field in the CAN_MSRx register before and after reading
CAN_MDHx and CAN_MDLx. If the MMI flag is set again after the data registers have been
read, the software application has to re-read CAN_MDHx and CAN_MDLx (see Figure 40-12).
Figure 40-12. Receive with Overwrite Mailbox
Message ID = CAN_MIDx
CAN BUS
Message 1
Message 2
Message 3
Message 4
MRDY
(CAN_MSRx)
MMI
(CAN_MSRx)
(CAN_MDLx
CAN_MDHx)
Message 1
Message 2
Message 3
Message 4
MTCR
(CAN_MCRx)
Reading CAN_MSRx
Reading CAN_MDHx & CAN_MDLx
Writing CAN_MCRx
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40.7.3.4
Chaining Mailboxes
Several mailboxes may be used to receive a buffer split into several messages with the same ID.
In this case, the mailbox with the lowest number is serviced first. In the receive and receive with
overwrite modes, the field PRIOR in the CAN_MMRx register has no effect. If Mailbox 0 and
Mailbox 5 accept messages with the same ID, the first message is received by Mailbox 0 and the
second message is received by Mailbox 5. Mailbox 0 must be configured in Receive Mode (i.e.,
the first message received is considered) and Mailbox 5 must be configured in Receive with
Overwrite Mode. Mailbox 0 cannot be configured in Receive with Overwrite Mode; otherwise, all
messages are accepted by this mailbox and Mailbox 5 is never serviced.
If several mailboxes are chained to receive a buffer split into several messages, all mailboxes
except the last one (with the highest number) must be configured in Receive Mode. The first
message received is handled by the first mailbox, the second one is refused by the first mailbox
and accepted by the second mailbox, the last message is accepted by the last mailbox and
refused by previous ones (see Figure 40-13).
Figure 40-13. Chaining Three Mailboxes to Receive a Buffer Split into Three Messages
Buffer split in 3 messages
CAN BUS
Message s1
Message s2
Message s3
MRDY
(CAN_MSRx)
MMI
(CAN_MSRx)
MRDY
(CAN_MSRy)
MMI
(CAN_MSRy)
MRDY
(CAN_MSRz)
MMI
(CAN_MSRz)
Reading CAN_MSRx, CAN_MSRy and CAN_MSRz
Reading CAN_MDH & CAN_MDL for mailboxes x, y and z
Writing MBx MBy MBz in CAN_TCR
If the number of mailboxes is not sufficient (the MMI flag of the last mailbox raises), the user
must read each data received on the last mailbox in order to retrieve all the messages of the buffer split (see Figure 40-14).
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Figure 40-14. Chaining Three Mailboxes to Receive a Buffer Split into Four Messages
Buffer split in 4 messages
CAN BUS
Message s1
Message s2
Message s3
Message s4
MRDY
(CAN_MSRx)
MMI
(CAN_MSRx)
MRDY
(CAN_MSRy)
MMI
(CAN_MSRy)
MRDY
(CAN_MSRz)
MMI
(CAN_MSRz)
Reading CAN_MSRx, CAN_MSRy and CAN_MSRz
Reading CAN_MDH & CAN_MDL for mailboxes x, y and z
Writing MBx MBy MBz in CAN_TCR
40.7.3.5
Transmission Handling
A mailbox is in Transmit Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance mask must be set before Receive Mode is enabled.
After Transmit Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set
until the first command is sent. When the MRDY flag is set, the software application can prepare
a message to be sent by writing to the CAN_MDx registers. The message is sent once the software asks for a transfer command setting the MTCR bit and the message data length in the
CAN_MCRx register.
The MRDY flag remains at zero as long as the message has not been sent or aborted. It is
important to note that no access to the mailbox data register is allowed while the MRDY flag is
cleared. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be
masked depending on the mailbox flag in the CAN_IMR global register.
It is also possible to send a remote frame setting the MRTR bit instead of setting the MDLC field.
The answer to the remote frame is handled by another reception mailbox. In this case, the
device acts as a consumer but with the help of two mailboxes. It is possible to handle the remote
frame emission and the answer reception using only one mailbox configured in Consumer Mode.
Refer to the section “Remote Frame Handling” on page 753.
Several messages can try to win the bus arbitration in the same time. The message with the
highest priority is sent first. Several transfer request commands can be generated at the same
time by setting MBx bits in the CAN_TCR register. The priority is set in the PRIOR field of the
CAN_MMRx register. Priority 0 is the highest priority, priority 15 is the lowest priority. Thus it is
possible to use a part of the message ID to set the PRIOR field. If two mailboxes have the same
priority, the message of the mailbox with the lowest number is sent first. Thus if mailbox 0 and
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mailbox 5 have the same priority and have a message to send at the same time, then the message of the mailbox 0 is sent first.
Setting the MACR bit in the CAN_MCRx register aborts the transmission. Transmission for several mailboxes can be aborted by writing MBx fields in the CAN_MACR register. If the message
is being sent when the abort command is set, then the application is notified by the MRDY bit set
and not the MABT in the CAN_MSRx register. Otherwise, if the message has not been sent,
then the MRDY and the MABT are set in the CAN_MSR register.
When the bus arbitration is lost by a mailbox message, the CAN controller tries to win the next
bus arbitration with the same message if this one still has the highest priority. Messages to be
sent are re-tried automatically until they win the bus arbitration. This feature can be disabled by
setting the bit DRPT in the CAN_MR register. In this case if the message was not sent the first
time it was transmitted to the CAN transceiver, it is automatically aborted. The MABT flag is set
in the CAN_MSRx register until the next transfer command.
Figure 40-15 shows three MBx message attempts being made (MRDY of MBx set to 0).
The first MBx message is sent, the second is aborted and the last one is trying to be aborted but
too late because it has already been transmitted to the CAN transceiver.
Figure 40-15. Transmitting Messages
CAN BUS
MBx message
MBx message
MRDY
(CAN_MSRx)
MABT
(CAN_MSRx)
MTCR
(CAN_MCRx)
MACR
(CAN_MCRx)
Abort MBx message
Try to Abort MBx message
Reading CAN_MSRx
Writing CAN_MDHx &
CAN_MDLx
40.7.3.6
Remote Frame Handling
Producer/consumer model is an efficient means of handling broadcasted messages. The push
model allows a producer to broadcast messages; the pull model allows a customer to ask for
messages.
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Figure 40-16. Producer / Consumer Model
Producer
Request
PUSH MODEL
CAN Data Frame
Consumer
Indication(s)
PULL MODEL
Producer
Indications
Response
Consumer
CAN Remote Frame
Request(s)
CAN Data Frame
Confirmation(s)
In Pull Mode, a consumer transmits a remote frame to the producer. When the producer
receives a remote frame, it sends the answer accepted by one or many consumers. Using transmit and receive mailboxes, a consumer must dedicate two mailboxes, one in Transmit Mode to
send remote frames, and at least one in Receive Mode to capture the producer’s answer. The
same structure is applicable to a producer: one reception mailbox is required to get the remote
frame and one transmit mailbox to answer.
Mailboxes can be configured in Producer or Consumer Mode. A lonely mailbox can handle the
remote frame and the answer. With 16 mailboxes, the CAN controller can handle 16 independent producers/consumers.
40.7.3.7
Producer Configuration
A mailbox is in Producer Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is
enabled.
After Producer Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set
until the first transfer command. The software application prepares data to be sent by writing to
the CAN_MDHx and the CAN_MDLx registers, then by setting the MTCR bit in the CAN_MCRx
register. Data is sent after the reception of a remote frame as soon as it wins the bus arbitration.
The MRDY flag remains at zero as long as the message has not been sent or aborted. No
access to the mailbox data register can be done while MRDY flag is cleared. An interrupt is
pending for the mailbox while the MRDY flag is set. This interrupt can be masked according to
the mailbox flag in the CAN_IMR global register.
If a remote frame is received while no data are ready to be sent (signal MRDY set in the
CAN_MSRx register), then the MMI signal is set in the CAN_MSRx register. This bit is cleared
by reading the CAN_MSRx register.
The MRTR field in the CAN_MSRx register has no meaning. This field is used only when using
Receive and Receive with Overwrite modes.
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After a remote frame has been received, the mailbox functions like a transmit mailbox. The message with the highest priority is sent first. The transmitted message may be aborted by setting
the MACR bit in the CAN_MCR register. Please refer to the section “Transmission Handling” on
page 752.
Figure 40-17. Producer Handling
Remote Frame
CAN BUS
Message 1
Remote Frame
Remote Frame
Message 2
MRDY
(CAN_MSRx)
MMI
(CAN_MSRx)
Reading CAN_MSRx
MTCR
(CAN_MCRx)
(CAN_MDLx
CAN_MDHx)
40.7.3.8
Message 1
Message 2
Consumer Configuration
A mailbox is in Consumer Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is
enabled.
After Consumer Mode is enabled, the MRDY flag in the CAN_MSR register is automatically
cleared until the first transfer request command. The software application sends a remote frame
by setting the MTCR bit in the CAN_MCRx register or the MBx bit in the global CAN_TCR register. The application is notified of the answer by the MRDY flag set in the CAN_MSRx register.
The application can read the data contents in the CAN_MDHx and CAN_MDLx registers. An
interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked
according to the mailbox flag in the CAN_IMR global register.
The MRTR bit in the CAN_MCRx register has no effect. This field is used only when using
Transmit Mode.
After a remote frame has been sent, the consumer mailbox functions as a reception mailbox.
The first message received is stored in the mailbox data registers. If other messages intended
for this mailbox have been sent while the MRDY flag is set in the CAN_MSRx register, they will
be lost. The application is notified by reading the MMI field in the CAN_MSRx register. The read
operation automatically clears the MMI flag.
If several messages are answered by the Producer, the CAN controller may have one mailbox in
consumer configuration, zero or several mailboxes in Receive Mode and one mailbox in Receive
with Overwrite Mode. In this case, the consumer mailbox must have a lower number than the
Receive with Overwrite mailbox. The transfer command can be triggered for all mailboxes at the
same time by setting several MBx fields in the CAN_TCR register.
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Figure 40-18. Consumer Handling
Remote Frame
CAN BUS
Message x
Remote Frame
Message y
MRDY
(CAN_MSRx)
MMI
(CAN_MSRx)
MTCR
(CAN_MCRx)
(CAN_MDLx
CAN_MDHx)
40.7.4
Message y
Message x
CAN Controller Timing Modes
Using the free running 16-bit internal timer, the CAN controller can be set in one of the two following timing modes:
• Timestamping Mode: The value of the internal timer is captured at each Start Of Frame or
each End Of Frame.
• Time Triggered Mode: The mailbox transfer operation is triggered when the internal timer
reaches the mailbox trigger.
Timestamping Mode is enabled by clearing the TTM bit in the CAN_MR register. Time Triggered
Mode is enabled by setting the TTM bit in the CAN_MR register.
40.7.4.1
Timestamping Mode
Each mailbox has its own timestamp value. Each time a message is sent or received by a mailbox, the 16-bit value MTIMESTAMP of the CAN_TIMESTP register is transferred to the LSB bits
of the CAN_MSRx register. The value read in the CAN_MSRx register corresponds to the internal timer value at the Start Of Frame or the End Of Frame of the message handled by the
mailbox.
Figure 40-19. Mailbox Timestamp
Start of Frame
CAN BUS
Message 1
End of Frame
Message 2
CAN_TIM
TEOF
(CAN_MR)
TIMESTAMP
(CAN_TSTP)
Timestamp 1
MTIMESTAMP
(CAN_MSRx)
Timestamp 1
MTIMESTAMP
(CAN_MSRy)
Timestamp 2
Timestamp 2
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40.7.4.2
Time Triggered Mode
In Time Triggered Mode, basic cycles can be split into several time windows. A basic cycle starts
with a reference message. Each time a window is defined from the reference message, a transmit operation should occur within a pre-defined time window. A mailbox must not win the
arbitration in a previous time window, and it must not be retried if the arbitration is lost in the time
window.
Figure 40-20. Time Triggered Principle
Time Cycle
Reference
Message
Reference
Message
Time Windows for Messages
Global Time
Time Trigger Mode is enabled by setting the TTM field in the CAN_MR register. In Time Triggered Mode, as in Timestamp Mode, the CAN_TIMESTP field captures the values of the internal
counter, but the MTIMESTAMP fields in the CAN_MSRx registers are not active and are read at
0.
40.7.4.3
Synchronization by a Reference Message
In Time Triggered Mode, the internal timer counter is automatically reset when a new message
is received in the last mailbox. This reset occurs after the reception of the End Of Frame on the
rising edge of the MRDY signal in the CAN_MSRx register. This allows synchronization of the
internal timer counter with the reception of a reference message and the start a new time
window.
40.7.4.4
Transmitting within a Time Window
A time mark is defined for each mailbox. It is defined in the 16-bit MTIMEMARK field of the
CAN_MMRx register. At each internal timer clock cycle, the value of the CAN_TIM is compared
with each mailbox time mark. When the internal timer counter reaches the MTIMEMARK value,
an internal timer event for the mailbox is generated for the mailbox.
In Time Triggered Mode, transmit operations are delayed until the internal timer event for the
mailbox. The application prepares a message to be sent by setting the MTCR in the CAN_MCRx
register. The message is not sent until the CAN_TIM value is less than the MTIMEMARK value
defined in the CAN_MMRx register.
If the transmit operation is failed, i.e., the message loses the bus arbitration and the next transmit attempt is delayed until the next internal time trigger event. This prevents overlapping the
next time window, but the message is still pending and is retried in the next time window when
CAN_TIM value equals the MTIMEMARK value. It is also possible to prevent a retry by setting
the DRPT field in the CAN_MR register.
40.7.4.5
Freezing the Internal Timer Counter
The internal counter can be frozen by setting TIMFRZ in the CAN_MR register. This prevents an
unexpected roll-over when the counter reaches FFFFh. When this occurs, it automatically
freezes until a new reset is issued, either due to a message received in the last mailbox or any
other reset counter operations. The TOVF bit in the CAN_SR register is set when the counter is
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frozen. The TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register.
Depending on the corresponding interrupt mask in the CAN_IMR register, an interrupt is generated when TOVF is set.
Figure 40-21. Time Triggered Operations
Message x
Arbitration Lost
End of Frame
CAN BUS
Reference
Message
Message y
Arbitration Win
Message y
Internal Counter Reset
CAN_TIM
Cleared by software
MRDY
(CAN_MSRlast_mailbox_number)
Timer Event x
MTIMEMARKx == CAN_TIM
MRDY
(CAN_MSRx)
MTIMEMARKy == CAN_TIM
Timer Event y
MRDY
(CAN_MSRy)
Time Window
Basic Cycle
Message x
Arbitration Win
End of Frame
CAN BUS
Reference
Message
Message x
Internal Counter Reset
CAN_TIM
Cleared by software
MRDY
(CAN_MSRlast_mailbox_number)
Timer Event x
MTIMEMARKx == CAN_TIM
MRDY
(CAN_MSRx)
Time Window
Basic Cycle
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40.8
Controller Area Network (CAN) User Interface
Table 40-4.
Register Mapping
Offset
Register
Name
Access
Reset
0x0000
Mode Register
CAN_MR
Read-write
0x0
0x0004
Interrupt Enable Register
CAN_IER
Write-only
-
0x0008
Interrupt Disable Register
CAN_IDR
Write-only
-
0x000C
Interrupt Mask Register
CAN_IMR
Read-only
0x0
0x0010
Status Register
CAN_SR
Read-only
0x0
0x0014
Baudrate Register
CAN_BR
Read-write
0x0
0x0018
Timer Register
CAN_TIM
Read-only
0x0
0x001C
Timestamp Register
CAN_TIMESTP
Read-only
0x0
0x0020
Error Counter Register
CAN_ECR
Read-only
0x0
0x0024
Transfer Command Register
CAN_TCR
Write-only
-
0x0028
Abort Command Register
CAN_ACR
Write-only
-
–
–
–
CAN_MMR
Read-write
0x0
0x0100 - 0x01FC
Reserved
(2)
0x0200 + mb_num * 0x20 + 0x00
Mailbox Mode Register
0x0200 + mb_num * 0x20 + 0x04
Mailbox Acceptance Mask Register
CAN_MAM
Read-write
0x0
0x0200 + mb_num * 0x20 + 0x08
Mailbox ID Register
CAN_MID
Read-write
0x0
0x0200 + mb_num * 0x20 + 0x0C
Mailbox Family ID Register
CAN_MFID
Read-only
0x0
0x0200 + mb_num * 0x20 + 0x10
Mailbox Status Register
CAN_MSR
Read-only
0x0
0x0200 + mb_num * 0x20 + 0x14
Mailbox Data Low Register
CAN_MDL
Read-write
0x0
0x0200 + mb_num * 0x20 + 0x18
Mailbox Data High Register
CAN_MDH
Read-write
0x0
0x0200 + mb_num * 0x20 + 0x1C
Mailbox Control Register
CAN_MCR
Write-only
-
2. Mailbox number ranges from 0 to 15.
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40.8.1
Name:
CAN Mode Register
CAN_MR
Address:
0xFFFAC000
Access:
Read-write
31
–
30
–
29
–
28
–
27
–
26
25
24
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
DRPT
6
TIMFRZ
5
TTM
4
TEOF
3
OVL
2
ABM
1
LPM
0
CANEN
• CANEN: CAN Controller Enable
0 = The CAN Controller is disabled.
1 = The CAN Controller is enabled.
• LPM: Disable/Enable Low Power Mode
w Power Mode.
1 = Enable Low Power M
CAN controller enters Low Power Mode once all pending messages have been transmitted.
• ABM: Disable/Enable Autobaud/Listen mode
0 = Disable Autobaud/listen mode.
1 = Enable Autobaud/listen mode.
• OVL: Disable/Enable Overload Frame
0 = No overload frame is generated.
1 = An overload frame is generated after each successful reception for mailboxes configured in Receive with/without overwrite Mode, Producer and Consumer.
• TEOF: Timestamp messages at each end of Frame
0 = The value of CAN_TIM is captured in the CAN_TIMESTP register at each Start Of Frame.
1 = The value of CAN_TIM is captured in the CAN_TIMESTP register at each End Of Frame.
• TTM: Disable/Enable Time Triggered Mode
0 = Time Triggered Mode is disabled.
1 = Time Triggered Mode is enabled.
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• TIMFRZ: Enable Timer Freeze
0 = The internal timer continues to be incremented after it reached 0xFFFF.
1 = The internal timer stops incrementing after reaching 0xFFFF. It is restarted after a timer reset. See “Freezing the Internal Timer Counter” on page 757.
• DRPT: Disable Repeat
0 = When a transmit mailbox loses the bus arbitration, the transfer request remains pending.
1 = When a transmit mailbox lose the bus arbitration, the transfer request is automatically aborted. It automatically raises
the MABT and MRDT flags in the corresponding CAN_MSRx.
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40.8.2
Name:
CAN Interrupt Enable Register
CAN_IER
Address:
0xFFFAC004
Access:
Write-only
31
–
30
–
29
–
28
BERR
27
FERR
26
AERR
25
SERR
24
CERR
23
TSTP
22
TOVF
21
WAKEUP
20
SLEEP
19
BOFF
18
ERRP
17
WARN
16
ERRA
15
MB15
14
MB14
13
MB13
12
MB12
11
MB11
10
MB10
9
MB9
8
MB8
7
MB7
6
MB6
5
MB5
4
MB4
3
MB3
2
MB2
1
MB1
0
MB0
• MBx: Mailbox x Interrupt Enable
0 = No effect.
1 = Enable Mailbox x interrupt.
• ERRA: Error Active Mode Interrupt Enable
0 = No effect.
1 = Enable ERRA interrupt.
• WARN: Warning Limit Interrupt Enable
0 = No effect.
1 = Enable WARN interrupt.
• ERRP: Error Passive Mode Interrupt Enable
0 = No effect.
1 = Enable ERRP interrupt.
• BOFF: Bus Off Mode Interrupt Enable
0 = No effect.
1 = Enable BOFF interrupt.
• SLEEP: Sleep Interrupt Enable
0 = No effect.
1 = Enable SLEEP interrupt.
• WAKEUP: Wakeup Interrupt Enable
0 = No effect.
1 = Enable SLEEP interrupt.
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• TOVF: Timer Overflow Interrupt Enable
0 = No effect.
1 = Enable TOVF interrupt.
• TSTP: TimeStamp Interrupt Enable
0 = No effect.
1 = Enable TSTP interrupt.
• CERR: CRC Error Interrupt Enable
0 = No effect.
1 = Enable CRC Error interrupt.
• SERR: Stuffing Error Interrupt Enable
0 = No effect.
1 = Enable Stuffing Error interrupt.
• AERR: Acknowledgment Error Interrupt Enable
0 = No effect.
1 = Enable Acknowledgment Error interrupt.
• FERR: Form Error Interrupt Enable
0 = No effect.
1 = Enable Form Error interrupt.
• BERR: Bit Error Interrupt Enable
0 = No effect.
1 = Enable Bit Error interrupt.
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40.8.3
Name:
CAN Interrupt Disable Register
CAN_IDR
Address:
0xFFFAC008
Access:
Write-only
31
–
30
–
29
–
28
BERR
27
FERR
26
AERR
25
SERR
24
CERR
23
TSTP
22
TOVF
21
WAKEUP
20
SLEEP
19
BOFF
18
ERRP
17
WARN
16
ERRA
15
MB15
14
MB14
13
MB13
12
MB12
11
MB11
10
MB10
9
MB9
8
MB8
7
MB7
6
MB6
5
MB5
4
MB4
3
MB3
2
MB2
1
MB1
0
MB0
• MBx: Mailbox x Interrupt Disable
0 = No effect.
1 = Disable Mailbox x interrupt.
• ERRA: Error Active Mode Interrupt Disable
0 = No effect.
1 = Disable ERRA interrupt.
• WARN: Warning Limit Interrupt Disable
0 = No effect.
1 = Disable WARN interrupt.
• ERRP: Error Passive Mode Interrupt Disable
0 = No effect.
1 = Disable ERRP interrupt.
• BOFF: Bus Off Mode Interrupt Disable
0 = No effect.
1 = Disable BOFF interrupt.
• SLEEP: Sleep Interrupt Disable
0 = No effect.
1 = Disable SLEEP interrupt.
• WAKEUP: Wakeup Interrupt Disable
0 = No effect.
1 = Disable WAKEUP interrupt.
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• TOVF: Timer Overflow Interrupt
0 = No effect.
1 = Disable TOVF interrupt.
• TSTP: TimeStamp Interrupt Disable
0 = No effect.
1 = Disable TSTP interrupt.
• CERR: CRC Error Interrupt Disable
0 = No effect.
1 = Disable CRC Error interrupt.
• SERR: Stuffing Error Interrupt Disable
0 = No effect.
1 = Disable Stuffing Error interrupt.
• AERR: Acknowledgment Error Interrupt Disable
0 = No effect.
1 = Disable Acknowledgment Error interrupt.
• FERR: Form Error Interrupt Disable
0 = No effect.
1 = Disable Form Error interrupt.
• BERR: Bit Error Interrupt Disable
0 = No effect.
1 = Disable Bit Error interrupt.
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40.8.4
Name:
CAN Interrupt Mask Register
CAN_IMR
Address:
0xFFFAC00C
Access:
Read-only
31
–
30
–
29
–
28
BERR
27
FERR
26
AERR
25
SERR
24
CERR
23
TSTP
22
TOVF
21
WAKEUP
20
SLEEP
19
BOFF
18
ERRP
17
WARN
16
ERRA
15
MB15
14
MB14
13
MB13
12
MB12
11
MB11
10
MB10
9
MB9
8
MB8
7
MB7
6
MB6
5
MB5
4
MB4
3
MB3
2
MB2
1
MB1
0
MB0
• MBx: Mailbox x Interrupt Mask
0 = Mailbox x interrupt is disabled.
1 = Mailbox x interrupt is enabled.
• ERRA: Error Active Mode Interrupt Mask
0 = ERRA interrupt is disabled.
1 = ERRA interrupt is enabled.
• WARN: Warning Limit Interrupt Mask
0 = Warning Limit interrupt is disabled.
1 = Warning Limit interrupt is enabled.
• ERRP: Error Passive Mode Interrupt Mask
0 = ERRP interrupt is disabled.
1 = ERRP interrupt is e