Fractional-N Frequency Synthesizer ADF4154 FEATURES GENERAL DESCRIPTION RF bandwidth 500 MHz to 4 GHz 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable dual-modulus prescaler 4/5, 8/9 Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with the ADF4110/ADF4111/ ADF4112/ADF4113, ADF4106 and ADF4153 Programmable modulus on fractional-N synthesizer Trade-off noise versus spurious performance Fast-lock mode with built-in timer The ADF4154 is a fractional-N frequency synthesizer that implements local oscillators in the up conversion and down conversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). In addition, the 4-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a voltage controlled oscillator (VCO). APPLICATIONS A key feature of the ADF4154 is the fast-lock mode with a builtin timer. The user can program a predetermined count-down time value so that the PLL will remain in wide bandwidth mode, instead of having to control this time externally. CATV equipment Base stations for mobile radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs Communications test equipment Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V, and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP SDVDD RSET REFERENCE 4-BIT R COUNTER ×2 DOUBLER + PHASE FREQUENCY DETECTOR – CHARGE PUMP HIGH Z DGND LOCK DETECT MUXOUT OUTPUT MUX VDD RDIV CURRENT SETTING FAST-LOCK SWITCH RFCP3 RFCP2 RFCP1 NDIV RFINA N COUNTER RFINB THIRD ORDER FRACTIONAL INTERPOLATOR CLOCK DATA LE CP VDD FRACTION REG 24-BIT DATA REGISTER MODULUS REG INTEGER REG P = 4/5 OR 8/9 B = 9 BITS; A = 3 BITS ADF4154 AGND DGND CPGND 04833-0-001 REFIN Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADF4154 TABLE OF CONTENTS Specifications..................................................................................... 3 R-Divider Register, R1 ............................................................... 15 Timing Characteristics..................................................................... 4 Control Register, R2 ................................................................... 15 Absolute Maximum Ratings............................................................ 5 Noise and Spur Register, R3 ...................................................... 16 ESD Caution.................................................................................. 5 Reserved Bits............................................................................... 16 Pin Configuration and Pin Function Descriptions...................... 6 RF Synthesizer: A Worked Example ........................................ 16 Typical Performance Characteristics ............................................. 7 Modulus....................................................................................... 17 Circuit Description........................................................................... 9 Reference Doubler and Reference Divider ............................. 17 Reference Input Section............................................................... 9 12-Bit Programmable Modulus................................................ 17 RF Input Stage............................................................................... 9 Spurious Optimization and Fast-lock...................................... 17 RF INT Divider............................................................................. 9 Fast-Lock Timer and Register Sequences ............................... 17 INT, FRAC, MOD, and R Relationship...................................... 9 Fast-Lock: A Worked Example ................................................. 18 RF R Counter ................................................................................ 9 Fast-Lock: Loop Filter Topology .............................................. 18 Phase Frequency Detector (PFD) and Charge Pump.............. 9 Spurious Signals.......................................................................... 18 MUXOUT and Lock Detect...................................................... 10 Filter Design—ADIsimPLL....................................................... 18 Input Shift Registers ................................................................... 10 Interfacing ................................................................................... 18 Program Modes .......................................................................... 10 PCB Design Guidelines for Chip Scale Package .................... 19 Registers ........................................................................................... 11 Outline Dimensions ....................................................................... 20 Register Definition ..................................................................... 15 Ordering Guide .......................................................................... 20 Rev. 0 | Page 2 of 20 ADF4154 SPECIFICATIONS Table 1. AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. The operating temperature for the B version is −40°C to +80°C. Parameter RF CHARACTERISTICS (3 V) RF Input Frequency (RFIN)1 REFERENCE CHARACTERISTICS REFIN Input Frequency1 REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency2 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD, SDVDD VP IDD3 Low Power Sleep Mode NOISE CHARACTERISTICS Phase Noise Figure of Merit4 ADF4154 Phase Noise Floor5 Phase Noise Performance6 1750 MHz Output7 B Version Unit Test Conditions/Comments 0.5/4.0 1.0/4.0 GHz min/max GHz min/max See Figure 18 for input circuit. −8 dBm/0 dBm min/max. For lower frequencies, ensure slew rate > 396 V/µs. −10 dBm/0 dBm min/max. See Figure 17 for input circuit. 10/250 MHz min/max For f < 10 MHz, use a dc-coupled, CMOS compatible square wave, slew rate > 21 V/µs. 0.7/AVDD AC-coupled. 0 to AVDD 10 ±100 V p-p min/max V max pF max µA max 32 MHz max 5 312.5 2.5 1.5/10 1 2 2 2 mA typ µA typ % typ kΩ min/max nA typ % typ % typ % typ 1.4 0.6 ±1 10 V min V max µA max pF max 1.4 0.4 V min V max 2.7/3.3 AVDD AVDD/5.5 24 1 V min/V max V min/V max mA max µA typ −213 −143 −139 dBc/Hz typ dBc/Hz typ dBc/Hz typ −102 dBc/Hz typ CMOS compatible. Programmable. See Table 5. With RSET = 5.1 kΩ. With RSET = 5.1 kΩ. Sink and source current. 0.5 V < VCP < VP – 0.5. 0.5 V < VCP < VP – 0.5. VCP = VP/2. Open-drain 1 kΩ pull-up to 1.8 V. IOL = 500 µA. 20 mA typical. @ 10 MHz PFD frequency. @ 26 MHz PFD frequency. @ VCO output. @ 1 kHz offset, 26 MHz PFD frequency. 1 Use a square wave for frequencies below fMIN. Guaranteed by design. Sample tested to ensure compliance. 3 AC coupling ensures AVDD/2 bias. See Figure 17 for typical circuit. 4 This figure can be used to calculate phase noise for any application. Use the formula –213 + 10log(fPFD) + 20logN to calculate in-band phase noise performance, as seen at the VCO output. The value given is the lowest noise mode. 5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N-divider value). The value given is the lowest noise mode. 6 The phase noise is measured with the EVAL-ADF4154EB1 evaluation board and the HP8562E spectrum analyzer. 7 fREFIN = 26 MHz; fPFD = 26 MHz; offset frequency = 1 kHz; RFOUT = 1750 MHz; loop B/W = 20 kHz; lowest noise mode. 2 Rev. 0 | Page 3 of 20 ADF4154 TIMING CHARACTERISTICS Table 2. AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Parameter1 t1 t2 t3 t4 t5 t6 t7 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE Setup Time DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulse Width Guaranteed by design, but not production tested. t4 t5 CLOCK t2 DATA DB23 (MSB) t3 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 t6 04833-0-026 1 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 LE Figure 2. Timing Diagram Rev. 0 | Page 4 of 20 ADF4154 ABSOLUTE MAXIMUM RATINGS Table 3. Absolute Maximum Ratings.1, 2, 3 TA = 25°C, unless otherwise noted. Parameter VDD to GND VDD to VDD VP to GND VP to VDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFIN to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance LFCSP θJA Thermal Impedance (Paddle Soldered) LFCSP θJA Thermal Impedance (Paddle Not Soldered) Lead Temperature, Soldering Vapor Phase (60 sec) Infrared Rating −0.3 V to +4 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to +5.8 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +85°C −65°C to +150°C 150°C 150.4°C/W 122°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 This device is a high performance RF integrated circuit with an ESD rating of < 2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 2 GND = AGND = DGND = 0 V. 3 VDD = AVDD = DVDD = SDVDD. 216°C/W 215°C 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 20 ADF4154 16 VP CP 2 15 DVDD CPGND 3 14 MUXOUT ADF4154 CPGND AGND AGND RFINB RFINA LE TOP VIEW RFINB 5 (Not to Scale) 12 DATA 11 CLK RFINA 6 13 10 SDVDD REFIN 8 9 DGND 1 2 3 4 5 PIN 1 INDICATOR ADF4154 TOP VIEW 15 MUXOUT 14 LE 13 DATA 12 CLK 11 SDVDD AVDD 6 AVDD 7 REFIN 8 DGND 9 DGND 10 AVDD 7 04833-0-002 AGND 4 Figure 3. TSSOP Pin Configuration 04833-0-003 RSET 1 20 CP 19 RSET 18 VP 17 DVDD 16 DVDD PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS Figure 4. LFCSP Pin Configuration Table 4. Pin Function Descriptions TSSOP 1 LFCSP 19 Mnemonic RSET Description Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relationship between ICP and RSET is I CP max = 2 20 CP 3 4 5 1 2, 3 4 CPGND AGND RFINB 6 7 5 6, 7 RFINA AVDD 8 8 REFIN 9 10 9, 10 11 DGND SDVDD 11 12 CLK 12 13 DATA 13 14 LE 14 15 MUXOUT 15 16, 17 DVDD 16 18 VP 25.5 RSET where RSET = 5.1 kΩ and ICPmax = 5 mA. Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the external VCO. Charge Pump Ground. This is the ground return path for the charge pump. Analog Ground. This is the ground return path of the prescaler. Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF (see Figure 18). Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO. Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. AVDD has a value of 3 V ± 10%. AVDD must have the same voltage as DVDD. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ (see Figure 17). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. Digital Ground. Σ-∆ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. SDVDD has a value of 3 V ± 10%. SDVDD must have the same voltage as DVDD. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD has a value of 3 V ± 10%. DVDD must have the same voltage as AVDD. Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V. Rev. 0 | Page 6 of 20 ADF4154 TYPICAL PERFORMANCE CHARACTERISTICS Figure 5 to Figure 10, and Figure 12: RFOUT = 1.722 GHz, PFD Frequency = 26 MHz, INT = 66, Channel Spacing = 200 kHz, Modulus = 130, Fraction = 30/130, and ICP = 5 mA. Loop Bandwidth = 20 kHz, Reference = 26 MHz, VCO = Vari-L VCO190-1750T, Evaluation Board = EVAL-ADF4154EB1. Measurements were taken on the HP8562E spectrum analyzer. 0 0 REFERENCE LEVEL = –4dBm OUTPUT POWER (dB) –20 –30 –40 –10 –20 OUTPUT POWER (dB) –10 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 26MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz LOWEST NOISE MODE N = 66 30/130 RBW = 10Hz –50 –60 –70 REFERENCE LEVEL = –4.2dBm –30 –40 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 26MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz LOWEST NOISE MODE N = 66 30/130 RBW = 10Hz –50 –60 –71dBc@200kHz –70 –80 –90 –90 –100 –2kHz –1kHz 1.722GHz 1kHz 2kHz 04833-0-004 –80 –100 –400kHz Figure 5. Phase Noise (Lowest Noise Mode) 400kHz –20 –60 –95dBc/Hz –70 –30 –40 –74dBc@200kHz –60 –70 –80 –80 –90 –2kHz –1kHz 1.722GHz 1kHz 2kHz VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 26MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz LOW NOISE AND SPUR MODE N = 66 30/130 RBW = 10Hz –50 –90 –100 REFERENCE LEVEL = –4.2dBm –100 –400kHz Figure 6. Phase Noise (Low Noise Mode and Spur Mode) –200kHz 1.722GHz 200kHz 400kHz 04833-0-008 –50 –10 04833-0-005 Figure 9. Spurs (Low Noise and Spur Mode) 0 0 –30 –40 –10 –50 –60 –90dBc/Hz –70 –30 –40 –60 –70 –90 –1kHz 1.722GHz 1kHz 2kHz 04833-0-006 –80 –90 –2kHz VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 26MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz LOWEST SPUR NOISE N = 66 30/130 RBW = 10Hz –50 –80 –100 REFERENCE LEVEL = –4.2dBm –20 OUTPUT POWER (dB) REFERENCE LEVEL = –4.2dBm VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 26MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz LOWEST SPUR MODE N = 66 30/130 RBW = 10Hz –100 –400kHz Figure 7. Phase Noise (Lowest Spur Mode) –200kHz 1.722GHz 200kHz Figure 10. Spurs (Lowest Spur Mode) Rev. 0 | Page 7 of 20 400kHz 04833-0-009 OUTPUT POWER (dB) –30 –40 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 26MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz LOW NOISE AND SPUR MODE N = 66 30/130 RBW = 10Hz OUTPUT POWER (dB) REFERENCE LEVEL = –4.2dBm –20 OUTPUT POWER (dB) 200kHz 0 –10 –20 1.722GHz Figure 8. Spurs (Lowest Noise Mode) 0 –10 –200kHz 04833-0-007 –102dBc/Hz ADF4154 –130 –80 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) –85 –140 –150 –90 –95 –100 –160 1000 10000 100000 PHASE DETECTOR FREQUENCY (kHz) –110 0 5 Figure 11. PFD Noise Floor vs. PFD Frequency (Lowest Noise Mode) 10 15 20 RSET VALUE (kΩ) 25 30 35 04833-0-013 –170 100 04833-0-010 –105 Figure 14. Phase Noise vs. RSET 5 –90 0 –92 P = 4/5 –15 –20 –25 –30 0 0.5 1.0 1.5 2.0 2.5 3.0 –96 –98 –100 –102 3.5 4.0 4.5 FREQUENCY (GHz) 04833-0-011 –35 P = 8/9 –94 –104 –60 –40 –20 0 20 40 TEMPERATURE(°C) 60 80 100 95 100 04833-0-014 –10 PHASE NOISE (dBc/Hz) AMPLITUDE (dBm) –5 Figure 12. RF Input Sensitivity Figure 15. Phase Noise vs. Temperature 6 1.700 5 1.696 1.692 4 1.688 3 1.684 FREQUENCY (GHz) 2 –1 –2 –3 1.676 B 1.672 1.668 1.664 1.660 1.656 1.652 –4 1.648 –5 0 1 2 3 4 VCP(V) Figure 13. Charge Pump Output Characteristics 5 1.644 1.640 0 10 20 30 40 50 60 TIME (µs) 65 75 85 04833-0-028 –6 04833-0-012 ICP(mA) 1 0 A 1.680 Figure 16. A) Lock Time in Fast-lock Mode. Fast Counter = 150, Low Spur Mode: a 1649.7 MHz to 1686.8 MHz Frequency Jump. Final Loop Bandwidth = 60 kHz B) Lock Time with the PLL in Normal Mode (Non Fast-lock), Low Spur Mode, a 1649.7 MHz to 1686.8 MHz Frequency Jump. Final Loop Bandwidth = 60 kHz Rev. 0 | Page 8 of 20 ADF4154 CIRCUIT DESCRIPTION FPFD = REFIN × (1 + D ) R REFERENCE INPUT SECTION The reference input stage is shown in Figure 17. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that the REFIN pin is not loaded on power-down. POWER-DOWN CONTROL 100kΩ NC SW2 TO R COUNTER REFIN NC BUFFER 04833-0-027 SW1 SW3 NO (2) where: REFIN is the reference input frequency. D is the REFIN doubler bit. R is the preset divide ratio of binary 4-bit programmable reference counter (1 to 15). INT is the preset divide ratio of binary 9-bit counter (31 to 511). MOD is the preset modulus ratio of binary 12-bit programmable FRAC counter (2 to 4095). FRAC is the preset fractional ratio of binary 12-bit programmable FRAC counter (0 to MOD). RF R COUNTER Figure 17. Reference Input Stage The 4-bit RF R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the PFD. Division ratios from 1 to 15 are allowed. RF INPUT STAGE The RF input stage is shown in Figure 18. It is followed by a 2-stage limiting amplifier to generate the current mode logic (CML) clock levels needed for the prescaler. RF N-DIVIDER FROM RF INPUT STAGE N = INT + FRAC/MOD TO PFD N COUNTER 1.6V BIAS GENERATOR THIRD ORDER FRACTIONAL INTERPOLATOR AVDD 2kΩ 2kΩ MOD REG FRAC VALUE 04833-0-016 INT REG RFINA Figure 19. A and B Counters RFINB Figure 18. RF Input Stage RF INT DIVIDER The RF INT CMOS counter allows a division ratio in the PLL feedback counter. Division ratios from 31 to 511 are allowed. The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 20 is a simplified schematic. The PFD includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns. This pulse ensures that there is no dead zone in the PFD transfer function and gives a consistent reference spur level. HI INT, FRAC, MOD, AND R RELATIONSHIP Q1 UP U1 The INT, FRAC, and MOD values, in conjunction with the R counter, make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (PFD). See the RF Synthesizer: A Worked Example section for more information. The RF VCO frequency (RFOUT) equation is RFOUT = FPFD × (INT + (FRAC MOD)) D1 +IN CLR1 DELAY (1) HI U3 CHARGE PUMP CLR2 DOWN D2 Q2 U2 where RFOUT is the output frequency of the external voltage controlled oscillator (VCO). –IN Figure 20. PFD Simplified Schematic Rev. 0 | Page 9 of 20 CP 04833-0-017 AGND 04833-0-015 PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP ADF4154 MUXOUT AND LOCK DETECT The output multiplexer on the ADF4154 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 (see Table 9). Figure 21 shows the MUXOUT section in block diagram form. The N-channel, open-drain, analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When lock has been detected, the lock detect is high with narrow low-going pulses. PROGRAM MODES Table 5 through Table 10 show how to set up the program modes in the ADF4154. DVDD The ADF4154 programmable modulus is double-buffered. This means that two events have to occur before the part uses a new modulus value. First, the new modulus value is latched into the device by writing to the R-divider register. Second, a new write must be performed on the N-divider register. Therefore, whenever the modulus value is updated, the N-divider register must then be written to so that the modulus value is loaded correctly. LOGIC LOW ANALOG LOCK DETECT R-DIVIDER OUTPUT N-DIVIDER OUTPUT MUX MUXOUT CONTROL FAST-LOCK CONTROL THREE-STATE OUTPUT 04833-0-018 DIGITAL LOCK DETECT LOGIC HIGH DGND Figure 21. MUXOUT Schematic INPUT SHIFT REGISTERS The ADF4154 digital section includes a 4-bit RF R counter, a 9-bit RF N counter, a 12-bit FRAC counter, and a 12-bit modulus counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2 and C1) in the shift register. These are the 2 LSBs, DB1, and DB0, as shown in Figure 2. The truth table for these bits is shown in Table 5. Table 6 shows a summary of how the latches are programmed. Table 5. C2 and C1 Truth Table Control Bits C2 C1 0 0 0 1 1 0 1 1 Rev. 0 | Page 10 of 20 Data Latch N-divider register R-divider register Control register Noise and spur register ADF4154 REGISTERS Table 6. Register Summary FAST-LOCK N-DIVIDER REG DB23 DB22 FL1 N9 DB21 DB20 N8 N7 DB19 DB18 N6 DB17 N5 N4 CONTROL BITS 12-BIT RF FRACTIONAL VALUE 9-BIT RF INTEGER VALUE DB16 DB15 DB14 N3 N2 N1 DB13 DB12 DB11 F12 F11 DB10 DB9 DB8 F9 F8 F7 F10 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 F6 F5 F4 F3 F2 F1 C2 (0) C1 (0) MUXOUT DB23 DB22 P3 M3 DB21 DB20 M2 M1 PRESCALER RESERVED LOAD CONTROL R-DIVIDER REG 4-BIT R COUNTER DB19 DB18 P2 DB17 P1 R4 DB16 DB15 R3 CONTROL BITS 12-BIT MODULUS DB14 DB13 DB12 R1 M12 M11 R2 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 M10 M8 M7 M6 M5 M4 M3 M2 M1 M9 DB1 DB0 C2 (0) C1 (1) DB12 DB11 DB10 0 COUNTER RESET 0 CP THREE-STATE DB13 0 POWERDOWN DB14 0 LDP DB15 PD POLARITY RESERVED DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 CP2 CP1 CP0 U5 U4 U3 U2 U1 CP/2 REFERENCE DOUBLER CONTROL REG U6 CP3 CP CURRENT SETTING CONTROL BITS DB1 DB0 C2 (1) C1 (0) RESERVED DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 T9 T8 T7 T6 T5 T4 T3 T2 T1 NOISE AND SPUR MODE NOISE AND SPUR MODE RESERVED Table 7. Noise and Spur Register RESERVED CONTROL BITS DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 T9 T8 T7 T6 T5 T4 T3 T2 T1 C2 (1) C1 (1) DB10, DB5, DB4, DB3 0 RESERVED RESERVED DB9, DB8, DB7, DB6, DB2 00000 11100 11111 NOISE AND SPUR SETTING LOWEST SPUR MODE LOW NOISE AND SPUR MODE LOWEST NOISE MODE Rev. 0 | Page 11 of 20 04833-0-023 THESE BITS MUST BE SET TO 0 FOR NORMAL OPERATION. CONTROL BITS DB1 C2 (1) DB0 C1 (1) 04833-0-019 NOISE AND SPUR MODE NOISE AND SPUR MODE RESERVED NOISE AND SPUR REG ADF4154 FAST-LOCK Table 8. N-Divider Register Map DB23 DB22 FL1 N9 DB21 DB20 DB19 DB18 N8 N7 N6 DB17 N5 N4 DB16 DB15 N3 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C2 (0) C1 (0) N2 F12 F11 F10 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... F3 F2 F1 FRACTIONAL VALUE (FRAC) 0 0 0 0 . . . 1 1 1 1 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 0 1 2 3 . . . 4092 4093 4094 4095 N8 N7 N6 N5 N4 N3 N2 N1 INTEGER VALUE (INT) 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 1 1 1 0 1 1 1 . . . 1 1 1 1 0 0 0 . . . 1 1 1 1 0 0 0 . . ... 1 1 1 1 0 0 0 . . . 1 1 1 1 0 0 1 . . . 0 1 1 1 0 1 0 . . . 1 0 1 31 32 33 34 . . . 509 510 511 FAST-LOCK 0 1 NORMAL OPERATION FAST-LOCK ENABLED 04833-0-020 N9 FL1 CONTROL BITS 12-BIT FRACTIONAL VALUE (FRAC) 9-BIT INTEGER VALUE (INT) Rev. 0 | Page 12 of 20 ADF4154 DB23 DB22 DB21 DB20 P3 M3 M2 DB19 DB18 M1 P2 P1 4-BIT R COUNTER DB17 DB16 DB15 DB14 DB13 R4 P3 LOAD CONTROL P1 PRESCALER 0 1 0 1 4/5 8/9 NORMAL OPERATION LOAD FAST-LOCK TIMER R3 R2 R1 M12 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 M11 M8 M7 M6 M5 M4 M3 M2 M1 M10 M9 M12 M11 M10 0 0 0 . . . 1 1 1 1 0 0 0 . . . 1 1 1 1 0 0 0 . . . 1 1 1 1 R4 R3 R2 R1 RF R-COUNTER DIVIDE RATIO 0 0 0 0 . . . 1 1 1 1 0 0 0 1 . . . 1 1 1 1 0 1 1 0 . . . 0 0 1 1 1 0 1 0 . . . 0 1 0 1 1 2 3 4 . . . 12 13 14 15 M3 M2 M1 MUXOUT 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 THREE-STATE OUTPUT DIGITAL LOCK DETECT ANALOG LOCK DETECT N-DIVIDER OUTPUT LOGIC HIGH LOGIC LOW R-DIVIDER OUTPUT FAST-LOCK SWITCH CONTROL BITS 12-BIT INTERPOLATOR MODULUS VALUE (MOD) .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... M3 M2 M1 0 0 1 . . . 1 1 1 1 1 1 0 . . . 0 0 1 1 0 1 0 . . . 0 1 0 1 DB1 DB0 C2 (0) C1 (1) INTERPOLATOR MODULUS VALUE (MOD) 2 3 4 . . . 4092 4093 4094 4095 04833-0-021 MUXOUT PRESCALER RESERVED LOAD CONTROL Table 9. R-Divider Register Map Rev. 0 | Page 13 of 20 ADF4154 LDP POWERDOWN CP THREE-STATE COUNTER RESET DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CP3 CP2 CP1 CP0 U5 U4 U3 U2 U1 C2 (1) C1 (0) RESERVED DB15 DB14 DB13 0 0 0 DB12 DB11 0 U6 CP/2 REFERENCE DOUBLE PD POLARITY Table 10. Control Register Map U6 REFERENCE DOUBLER 0 1 DISABLED ENABLED CP CURRENT SETTING U1 0 1 CONTROL BITS COUNTER RESET DISABLED ENABLED U2 CP THREE-STATE 0 1 DISABLED THREE-STATE U3 POWER-DOWN 0 1 NORMAL OPERATION POWER-DOWN CP0 CP1 CP0 2.700kΩ 5.100kΩ 10.00kΩ 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1.090 2.180 3.260 4.350 5.440 6.530 7.620 8.700 0.630 1.250 1.880 2.500 3.130 3.750 4.380 5.000 0.290 0.590 0.880 1.150 1.470 1.760 2.060 2.350 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0.540 1.100 1.640 2.180 2.730 3.270 3.810 4.350 0.310 0.630 0.940 1.250 1.570 1.880 2.190 2.500 0.150 0.300 0.440 0.588 0.740 0.880 1.030 1.180 U4 LDP 0 1 3 5 U5 PD POLARITY 0 1 NEGATIVE POSITIVE Rev. 0 | Page 14 of 20 04833-0-022 ICP(mA) ÷3 ADF4154 REGISTER DEFINITION Prescaler (P/P + 1) N-Divider Register, R0 The dual-modulus prescaler (P/P + 1), along with the INT, FRAC, and MOD counters, determines the overall division ratio from the RFIN to the PFD input. Operating at CML levels, it takes the clock from the RF input stage and divides it down for the counters. It is based on a synchronous 4/5 core. When set to 4/5, the maximum RF frequency allowed is 2 GHz. Therefore, when operating the ADF4154 above 2 GHz, this must be set to 8/9. The prescaler limits the INT value. The on-chip N-divider register is programmed by setting R0[1, 0] to [0, 0]. Table 8 shows the input data format for programming this register. 9-Bit INT Value These nine bits control what is loaded as the INT value. This is used to determine the overall feedback division factor (see Equation 1). With P = 4/5, NMIN = 31. With P = 8/9, NMIN = 91. 12-Bit FRAC Value These 12 bits control what is loaded as the FRAC value into the fractional interpolator. This value helps determine the overall feedback division factor (see Equation 1). The FRAC value must be less than the value loaded into the MOD register. Fast-Lock The prescaler can also influence the phase noise performance. If INT < 91, a prescaler of 4/5 should be used. For applications where INT > 91, P = 8/9 should be used for optimum noise performance (see Table 9). 4-Bit RF R Counter Setting the part to logic high enables fast-lock mode. To use fast-lock, the required time value for wide bandwidth mode needs to be loaded into the R-divider register. The charge pump current increases from 16× the minimum current and reverts back to 1× the minimum current once the time value loaded has expired. The 4-bit RF R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 15 are allowed. 12-Bit Interpolator Modulus/Fast-Lock Timer Bits DB13–DB2 have two functions depending on the value of the load control bit: modulus or fast lock timer value. See the Fast-Lock Timer and Register Sequences section for more information. When the load control bit = 0 (DB23), the required modulus may be programmed into the R-divider register (DB13–DB2). R-DIVIDER REGISTER, R1 The on-chip R-divider register is programmed by setting R1[1, 0] to [0, 1]. Table 9 shows the input data format for programming this register. When the load control bit = 1 (DB23), the required fast-lock timer value may be programmed into the R-divider register (DB13–DB2). Load Control When set to logic high, the value being programmed in the modulus is not loaded into the modulus. Instead, it sets the fastlock timer. The value of the fast-lock timer/FPFD is the amount of time the PLL stays in wide bandwidth mode. MUXOUT The on-chip multiplexer is controlled by R1[22...20] on the ADF4154. Table 9 shows the truth table. Digital Lock Detect The digital lock detect output goes high if there are 40 successive PFD cycles with an input error of less than 15 ns. It stays high until a new channel is programmed or until the error at the PFD input exceeds 30 ns for one or more cycles. If the loop bandwidth is narrow compared to the PFD frequency, the error at the PFD inputs may drop below 15 ns for 40 cycles around a cycle slip. Therefore, the digital lock detect may go falsely high for a short period until the error again exceeds 30 ns. In this case, the digital lock detect is reliable only as a loss-of-lock detector. This programmable register sets the fractional modulus, which is the ratio of the PFD frequency to the channel step resolution on the RF output. Refer to the RF Synthesizer: A Worked Example section for more information. The ADF4154 programmable modulus is double-buffered. This means that two events must occur before the part uses a new modulus value. First, the new modulus value is latched into the device by writing to the R-divider register. Second, a new write must be performed on the N-divider register. Therefore, whenever the modulus value is updated, the N-divider register must be written to so that the modulus value is loaded correctly. CONTROL REGISTER, R2 The on-chip control register is programmed by setting R2[1, 0] to [0, 1]. Table 10 shows the input data format for programming this register. RF Counter Reset DB3 is the RF counter reset bit for the ADF4154. When this is 1, the RF synthesizer counters are held in reset. For normal operation, this bit should be 0. Rev. 0 | Page 15 of 20 ADF4154 RF Charge Pump Three-State NOISE AND SPUR REGISTER, R3 This bit puts the charge pump into three-state mode when programmed to 1. It should be set to 0 for normal operation. The on-chip noise and spur register is programmed by setting R3[1, 0] to [1, 1]. Table 7 shows the input data format for programming this register. RF Power-Down DB4 on the ADF4154 provides the programmable power-down mode. Setting Bit DB4 to 1 powers down the device. Setting Bit DB4 to 0 returns the synthesizer to normal operation. While in software power-down mode, the part retains all information in its registers. Only when supplies are removed are the register contents lost. When a power-down is activated, the following events occur: 1. All active dc current paths are removed. 2. The synthesizer counters are forced to their load state conditions. 3. The charge pump is forced into three-state mode. 4. The digital lock detect circuitry is reset. 5. The RFIN input is de-biased. 6. The input register remains active and capable of loading and latching data. Lock Detect Precision (LDP) When the LDP bit is programmed to 0, 24 consecutive reference cycles of 15 ns must occur before the digital lock detect is set. When this bit is programmed to 1, 40 consecutive reference cycles of 15 ns must occur before digital lock detect is set. Phase Detector Polarity DB6 in the ADF4154 sets the phase detector polarity. When the VCO characteristics are positive, this should be set to 1. When they are negative, it should be set to 0. Noise and Spur Mode Noise and spur mode allows the user to optimize a design either for improved spurious performance or for improved phase noise performance. When the lowest spur setting is chosen, dither is enabled. This randomizes the fractional quantization noise so that it looks more like white noise rather than spurious noise. This means that the part is optimized for improved spurious performance. This operation would normally be used when the PLL closed-loop bandwidth is wide for fast-locking applications. A wide-loop bandwidth is seen as a loop bandwidth greater than 1/10 of the RFOUT channel step resolution (fRES). A wide-loop filter does not attenuate the spurs to a level that a narrow-loop bandwidth would. When the low noise and spur setting is enabled, dither is disabled. This optimizes the synthesizer to operate with improved noise performance. However, the spurious performance is degraded in this mode compared to the lowest spurs setting. To further improve noise performance, the lowest noise setting option can be used, which reduces the phase noise. As well as disabling the dither, it ensures that the charge pump operates in an optimum region for noise performance. This setting is extremely useful where a narrow-loop filter bandwidth is available. The synthesizer ensures extremely low noise and the filter attenuates the spurs. The typical performance characteristics give the user an idea of the trade-off in a typical WCDMA setup for the different noise and spur settings. RESERVED BITS Charge Pump Current Setting These bits should be set to 0 for normal operation. DB7, DB8, DB9, and DB10 set the charge pump current, which should be set according to the loop filter design (see Table 10). RF SYNTHESIZER: A WORKED EXAMPLE REFIN Doubler Setting the REFIN bit to 0 feeds the REFIN signal directly to the 4-bit RF R counter, which disables the doubler. Setting the REFIN bit to 1 multiplies the REFIN frequency by a factor of 2 before feeding into the 4-bit R counter. When the doubler is disabled, the REFIN falling edge is the active edge at the PFD input to the fractional synthesizer. When the doubler is enabled, both the rising and falling edges of REFIN become active edges at the PFD input. When the doubler is enabled and the lowest spur mode is chosen, the in-band phase noise performance is sensitive to the REFIN duty cycle. The phase noise degradation can be as much as 5 dB for the REFIN duty cycles outside a 45% to 55% range. The phase noise is insensitive to the REFIN duty cycle in the lowest noise mode and in the lowest noise and spur mode. The phase noise is insensitive to the REFIN duty cycle when the doubler is disabled. This equation governs how the synthesizer should be programmed. RFOUT = [INT + (FRAC/MOD)] × [FPFD] (3) where: RFOUT is the RF frequency output. INT is the integer division factor. FRAC is the fractionality. MOD is the modulus. FPFD = [REFIN × (1 = D)/R] where: REFIN is the reference frequency input. D is the RF REFIN doubler bit. R is the RF reference division factor. Rev. 0 | Page 16 of 20 (4) ADF4154 For example, in a GSM 1800 system, where a 1.8 GHz RF frequency output (RFOUT) is required, a 13 MHz reference frequency input (REFIN) is available and a 200 kHz channel resolution (fRES) is required on the RF output. MOD = REFIN f RES MOD = 13 MHz 200 kHz = 65 From Equation 4, FPFD = [13 MHz × (1 + 0)/1] = 13 MHz 1.8 G = 13 MHz × (INT + FRAC 65) ≥ (5) (6) INT = 138; ≥ FRAC = 30 resolution. A 13 MHz reference signal could be fed directly to the PFD. The modulus would be programmed to 520 when in PDC mode (13 MHz/520 = 25 kHz). The modulus would be reprogrammed to 65 for GSM 1800 operation (13 MHz/65 = 200 kHz). It is important that the PFD frequency remains constant (13 MHz). By keeping the PFD constant, the user can design a one-loop filter that can be used in both setups without running into stability issues. The ratio of the RF frequency to the PFD frequency affects the loop design. Keeping this relationship constant instead of changing the modulus factor results in a stable filter. SPURIOUS OPTIMIZATION AND FAST-LOCK MODULUS The choice of modulus (MOD) depends on the reference signal (REFIN) available and the channel resolution (fRES) required at the RF output. For example, a GSM system with 13 MHz REFIN would set the modulus to 65, resulting in the RF output resolution (fRES) of 200 kHz (13 MHz/65) that is necessary for GSM. REFERENCE DOUBLER AND REFERENCE DIVIDER The reference doubler on-chip allows the input reference signal to be doubled. This is useful for increasing the PFD comparison frequency. Making the PFD frequency higher improves the noise performance of the system. Doubling the PFD frequency usually results in an improvement in noise performance of 3 dB. It is important to note that the PFD cannot be operated above 32 MHz due to a limitation in the speed of the Σ-Δ circuit of the N divider. 12-BIT PROGRAMMABLE MODULUS Unlike most other fractional-N PLLs, the ADF4154 allows the user to program the modulus over a 12-bit range. This means that the user can set up the part in many different configurations for the application, when combined with the reference doubler and the 4-bit R counter. The ADF4154 can be optimized for low spurious signals by using the noise and spur register. However, in order to achieve fast-lock time, a wider loop bandwidth is needed. Note that a wider loop bandwidth can lead to notable spurious signals, which cannot be reduced significantly by the loop filter. Using the fast-lock feature can achieve the same fast-lock time as the noise and spur register, but with the advantage of lower spurious signals, since the final loop bandwidth is reduced by a quarter. FAST-LOCK TIMER AND REGISTER SEQUENCES If the fast-lock mode is used, a timer value needs to be loaded into the PLL to determine the time of the wide bandwidth. When the load control bit = 1, the timer value is loaded via the 12-bit modulus value. To use fast-lock, the PLL must be written to in the following sequence: 1. Load the R-divider register with DB23 = 1 and the chosen fast-lock timer value (DB13–DB2) instead of the modulus. Note that the duration of time the PLL remains in wide bandwidth is equal to the fast-lock timer/FPFD. 2. Load the noise and spur register. For example, consider an application that requires a 1.75 GHz RF and a 200 kHz channel step resolution. The system has a 13 MHz reference signal. 3. Load the control register. 4. One possible setup is feeding the 13 MHz directly to the PFD and programming the modulus to divide by 65, which would result in the required 200 kHz resolution. Load R-divider register with DB23 = 0 and MUXOUT = 110 (DB22–DB20). All the other needed parameters, including the modulus, also need to be loaded. 5. Load the N-divider register, including fast-lock = 1 (DB23), to activate fast-lock mode. Another possible setup is using the reference doubler to create 26 MHz from the 13 MHz input signal. The 26 MHz signal is then fed into the PFD, which programs the modulus to divide by 130. This setup also results in 200 kHz resolution and offers superior phase noise performance over the previous setup. Once this procedure is completed, future frequency jumps deploying fast-lock need to repeat only Step 5. The programmable modulus is also very useful for multistandard applications. If a dual-mode phone requires PDC and GSM 1800 standards, the programmable modulus is a huge benefit. The PDC requires a 25 kHz channel step resolution, whereas the GSM 1800 requires a 200 kHz channel step Rev. 0 | Page 17 of 20 ADF4154 If fast-lock is not used, then use the following sequence: ADF4154 R2 CP Load the noise and spur register. 2. Load the control register. 3. Load the R-divider register with DB23 = 0 and other necessary parameters. 4. Load the N-divider register, including fast-lock = 0 (DB23) for normal operation. Predicting Where They Appear If the time period chosen for the wide bandwidth is 40 µs, then Fast-lock timer value = time in wide bandwidth × FPFD Fast-lock timer value = 40 µs × 13 MHz = 520 Therefore, 520 has to be loaded into the R-divider register in Step 1 of the sequence described in the Fast-Lock Timer and Register Sequences section. FAST-LOCK: LOOP FILTER TOPOLOGY To use fast-lock mode, an extra connection from the PLL to the loop filter is needed. The MUXOUT must reduce the damping resistor in the loop filter to ¼ while in wide bandwidth mode. This is required because the charge pump current is increased by 16 while in wide bandwidth mode and stability must be ensured. This can be done with the following two topologies: 1. Divide the damping resistor (R1) into two values (R1 and R1A) of ratio 1:3 (see Figure 22). 2. Use an extra resistor (R1A) and connect it directly from the MUXOUT, as shown in Figure 22. The extra resistor must be chosen such that the parallel combination of an extra resistor and the damping resistor (R1) is reduced to ¼ of the original value of R1 alone (see Figure 23). R2 VCO C2 C3 R1 Figure 22 Fast-lock Loop Filter Topology—Topology 1 04833-0-029 MUXOUT R1A R1 SPURIOUS SIGNALS Consider an example in which PLL has reference frequencies of 13 MHz and FPFD = 13 MHz and a required lock time of 50 µs. Therefore, the PLL is set to wide bandwidth for 40 µs. C1 R1A C3 Figure 23. Fast-lock Loop Filter Topology—Topology 2 FAST-LOCK: A WORKED EXAMPLE CP C2 MUXOUT To change frequency, only Step 4 need be repeated. ADF4154 VCO C1 04833-0-030 1. As in integer-N PLLs, spurs appear at PFD frequency offsets from the carrier. In a fractional-N PLL, spurs also appear at frequencies equal to the RFOUT channel step resolution (fRES). The third-order fractional interpolator engine of the ADF4154 may also introduce subfractional spurs. If the fractional denominator (MOD) is divisible by 2, spurs appear at ½ fRES. If the fractional denominator (MOD) is divisible by 3, spurs appear at 1/3 fRES. Harmonics of all spurs mentioned also appear. With the lowest spur mode enabled, the fractional and subfractional spurs are attenuated dramatically. The worst-case spurs appear when the fraction is programmed to 1/MOD. For example, in a GSM 900 MHz system with a 26 MHz PFD frequency and an RFOUT channel step resolution (fRES) of 200 kHz, the MOD = 130. PFD spurs appear at 26 MHz offset and fractional spurs appear at 200 kHz offset. Since the MOD is divisible by 2, subfractional spurs are also present at 100 kHz offset. FILTER DESIGN—ADISIMPLL A filter design and analysis program is available to help the user implement the PLL design. Visit www.analog.com/pll for a free download of the ADIsimPLL software. The software designs, simulates, and analyzes the entire PLL frequency and time domain response. Various passive and active filter architectures are allowed. Rev. 2 of ADIsimPLL allows analysis of the ADF4154. INTERFACING The ADF4154 has a simple, SPI® compatible serial interface for writing to the device. SCLK, SDATA, and LE control the data transfer. When LE (latch enable) is high, the 22 bits that have been clocked into the input register on each rising edge of SCLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the latch truth table. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 909 kHz or one update every 1.1 µs. This is more than adequate for systems that have typical lock times in the hundreds of microseconds. Rev. 0 | Page 18 of 20 ADF4154 ADSP-21xx Figure 24 shows the interface between the ADF4154 and the ADuC812 MicroConverter®. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, bring the I/O port driving LE low. Each latch of the ADF4154 needs a 24-bit word, which is accomplished by writing three 8-bit bytes from the MicroConverter to the device. After the third byte is written, the LE input should be brought high to complete the transfer. When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 180 kHz. ADuC812 SCLOCK MOSI ADF4154 SCLK ADF4154 SCLOCK DT TFS I/O FLAGS SCLK SDATA LE MUXOUT (LOCK DETECT) 04833-0-025 ADuC812 Interface Figure 25. ADSP-21xx to ADF4154 Interface PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The lands on the chip scale package (CP-20) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. SDATA The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to avoid shorting. LE MUXOUT (LOCK DETECT) 04833-0-024 I/O PORTS Figure 24. ADuC812 to ADF4154 Interface ADSP-2181 Interface Figure 25 shows the interface between the ADF4154 and the ADSP-21xx digital signal processor. As discussed previously, the ADF4154 needs a 24-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for eight bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store each of the three 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated into the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. of copper to plug the via. The user should connect the printed circuit board thermal pad to AGND. Rev. 0 | Page 19 of 20 ADF4154 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153AB Figure 26. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 0.60 MAX 4.0 BSC SQ 0.60 MAX PIN 1 INDICATOR 11 10 0.80 MAX 0.65 TYP 12° MAX 1.00 0.85 0.80 0.20 REF 2.25 2.10 SQ 1.95 6 5 0.25 MIN 0.30 0.23 0.18 0.05 MAX 0.02 NOM 0.50 BSC 20 1 BOTTOM VIEW 0.75 0.55 0.35 SEATING PLANE 16 15 3.75 BSC SQ TOP VIEW COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 27. 20-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body, (CP-20) Dimensions shown in millimeters ORDERING GUIDE Model ADF4154BRU ADF4154BRU-REEL ADF4154BRU-REEL7 ADF4154BCP ADF4154BCP-REEL ADF4154BCP-REEL7 EVAL-ADF4154EB1 Description Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Lead Frame Chip Scale Package (LFCSP) Lead Frame Chip Scale Package (LFCSP) Lead Frame Chip Scale Package (LFCSP) Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Option RU-16 RU-16 RU-16 CP-20 CP-20 CP-20 Purchase of licensed I2C components of Analog Devices, Inc. or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04833–0–4/04(0) Rev. 0 | Page 20 of 20