Sony CXA3252N All band tv tuner ic with on-chip pll Datasheet

CXA3252N
All Band TV Tuner IC with On-chip PLL
Description
32 pin SSOP (Plastic)
The CXA3252N is a monolithic TV tuner IC which
integrates local oscillator and mixer circuits for VHF
band, local oscillator and mixer circuits for UHF band,
an IF amplifier and a tuning PLL onto a single chip,
enabling further miniaturization of the tuner.
Features
• Superior cross modulation
• Supports both IF double-tuned filter and adjacent
channel trap.
• Balanced UHF oscillator (4 pins) with excellent oscillation stability
• Supports both I2C and 3-wire bus modes
Absolute Maximum Ratings (Ta=25 °C)
V
VCC1, VCC2 −0.3 to + 5.5
VCC3 −0.3 to +10.0 V
• Storage temperature
Tstg
−55 to + 150 °C
• Allowable power dissipation
• Supply voltage
• Automatic identification of 18, 19 or 27-bit control
(during 3-wire bus mode)
• On-chip high voltage drive transistor for charge pump
• Reference frequency selectable from 31.25, 50 or
62.5 kHz (when using a 4 MHz crystal)
• Low-phase noise synthesizer
• On-chip 4-output band switch
(supports output voltages from 5 to 9 V)
• 32 pin SSOP
Operating Conditions
• Supply voltage
VCC1, VCC2 4.75 to 5.30
V
VCC3
4.75 to 9.45
V
• Operating temperature Topr
−25 to +75 °C
PD
580
mW
(when mounted on a printed circuit board)
Applications
• TV tuners
• VCR tuners
• CATV tuners
Structure
Bipolar silicon monolithic IC
This IC has the pins whose electrostatic discharge strength is weak as the operating frequency is high and the high-frequency
process is used for this IC.
Take care of handling the IC.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00301-TE
CXA3252N
Block Diagram and Pin Configuration
CL
1
DA
2
ADSW
32 /CE
BUS
Interface
31 VCC3
BS3
3
BS1
4
Shift
Register
Divider
1/64, 80, 128
REF
OSC
Phase
Detector
Charge
Pump
IFIN1 5
Band
SW
Driver
IFIN2 6
BS2
BS4
Programable
Divider
14/15bit
VSW
9
28 VT
27 NC
IF AMP
VCC1
29 CPO
LOCK
Det
7
8
30 REFOSC
26 IFOUT
V.REG
25 GND2
Bus
Select
Buffer
24 VCC2
MIXout1 10
23 UOSCB2
MIXout2 11
GND1 12
BYP/MS 13
VHFin 14
Buffer
UHF
OSC
VHF
MIX
22 UOSCE2
21 UOSCE1
20 UOSCB1
19 VOSC2
Buffer
UHFin1 15
UHFin2 16
VHF
UHF
MIX
VHF
OSC
18 GND
17 VOSC1
–2–
CXA3252N
Pin Description
Pin No.
Symbol
Description
2
1
CL
CLOCK/SCL (I C bus)
2
DA
DATA/SDA (I2C bus)
3
BS3
Band switch output 3
4
BS1
Band switch output 1 (VHF low band)
5
IFIN1
IF amplifier input 1
6
IFIN2
IF amplifier input 2
7
BS2
Band switch output 2 (VHF high band)
8
BS4
Band switch output 4
9
VCC1
10
MIXOUT1
MIX output (open collector)
11
MIXOUT2
MIX output (open collector)
12
GND1
13
BYP/MS
14
VHFIN
VHF input
15
UHFIN1
UHF input
16
UHFIN2
UHF input
17
VOSC1
VHF oscillator (base input)
18
GND
19
VOSC2
20
UOSCB1
UHF oscillator (base pin)
21
UOSCE1
UHF oscillator (emitter pin)
22
UOSCE2
UHF oscillator (emitter pin)
23
UOSCB2
UHF oscillator (base pin)
24
VCC2
PLL circuit Vcc
25
GND2
PLL circuit GND
26
IFOUT
IF amplifier output
27
NC
OPEN
28
VT
Tuning voltage output (open collector)
29
CPO
30
REFOSC
31
VCC3
32
ADSW/CE
Analog circuit Vcc
Analog circuit GND
VHF input GND and control bus switching
GND
VHF oscillator (collector output)
Charge pump output (loop filter connection)
Crystal connection
Band switch power supply
Enable/address selection (I2C bus)
–3–
CXA3252N
Pin Description and Equivalent Circuit
Pin
No.
Symbol
Pin Voltage
[V]
Equivalent circuit
Description
23
1
CL
—
Clock input.
40k
1
23
2
DA
—
2
DATA input.
40k
2.5p
20
31
3
BS3
ON : 4.8
OFF : 0.0
3
8
8
BS4
Band switch outputs.
The pin corresponding to the
selected band goes High.
31
4
BS1
4
2.1
7
8
BS2
12k
25k
8
5
IFIN1
2.1
5
6
1.2k
5k
6
IFIN2
9
VCC1
5k
—
Analog circuit power supply.
–4–
CXA3252N
Pin
No.
Symbol
Pin Voltage
[V]
Equivalent circuit
10
10
MIXOUT1
—
11
MIXOUT2
—
12
GND1
—
Description
11
Mixer output.
These pins output the signal with
open collector, and they must be
connected to the power supply via
the load.
—
Analog circuit GND.
3.8 during
VHF reception
13
BYP/MS
3.8 during
UHF reception
9
24
15p
3k
0.1 during
2.6 during
9
UHF reception
UHFin1
Pin 13 : VHF input.
Input format is the unbalanced input.
13
UHF reception
15
76k
3k
VHF reception
VHFin
Pin 12 : VHF input grounding and
control bus switching.
14
2.6 during
14
24k
0.1 during
15
VHF reception
16
3k
2.6 during
UHF inputs.
Input the signal to Pins 14 and 15
symmetrically or ground either of
Pin 14 or 15 with the capacitor and
input the signal to the rest.
3k
UHF reception
16
UHFin2
0.1 during
VHF reception
2.1 during
VHF reception
17
VOSC1
9
400
2.3 during
19
UHF reception
50
17
4.2 during
VHF reception
19
3k
3k
External resonance circuit connection for VHF oscillator.
VOSC2
5.0 during
UHF reception
18
GND
—
GND for separating the analog and
PLL systems.
—
–5–
CXA3252N
Pin
No. Symbol
Pin Voltage
[V]
20 UOSCB1
2.1 during UHF reception
2.3 during VHF reception
21 UOSCE1
1.4 during UHF reception
1.8 during VHF reception
Equivalent circuit
Description
9
23
22
External resonance circuit
connection for UHF oscillator.
21
22 UOSCE2
23 UOSCB2
1.4 during UHF reception
1.8 during VHF reception
20
3k
3k
2.1 during UHF reception
2.3 during VHF reception
24
VCC2
—
—
PLL circuit power supply
25
GND2
—
—
PLL circuit GND.
9
26
IFOUT
2.7
27
NC
—
I/F output.
26
—
24
28
VT
—
Varicap drive voltage output.
This pin outputs the signal with
open collector, and this must
be connected to the tuning
power supply via the load.
Charge pump output.
Connects the loop filter.
29
28
70
29
CPO
2.0
24
60k
30p
30
30 REFOSC
4.3
31
—
VCC3
30p
Crystal connection for reference
oscillator.
—
Power supply for external supply.
5p
I2C bus setting :
Address selection.
Bits 1 and 2 of the address
byte are controlled.
3-wire bus setting :
Enable input.
23
150k
32 ADSW/CE
1.25
(when open)
3
50k
–6–
CXA3252N
Electrical Characteristics
Circuit Current
(VCC=5 V, Ta=25°C)
Item
Symbol
Min.
Typ.
Max.
Unit
AICCV
VCC1 current, band switch output
open during VHF operation
mA
AICCU
VCC1 current, band switch output
open during UHF operation
mA
DICC
VCC2 current
mA
Circuit current A
Circuit current D
Measurement conditions
OSC/MIX/IF Amplifier Block
Item
Symbol
Conversion gain
Noise figure *1, *2
1% cross
modulation
*1,*3
Maximum output
power
Switch ON drift
Measurement conditions
Min.
Typ.
Max.
Unit
CG1
VHF operation fRF=55 MHz
dB
CG2
VHF operation fRF=360 MHz
dB
CG3
UHF operation fRF=360 MHz
dB
CG4
UHF operation fRF=800 MHz
dB
NF1
VHF operation fRF=55 MHz
dB
NF2
VHF operation fRF=360 MHz
dB
NF3
UHF operation fRF=360 MHz
dB
NF4
UHF operation fRF=800 MHz
dB
CM1
VHF operation
fD=55 MHz, fUD=±12 MHz
dBµ
CM2
VHF operation
fD=360 MHz, fUD=±12 MHz
dBµ
CM3
UHF operation
fD=360 MHz, fUD=±12 MHz
dBµ
CM4
UHF operation
fD=800 MHz, fUD=±12 MHz
dBµ
Pomax
50 Ω load saturation output
dBm
∆ fsw1
VHF operation fOSC=100 MHz
∆ f from 3 s to 3 min after switch ON
kHz
∆ fsw2
VHF operation fOSC=405 MHz
∆ f from 3 s to 3 min after switch ON
kHz
∆ fsw3
UHF operation fOSC=405 MHz
∆ f from 3 s to 3 min after switch ON
kHz
∆ fsw4
UHF operation fOSC=845 MHz
∆ f from 3 s to 3 min after switch ON
kHz
*4
–7–
CXA3252N
Item
Symbol
Measurement conditions
Min.
Typ.
Max.
Unit
∆ fst1
VHF operation fOSC=100 MHz
∆ f when Vcc 5 V changes ±5%
kHz
∆ fst2
VHF operation fOSC=405 MHz
∆ f when Vcc 5 V changes ±5%
kHz
∆ fst3
UHF operation fOSC=405 MHz
∆ f when Vcc 5 V changes ±5%
kHz
∆ fst4
UHF operation fOSC=845 MHz
∆ f when Vcc 5 V changes ±5%
kHz
Oscillator phase
noise
C/N V
10 kHz offset
dBc/Hz
C/N U
10 kHz offset
dBc/Hz
Reference leak
REFL
Phase comparison frequency of
62.5 kHz, CP : 1
Supply voltage
drift
Lock-up time
*4
dB
LUT 1
msec
LUT 2
msec
*1
Value measured with untuned input.
NF meter direct-reading value (DSB measurement).
*3
Value with a desired reception signal input level of −30 dBm, an interference signal of 100 kHz/30 % AM, and an
interference signal level where S/I=46 dB measuered with a spectrum analyzer.
*4
Value when the PLL is not operating.
*2
–8–
CXA3252N
PLL Block
Item
Symbol
Measurement conditions
Min.
Typ.
Max.
Unit
CL, DA pins
“H” level input voltage
VIH
3
VCC
V
“L” level input voltage
VIL
GND
1.5
V
“H” level input current
IIH
VIH=VCC
0
–0.1
µA
“L” level input current
IIL
VIL=GND
–0.3
–4
µA
CE input
“H” level input voltage
VIH
3
VCC
V
“L” level input voltage
VIL
GND
1.5
V
“H” level input current
IIH
VIH=VCC
–100
–200
µA
“L” level input current
IIL
VIL=GND
35
100
µA
“H” output leak current
VIH
Vin=5.5 V
5
V
“L” output voltage
VIL
Iout=–3 mA
GND
0.4
V
Output current 1
ICPO1
Byte4/Bit6=0
±35
±75
µA
Leak current 1
LeakCP1
Byte4/Bit6=0
30
nA
Output current 2
ICPO2
Byte4/Bit6=1
±300
µA
Leak current 2
LeakCP2
Byte4/Bit6=1
100
nA
33
V
0.8
V
VCC-0.5
VCC
V
0
0.5
V
12
MHz
24
26
pF
–2
–1
kΩ
–25
mA
SDA output
CPO (charge pump)
±140
±50
±200
VT (VC voltage output)
Maximum output voltage
VTH
Minimum output voltage
VTL
0.5
LOCK
“H” output voltage
VLOCKH
When locked
“L” output voltage
VLOCKL
When unlocked
REFOSC
Oscillation frequency range
FXTOSC
3
Input capacitance
CXTOSC
22
Negative resistance
RNEG
Crystal source impedance
Output current
IBS
When ON
Saturation voltage
VSAT
When ON Source
current=20 mA
120
240
mV
Leak current
LeakBS
When OFF
0.5
3
µA
Band SW
–9–
CXA3252N
Item
Symbol
Measurement conditions
Min.
Typ.
Max.
Unit
400
kHz
2
Bus timing (I C bus)
SCL clock frequency
fSCL
0
Start waiting time
tWSTA
1300
ns
Start hold time
tHSTA
600
ns
“L” hold time
tLOW
1300
ns
“H” hold time
tHIGH
600
ns
Start setup time
tSSTA
600
ns
Data hold time
taHDAT
1300
ns
Data setup time
tSDAT
600
ns
Rise time
tR
300
ns
Fall time
tF
300
ns
Stop setup time
tSSTO
600
ns
Data setup time
tSD
300
ns
Data hold time
tHD
600
ns
Enable waiting time
tWE
300
ns
Enable setup time
tSE
300
ns
Enable hold time
tHE
600
ns
Bus timing (3-wire bus)
–10–
CXA3252N
Electrical Characteristics Measurement Circuit (I2C bus control)
+30V
22k
8200p
1.2k
6.8k 0.047µ
100p
33p
47k
3.2φ
5.5t
1n
47k
51
3.2φ
2.5t
1n
47k
51
+5V
47k
3.3µ
1n
2.6φ
2.5t
0.75p
0.5p 0.5p
IFOUT
1T363
150p
1T363
47k
1T363
7p
XTAL
4MHz
47k
1T362
56p
1n
REFOSC
CPO
VT
NC
IFOUT
23
24
22
21
20
18
19
47k
17
VOSC1
VCC3
25
GND
26
VOSC2
27
20 16p
6p
UOSCB1
28
2p
UOSCE2
29
UOSCB2
30
VCC2
31
GND2
32
ADSW/CE
6p
UOSCE1
100p
1n
1p
56p
47k
CL
DA
BS3
BS1
IFIN1
IFIN2
BS2
BS4
VCC1
MIXout1
MIXout2
GND1
BYP/MS
VHFin
UHFin1
UHFin2
CXA3252N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2k
12p
1n
1n
1n
12p
200
200
200
240
240
240
4.5t
240
4.5t
56p 56p
100
2.2µ
ADSW SCL
1n
VHF IN
UHF IN
SDA
+5V
Unmarked Ls are air coils with a wire diameter of 0.5 mm.
–11–
CXA3252N
Electrical Characteristics Measurement Circuit (3-wire bus control)
+30V
22k
8200p
1.2k
6.8k 0.047µ
100p
33p
47k
3.2φ
5.5t
1n
47k
51
3.2φ
2.5t
1n
47k
51
+5V
47k
3.3µ
1n
2.6φ
2.5t
0.75p
0.5p 0.5p
IFOUT
1T363
150p
1T363
47k
1T363
7p
XTAL
4MHz
47k
1T362
56p
1n
REFOSC
CPO
VT
NC
IFOUT
23
24
22
21
20
18
19
47k
17
VOSC1
VCC3
25
GND
26
VOSC2
27
20 16p
6p
UOSCB1
28
2p
UOSCE2
29
UOSCB2
30
VCC2
31
GND2
32
ADSW/CE
6p
UOSCE1
100p
1n
1p
56p
47k
CL
DA
BS3
BS1
IFIN1
IFIN2
BS2
BS4
VCC1
MIXout1
MIXout2
GND1
BYP/MS
VHFin
UHFin1
UHFin2
CXA3252N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2k
12p
1n
1n
1n
1n
12p
200
200
200
240
240
240
4.5t
240
4.5t
56p 56p
100
2.2µ
ADSW SCL
1n
VHF IN
UHF IN
SDA
+5V
Unmarked Ls are air coils with a wire diameter of 0.5 mm.
–12–
CXA3252N
Application Circuit (I2C bus control)
+30V
+5V
22k
100
39k
SWD
10k
4.7n
100p
82n
2.2n
10k
2p
1.2k
3.2φ 1n
5.5t
SWD
47k
150p 1n
3.2φ
2.5t
0.5p
47k
1.2k
10k
10k
2.2φ
1.5t
330p
IFOUT
ADSW
1T363
0.5p
1T363
10k
1n
XTAL
4MHz
15p
3.3µ
100p
10p
100p
2p
1T362
20p
1n
20
REFOSC
CPO
VT
NC
IFOUT
24
23
22
21
20
18
19
17
VOSC1
VCC3
25
GND
26
VOSC2
27
6p
UOSCB1
28
5p
UOSCE2
29
UOSCB2
30
VCC2
31
GND2
32
ADSW/CE
16p
UOSCE1
100p
3k
10k
CL
DA
BS3
BS1
IFIN1
IFIN2
BS2
BS4
VCC1
MIXout1
MIXout2
GND1
BYP/MS
VHFin
UHFin1
UHFin2
CXA3252N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
200
200
3.2φ
7.5t
150p
2k
68p
L1
47p
1000p
47p
CL
3.2φ
9.5t 1000p
56p
1n
1n
56p
VHF IN
DA
100
3.3µ
1n
UHF IN
1n
1n
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any
problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
–13–
CXA3252N
Application Circuit (3-wire bus control)
+30V
+5V
22k
100
39k
SWD
10k
4.7n
100p
82n
2.2n
10k
2p
1.2k
3.2φ 1n
5.5t
SWD
47k
150p 1n
3.2φ
2.5t
0.5p
47k
1.2k
10k
10k
2.2φ
1.5t
330p
IFOUT
ADSW
1T363
0.5p
1T363
10k
1n
XTAL
4MHz
15p
3.3µ
100p
10p
100p
2p
1T362
20p
1n
20
REFOSC
CPO
VT
NC
IFOUT
23
24
22
21
20
18
19
17
VOSC1
VCC3
25
GND
26
VOSC2
27
6p
UOSCB1
28
5p
UOSCE2
29
UOSCB2
30
VCC2
31
GND2
32
ADSW/CE
16p
UOSCE1
100p
3k
10k
CL
DA
BS3
BS1
IFIN1
IFIN2
BS2
BS4
VCC1
MIXout1
MIXout2
GND1
BYP/MS
VHFin
UHFin1
UHFin2
CXA3252N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
200
200
3.2φ
7.5t
150p
2k
68p
L1
47p
1000p
47p
CL
3.2φ
9.5t 1000p
56p
1n
1n
1n
56p
VHF IN
DA
100
3.3µ
1n
UHF IN
1n
1n
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any
problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
–14–
CXA3252N
Description of Functions
The CXA3252N is a ground wave broadcast tuner IC which converts frequencies to IF in order to tune and
detect only the desired reception frequency of VHF, CATV and UHF band signals.
In addition to the mixer, local oscillation and IF amplifier circuits required for frequency conversion to IF, this IC
also integrates a PLL circuit for local oscillation frequency control onto a single chip.
The functions of the various circuits are described below.
1. Mixer circuit
This circuit outputs the frequency difference between the signal input to VHFIN or UHFIN and the local oscillation signal.
2. Local oscillation circuit
A VCO is formed by externally connecting an LC resonance circuit composed of a varicap diode and inductance.
3. IF amplifier circuit
This circuit amplifies the mixer IF output, and consists of an amplifier stage and low impedance output stage.
4. PLL circuit
This PLL circuit fixes the local oscillation frequency to the desired frequency. It consists of a programmable
divider, reference divider, phase detector, charge pump and reference oscillator. The control format supports
both the I2C bus and 3-wire bus formats.
During I2C bus control, the frequency steps of 31.25, 50 or 62.5 kHz can be selected by the frequency division
setting value of the data-based referencedivider.
During 3-wire bus control, these frequency steps can be selected by the combination of the data length (18 or
19 bits) and the voltage applied to the BYP/MS pin.
5. Band switch circuit
The CXA3252N has four sets of built-in PNP transistors for switching between the VL, VH and UHF bands and
for switching the FM trap, etc. These PNP transistors can be controlled by the bus data.
The emitters for these PNP transistors are connected to an independent power supply pin (VCC3) from the
oscillator, mixer and PLL circuits, and support either 5 V or 9 V as the RF amplifier power supply.
–15–
CXA3252N
Description of Analog Block Operation
(See the Electrical Characteristics Measurement Circuit.)
VHF oscillator circuit
• This circuit is a differential amplifier type oscillator circuit. Pin 19 is the output and Pin 17 is the input.
Oscillation is performed by connecting an LC resonance circuit including a varicap to Pin 19 via coupled capacitance, inputting to Pin 17 with feedback capacitance, and applying positive feedback.
• The amplifier between Pins 17 and 19 has an extremely high gain. Therefore, care should be taken to avoid
creating parasitic capacitance, resistance or other feedback loops as this may produce abnormal oscillation.
VHF mixer circuit
• The mixer circuit employs a double balanced mixer with little local oscillation signal leakage.
The input format is base input type, with Pin 13 grounded via a capacitor and the RF signal input to Pin 14. (Pin
13 can also be used to switch the PLL mode according to the applied DC voltage value.)
• The RF signal is converted to IF frequency by oscillator signal and output from Pins 10 and 11.
Pins 10 and 11 are open collectors, so external power supply is necessary. In addition, single-tuned filters are
connected to Pins 10 and 11.
UHF oscillator circuit
• This oscillator circuit is designed so that two collector ground type Colpitts oscillators perform differential oscillation operation via an LC resonance circuit including a varicap.
• Resonance capacitance is connected between Pins 20 and 21, Pins 21 and 22, and Pins 22 and 23, and an LC
resonance circuit including a varicap is connected between Pins 20 and 23.
UHF mixer circuit
• This circuit employs a double balanced mixer like the VHF mixer circuit.
The input format is base input type, with Pins 15 and 16 as the RF input pins. The input method can be selected
from balanced input consisting of differential input to Pins 15 and 16 or unbalanced input consisting of grounding Pin 15 via a capacitor and input to Pin 16.
• Pins 10 and 11 are the mixer outputs. Pins 10 and 11 are open collectors, so external power supply is necessary. In addition, single-tuned filters are connected to Pins 10 and 11.
IF amplifier circuit
• Pins 5 and 6 are IF amplifier inputs with an input impedance of approximately 1 kΩ.
• The signals frequency converted by the mixer are output from Pins 10 and 11, so Pins 10 and 11 are connected
to Pins 5 and 6 via capacitors. ( A neighboring channel trap circuit can be formed by connecting a L and C
parallel circuit instead of capacitors.)
• The signal amplified by the IF amplifier is output from Pin 26.
The output impedance is approximately 75 Ω.
–16–
CXA3252N
Description of PLL Block
This IC supports both I2C bus and 3-wire bus control.
The I2C bus conforms to the standard I2C bus format, and bidirectional bus control is possible consisting of a
write mode in which various data are received and a read mode in which various data are sent.
The 3-wire bus is equipped with an 18- or 19-bit auto identify function, and the frequency step can be switched
according to the voltage applied to the BYP/MS pin.
The PLL of this IC does not have a fixed frequency division circuit and performs high-speed phase comparison,
providing low reference leak and quick lock-up time characteristics.
Pin Function Table
Symbol
I2C bus
3-wire bus
CL
SCL input
CLOCK input
DA
SDA I/O
DATA input
ADSW/CE
Address selection
ENABLE input
1) PLL Mode Setting Method
The selected control bus is set according to the BYP/MS pin (Pin 13) voltage.
BYP/MS pin
Control bus
GND
I2C Bus
OPEN
3-wire bus
VCC
3-wire bus
During 3-wire bus control, the transferred bit length (18, 19 or 27 bits) is automatically identified.
During 18- or 19-bit transfer, the frequency steps in the table below are set according to the combination of the
BYP/MS pin voltage and the bit length. This IC does not have a fixed frequency division circuit, so the phase
comparison frequency becomes the frequency step.
BYP/MS
Pin voltage
Transfer bit length
Reference
Divider
Phase comparison
frequency
Frequency
Step*
18
64
62.5 kHz
62.5 kHz
OPEN
19
128
31.25 kHz
31.25 kHz
OPEN
or
VCC
27
Selectable from
64, 80 or 128
62.5 kHz/
50.0 kHz/
31.25 kHz
62.5 kHz/
50.0 kHz/
31.25 kHz
VCC
18
80
50.0 kHz
50.0 kHz
VCC
19
80
50.0 kHz
50.0 kHz
* Phase comparison frequency and frequency step are for when the crystal oscillation=4 MHz.
–17–
CXA3252N
2) Programming
The VCO lock frequency is obtained according to the following formula.
fosc = fref × (32 M + S)
fosc : local oscillator frequency
fref : phase comparison frequency
M : main divider frequency division ratio
S : swallow counter frequency division ratio
The variable frequency division ranges of M and S are as follows, and are set as binary.
S < M ≤ 1023 (S < M ≤ 511 during 18-bit transfer)
0 ≤ S ≤ 31
3) I2C Bus Control
This IC conforms to the standard I2C bus format, and bidirectional bus control is possible consisting of a write
mode in which various data are received and a read mode in which various data are sent. Write and read
modes are recognized according to the setting of the final bit (R/W bit) of the address byte. Write mode is set
when the R/W bit is “0” and read mode is set when the R/W bit is “1”.
–18–
CXA3252N
3-1) Address settings
Up to four addresses can be selected by the hardware bit settings, so that multiple PLL can exist within one
system.
The responding address can be set according to the ADSW/CE pin voltage.
1
1
0
0
0
MA1
MA0
R/W
Address
“CE” pin voltage
MA1
MA0
0 to 0.1 VCC
0
0
OPEN or
0.2 VCC to 0.3 VCC
0
1
0.4 VCC to 0.6 VCC
1
0
0.9 VCC to VCC
1
1
Hardware bits
3-2) Write mode
Write mode is used to receive various data. In this mode, byte 1 contains the address data, bytes 2 and 3
contain the frequency data, byte 4 contains the control data, and byte 5 contains the band switch data.
These data are latch transferred in the manner of byte 1, byte 2 + byte 3, and byte 4 + byte 5.
When the correct address is received and acknowledged, the data is recognized as frequency data if the
first bit of the next byte is “0”, and as control data and band switch data if this bit is “1”.
Also, when data transmission is stopped part-way, the previously programmed data is valid. Therefore,
once the control and band switch data have been programmed, 3-byte commands consisting of the address
and frequency data are possible.
Further, even if the I2C bus stop conditions are not met, data can be input by sending the start conditions
and the new address.
–19–
CXA3252N
The control format is as shown in the table below.
Write-mode : Slave Receiver
MSB
LSB
MODE
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address byte
1
1
0
0
0
MA1
MA0
0
A
Divider byte 1
0
M9
M8
M7
M6
M5
M4
M3
A
Divider byte 2
M2
M1
M0
S4
S3
S2
S1
S0
A
Control byte
1
CP
0
CD
X
R1
R0
OS
A
Band SW byte
X
X
X
X
BS4
BS3
BS2
BS1
A
X : Don’t care
A
:
MA0, MA1 :
M0 to
:
S0 to
:
CD
:
OS
:
CP
:
BS1 to BS4
R0, R1
:
Acknowledge bit
address setting
main divider frequency division ratio setting
swallow counter frequency division ratio setting
charge pump OFF (when “1”)
varicap output OFF (when “1”)
charge pump current switching (200 µA when “1”, 50 µA when “0”)
:
band switch control (output PNP transistor ON when “1”)
reference divider frequency division ratio setting.
(see the Reference Divider Frequency Division Ratio Table)
Reference Divider Frequency Division Ratio Table
R1
R0
Reference divider
0
1
128
1
1
64
X
0
80
X : Don’t care
–20–
CXA3252N
3-3) Read mode
In read mode, power- on reset operation status the phase comparator locked/unlocked status and 5-level A/
D converter input pin voltage status are transmitted and output to the master.
The read data format is as shown in the table below.
Read mode : Slave Transmitter
MODE
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address byte
1
1
0
0
0
MA1
MA0
1
A
Status byte
X
FL
1
1
1
0
0
0
A
A
: Acknowledge bit
MA0, MA1 : address setting
FL
: lock detection signal (1 : locked, 0 : unlocked)
–21–
CXA3252N
Example of Representative Characteristics
Circuit current vs. Supply voltage 1
Circuit current vs. Supply voltage 2
60
20
58
54
DICC-Circuit current [mA]
AICC-Circuit current [mA]
56
VHF
UHF
52
50
48
46
15
44
42
40
4.7
4.8
4.9
5
5.1
5.2
5.3
10
4.6
5.4
4.8
VCC1-Supply voltage [V]
Band SW output voltage vs. Output current (BS1, BS2, BS3, BS4)
9.2
VCC3=9V
9.0
8.8
8.6
VCC3=5V
8.8
8.6
VCC3=5V
5.0
4.8
4.8
4.6
4.6
4.4
4.4
0
5
10
15
20
25
0
Output current [mA]
I/O characteristics (Untuned input)
10
0
–10
–20
fRF=145MHz (VHF)
fRF=495MHz (UHF)
fIF is both f=45MHz
–30
–40
–50
–60
–60
–50
–40
–30
–20
–10
1
2
3
4
Output current [mA]
20
IF output level [dBm]
5.4
Band SW output voltage vs. Output current
VCC3=9V
5.0
5.2
9.2
Output voltage [V]
Output voltage [V]
9.0
5
VCC2-Supply voltage [V]
0
10
20
RF level [dBm]
–22–
5
6
CXA3252N
Conversion gain vs. Reception frequency (Untuned input)
Noise figure vs. Reception frequency (Untuned input, in DSB)
20
fIF=45MHz
40
30
UHF
VHF (Low)
20
NF-Noise figure [dB]
CG-Conversion gain [dB]
fIF=45MHz
VHF (High)
10
15
VHF (Low) VHF (High)
UHF
10
5
0
0
0
100
200
300
400
500
600
700
800
0
900
100
200
Reception frequency [MHz]
500
600
700
800
900
Vcc–5%
Vcc+5%
(Vcc=5V)
200
VHF (Low) VHF (High)
80
+B drift [kHz]
CM-Cross modulation [dBµ]
400
Oscillation frequency power supply fluctuation (PLL off)
Next adjacent cross modulation vs. Reception frequency (Untuned input)
400
120
VHF (Low) VHF (High)
UHF
300
100
60
fIF=45MHz
fUD=fD+12MHz
fUD=fD–12MHz
(100kHz, 30%AM)
40
100
UHF
0
–100
–200
20
–300
–400
0
0
100
200
300
400
500
600
700
800
900
PCS beat characteristics
+20
+10
0
fIF
–10
–20
–30
fBeat
–40
VHF (Low)
fLocal=95MHz
fP=49.25MHz
fC=52.83MHz (fP–12dB)
fS=53.75MHz (fP–1.7dB)
–50
–60
–70
–80
–40
fIF=45.75MHz
fBeat=fIF±920kHz
–30
–20
–10
0
+10
0
100
200
300
400
500
600
Oscillation frequency [MHz]
Reception frequency [MHz]
IF output level [dBm]
300
Reception frequency [MHz]
+20
SG output level [dBm] (fP level)
–23–
700
800
900
CXA3252N
Tuning Response Time 1
VHF (Low) 95MHz → VHF (High) 395MHz (CP=1)
T=27.2msec
5.0V/div
Offset 10.0V
–40,0000ms
10,0000ms
10.0ms/div
60,0000ms
real time
VHF (Low) 95MHz → VHF (High) 395MHz (CP=0)
T=75.6msec
5.0V/div
Offset 10.0V
–130,000ms
20,0000ms
30.0ms/div
–24–
170,000ms
real time
CXA3252N
Tuning Response Time 2
UHF 413MHz → UHF 847MHz (CP=1)
T=34.2msec
5.0V/div
Offset 10.0V
–40,0000ms
10,0000ms
10.0ms/div
60,0000ms
real time
UHF 413MHz → UHF 847MHz (CP=0)
T=86.0msec
5.0V/div
Offset 10.0V
–70,0000ms
30,0000ms
20.0ms/div
–25–
130,000ms
real time
CXA3252N
Tuning Response Time 3
VHF (High) 395MHz → VHF (Low) 95MHz (CP=1)
T=12.6msec
5.0V/div
Offset 10.0V
–40,0000ms
10,0000ms
10.0ms/div
60,0000ms
real time
VHF (High) 395MHz → VHF (Low) 95MHz (CP=0)
T=39.2msec
5.0V/div
Offset 10.0V
–100,000ms
0,00000ms
20.0ms/div
–26–
100,000ms
real time
CXA3252N
Tuning Response Time 4
UHF 847MHz → UHF 413MHz (CP=1)
T=15.0msec
5.0V/div
Offset 10.0V
–40,0000ms
10,0000ms
20.0ms/div
600,000ms
real time
UHF 847MHz → UHF 413MHz (CP=0)
T=50.0msec
5.0V/div
Offset 10.0V
–100,000ms
0,00000ms
20.0ms/div
–27–
100,000ms
real time
CXA3252N
IF output spectrum
10dB/div
VHF (Low)
fRF=55MHz
fL0=100MHz
RF input level : –40dBm
CENTER 45.0MHz
#RES BW 1.0kHz
SPAN 100.0kHz
SWP 30.0 sec
#VBW 10Hz
IF output spectrum
10dB/div
VHF (High)
fRF=350MHz
fL.0=395MHz
RF input level : –40dBm
CENTER 45.0MHz
#RES BW 1.0kHz
#VBW 10Hz
–28–
SPAN 100.0kHz
SWP 30.0 sec
CXA3252N
IF output spectrum
10dB/div
UHF
fRF=800MHz
fL0=845MHz
RF input level : –40dBm
CENTER 45.0 270MHz
#RES BW 1.0kHz
#VBW 10Hz
–29–
SPAN 100.0kHz
SWP 30.0 sec
CXA3252N
VHF Input Impedance
j50
j25
50MHz
VHFin
0
BYP/MS
j100
13
14
1000p
S11
350MHz
–j100
–j25
–j50
UHF Input Impedance
j50
j25
UHFin2
0
UHFin1
j100
15
16
1000p
S11
350MHz
800MHz
–j100
–j25
–j50
–30–
CXA3252N
IF Output Impedance
j50
j25
j100
45MHz
38MHz
0
–j100
–j25
–j50
–31–
CXA3252N
Package Outline
Unit : mm
32PIN SSOP(PLASTIC)
x4
11.0
1.45MAX
0.1
0.1 S A B
A
S
x2
B
5.6
17
0.2 S A B
7.6
32
A
16
0.1
1
0.65
0.1 S
0.13 M S A
0.6 ± 0.15
0.25
0.1 ± 0.05
+ 0.1
0.22 – 0.06
0˚ to 8˚
DETAIL A
DETAIL B
(0.15)
+ 0.05
0.15 – 0.02
B
(0.5)
(0.22)
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SSOP-32P-L01
LEAD TREATMENT
PALLADIUMA PLATING
EIAJ CODE
SSOP032-P-0056
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.1g
JEDEC CODE
Sony Corporation
–32–
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