Supertex inc. HV7100 24/48V Fan Driver/Controller With High-Side Drive Features ►► ►► ►► ►► ►► ►► ►► High-side drive allows use of tachs Direct interface to host controller Noise-immune linear speed control 4-bit digital speed control Operates from single +24/+48V supply Programmable PWM frequency Undervoltage lockout The HV7100 is an integrated PWM speed controller for driving 24 and 48VDC fans. The features and benefits provided by the HV7100 make driving fans simple and low cost. The HV7100 drives a high side external P-channel FET, allowing the use of fans having a ground-based tachometer signal. It has a wide input voltage range of +16 to +90V, ideal for +24 or +48V systems. No low voltage supply is needed. A 4-bit digital control input provides direct interfacing with a micro controller or system processor to control the fan speed. It can also be used as a stand-alone fan controller, via a thermistor connection to the Linear Control pin. Applications ►► ►► ►► ►► ►► ►► General Description 24/48V chassis cooling tray Servers SAN equipment Cellular and fix wireless systems 24/48V PBX system Base stations The HV7100 has a wide PWM frequency range. When driving fans directly with a PWM supply voltage, frequency may be set low, around 50 - 120Hz. When used to drive fans requiring a DC supply, an LC filter may be employed. In this case, PWM frequency may be as high as 100kHz, reducing component sizes in the filter. The HV7100 is an ideal device to incorporate in fan trays and fan control modules, as it reduces circuit complexity and minimizes parts count and overall cost for thermal management. Typical Application Circuit VPP VPP1 speed control enable VPP2 VGATE DIN0 - DIN3 HV7100 EN Optional LC filter for providing a DC fan drive LIN Host Controller CT OUT RT VDD GND tach signals Doc.# DSFP-HV7100 B072413 Supertex inc. www.supertex.com HV7100 Pin Configuration Ordering Information Part Number Package Packing VDD 1 14 OUT HV7100NG-G 14-Lead SOIC (NB) 53/Tube LIN 2 13 VPP2 DIN0 3 12 VPP1 HV7100NG-G M903 14-Lead SOIC (NB) 2500/Reel -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings Parameter Value VPP to GND -0.5V to 90V VDD to GND DIN1 4 11 VGATE DIN2 5 10 RT DIN3 6 9 CT EN 7 8 GND 14-Lead SOIC (top view) -0.3V to +6V Input voltage, LIN -0.3V to (VDD + 0.3V) Input voltage, DIN0 - DIN2 Product Marking -0.3V to (VDD + 0.3V) Gate to VPP Top Marking +0.5V to -15V Continuous power dissipation Operating temperature range YWW -40°C to +85°C Storage temperature range Recommended Operating Conditions Min Typ Max Units VDD Externally applied VDD 3.7 - 5.5 V VPP High voltage supply 16 - 75 V fOSC Oscillator frequency 50 - 100 kHz RT Oscillator timing resistor 12 - 500 kΩ LLLLLLLL Bottom Marking -65°C to +150°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Sym Parameter Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging HV7100NG 750mW (TA = +25°C) CCCCCCCCC AAA *May be part of top marking Package may or may not include the following marks: Si or 14-Lead SOIC Typical Thermal Resistance Package θja 44-Lead PLCC 37OC/W Electrical Characteristics (Operating specifications are at TA = 25°C, VPP = 16 to 75V, VDD = 3.0 to 5.5V, unless otherwise noted) Sym Parameter Min Typ Max Units - - 4.0 mA Conditions Supplies IPP VPP supply current No ext load on VDD, fOSC = 50kHz, 250pF on OUT pin UVPP(ON) VPP UVLO turn-on threshold 11.7 13.0 14.3 V --- UVPP(HYS) VPP UVLO hysteresis 1.5 2.0 2.5 V --- VDD VDD internal regulation 3.0 3.3 3.6 V VPP = 16V to 75V Doc.# DSFP-HV7100 B072413 2 Supertex inc. www.supertex.com HV7100 Electrical Characteristics (cont.) (Operating specifications are at TA = 25°C, VPP = 16 to 75V, VDD = 3.0 to 5.5V, unless otherwise noted) Sym Parameter Min Typ Max Units IDD(INT) IDD(EXT) Conditions VDD supply current - - 2.0 mA External applied VDD = 5.0V, fOSC = 50kHz Current available from internal VDD regulator for external circuitry - - 2.0 mA ∆VDD<200mV Gate Driver VGATE Gate regulator output voltage -10.2 -12 -13.8 V Referenced to VPP VOUTH Gate drive output voltage high -10.2 -12 -13.8 V Referenced to VPP, VOUTL Gate drive output voltage low 0 - -0.8 V Test current = 15mA RSRC Pull-up resistance - - 25 Ω Test Current = 15mA RSINK Pull-down resistance - - 25 Ω Test Current = -15mA tRISE Rise time - - 100 ns CLOAD = 250pF tFALL Fall time - - 100 ns CLOAD = 250pF Oscillator fOSC Oscillator frequency 51 60 69 Hz CT = 100nF, RT = 43.0kΩ fOSC Oscillator frequency 34 40 46 kHz CT = 330pF, RT = 19.5kΩ 0.7 x VDD - - V --- Logic input voltage, low - - 0.3 x VDD V --- TEN(ON) Enable to gate turn on delay 0 - 150 ns LIN = VDD, DIN0 - DIN3 = 1111 TEN(OFF) Enable to gate turn off delay 0 - 150 ns LIN = VDD, DIN0 - DIN3 = 1111 Digital input pull down resistance 200 330 460 kΩ --- Linear control input current -1.0 - 1.0 uA -40C to +85C D Duty cycle 16 20 24 % VLIN = 0.9V, DIN = 0000 D Duty cycle 75 80 85 % VLIN = 2.1V, DIN = 0000 D Duty cycle 16 20 24 % VLIN = 0V, DIN = 0011 D Duty cycle 75 80 85 % VLIN = 0V, DIN = 1100 D Duty cycle - - 0 % VLIN = 0V, DIN = 0000 D Duty cycle 100 - - % VLIN = 0V, DIN = 1111 Logic and Linear Inputs VDIN0-3(hi), Logic input voltage, high VEN(hi) VDIN0-3(lo), VEN(lo) IDIN0-3 ILIN Duty Cycle Doc.# DSFP-HV7100 B072413 3 Supertex inc. www.supertex.com HV7100 Functional Block Diagram VPP VDD powered by VDD - GND DIN0-3 DAC VPP1 VPP2 powered by VPP - VGATE Reg 3.3V Ideal Diodes UVLO LIN CT RT OUT Level Translator Ramp Gen Reg GND EN Functional Description P-Channel Gate Driver The HV7100 requires a single +16 to +75V supply to bias its internal circuitry. It internally generates 3.3V for VDD, and -12V relative to VPP for driving the external P-channel MOSFET. If an external VDD is applied (greater than 3.6V but less than 5.5V), the internal regulator will shut off. The HV7100 drives an external P-channel FET to drive the 24V/48V DC fan. The PWM output of the comparator circuit is level translated and is the input to the gate drive circuit. The gate drive circuit turns an external P-channel FET on and off by applying -12V and 0V (reference to VPP), respectively, between its gate and source. The -12V supply to the gate drive circuit is generated internally from VPP. An external diode, connected across the fan terminals, is required to clamp the voltage across the fan to a diode drop during the off period. Enable The EN pin directly controls the gate drive circuit. Pulling this pin to logic ground applies 0V to the external P-channel gate to turn it off. Applying a logic HIGH signal or pulling the voltage to VDD resumes the switching cycle of the PWM signal. Pulse Width Modulator The PWM circuit compares the internal triangle wave oscillator (0.5 – 2.5V pk-pk) with the linear control voltage or the DAC output. Its output is a square-wave PWM signal with duty cycle ranging from 0% to 100%. Speed Control The fan speed can be controlled in three ways: When an external PWM signal is applied to the Enable input and the internal PWM generator is not needed, RT and LIN should be connected to VDD and CT connected to GND. Linear Control - Applying a DC voltage between 0.5V to 2.5V to the LIN pin varies the duty cycle of the voltage driving the fans from 0% to 100% according to: Oscillator A capacitor connected between the CT and GND sets the frequency of the internal triangular frequency oscillator in conjunction with the timing resistor RT. RT sets the charge/ discharge current into and out of CT. D= VLIN 2 - 0.25 Linear control voltage below 0.5V will turn off the fan completely (0% duty cycle), while voltage greater than 2.5V will fully turn the fan on (100% duty cycle). The frequency is determined by the following equation: f= VGATE (0.258) (RT x CT) Doc.# DSFP-HV7100 B072413 4 Supertex inc. www.supertex.com HV7100 Table 1. DAC signal and LIN voltage to Duty Cycle Programming. When using linear control mode, DIN0 – DIN3 should be set to logic 0. If desired, DIN may be used to set a lower limit on the fan speed. This input is immune to moderate noise on the control signal. Digital Control - Applying logic signals to the DIN0 – DIN3 pins sets the duty cycle of the output. 0000 = 0% and 1111 = 100%. See Table 1 for details. In digital control mode, LIN should be set to 0V. DIN0 – DIN3 pins have internal pull downs so that the DAC output will default to 0V when it is not used. External PWM - An external PWM signal can be applied to the Enable pin to directly control the duty cycle. A logic 0 turns the transistor off, and a logic 1 turns it on. When using this control method, connect DIN0 – DIN3, LIN, and RT to VDD. Connect CT to GND. The DAC output and the Linear Control signals are OR’d together. Whichever has the higher value dominates. This allows an analog temperature sensing circuit to override the digital inputs (DIN0 – DIN3) for added system protection. The following table illustrates the correlation between the digital inputs and LIN voltage to the PWM duty cycle. DIN3 DIN2 DIN1 DIN0 LIN Gate Drive Duty Cycle 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.500V 0.633V 0.766V 0.900V 1.033V 1.167V 1.300V 1.433V 1.567V 1.700V 1.833V 1.967V 2.100V 2.233V 2.367V 2.500V 0%* 6.7% 13.3% 20.0% 26.7% 33.3% 40.0% 46.7% 53.3% 60.0% 66.7% 73.3% 80.0% 86.7% 93.3% 100%* * Guaranteed 0% @ 0000 and 100% @ 1111 PWM Fan Drive VPP VPP1 VDD D3 D2 D1 D0 VPP2 VGATE HV7100 EN LIN OUT CT RT VDD GND When using direct PWM drive to the fans, it is best to set a low PWM frequency, in the range of 50Hz -120Hz. Doc.# DSFP-HV7100 B072413 5 Supertex inc. www.supertex.com HV7100 DC Fan Drive VPP VPP1 VPP2 VGATE DIN0 – DIN3 EN The addition of an LC low pass filter converts the PWM output to a DC voltage HV7100 LIN OUT CT RT VDD GND The HV7100 controls the fans with a PWM supply voltage. However, some fans require a steady DC voltage for proper operation. In order for these fans to function properly, an LC low pass filter should be added to cancel the PWM output to a steady DC voltage. The LC filter also provides another advantage. Some fans draw large spikes of current during start-up and/or during normal operation. Without the LC filter, these current spikes would be drawn directly from the +24 or +48V supply, causing potential conducted EMI problems. The LC filter prevents these spikes from occuring and/or reaching the +24 or +48V supply. Setting a Lower Speed Limit VPP VPP1 VDD D3 D2 D1 D0 VPP2 VGATE HV7100 EN LIN OUT CT RT VDD GND When using the linear control input, the digital control inputs may be used to set a lower limit on the duty cycle. This is based on the fact that the higher control setting, linear Doc.# DSFP-HV7100 B072413 or digital, dominates. In the example above, duty cycle is prevented from falling below 25% even if the linear control signal goes to 0V. 6 Supertex inc. www.supertex.com HV7100 Pin Description Pin # Function Description 1 VDD Output of an internal linear voltage regulator, which in turn is powered by VPP. It provides power to the internal low-side (ground referenced) circuitry. An external voltage may be applied to this pin, provided it is higher than 3.6V but less than 5.5V. Bypass this pin with a 100nF ceramic capacitor to ground. 2 LIN A DC voltage ranging from 0.5 to 2.5V sets the duty cycle of the gate output from 0% to 100%. This input is immune to moderate noise on the control signal. 3 DIN0 4 DIN1 5 DIN2 6 DIN3 7 EN 8 GND Ground return for all the internal circuitry. This pin must be electrically connected to the ground of the power train and logic return. 9 CT In conjunction with RT, a capacitor from this pin to ground sets PWM frequency. A triangle wave appears on this pin, with an amplitude of 0.5 - 2.5V and at the PWM frequency. 10 RT In conjunction with CT, a resistor from this pin to ground sets PWM frequency. 11 VGATE 12 VPP1 13 VPP2 Supply voltage pins. Both must be connected to the supply voltage (+24V/+48V). Connect together as close as possible to the IC. Bypass locally with a ceramic capacitor to ground. 14 OUT This pin is the output gate driver for an external P-channel power MOSFET. Doc.# DSFP-HV7100 B072413 Applying 0000 to 1111 to these logic input pins sets the duty cycle of the gate output from 0 to 100%. A 1-bit increment is equal to 6.67% increment in duty cycle. See Table 1 on page 5. Enable input. A logic high applied to this input enables the output. This is the output pin of the internal linear regulator that biases the gate drive circuit. Bypass with 100nF ceramic capacitor to VPP. 7 Supertex inc. www.supertex.com HV7100 14-Lead SOIC (Narrow Body) Package Outline (NG) 8.65x3.90mm body, 1.75mm height (max), 1.27mm pitch D θ1 14 Note 1 (Index Area D/2 x E1/2) E1 E Gauge Plane L2 e 1 L1 b Top View L Seating Plane θ View B View B A h h A A2 Seating Plane A1 Side View View A-A A Note: 1. This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol MIN Dimension NOM (mm) MAX A A1 A2 b 1.35* 0.10 1.25 0.31 - - - - 1.75 0.25 1.65* 0.51 D E E1 8.55* 5.80* 3.80* 8.65 6.00 3.90 8.75* 6.20* 4.00* e 1.27 BSC h L 0.25 0.40 - - 0.50 1.27 L1 1.04 REF L2 0.25 BSC θ θ1 0O 5O - - 8O 15O JEDEC Registration MS-012, Variation AB, Issue E, Sept. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-14SOICNG, Version F041309. (The package drawings in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV7100 B072413 8 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com