Catalyst CAT661 High frequency 100ma cmos charge pump, inverter/doubler Datasheet

H
CAT661
EE
GEN FR
ALO
High Frequency 100mA CMOS Charge Pump, Inverter/Doubler
LE
FEATURES
■ Converts V+ to V- or V+ to 2V+
A D F R E ETM
■ Pin-compatible to MAX660, LTC660 with higher
frequency operation
■ Low output resistance, 10Ω max.
■ Available in 8-pin SOIC, DIP and 0.8mm thin
■ High power efficiency
■ Selectable charge pump frequency of 25kHz
or 135kHz; optimize capacitor size.
4x4mm TDFN packages
■ Lead-free, halogen-free package option
■ Low quiescent current
APPLICATIONS
■ Negative voltage generator
■ Low EMI power source
■ Instrumentation
■ Voltage doubler
■ GaAs FET biasing
■ LCD contrast bias
■ Voltage splitter
■ Lithium battery power supply
■ Cellular phones, pagers
DESCRIPTION
The CAT661 is a charge-pump voltage converter. It can
invert a positive input voltage to a negative output. Only
two external capacitors are needed. With a guaranteed
100mA output current capability, the CAT661 can replace
a switching regulator and its inductor. Lower EMI is
achieved due to the absence of an inductor.
connected to V+. The operating frequency can also be
adjusted with an external capacitor at the OSC pin or by
driving OSC with an external clock.
Both 8-pin DIP and SO packages are available. The
TDFN package 4x4mm footprint features a 0.8mm
maximum height. For die availability, contact Catalyst
Semiconductor marketing.
In addition, the CAT661 can double a voltage supplied
from a battery or power supply. Inputs from 2.5V to 5.5V
will yield a doubled, 5V to 11V output.
The CAT661 can replace the MAX660 and the LTC660
in applications where higher oscillator frequency and
smaller capacitors are needed. In addition, the CAT661
is pin compatible with the 7660/1044, offering an easy
upgrade for applications with 100mA loads.
A Frequency Control pin (BOOST/FC) is provided to
select either a high (typically 135kHz) or low (25kHz)
internal oscillator frequency, thus allowing quiescent
current vs. capacitor size trade-offs to be made. The
135kHz frequency is selected when the FC pin is
TYPICAL APPLICATION
+VIN
1.5V to 5.5V
C1
+
1
BOOST/FC
2
CAP+
3
4
GND
CAT661
CAP-
V+
8
OSC
7
LV
OUT
6
5
Inverted
Negative
Voltage
Output
C1
VIN = 2.5V to 5.5V
VOLTAGE INVERTER
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
+
1
BOOST/FC
V+
8
2
CAP+
OSC
7
3
GND
LV
6
4
CAP-
OUT
5
CAT661
Doubled
Positive
Voltage
Output
POSITIVE VOLTAGE DOUBLER
1
Doc. No. 5003, Rev. J
CAT661
PIN CONFIGURATION
DIP Package (P)
SO Package (S, X)
8 V+
BOOST/FC 1
CAP+ 2
CAT661
CAP+ 2
6 LV
GND 3
CAT661
7 OSC
6 LV
GND 3
5 OUT
CAP- 4
8 V+
BOOST/FC 1
7 OSC
5 OUT
CAP- 4
TDFN Package (RD8, ZD8)
BOOST/FC 1
CAP+ 2
8 V+
CAT661
7 OSC
GND 3
6 LV
CAP- 4
5 OUT
(Top View)
TDFN Package: 4mm x 4mm
0.8mm maximum height
PIN DESCRIPTIONS
Circuit Configuration
Pin Number
Name
1
Boost/FC
Inverter
Freqency Control for the internal oscillator.
With an external oscillator BOOST/FC has
no effect.
Boost/FC Oscillator Frequency
Doubler
Oscillator Frequency
Open
25kHz typical, 10kHz minimum
40kHz typical
V+
135kHz typical, 80kHz minimum 135kHz typical, 40kHz minimum
Same as inverter.
2
CAP+
Charge Pump Capacitor. Positive terminal.
Same as inverter.
3
GND
Power Supply Ground.
Power supply. Positive voltage input.
4
CAP-
Charge pump capacitor. Negative terminal.
Same as inverter.
5
OUT
Output for negative voltage.
Power supply ground.
6
LV
Low-Voltage selection pin. When the input
voltage is less than 3V, connect LV to GND.
For input voltages above 3V, LV may be
connected to GND or left open. If OSC is
driven externally, connect LV to GND.
LV must be tied to OUT for all input
voltages.
7
OSC
Oscillator control input. An external capacitor
can be connected to lower the oscillator
frequency. An external oscillator can drive
OSC and set the chip operating frequency.
The charge-pump frequency is one-half the
frequency at OSC.
Same as inverter. Do not overdrive
OSC in doubling mode. Standard logic
levels will not be suitable. See the
applications section for additional
information.
8
V+
Power supply. Positive voltage input.
Positive voltage output.
ORDERING INFORMATION
Part Number
Package
Temperature Range
CAT661EPA
8 lead Plastic DIP
-40°C to 85°C
CAT661ESA
8-lead SO
-40°C to 85°C
CAT661ESA-TE13
8-lead SO, Tape & Reel
-40°C to 85°C
CAT661EVA
8-lead SO (Lead-free, Halogen-free)
-40°C to 85°C
CAT661EVA-TE13
8-lead SO (Lead-free, Halogen-free)
-40°C to 85°C
CAT661ERD8
8-pad TDFN
-40°C to 85°C
CAT661EZD8
8-pad TDFN (Lead-free, Halogen-free)
-40°C to 85°C
Doc. No. 5003, Rev. J
2
CAT661
ABSOLUTE MAXIMUM RATINGS
V+ to GND ............................................................. 6V
Storage Temperature ......................... -65°C to 160°C
Lead Soldering Temperature (10 sec) ............. 300°C
Input Voltage (Pins 1, 6 and 7) .. -0.3V to (V+ + 0.3V)
ESD Rating-Human Body Model ..................... 2000V
BOOST/FC and OSC Input Voltage ........... The least
negative of (Out - 0.3V) or (V+ - 6V) to (V+ + 0.3V)
Note: TA = Ambient Temperature
These are stress ratings only and functional operation is not
implied. Exposure to absolute maximum ratings for prolongued
time periods may affect device reliability. All voltages are with
respect to ground.
Output Short-circuit Duration to GND .............. 1 sec.
(OUT may be shorted to GND for 1 sec without damage but
shorting OUT to V+ should be avoided.)
Operating Ambient Temperature Ranges
Continuous Power Dissipation (TA = 70°C)
Plastic DIP ................................................ 730mW
CAT661E .............. -40°C to 85°C
SO ............................................................ 500mW
TDFN ............................................................... 1W
ELECTRICAL CHARACTERISTICS
V+ = 5V, C1 = C2 = 100µF, Boost/FC = Open, COSC = 0pF, and Test Circuit is Figure 1 unless otherwise noted.
Temperature is TA = TAMIN to TAMAX unless otherwise noted.
Parameter
Supply Voltage
Supply Current
Symbol
VS
IS
Conditions
Min.
Output Resistance
IOUT
RO
Max.
Units
V
Inverter: LV = Open. RL = 1kΩ
3.0
5.5
Inverter: LV = GND. RL = 1kΩ
1.5
5.5
Doubler: LV = OUT. RL = 1kΩ
2.5
5.5
BOOST/FC = open, LV = Open
BOOST/FC = V+ , LV = Open
Output Current
Typ
OUT is more negative than -4V
0.2
0.5
1
3
100
C1 = C2 = 10µF,
mA
mA
3.5
10
3.5
10
Ω
BOOST/FC = V+ (C1, C2 ESR ≤ 0.5Ω)
C1 = C2 = 100µF (Note 2)
Oscillator Frequency FOSC
BOOST/FC = Open
10
25
(Note 3)
BOOST/FC = V+
80
135
OSC Input Current
Power Efficiency
IOSC
PE
±2
±10
µA
96
98
%
92
96
BOOST/FC = Open
BOOST/FC = V+
RL = 1kΩ connected between V+ and
kHz
OUT, TA = 25°C (Doubler)
RL = 500Ω connected between GND and
OUT, TA = 25°C (Inverter)
IL = 100mA to GND, TA = 25°C (Inverter)
Voltage Conversion
VEFF
No load, TA = 25°C
88
99
99.9
%
Efficiency
1. In Figure 1, test circuit electrolytic capacitors C1 and C2 are 100µF and have 0.2Ω maximum ESR. Higher ESR levels may reduce
efficiency and output voltage.
2. The output resistance is a combination of the internal switch resistance and the external capacitor ESR. For maximum voltage and
efficiency keep external capacitor ESR under 0.2Ω.
3. FOSC is tested with COSC = 100pF to minimize test fixture loading. The test is correlated back to COSC=0pF to simulate the capacitance at
OSC when the device is inserted into a test socket without an external COSC.
3
Doc. No. 5003, Rev. J
CAT661
Figure 1. Test Circuit Voltage Inverter
1
V+
2
+
3
C1
100µF
4
BOOST/FC
V+
CAP+
OSC
CAT661
GND
LV
CAP-
OUT
8
IS
7
V+
5V
External
Oscillator
6
COSC
5
RL
IL
VOUT
C2
+ 100µF
TYPICAL OPERATING CHARACTERISTICS
Typical characteristic curves are generated using the circuit in Figure 1. Inverter test conditions are: V+ 5V, LV = GND,
BOOST/FC = Open and TA = 25˚C unless otherwise indicated. Note that the charge-pump frequency is one-half the
oscillator frequency.
Supply Current vs. Input Voltage
Supply Current vs. Temperature (No Load)
250
1200
INPUT CURRENT [µA]
INPUT CURRENT [µA]
1400
1000
800
FC = V+
600
400
FC = open
200
VIN = 5V
200
150
VIN = 3V
100
50
VIN = 2V
0
1
2
3
4
5
INPUT VOLTAGE [V]
0
-50
6
0
25
50
75
100
125
TEMPERATURE [oC]
Output Resistance vs. Temperature (50Ω load)
Output Resistance vs. Input Voltage
10
8
OUTPUT RESISTANCE [Ω]
OUTPUT RESISTANCE [Ω]
-25
8
6
4
2
0
1
2
3
4
5
6
6
VIN = 3V
5
VIN = 2V
4
3
VIN = 5V
2
-50
INPUT VOLTAGE [V]
Doc. No. 5003, Rev. J
7
4
-25
0
25 50 75 100 125
TEMPERATURE [oC]
CAT661
TYPICAL OPERATING CHARACTERISTICS
Inverted Output voltage vs. Load, V+ = 5V
Output Voltage Drop vs. Load Current
1.0
OUTPUT VOLTAGE [V]
INV. OUTPUT VOLTAGE [V]
5.0
4.8
4.6
4.4
4.2
4.0
0.6
0.4
20
40
60
80
LOAD CURRENT [mA]
0.2
100
V+ = 5V
0
40
60
80
100
Oscillator Frequency vs. Supply Voltage
200
40
160
FREQUENCY [kHz]
50
30
FC = Open
20
20
LOAD CURRENT [mA]
Oscillator Frequency vs. Supply Voltage
10
FC = V+
120
80
40
0
0
1
2
3
4
5
SUPPLY VOLTAGE [V]
1
6
Supply Current vs. Oscillator Frequency
2
3
4
5
SUPPLY VOLTAGE [V]
6
Efficiency vs. Load Current
10000
100
NoLoad
No
L d
90
EFFICIENCY [%]
INPUT CURRENT [µA]
V+ = 3V
0.0
0
FREQUENCY [kHz]
0.8
1000
100
10
1
V+ =5V
V+ = 3V
80
70
60
50
40
10
100
1000
OSCILLATOR FREQUENCY [KHz]
0
50
100
LOAD CURRENT [mA]
5
Doc. No. 5003, Rev. J
CAT661
Figure 2. Test Circuit Voltage Doubler
1
V+
2
C1
+
100µF
V+
5V
3
4
BOOST/FC
V+
CAP+
OSC
CAT661
GND
LV
CAP-
OUT
8
10V VOUT
7
External
Oscillator
6
5
C2
100µF
TYPICAL OPERATING CHARACTERISTICS
Typical characteristic curves are generated using the circuit in Figure 2. Doubler test conditions are: V+ 5V, LV = GND,
BOOST/FC = Open and TA = 25˚C unless otherwise indicated.
Supply Current vs. Input Voltage (No Load)
Output Resistance vs. Input Voltage
10
OUTPUT RESISTANCE [Ω]
INPUT CURRENT [µA]
3000
2500
2000
1500
FC = V+
1000
FC = open
500
0
0
1
2
3
4
5
8
6
4
2
0
6
1
2
3
INPUT VOLTAGE [V]
Supply Current vs. Oscillator Frequency
5
6
Output Voltage Drop vs. Load Current
1.0
10000
No Load
OUTPUT VOLTAGE [V]
INPUT CURRENT [µA]
4
INPUT VOLTAGE [V]
1000
100
0.8
0.6
0.4
V+ = 3V
0.2
V+ = 5V
0.0
10
1
10
100
1000
0
OSCILLATOR FREQUENCY [KHz]
Doc. No. 5003, Rev. J
20
40
60
80
LOAD CURRENT [mA]
6
100
CAT661
APPLICATION INFORMATION
Circuit Description and Operating Theory
The 1/FC1 term can be modeled as an equivalent
impedance REQ. A simple equivalent circuit is shown in
figure 4. This circuit does not include the switch resistance
nor does it include output voltage ripple. It does allow
one to understand the switch-capacitor topology and
make prudent engineering tradeoffs.
The CAT661 switches capacitors to invert or double an
input voltage.
Figure 3 shows a simple switch capacitor circuit. In
position 1 capacitor C1 is charged to voltage V1. The
total charge on C1 is Q1 = C1V1. When the switch
moves to position 2, the input capacitor C1 is discharged
to voltage V2. After discharge, the charge on C1 is Q2 =
C1V2.
For example, power conversion efficiency is set by the
output impedance, which consists of REQ and switch
resistance. As switching frequency is decreased, REQ,
the 1/FC1 term, will dominate the output impedance,
causing higher voltage losses and decreased efficiency.
As the frequency is increased quiescent current
increases. At high frequency this current becomes
significant and the power efficiency degrades.
The charge transferred is:
∆Q = Q1 - Q2 = C1 × (V1 - V2)
If the switch is cycled "F" times per second, the current
(charge transfer per unit time) is:
The oscillator is designed to operate where voltage
losses are a minimum. With external 150µF capacitors,
the internal switch resistances and the Equivalent Series
Resistance (ESR) of the external capacitors determine
the effective output impedance.
I = F × ∆Q = F × C1 (V1 - V2)
Rearranging in terms of impedance:
(V1-V2)
I=
=
(1/FC1)
V1-V2
A block diagram of the CAT661 is shown in figure 5.
REQ
Figure 3. Switched-Capacitor Building Block
V1
Figure 4. Switched-Capacitor Equivalent Circuit
REQ
V2
C1
C2
V1
RL
V2
C2
RL
REQ = 1
FC1
7
Doc. No. 5003, Rev. J
CAT661
OSCILLATOR FREQUENCY CONTROL
The switching frequency can be raised, lowered or driven from an external source. Figure 6 shows a functional diagram
of the oscillator circuit.
The CAT661 oscillator has four control modes:
BOOST/FC Pin Connection
OSC Pin Connection
Nominal Oscillator Frequency
Open
Open
25kHz
BOOST/FC= V+
Open
135kHz
Open or BOOST/FC= V+
External Capacitor
—
Open
External Clock
Frequency of external clock
If BOOST/FC and OSC are left floating (Open), the
nominal oscillator frequency is 25kHz. The pump
frequency is one-half the oscillator frequency.
an external capacitor at OSC, the operating frequency
can be set.
Note that the frequency appearing at CAP+ or CAP- is
one-half that of the oscillator.
By connecting the BOOST/FC pin to V+, the charge and
discharge currents are increased, and the frequency is
increased by approximately 6 times. Increasing the
frequency will decrease the output impedance and ripple
currents. This can be an advantage at high load currents.
Increasing the frequency raises quiescent current but
allows smaller capacitance values for C1 and C2.
Driving the CAT661 from an external frequency source
can be easily achieved by driving Pin 7 and leaving the
BOOST pin open, as shown in figure 6. The output
current from Pin 7 is small, typically 1µA to 8µA, so a
CMOS can drive the OSC pin. For 5V applications, a TTL
logic gate can be used if an external 100kΩ pull-up
resistor is used as shown in figure 7.
If pin 7, OSC, is loaded with an external capacitor the
frequency is lowered. By using the BOOST/FC pin and
Figure 5. CAT661 Block Diagram
V+
(8)
SW1
BOOST/FC
Ο
8x
(1)
CAP+
(2)
SW2
+
C1
OSC
2
CAP(4)
Ο
OSC
(7)
VOUT
(5)
C2
+
LV
(6)
CLOSED WHEN
V+ > 3.0V
GND
(3)
(N) = Pin Number
Doc. No. 5003, Rev. J
8
CAT661
CAPACITOR SELECTION
Low ESR capacitors are necessary to minimize voltage
losses, especially at high load currents. The exact
values of C1 and C2 are not critical but low ESR
capacitors are necessary.
Output voltage ripple is determined by the value of C2
and the load current. C2 is charged and discharged at a
current roughly equal to the load current. The internal
switching frequency is one-half the oscillator frequency.
The ESR of capacitor C1, the pump capacitor, can have
a pronounced effect on the output. C1 currents are
approximately twice the output current and losses occur
on both the charge and discharge cycle. The ESR
effects are thus multiplied by four. A 0.5Ω ESR for C1 will
have the same effect as a 2Ω increase in CAT661 output
impedance.
VRIPPLE = IOUT/(FOSC x C2) + IOUT x ESRC2
For example, with a 25kHz oscillator frequency (12.5kHz
switching frequency), a 150µF C2 capacitor with an ESR
of 0.2Ω and a 100mA load peak-to-peak the ripple
voltage is 45mV.
VRIPPLE vs. FOSC
VRIPPLE (mV)
IOUT (mA)
FOSC (kHz)
C2 (µF)
C2 ESR (Ω)
45
100
25
150
0.2
25
100
135
150
0.2
Figure 6. Oscillator
Figure 7. External Clocking
V+
V+
7.0 I
REQUIRED FOR TTL LOGIC
I
BOOST/FC
(1)
NC
1
2
+
C1
3
4
BOOST/FC
CAP+
CAT661
V+
OSC
GND
LV
CAP-
OUT
8
100k
7
OSC INPUT
6
5
-V+
OSC
(7)
+
C2
~18pF
7.0 I
I
LV
(6)
9
Doc. No. 5003, Rev. J
CAT661
CAPACITOR SUPPLIERS
The following manufacturers supply low-ESR capacitors:
Manufacturer
Capacitor Type
Phone
WEB
Email
Comments
AVX/Kyocera
TPS/TPS3
843-448-9411
www.avxcorp.com
[email protected]
Tantalum
Vishay/Sprague 595
402-563-6866
www.vishay.com
—
Aluminum
Sanyo
MV-AX, UGX
619-661-6835
www.sanyo.com
Nichicon
F55
847-843-7500
www.nichicon-us.com
[email protected] Aluminum
—
HC/HD
Tantalum
Aluminum
Capacitor manufacturers continually introduce new series
and offer different package styles. It is recommended
that before a design is finalized capacitor manufacturers
should be surveyed for their latest product offerings.
CONTROLLING LOSS IN CAT661 APPLICATIONS
There are three primary sources of voltage loss:
The effective output impedance of a CAT661 circuit is
approximately:
1. Output resistance
VLOSS = ILOAD x ROUT, where ROUT is the
CAT661 output resistance and ILOAD is the
load current.
2. Charge pump (C1) capacitor ESR:
VLOSSC1 ≈ 4 x ESRC1 x ILOAD, where
ESRC1 is the ESR of capacitor C1.
3. Output or reservoir (C2) capacitor ESR:
VLOSSC2 = ESRC2 x ILOAD, where ESRC2
is the ESR of capacitor C2.
Rcircuit ≈ Rout 661 + (4 x ESRC1) + ESRC2
VOLTAGE INVERSION POSITIVE-TO-NEGATIVE
The CAT661 easily provides a negative supply voltage
from a positive supply in the system. Figure 8 shows a
typical circuit. The LV pin may be left floating for positive
input voltages at or above 3.3V.
Increasing the value of C2 and/or decreasing its ESR will
reduce noise and ripple.
TYPICAL APPLICATIONS
NC
1
2
+
C1
3
4
V+
BOOST/FC
OSC
CAP+
CAT661
GND
LV
CAP-
OUT
8
VIN
7
1.5V to 5.5V
6
5
+
Figure 8: Voltage Inverter
Doc. No. 5003, Rev. J
10
C2
VOUT = -VIN
CAT661
POSITIVE VOLTAGE DOUBLER
The voltage doubler circuit shown in figure 9 gives VOUT = 2 x VIN for input voltages from 2.5V to 5.5V.
1N5817*
1
2
+
3
VIN
4
2.5V to 5.5V
V+
BOOST/FC
OSC
CAP+
CAT661
GND
LV
CAP-
OUT
8
7
VOUT = 2VIN
+
6
5
*SCHOTTKY DIODE IS FOR START-UP ONLY
Figure 9: Voltage Doubler
PRECISION VOLTAGE DIVIDER
A precision voltage divider is shown in figure 10. With load currents under 100nA, the voltage at pin 2 will be within
0.002% of V+/2 .
1
2
+
V+ + 0.002%
2
IL < 100nA
BOOST/FC
V+
OSC
CAP+
CAT661
8
7
3
GND
LV
6
4
CAP-
OUT
5
V+
3V to 11V
+
Figure 10: Precision Voltage Divider (Load ≤ 100nA)
11
Doc. No. 5003, Rev. J
CAT661
BATTERY VOLTAGE SPLITTER
Positive and negative voltages that track each other can be obtained from a battery. Figure 11 shows how a 9V battery
can provide symmetrical positive and negative voltages equal to one-half the battery voltage.
BATTERY
9V
1
VBAT
2
+
3V < VBAT < 11V
V+
BOOST/FC
OSC
CAP+
CAT661
V
+ BAT (4.5V)
2
8
7
3
GND
LV
6
4
CAP-
OUT
5
-
VBAT
(-4.5V)
2
+
Figure 11: Battery Splitter
CASCADE OPERATION FOR HIGHER NEGATIVE VOLTAGES
The CAT661 can be cascaded as shown in figure 12 to generate more negative voltage levels. The output resistance
is approximately the sum of the individual CAT661 output resistance.
VOUT= -N x VIN, where N represents the number of cascaded devices.
+VIN
8
2
C1
+
3
4
8
2
CAT661
"1"
C1N
+
3
5
CAT661
"N"
5
4
+
C2
VOUT = -NVIN
Figure 12: Cascading to Increase Output Voltage
Doc. No. 5003, Rev. J
12
+
C2
CAT661
PARALLEL OPERATION
Paralleling CAT661 devices will lower output resistance. As shown in figure 13, each device requires its own pump
capacitor, C2, but the output reservoir capacitor is shared with all devices. The value of C2 should be increased by
a factor of N, where N is the number of devices.
ROUT (of CAT661)
ROUT =
N (NUMBER OF DEVICES)
+VIN
8
2
C1
+
3
4
8
2
CAT661
"1"
C1N
+
5
3
4
CAT661
"N"
5
+
C2
Figure 13: Reduce Output Resistance by Paralleling Devices
13
Doc. No. 5003, Rev. J
CAT661
PACKAGE MECHANICAL DRAWINGS
8-LEAD 150 WIDE SOIC (S, X)
0.0099 (0.25)
X 45˚
0.0196 (0.50)
0.149 (3.80)
0.1574 (4.00)
0.0075 (0.19)
0.0098 (0.25)
0.2284 (5.80)
0.2440 (6.20)
0˚-8˚
0.016 (0.40)
0.050 (1.27)
D
Dimension D
0.0532 (1.35)
0.0688 (1.75)
0.050 (1.27) BSC
0.0040 (0.10)
0.0098 (0.25)
Pkg
Min
Max
8L
0.1890(4.80)
0.1968(5.00)
0.013 (0.33)
0.020 (0.51)
8-LEAD 300 MIL WIDE PLASTIC DIP (P)
0.300 (7.62)
0.325 (8.26)
0.245 (6.17)
0.295 (7.49)
D
0.310 (7.87)
0.380 (9.65)
0.120 (3.05)
0.150 (3.81) 0.180 (4.57) MAX
Dimension D
0.015 (0.38)
—
0.110 (2.79)
0.150 (3.81)
Pkg
Min
Max
8L
0.355 (9.02)
0.400 (10.16)
0.100 (2.54)
BSC
0.045 (1.14)
0.060 (1.52)
0.014 (0.36)
0.022 (0.56)
Notes:
1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
Doc. No. 5003, Rev. J
14
CAT661
8-PAD TDFN (RD8, ZD8)
8
0.75+0.05
A
5
4.00+0.10
(S)
B
0.0-0.05
1
4
4.00+0.10
(S)
PIN 1
INDEX AREA
0.20 REF.
C
5
DAP SIZE 3.5 X 2.4
8
0.10 MAX TYP.
0.15
0.15
0.20
0.10
2.20+0.10
NOTE:
PIN 1 ID
0.10
0.20
0.50+0.10 (8x)
0.30+0.05 (8x)
0.80 TYP. (6x)
2.40 REF. (2x)
15
1. ALL DIMENSIONS ARE IN mm.
ANGLES IN DEGREES.
2. COPLANARITY APPLIES TO THE
EXPOSED PAD AS WELL AS
THE TERMINALS.
COPLANARITY SHALL NOT
EXCEED 0.08mm.
3. WARPAGE SHALL NOT
EXCEED 0.10mm.
4. PACKAGE LENGTH/PACKAGE
WIDTH ARE CONSIDERED AS
SPECIAL CHARACTERISTIC. (S)
Doc. No. 5003, Rev. J
REVISION HISTORY
Date
Rev.
Reason
10/15/03
G
Updated Description - eliminated Commercial temperature range
10/27/04
H
Minor changes throughout data sheet
1/20/2005
I
Changed ordering information for CAT661EXA to CAT661EVA
04/22/2005
J
Changed ordering information for CAT661EXA-TE13 to CAT661EVA-TE13
Removed Preliminary Information from data sheet header
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Publication #:
Revison:
Issue date:
5003
J
04/22/05