® LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.0 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Rev. 1.7 Rev. 1.8 Rev. 1.9 Rev. 2.0 Description Initial Issue Deleted Icc1 Spec. Revised Truth Table Deleted Data Retention Waveform(2)(UB & LB controlled) Revised the typo in Page 1 Added PKG Type : 48-ball 6mm x 8mm TFBGA Revised Test Condition of ISB1/IDR Added I Grade Spec. Revised VTERM to VT1 and VT2 Added -20ns Spec. Added LL Spec. Revised Test Condition of ISB Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Added packing type in ORDERING INFORMATION Revised PACKAGE OUTLINE DIMENSION in page 11 Revised ORDERING INFORMATION in page 12 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 Issue Date Jul.25.2004 Sep.21.2004 Jun.20.2005 Feb.13.2006 Jun.13.2007 Feb.4.2008 Mar.31.2008 Aug.7.2008 Apr.17.2009 May.6.2010 Aug.25.2010 ® LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.0 FEATURES GENERAL DESCRIPTION Fast access time : 8/10/12/15/20ns Low power consumption: Operating current : 115/105/95/85/70mA (TYP.) Standby current : 0.6mA (TYP.) 100µA( (MAX. for 20ns LL version) Single 3.3V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 2.0V (MIN.) Green package available Package : 44-pin 400 mil TSOP-II 48-ball 6mm x 8mm TFBGA The LY61L6416 is a 1,048,576-bit low power CMOS static random access memory organized as 65,536 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY61L6416 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The LY61L6416 operates from a single power supply of 3.3V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Operating Family Temperature 0 ~ 70℃ LY61L6416 0 ~ 70℃ LY61L6416 0 ~ 70℃ LY61L6416(LL) -20 ~ 80℃ LY61L6416(E) -20 ~ 80℃ LY61L6416(E) LY61L6416(LLE) -20 ~ 80℃ -40 ~ 85℃ LY61L6416(I) -40 ~ 85℃ LY61L6416(I) -40 ~ 85℃ LY61L6416(LLI) Vcc Range Speed 3.15 ~ 3.6V 3.0 ~ 3.6V 3.0 ~ 3.6V 3.15 ~ 3.6V 3.0 ~ 3.6V 3.0 ~ 3.6V 3.15 ~ 3.6V 3.0 ~ 3.6V 3.0 ~ 3.6V 8/10ns 12/15/20ns 20ns 8/10ns 12/15/20ns 20ns 8/10ns 12/15/20ns 20ns Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 0.6mA(TYP.) 115/105mA 0.6mA(TYP.) 95/85/70mA 100µA(MAX.) 70mA 0.6mA(TYP.) 115/105mA 0.6mA(TYP.) 95/85/70mA 100µA(MAX.) 70mA 0.6mA(TYP.) 115/105mA 0.6mA(TYP.) 95/85/70mA 100µA(MAX.) 70mA Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1 ® LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.0 PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM Vcc Vss A0-A15 DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# WE# OE# LB# UB# SYMBOL DESCRIPTION A0 - A15 Address Inputs DQ0 – DQ15 Data Inputs/Outputs DECODER I/O DATA CIRCUIT 64Kx16 MEMORY ARRAY CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground COLUMN I/O CONTROL CIRCUIT Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2 ® LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.0 PIN CONFIGURATION A4 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE# A0 5 40 UB# 6 39 LB# 7 38 DQ15 DQ1 8 37 DQ14 DQ2 9 36 DQ13 DQ3 10 35 DQ12 Vcc 11 34 Vss Vss 12 33 Vcc DQ4 13 32 DQ11 DQ5 14 31 DQ10 DQ6 15 30 DQ7 16 WE# LY61L6416 CE# DQ0 A LB# OE# A0 A1 B DQ8 UB# A3 A4 CE# DQ0 DQ9 C DQ9 DQ10 A5 A6 DQ1 DQ2 29 DQ8 D Vss DQ11 NC A7 DQ3 Vcc 17 28 NC E Vcc DQ12 NC NC DQ4 Vss A15 18 27 A8 A14 19 26 A9 F DQ14 DQ13 A14 A15 DQ5 DQ6 A13 20 25 A10 G DQ15 NC A12 A13 WE# DQ7 A12 21 24 A11 H A10 NC 22 23 NC NC A8 A9 1 2 3 4 TFBGA TSOP II A2 NC A11 NC 5 6 ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to VCC+0.5 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3 ® LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.0 TRUTH TABLE MODE CE# OE# H L L L L L L L L X H H L L L X X X Standby Output Disable Read Write Note: WE# LB# X H H H H H L L L UB# X L X L H L L H L X X L H L L H L L I/O OPERATION DQ0-DQ7 DQ8-DQ15 High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z DOUT High – Z DOUT DOUT DIN High – Z DIN High – Z DIN DIN SUPPLY CURRENT ISB,ISB1 ICC ICC ICC H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Supply Voltage VCC Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage VIH *2 VIL ILI Average Operating Power supply Current Standby Power Supply Current TEST CONDITION -8/-10 -12/-15/-20 *1 ILO VOH VOL ICC VCC ≧ VIN ≧ VSS VCC ≧ VOUT ≧ VSS, Output Disabled IOH = -4mA IOL = 8mA -8 -10 -12 -15 -20 Cycle time = Min. CE# = VIL , II/O = 0mA Other pins at VIH or VIL ISB CE# = VIH, other pins at VIH or VIL ISB1 8/10/12/15/20 CE# ≧VCC - 0.2V Others at 0.2V or VCC - 0.2V 20LL MIN. 3.15 3.0 2.0 - 0.3 -1 TYP. 3.3 3.3 - *4 MAX. UNIT 3.6 V 3.6 V VCC+0.3 V 0.8 V 1 µA -1 - 1 µA 2.4 - 115 105 95 85 70 3 0.6 20 0.4 150 120 100 90 75 10 *5 3 6 100* V V mA mA mA mA mA mA mA µA Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25℃ 5. 1mA for special request 6. 50µA for special request CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - Note : These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 MAX 6 8 UNIT pF pF ® LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.0 AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE SYM. LY61L6416 LY61L6416 LY61L6416 LY61L6416 LY61L6416 UNIT -8 -10 -12 -15 -20 MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. ns Read Cycle Time 8 10 12 15 20 tRC ns Address Access Time 8 10 12 15 20 tAA ns Chip Enable Access Time 8 10 12 15 20 tACE ns Output Enable Access Time 4 5 6 7 8 tOE ns Chip Enable to Output in Low-Z 2 2 3 4 4 tCLZ* ns Output Enable to Output in Low-Z tOLZ* 0 0 0 0 0 ns Chip Disable to Output in High-Z 4 5 6 7 8 tCHZ* ns Output Disable to Output in High-Z tOHZ* 4 5 6 7 8 ns Output Hold from Address Change tOH 3 3 3 3 3 ns LB#, UB# Access Time 4 5 6 7 8 tBA ns LB#, UB# to High-Z Output 4 5 6 7 8 tBHZ* ns LB#, UB# to Low-Z Output 0 0 0 0 0 tBLZ* PARAMETER (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. LY61L6416 LY61L6416 LY61L6416 LY61L6416 LY61L6416 UNIT -8 -10 -12 -15 -20 MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. 8 10 12 15 20 ns tWC 6.5 8 10 12 15 ns tAW 6.5 8 10 12 15 ns tCW 0 0 0 0 0 ns tAS 6.5 8 9 10 12 ns tWP 0 0 0 0 0 ns tWR 5 6 7 8 9 ns tDW 0 0 0 0 0 ns tDH 2 3 4 5 ns tOW* 1.5 5 6 7 8 9 ns tWHZ* 6.5 8 10 12 15 ns tBW *These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 ® LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.0 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE LB#,UB# tBA OE# tOE tOH tOHZ tBHZ tCHZ tOLZ tBLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6 ® LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.0 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW tDH Data Valid Din Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7 ® LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.0 WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) tWC Address tAW tWR CE# tAS tCW tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW tDH Data Valid Din Notes : 1.WE#,CE#, LB#, UB# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 ® LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.0 DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time MIN. 2.0 8/10/12/15/20 - IDR VCC = 2.0V CE# ≧ VCC - 0.2V others at 0.2V or VCC - 0.2V 20LL tCDR See Data Retention Waveforms (below) tR DATA RETENTION WAVEFORM VDR ≧ 2.0V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ≧ Vcc-0.2V VIH Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9 TYP. 0.4 MAX. UNIT 3.6 V 2 mA - 10 50 µA 0 - - ns tRC* - - ns ® LY61L6416 64K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.0 PACKAGE OUTLINE DIMENSION θ 44-pin 400mil TSOP-Ⅱ Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 3 6 0 DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 o o o 0 3 6 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10 ® LY61L6416 Rev. 2.0 64K X 16 BIT HIGH SPEED CMOS SRAM 48-ball 6mm × 8mm TFBGA Package Outline Dimension Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11 ® LY61L6416 Rev. 2.0 64K X 16 BIT HIGH SPEED CMOS SRAM ORDERING INFORMATION Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 12 ® LY61L6416 Rev. 2.0 64K X 16 BIT HIGH SPEED CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 13