LM98714 www.ti.com SNAS254 – OCTOBER 2006 LM98714 Three Channel, 16-Bit, 45 MSPS Digital Copier Analog Front End with Integrated CCD/CIS Sensor Timing Generator and LVDS Output Check for Samples: LM98714 FEATURES DESCRIPTION • • The LM98714 is a fully integrated, high performance 16-Bit, 45 MSPS signal processing solution for digital color copiers, scanners, and other image processing applications. High-speed signal throughput is achieved with an innovative architecture utilizing Correlated Double Sampling (CDS), typically employed with CCD arrays, or Sample and Hold (S/H) inputs (for Contact Image Sensors and CMOS image sensors). The signal paths utilize 8 bit Programmable Gain Amplifiers (PGA), a +/-9-Bit offset correction DAC and independently controlled Digital Black Level correction loops for each input. The PGA and offset DAC are programmed independently allowing unique values of gain and offset for each of the three inputs. The signals are then routed to a 45MHz high performance analog-todigital converter (ADC). The fully differential processing channel shows exceptional noise immunity, having a very low noise floor of -74dB. The 16-bit ADC has excellent dynamic performance making the LM98714 transparent in the image reproduction chain. 1 2 • • • • • LVDS/CMOS Outputs LVDS/CMOS Pixel Rate Input Clock or ADC Input Clock CDS or S/H Processing for CCD or CIS Sensors Independent Gain/Offset Correction for Each Channel Digital Black Level Correction Loop for Each Channel Programmable Input Clamp Voltage Flexible CCD/CIS Sensor Timing Generator APPLICATIONS • • • • Multi-Function Peripherals Facsimile Equipment Flatbed or Handheld Color Scanners High-Speed Document Scanner KEY SPECIFICATIONS • • • • • • • • • • • • • • • Maximum Input Level 1.2 or 2.4 Volt Modes – (Both with + or - Polarity Option) ADC Resolution 16-Bit ADC Sampling Rate 45 MSPS INL +/- 23 LSB (typ) Channel Sampling Rate 15/22.5/30 MSPS PGA Gain Steps 256 Steps PGA Gain Range 0.7 to 7.84x Analog DAC Resolution +/-9 Bits Analog DAC Range +/-300mV or +/-600mV Digital DAC Resolution +/-6 Bits Digital DAC Range -1024 LSB to + 1008 LSB SNR -74dB (@0dB PGA Gain) Power Dissipation 505mW (LVDS) 610mW (CMOS) Operating Temp 0 to 70°C Supply Voltage 3.3V Nominal (3.0V to 3.6V Range) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated LM98714 SNAS254 – OCTOBER 2006 www.ti.com System Block Diagram CCD/CIS Sensor Analog Front End SPI LM98714 Image Processor/ASIC Data Output Sensor Drivers 2 CCD Timing Generator Submit Documentation Feedback Motor Controllers Copyright © 2006, Texas Instruments Incorporated Product Folder Links: LM98714 Copyright © 2006, Texas Instruments Incorporated Product Folder Links: LM98714 OSB OSG OSR VCLP Reference Configuration Input Bias/ Clamping COLOR3DAC[9:0] Input Bias/ Clamping COLOR2DAC[9:0] Input Bias/ Clamping COLOR5DAC[9:0] COLOR4DAC[9:0] COLOR3DAC[9:0] COLOR2DAC[9:0] COLOR1DAC[9:0] VCLP Reference DAC CDS or Sample/Hold Amplifier Black Level Offset DAC CDS or Sample/Hold Amplifier Black Level Offset DAC CDS or Sample/Hold Amplifier 5:1 MUX AGND Black Level Offset DAC VA 4 Reference Generator COLOR3PGA[7:0] COLOR2PGA[7:0] COLOR5PGA[7:0] COLOR4PGA[7:0] COLOR3PGA[7:0] COLOR2PGA[7:0] COLOR1PGA[7:0] PGA PGA PGA 5:1 MUX VD Red Ch Black Level Correction 16 Green Ch Black Level Correction Config Registers CCD Timing Generator Digital Offset 16 Bit ADC DGND DVB 3:1 MUX VR CLKOUT/ CLK10 Data Out Config (CMOS/LVDS) Blue Ch Black Level Correction Serial Interface VC INCLK- INCLK+ DOUT0/ TXOUT0- DOUT1/ TXOUT0+ DOUT2/ TXOUT1- DOUT3/ TXOUT1+ DOUT4/ TXOUT2- DOUT5/ TXOUT2+ DOUT6/ TXCLK- DOUT7/ TXCLK+ SCLK SDIO SEN RESET LM98714 www.ti.com SNAS254 – OCTOBER 2006 LM98714 Overall Chip Block Diagram CLK9 CLK8 CLK7 CLK6 CLK5 CLK4 CLK3 CLK2 CLK1 SH SH_R VREFT VREFB VCLP Figure 1. Chip Block Diagram Submit Documentation Feedback 3 LM98714 SNAS254 – OCTOBER 2006 www.ti.com LM98714 Pin Out Diagram CLK3 1 48 CLK4 CLK2 2 47 VC CLK1 3 46 DGND SH 4 45 CLK5 RESET 5 44 CLK6 SH_R 6 43 CLK7 SDIO 7 42 CLK8 SCLK 8 41 CLK9 SEN 9 40 CLKOUT/CLK10 AGND 10 39 VD VA 11 38 DGND VREFB 12 37 DOUT0/TXOUT0- VREFT 13 36 DOUT1/TXOUT0+ VA 14 35 DOUT2/TXOUT1- AGND 15 34 DOUT3/TXOUT1+ VCLP 16 33 DOUT4/TXOUT2- VA 17 32 DOUT5/TXOUT2+ AGND 18 31 DOUT6/TXCLK- OSR 19 30 DOUT7/TXCLK+ AGND 20 29 INCLK- OSG 21 28 INCLK+ AGND 22 27 DVB OSB 23 26 VR AGND 24 25 DGND 48 Pin TSSOP (not to scale) Figure 2. LM98714 Pin Out Diagram 4 Submit Documentation Feedback Copyright © 2006, Texas Instruments Incorporated Product Folder Links: LM98714 LM98714 www.ti.com SNAS254 – OCTOBER 2006 Typical Application Diagram Serial Interface and Device Control Bus CCD Timing Generator Output Bus CCD Clock Drivers CLK3 CLK4 CLK2 VC CLK1 DGND SH CLK5 RESET CLK6 SH_R CLK7 SDIO CLK8 SCLK VA CLK10/CLKOUT AGND 0.1 PF 0.1 PF 0.1 PF AGND CCD Sensor and Output Signal Buffers VD VD VA 0.1 PF 0.1 PF 0.1 PF DGND CLK9 SEN 0.1 PF VC 0.1 PF DGND DGND VREFB D0/TXOUT0- VREFT D1/TXOUT0+ VA D2/TXOUT1- AGND D3/TXOUT1+ VCLP D4/TXOUT2- VA D5/TXOUT2+ AGND D6/TXCLK- OSR D7/TXCLK+ AGND INCLK- OSG INCLK+ AGND LVDS Deserializer (DS90CR218A or equiv.) * 100: DVB OSB VR VR AGND 0.1 PF DGND DGND DGND AGND 3.3V 3.3V VA + 4.7 PF ASIC and Clock Gen VR VD VC + AGND 4.7 PF * 100: used for LVDS INCLK only. If using CMOS INCLK, 100: is removed and INCLK- connected to DGND. DGND Figure 3. Typical Application Diagram Pin Descriptions Pin Name I/O (1) Typ Res Description 1 CLK3 O D PU Configurable sensor control output. 2 CLK2 O D PD Configurable sensor control output. 3 CLK1 O D PU Configurable sensor control output. 4 SH O D PD Sensor - Shift or transfer control signal for CCD and CIS sensors. 5 RESET I D PU Active-low master reset. NC when function not being used. 6 SH_R I D PD External request for an SH pulse. 7 SDIO I/O D 8 SCLK I D PD Serial Interface shift register clock. 9 SEN I D PU Active-low chip enable for the Serial Interface. 10 AGND P Analog ground return. 11 VA P Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND. 12 VREFB O A Bottom of ADC reference. Bypass with a 0.1μF capacitor to ground. 13 VREFT O A Top of ADC reference. Bypass with a 0.1μF capacitor to ground. 14 VA P Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND. 15 AGND P Analog ground return. 16 VCLP A Input Clamp Voltage. Normally bypassed with a 0.1μF, and a 4.7μF capacitor to AGND. An external reference voltage may be applied to this pin. (1) IO Serial Interface Data Input (I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal resistor), (PD=Pull Down with an internal resistor.). Submit Documentation Feedback Copyright © 2006, Texas Instruments Incorporated Product Folder Links: LM98714 5 LM98714 SNAS254 – OCTOBER 2006 www.ti.com Pin Descriptions (continued) Pin Name 17 VA 18 AGND 19 OSR 20 AGND 21 OSG 22 AGND 23 OSB 24 25 I/O (1) Typ Res Description P Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND. P Analog ground return. A Analog input signal. Typically sensor Red output AC-coupled thru a capacitor. P Analog ground return. A Analog input signal. Typically sensor Green output AC-coupled thru a capacitor. P Analog ground return. A Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor. AGND P Analog ground return. DGND P Digital ground return. 26 VR P Power supply input for internal voltage reference generator. Bypass this supply pin with a 0.1μF capacitor. 27 DVB O P Digital Core Voltage bypass. Not an input. Bypass with 0.1μF capacitor to DGND. 28 INCLK+ I D Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock is selected when pin 29 is held at DGND, otherwise clock is configured for LVDS operation. 29 INCLK- I D Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock. 30 DOUT7/ O D Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS Mode. O D Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS Mode. O D Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS Mode. O D Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS Mode. O D Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS Mode. O D Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS Mode. O D Bit 1 of the digital video output bus in CMOS Mode, LVDS Data Out0+ in LVDS Mode. O D Bit 0 of the digital video output bus in CMOS Mode, LVDS Data Out0- in LVDS Mode. I I I TXCLK+ 31 DOUT6/ TXCLK- 32 DOUT5/ TXOUT2+ 33 DOUT4/ TXOUT2- 34 DOUT3/ TXOUT1+ 35 DOUT2/ TXOUT1- 36 DOUT1/ TXOUT0+ 37 DOUT0/ TXOUT0- 38 DGND P Digital ground return. 39 VD P Power supply for the digital circuits. Bypass this supply pin with 0.1μF capacitor. A single 4.7μF capacitor should be used between the supply and the VD, VR and VC pins. 40 CLKOUT/ CLK10 O D PD Output clock for registering output data when using CMOS outputs, or configurable sensor control output. 41 CLK9 O D PD Configurable sensor control output. 42 CLK8 O D PD Configurable sensor control output. 43 CLK7 O D PD Configurable sensor control output. 44 CLK6 O D PU Configurable sensor control output. 45 CLK5 O D PD Configurable sensor control output. 46 DGND P 47 VC P 48 CLK4 O D Digital ground return. Power supply for the sensor control outputs. Bypass this supply pin with 0.1μF capacitor. PD Configurable sensor control output. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6 Submit Documentation Feedback Copyright © 2006, Texas Instruments Incorporated Product Folder Links: LM98714 LM98714 www.ti.com SNAS254 – OCTOBER 2006 Absolute Maximum Ratings (1) (2) (3) Supply Voltage (VA,VR,VD,VC) 4.2V Voltage on Any Input Pin (Not to exceed 4.2V) −0.3V to (VA + 0.3V) Voltage on Any Output Pin (except DVB and not to exceed 4.2V) −0.3V to (VA + 0.3V) DVB Output Pin Voltage 2.0V Input Current at any pin other than Supply Pins Package Input Current (except Supply Pins) (4) ±25 mA (4) ±50 mA Maximum Junction Temperature (TA) 150°C Thermal Resistance (θJA) 66°C/W Package Dissipation at TA = 25°C ESD Rating (6) (5) 1.89W Human Body Model 2500V Machine Model 250V −65°C to +150°C Storage Temperature Soldering process must comply with TI’s Reflow Temperature Profile specifications. Refer to www.ti.com/packaging. (1) (2) (3) (4) (5) (6) (7) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the Operating Ratings is not recommended. All voltages are measured with respect to AGND = DGND = 0V, unless otherwise specified. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25 mA to two. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX – TA)/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided. Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. Reflow temperature profiles are different for lead-free and non-lead-free packages. Operating Ratings (1) (2) 0°C ≤ TA ≤ +70°C Operating Temperature Range All Supply Voltage (1) (2) (7) +3.0V to +3.6V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the Operating Ratings is not recommended. All voltages are measured with respect to AGND = DGND = 0V, unless otherwise specified. Submit Documentation Feedback Copyright © 2006, Texas Instruments Incorporated Product Folder Links: LM98714 7 LM98714 SNAS254 – OCTOBER 2006 www.ti.com Electrical Characteristics The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C. (1) Symbol Parameter Conditions Min Typ (2) Max Units CMOS Digital Input DC Specifications (RESETb, SH_R, SCLK, SENb) VIH Logical “1” Input Voltage VIL Logical “0” Input Voltage IIH Logical “1” Input Current 2.0 V 0.8 RESET IIL V VIH = VD Logical “0” Input Current 235 nA SH_R, SCLK 70 μA SEN 130 nA μA VIL = DGND RESET 70 SH_R, SCLK 235 nA SEN 70 μA CMOS Digital Output DC Specifications (SH, CLK1 to CLK10, CMOS Data Outputs) VOH Logical “1” Output Voltage IOUT = -0.5mA VOL Logical “0” Output Voltage IOUT = 1.6mA 2.95 V IOS Output Short Circuit Current VOUT = DGND 16 VOUT= VD -20 IOZ CMOS Output TRI-STATE Current VOUT = DGND 20 VOUT = VD -25 0.25 V mA nA CMOS Digital Input/Output DC Specifications (SDIO) IIH Logical “1” Input Current VIH = VD 90 nA IIL Logical “0” Input Current VIL = DGND 90 nA LVDS/CMOS Clock Receiver DC Specifications (INCLK+ and INCLK- Pins) VIHL Differential LVDS Clock High Threshold Voltage RL = 100W VCM (LVDS Input Common Mode Voltage)= 1.25V VILL Differential LVDS Clock Low Threshold Voltage VIHC CMOS Clock High Threshold Voltage VILC CMOS Clock Low Threshold Voltage 0.8 V IIHL CMOS Clock Input High Current 280 μA IILC CMOS Clock Input Low Current -150 μA INCLK- = DGND 100 mV -100 mV 2.0 V LVDS Output DC Specifications (1) VOD Differential Output Voltage VOS LVDS Output Offset Voltage RL = 100Ω 180 328 450 mV 1.17 1.23 1.3 V The analog inputs are protected as shown below. Input voltage magnitudes beyond the supply rails will not damage the device, provided the current is limited per Absolute Maximum Ratings, Note 4. However, input errors will be generated If the input goes above VA and below AGND. VA I/O To Internal Circuitry AGND (2) 8 Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. Submit Documentation Feedback Copyright © 2006, Texas Instruments Incorporated Product Folder Links: LM98714 LM98714 www.ti.com SNAS254 – OCTOBER 2006 Electrical Characteristics (continued) The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.(1) Symbol Parameter Conditions IOS Output Short Circuit Current VOUT = 0V, RL = 100Ω Min Typ (2) Max Units 7.9 mA Power Supply Specifications IA IR VA Analog Supply Current VR Digital Supply Current VA Normal State VA Low Power State (Powerdown) 60 97 125 mA 12 23 32 mA VR Normal State (LVDS Outputs) 30 64 75 mA CMOS Output Data Format 15 47 55 mA LVDS Output Data Format with Data Outputs Disabled ID VD Digital Output Driver Supply Current IC VC CCD Timing Generator Output Driver Supply Current PWR Average Power Dissipation 47 LVDS Output Data Format mA 0.05 mA CMOS Output Data Format (ATE Loading of CMOS Outputs > 50pF) 12 40 mA Typical sensor outputs: SH, CLK1=Φ1A, CLK2=Φ2A, CLK3=ΦB, CLK4=ΦC, CLK5=RS, CLK6=CP (ATE Loading of CMOS Outputs > 50pF) 0.5 12 mA LVDS Output Data Format 350 505 650 mW CMOS Output Data Format (ATE Loading of CMOS Outputs > 50pF) 380 610 700 mW Input Sampling Circuit Specifications VIN IIN_SH Input Voltage Level Sample and Hold Mode Input Leakage Current CDS Gain=1x, PGA Gain=1x 2.3 CDS Gain=2x, PGA Gain= 1x 1.22 Vp-p Source Followers Off 50 70 CDS Gain = 1x (-70) (-40) μA OSX = VA (OSX = AGND) Source Followers Off 75 105 CDS Gain = 2x (-105) (-75) μA OSX = VA (OSX = AGND) Source Followers On -200 CDS Gain = 2x -10 200 nA -16 OSX = VA (OSX = AGND) CSH Sample/Hold Mode Equivalent Input Capacitance CDS Gain = 1x IIN_CDS CDS Mode Input Leakage Current Source Followers Off OSX = VA (OSX = AGND) RCLPIN CLPIN Switch Resistance 2.5 CDS Gain = 2x pF 4 -300 pF 7 (-25) 300 nA 16 50 Ω VCLP Reference Circuit Specifications VVCLP VCLP DAC Resolution 4 Bits VCLP DAC Step Size 0.16 V VCLP DAC Voltage Min Output VCLP Config. Register = 0001 0000b 0.14 0.26 0.43 V VCLP DAC Voltage Max Output VCLP Config. Register = 0001 1111b 2.38 2.68 2.93 V Resistor Ladder Enabled VCLP Config. Register = 0010 xxxxb 1.54 VA / 2 1.73 V Submit Documentation Feedback Copyright © 2006, Texas Instruments Incorporated Product Folder Links: LM98714 9 LM98714 SNAS254 – OCTOBER 2006 www.ti.com Electrical Characteristics (continued) The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.(1) Symbol Parameter Conditions Min ISC VCLP DAC Short Circuit Output Current VCLP Config. Register = 0001 xxxxb Typ (2) Max Units 30 mA 10 Bits Black Level Offset DAC Specifications Resolution Monotonicity Offset Adjustment Range Referred to AFE Input Specified by characterization CDS Gain = 1x Minimum DAC Code = 0x000 -614 Maximum DAC Code = 0x3FF 614 mV CDS Gain = 2x Offset Adjustment Range Referred to AFE Output DAC LSB Step Size Minimum DAC Code = 0x000 -307 Maximum DAC Code = 0x3FF 307 mV Minimum DAC Code = 0x000 -16000 -18200 Maximum DAC Code = 0x3FF 16000 18200 LSB CDS Gain = 1x 1.2 mV Referred to AFE Output (32) (LSB) DNL Differential Non-Linearity -0.95 3.25 LSB INL Integral Non-Linearity -3.1 2.65 LSB PGA Specifications Gain Resolution 8 Monotonicity Maximum Gain Minimum Gain CDS Gain = 1x 7.18 7.9 8.77 CDS Gain = 1x 17.1 17.9 18.9 dB CDS Gain = 1x 0.56 0.7 0.82 V/V -5 -3 -1.72 dB CDS Gain = 1x PGA Function Bits Specified by characterization V/V Gain (V/V) = (196/(280-PGA Code)) Gain (dB) = 20LOG10(196/(280-PGA Code)) Channel Matching Minimum PGA Gain 3 Maximum PGA Gain 12.7 % ADC Specifications VREFT Top of Reference 2.07 V VREFB Bottom of Reference 0.89 V VREFT VREFB Differential Reference Voltage 1.07 1.18 Overrange Output Code 65535 Underrange Output Code 0 1.29 V Digital Offset “DAC” Specifications 7 Bits Digital Offset DAC LSB Step Size Resolution Referred to AFE Output 16 LSB Offset Adjustment Range Referred to AFE Output Min DAC Code =7b0000000 -1024 Mid DAC Code =7b1000000 0 Max DAC Code = 7b1111111 1008 LSB Full Channel Performance Specifications 10 DNL Differential Non-Linearity -0.99 0.8/-0.6 2.55 LSB INL Integral Non-Linearity -73 +/-23 78 LSB Submit Documentation Feedback Copyright © 2006, Texas Instruments Incorporated Product Folder Links: LM98714 LM98714 www.ti.com SNAS254 – OCTOBER 2006 Electrical Characteristics (continued) The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.(1) Min Typ (2) Symbol Parameter Conditions SNR Total Output Noise Minimum PGA Gain -79 dB 7.2 LSB RMS PGA Gain = 1x -74 13 Maximum PGA Gain Channel to Channel Crosstalk Max Units dB 30 LSB RMS -56 dB 104 LSB RMS Mode 3 47 Mode 2 16 LSB Submit Documentation Feedback Copyright © 2006, Texas Instruments Incorporated Product Folder Links: LM98714 11 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM98714BCMT/NOPB ACTIVE TSSOP DGG 48 38 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 LM98714 BCMT LM98714BCMTX/NOPB ACTIVE TSSOP DGG 48 1000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 LM98714 BCMT LM98714CCMT/NOPB ACTIVE TSSOP DGG 48 38 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 LM98714 CCMT LM98714CCMTX NRND TSSOP DGG 48 1000 TBD Call TI Call TI 0 to 70 LM98714 CCMT LM98714CCMTX/NOPB ACTIVE TSSOP DGG 48 1000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 LM98714 CCMT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM98714BCMTX/NOPB TSSOP DGG 48 1000 330.0 24.4 8.6 13.2 1.6 12.0 24.0 Q1 LM98714CCMTX TSSOP DGG 48 1000 330.0 24.4 8.6 13.2 1.6 12.0 24.0 Q1 LM98714CCMTX/NOPB TSSOP DGG 48 1000 330.0 24.4 8.6 13.2 1.6 12.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM98714BCMTX/NOPB TSSOP DGG 48 1000 367.0 367.0 45.0 LM98714CCMTX TSSOP DGG 48 1000 367.0 367.0 45.0 LM98714CCMTX/NOPB TSSOP DGG 48 1000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. 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