16-Bit, 6 MSPS, PulSAR Differential ADC AD7625 Data Sheet FUNCTIONAL BLOCK DIAGRAM Throughput: 6 MSPS SNR: 93 dB INL: ±0.45 LSB typical, ±1 LSB maximum DNL: ±0.3 LSB typical, ±0.5 LSB maximum Power dissipation: 135 mW 32-lead LFCSP (5 mm × 5 mm) SAR architecture No latency/no pipeline delay 16-bit resolution with no missing codes Zero error: ±1.5 LSB Differential input voltage: ±4.096 V Serial LVDS interface Self-clocked mode Echoed-clock mode Can use LVDS or CMOS for conversion control (CNV signal) Reference options Internal: 4.096 V External (1.2 V) buffered to 4.096 V External: 4.096 V APPLICATIONS High dynamic range telecommunications Receivers Digital imaging systems High speed data acquisition Spectrum analysis Test equipment REFIN REF VCM 1.2V BAND GAP IN+ VIO CLOCK ÷2 LOGIC CAP DAC IN– AD7625 CNV+, CNV– SAR SERIAL LVDS D+, D– DCO+, DCO– CLK+, CLK– 07652-001 FEATURES Figure 1. GENERAL DESCRIPTION The AD7625 is a 16-bit, 6 MSPS, charge redistribution successive approximation register (SAR) based architecture analog-to-digital converter (ADC). SAR architecture allows unmatched performance both in noise (93 dB SNR) and in linearity (1 LSB). The AD7625 contains a high speed, 16-bit sampling ADC, an internal conversion clock, and an internal buffered reference. On the CNV± rising edge, it samples the voltage difference between the IN+ and IN− pins. The voltages on these pins swing in opposite phase between 0 V and REF. The 4.096 V reference voltage, REF, can be generated internally or applied externally. All converted results are available on a single LVDS self-clocked or echoed-clock serial interface, reducing external hardware connections. The AD7625 is housed in a 32-lead, 5 mm × 5 mm LFCSP with operation specified from −40°C to +85°C. Table 1. Fast PulSAR® ADC Selection Input Type Differential (Ground Sense) Resolution (Bits) 16 True Bipolar Differential (Antiphase) 16 16 18 Rev. B 1 MSPS to <2 MSPS AD7653 AD7667 AD7980 AD7983 AD7671 AD7677 AD7623 AD7643 AD7982 AD7984 2 MSPS to 3 MSPS AD7985 AD7621 AD7622 AD7641 AD7986 5 MSPS 6 MSPS 10 MSPS AD7625 AD7626 AD7961 AD7960 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2015 Analog Devices, Inc. All rights reserved. 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AD7625 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Information.................................................................... 13 Applications ....................................................................................... 1 Converter Information .............................................................. 13 Functional Block Diagram .............................................................. 1 Transfer Functions ..................................................................... 14 General Description ......................................................................... 1 Analog Inputs ............................................................................. 14 Revision History ............................................................................... 2 Typical Connection Diagram ................................................... 15 Specifications..................................................................................... 3 Driving the AD7625 ................................................................... 16 Timing Specifications .................................................................. 5 Voltage Reference Options ........................................................ 17 Absolute Maximum Ratings............................................................ 6 Power Supply............................................................................... 18 Thermal Resistance ...................................................................... 6 Digital Interface .......................................................................... 19 ESD Caution .................................................................................. 6 Applications Information .............................................................. 21 Pin Configuration and Function Descriptions ............................. 7 Layout, Decoupling, and Grounding ....................................... 21 Typical Performance Characteristics ............................................. 9 Outline Dimensions ....................................................................... 22 Terminology .................................................................................... 12 Ordering Guide .......................................................................... 22 Theory of Operation ...................................................................... 13 REVISION HISTORY 10/15—Rev. A to Rev. B Changes to Table 1 ............................................................................ 1 Added Aperture Delay Parameter and Current Drain Parameter, Table 2 ................................................................................................ 3 Changes to CLK± Period Parameter and Endnote 2, Table 3 ... 5 Changes to Figure 32 Caption and Ordering Guide .................. 22 7/12—Rev. 0 to Rev. A Change to Table 5 ..............................................................................6 Changes to Figure 2 ...........................................................................7 Updated Outline Dimensions (Changed CP-32-2 to CP-32-7) .... 22 Changes to Ordering Guide .......................................................... 22 1/09—Revision 0: Initial Version Rev. B | Page 2 of 24 Data Sheet AD7625 SPECIFICATIONS VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.5 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Common-Mode Input Range Common-Mode Rejection Ratio Input Current THROUGHPUT Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes Differential Linearity Error Transition Noise Zero Error Zero Error Drift Gain Error Gain Error Drift Power Supply Sensitivity1 AC ACCURACY External Reference Dynamic Range Signal-to-Noise Ratio Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) Internal Reference Dynamic Range Signal-to-Noise Ratio Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) −3 dB Input Bandwidth Aperture Delay Aperture Jitter INTERNAL REFERENCE Output Voltage Temperature Drift REFERENCE BUFFER REFIN Input Voltage Range REF Output Voltage Range Line Regulation EXTERNAL REFERENCE Voltage Range Current Drain Test Conditions/Comments Min 16 VIN+ − VIN− VIN+, VIN− to GND −VREF −0.1 VREF/2 − 0.05 fIN = 1 MHz Midscale input Typ Max Unit Bits +VREF VREF + 0.1 VREF/2 + 0.05 V V V dB μA 166 6 ns MSPS ±0.45 +1 ±0.3 0.6 ±1.5 0.5 8 0.4 0.4 0.2 +0.5 LSB Bits LSB LSB LSB ppm/°C LSB ppm/°C LSB LSB VREF/2 60 77 0.1 −1 16 −0.5 TMIN to TMAX −4 TMIN to TMAX VDD1 = 5 V ± 5% VDD2 = 2.5 V ± 5% +4 20 fIN = 20 kHz 92.5 92 91.5 93.2 93 106 −105.5 92 dB dB dB dB dB 93.2 92.9 106 −105.5 92.5 100 1.5 0.25 dB dB dB dB dB MHz ns ps rms 1.2 ±15 V ppm/°C fIN = 20 kHz 92.5 91.5 91 REFIN @ 25°C −40°C to +85°C VDD1 ± 5%, VDD2 ± 5% 1.2 4.096 5 REF 6 MSPS 4.096 590 4.076 Rev. B | Page 3 of 24 4.116 V V mV V μA AD7625 Parameter VCM PIN Output Voltage Output Impedance LVDS I/O (ANSI-644) Data Format Differential Output Voltage, VOD Common-Mode Output Voltage, VOCM2 Differential Input Voltage, VID Common-Mode Input Voltage, VICM POWER SUPPLIES Specified Performance VDD1 VDD2 VIO Operating Currents Static—Not Converting VDD1 VDD2 VIO With Internal Reference VDD1 VDD2 VIO Without Internal Reference VDD1 VDD2 VIO Power Dissipation3 Static—Not Converting With Internal Reference Without Internal Reference Energy per Conversion TEMPERATURE RANGE Specified Performance Data Sheet Test Conditions/Comments @ 25°C RL = 100 Ω RL = 100 Ω Min Typ Max Unit 4 REF/2 5 6 V kΩ 200 850 100 800 4.75 2.37 2.37 Self-clocked mode and echoedclock mode 6 MSPS throughput Self-clocked mode and echoedclock mode 6 MSPS throughput Self-clocked mode and echoedclock mode 6 MSPS throughput 6 MSPS throughput 6 MSPS throughput TMIN to TMAX −40 1 Serial LVDS twos complement 350 454 1250 1375 650 1575 mV mV mV mV 5 2.5 2.5 5.25 2.63 2.63 V V V 4.5 17 11 7.8 22.7 13 mA mA mA 11 21.5 13.5 15.4 28.3 16 mA mA mA 9 21 13.5 12.1 26 16 mA mA mA 95 145 135 22 130 190 165 mW mW mW nJ/sample +85 °C Using an external reference. The ANSI-644 LVDS specification has a minimum output common mode (VOCM) of 1125 mV. 3 Power dissipation is for the AD7625 device only. In self-clocked interface mode, 9 mW is dissipated in the 100 Ω terminator. In echoed-clock interface mode, 18 mW is dissipated in two 100 Ω terminators. 2 Rev. B | Page 4 of 24 Data Sheet AD7625 TIMING SPECIFICATIONS VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.37 V to 2.63 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Time Between Conversions1 Acquisition Time CNV± High Time CNV± to D± (MSB) Delay CNV± to Last CLK± (LSB) Delay CLK± Period2 CLK± Frequency CLK± to DCO± Delay (Echoed-Clock Mode) DCO± to D± Delay (Echoed-Clock Mode) CLK± to D± Delay 1 2 Symbol tCYC tACQ tCNVH tMSB tCLKL tCLK fCLK tDCO tD tCLKD Min 166 40 10 Typ (tCYC − tMSB + tCLKL)/n 4 250 4 0 4 0 0 Max 10,000 40 145 110 3.33 300 7 1 7 Unit ns ns ns ns ns ns MHz ns ns ns The maximum time between conversions is 10,000 ns. If CNV± is left idle for a time greater than the maximum value of tCYC, the subsequent conversion result is invalid. For the minimum CLK period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) that are read. In echoed-clock interface mode, n = 16; in self-clocked interface mode, n = 18. Rev. B | Page 5 of 24 AD7625 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Analog Inputs/Outputs IN+, IN− to GND1 2 REF to GND VCM, CAP2 to GND CAP1, REFIN to GND Supply Voltage VDD1 VDD2, VIO Digital Inputs to GND Digital Outputs to GND Input Current to Any Pin Except Supplies3 Operating Temperature Range (Commercial) Storage Temperature Range Junction Temperature ESD θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating −0.3 V to REF + 0.3 V or ±130 mA −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +2.7 V −0.3 V to +6 V −0.3 V to +3 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V ±10 mA −40°C to +85°C Table 5. Thermal Resistance Package Type 32-Lead LFCSP_WQ ESD CAUTION −65°C to +150°C 150°C 1 kV 1 See the Analog Inputs section. Keep CNV+/CNV− low for any external REF voltage > 4.3 V applied to the REF pin. 3 Transient currents of up to 100 mA do not cause SCR latch-up. 2 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 6 of 24 θJA 40 θJC 4 Unit °C/W Data Sheet AD7625 32 31 30 29 28 27 26 25 REF GND REF REF CAP2 GND CAP2 CAP2 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 AD7625 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 GND IN+ IN– VCM VDD1 VDD1 VDD2 CLK+ NOTES 1. CONNECT THE EXPOSED PAD TO THE GROUND PLANE OF THE PCB USING MULTIPLE VIAS. 07652-002 CNV+ D– D+ VIO GND DCO– DCO+ CLK– 9 10 11 12 13 14 15 16 VDD1 VDD2 CAP1 REFIN EN0 EN1 VDD2 CNV– Figure 2. Table 6. Pin Function Descriptions Pin No. 1 2 Mnemonic VDD1 VDD2 Type1 P P 3 4 CAP1 REFIN AO AI/O 5, 6 EN0, EN1 DI 7 8, 9 VDD2 CNV−, CNV+ P DI 10, 11 12 13 14, 15 D−, D+ VIO GND DCO−, DCO+ DO P P DO 16, 17 18 19, 20 CLK−, CLK+ VDD2 VDD1 DI P P 21 VCM AO 22 23 24 IN− IN+ GND AI AI P Description Analog 5 V Supply. Decouple the 5 V supply with a 100 nF capacitor. Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor. The 2.5 V supply source should supply this pin first and then be traced to the other VDD2 pins (Pin 7 and Pin 18). Connect this pin to a 10 nF capacitor. Prebuffer Reference Voltage. When using the internal reference, this pin outputs the band gap voltage and is nominally at 1.2 V. It can be overdriven with an external reference voltage such as the ADR280. In either internal or external reference mode, a 10 μF capacitor is required. If using an external 4.096 V reference (connected to REF), this pin is a no connect and does not require any capacitor. Enable Pins. The logic levels of these pins set the operation of the device as follows: EN1 = 0, EN0 = 0: Illegal state. EN1 = 0, EN0 = 1: Enable internal buffer, disable internal reference. An external 1.2 V reference connected to the REFIN pin is required. EN1 = 1, EN0 = 0: Disable internal reference and reference buffer. An external 4.096 V reference connected to the REF pin is required. EN1 = 1, EN0 = 1: Enable internal reference and reference buffer. Digital 2.5 V Supply. Decouple this pin with a 100 nF capacitor. Convert Input. These pins act as the conversion control pin. On the rising edge of these pins, the analog inputs are sampled and a conversion cycle is initiated. CNV+ works as a CMOS input when CNV− is grounded; otherwise, CNV+ and CNV− are differential LVDS inputs. LVDS Data Outputs. The conversion data is output serially on these pins. Input/Output Interface Supply. Use a 2.5 V supply and decouple this pin with a 100 nF capacitor. Ground. Return path for the 100 nF capacitor connected to Pin 12. LVDS Buffered Clock Outputs. When DCO+ is grounded, the self-clocked interface mode is selected. In this mode, the 16-bit results on D± are preceded by a 2-bit header (10) to allow synchronization of the data by the digital host with simple logic. When DCO+ is not grounded, the echoed-clock interface mode is selected. In this mode, DCO± is a copy of CLK±. The data bits are output on the falling edge of DCO+ and can be latched in the digital host on the next rising edge of DCO+. LVDS Clock Inputs. This clock shifts out the conversion results on the falling edge of CLK+. Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor. Analog 5 V Supply. Isolate these pins from Pin 1 with a ferrite bead and decouple them with a 100 nF capacitor. Common-Mode Output. When using any reference scheme, this pin produces one-half the voltage present on the REF pin, which can be useful for driving the common mode of the input amplifiers. Differential Negative Analog Input. Referenced to and must be driven 180° out of phase with IN+. Differential Positive Analog Input. Referenced to and must be driven 180° out of phase with IN−. Ground. Rev. B | Page 7 of 24 AD7625 Data Sheet Pin No. 25, 26, 28 Mnemonic CAP2 Type1 AO 27 29, 30, 32 GND REF P AI/O 31 EP GND Exposed Pad P 1 Description Connect all three CAP2 pins together and decouple them with the shortest trace possible to a single 10 μF, low ESR, low ESL capacitor. The other side of the capacitor must be placed close to Pin 27 (GND). Ground. Return path for the 10 μF capacitor connected to Pin 25, Pin 26, and Pin 28. Buffered Reference Voltage. When using the internal reference or the 1.2 V external reference (REFIN input), the 4.096 V system reference is produced at this pin. When using an external reference, such as the ADR434 or the ADR444, the internal reference buffer must be disabled. In either case, connect all three REF pins together and decouple them with the shortest trace possible to a single 10 μF, low ESR, low ESL capacitor. The other side of the capacitor must be placed close to Pin 31 (GND). Ground. Return path for the 10 μF capacitor connected to Pin 29, Pin 30, and Pin 32. The exposed pad is located on the underside of the package. Connect the exposed pad to the ground plane of the PCB using multiple vias. See the Exposed Pad section for more information. AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DO = digital output; P = power. Rev. B | Page 8 of 24 Data Sheet AD7625 0 –20 –20 –40 –40 –60 –60 –80 –100 –120 –100 –120 –140 –160 –160 1.0 1.5 2.0 2.5 3.0 Figure 3. FFT 2 kHz Input Tone, Full View 0 –180 –40 AMPLITUDE (dB) –180 07652-007 3.0 FREQUENCY (MHz) INPUT TONE = 100kHz SNR = 92.91dB SINAD = 92.55dB THD = –103.11dB SFDR = –103.41dB 0 0.8 0.3 0.6 0.2 0.4 0.1 0.2 INL (LSB) 0.4 0 –0.1 –0.3 –0.6 –0.4 –0.8 CODE 2.0 2.5 3.0 0 –0.4 49,152 1.5 –0.2 –0.2 65,536 07652-015 DNL (LSB) 1.0 32,768 1.0 Figure 7. FFT 100 kHz Input Tone 0.5 16,384 0.5 FREQUENCY (MHz) Figure 4. FFT 50 kHz Input Tone 0 45 –120 –160 –0.5 40 –100 –160 2.5 35 –80 –140 2.0 30 –60 –140 1.5 25 –40 –120 1.0 20 –20 –100 0.5 15 0 –80 0 10 Figure 6. FFT 2 kHz Input Tone, Zoom In on Input Tone and Harmonics –60 –180 5 FREQUENCY (kHz) INPUT TONE = 50kHz SNR = 93.04dB SINAD = 92.63dB THD = –103.57dB SFDR = –102.69dB –20 0 07652-008 0.5 Figure 5. Differential Nonlinearity vs. Code –1.0 0 16,384 32,768 49,152 CODE Figure 8. Integral Nonlinearity vs. Code Rev. B | Page 9 of 24 65,536 07652-014 0 FREQUENCY (MHz) AMPLITUDE (dB) –80 –140 –180 INPUT TONE = 2kHz SNR = 93.16dB SINAD = 92.09dB THD = –110.45dB SFDR = 111.37dB 07652-006 AMPLITUDE (dB) 0 07652-005 AMPLITUDE (dB) TYPICAL PERFORMANCE CHARACTERISTICS AD7625 Data Sheet –100.5 –94 –96 –0.5dBFS –98 –101.0 –100 –101.5 THD (dB) THD (dB) INTERNAL REF –3dBFS –1dBFS –102 –104 –106 –10dBFS –108 –102.0 –102.5 EXTERNAL REF –110 –5dBFS –112 –103.0 0 20 40 60 80 100 120 INPUT FREQUENCY (kHz) –103.5 –60 07652-012 –116 0 20 40 60 80 100 120 Figure 12. THD vs. Temperature (−0.5 dB, 20 kHz Input Tone) 93.8 93.2 93.6 93.0 DYNR vs. TEMP INTERNAL REF DYNR vs. TEMP EXTERNAL REF 93.4 92.8 SINAD vs. TEMP EXTERNAL REF SINAD (dB) 93.2 93.0 92.8 SNR vs. TEMP EXTERNAL REF SNR vs. TEMP INTERNAL REF 92.6 92.6 92.4 92.2 SINAD vs. TEMP INTERNAL REF 92.0 92.4 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 91.6 –60 07652-018 –40 –40 0 20 40 60 80 100 120 80 100 120 TEMPERATURE (°C) Figure 10. Dynamic Range and SNR vs. Temperature (−0.5 dB, 20 kHz Input Tone) Figure 13. SINAD vs. Temperature (−0.5 dB, 20 kHz Input Tone) 120 12 80 IN+ 60 40 20 IN– 0 –20 –4 –2 0 2 DIFFERENTIAL INPUT VOLTAGE (V) 4 6 07652-010 –40 Figure 11. Input Current (IN+, IN−) vs. Differential Input Voltage (6 MSPS) Rev. B | Page 10 of 24 10 8 GAIN ERROR 6 4 2 ZERO ERROR 0 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) Figure 14. Zero Error and Gain Error vs. Temperature 07652-020 ZERO ERROR AND GAIN ERROR (LSB) 100 –60 –6 –20 07652-019 91.8 92.2 –60 INPUT CURRENT (µA) –20 TEMPERATURE (°C) Figure 9. THD at Input Amplitudes of −0.5 dBFS to −10 dBFS vs. Frequency SNR, DYNAMIC RANGE (dB) –40 07652-021 –114 Data Sheet 250,000 AD7625 140,000 262,144 SAMPLES STD DEVIATION = 0.4829 128,084 201,320 200,000 129,601 262,144 SAMPLES STD DEVIATION = 0.5329 120,000 100,000 COUNT COUNT 150,000 100,000 80,000 60,000 40,000 50,000 0 54 FEC7 FEC8 FEC9 FECA FECB 20,000 46 0 FECC FECD CODE (HEX) 07652-022 0 30,073 Figure 15. Histogram of 262,144 Conversions of a DC Input at the Code Center (Internal Reference) 262,144 SAMPLES STD DEVIATION = 0.4814 201,614 COUNT 150,000 100,000 50,000 0 0 41 FEC8 FEC9 FECA FECB FECC 33 0 FECD FECE CODE (HEX) 07652-024 30,250 30,206 0 FEC6 2329 2130 FEC7 FEC8 FEC9 FECA 0 FECB CODE (HEX) Figure 17. Histogram of 262,144 Conversions of a DC Input at the Code Transition (Internal Reference) 250,000 200,000 0 Figure 16. Histogram of 262,144 Conversions of a DC Input at the Code Center (External Reference) Rev. B | Page 11 of 24 07652-023 30,651 AD7625 Data Sheet TERMINOLOGY Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of an 80 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN− at frequency fS. CMRR (dB) = 10log(Pf/PfS) Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. PSRR is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value. Reference Voltage Temperature Coefficient The reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of parts at the maximum and minimum reference output voltage (VREF) measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as where: Pf is the power at frequency f in the ADC output. PfS is the power at frequency fS in the ADC output. Differential Nonlinearity (DNL) Error In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Integral Nonlinearity (INL) Error Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the rms noise measured for an input typically at −60 dB. The value for dynamic range is expressed in decibels. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD and is expressed in bits by TCVREF ( ppm/C ) VREF ( 25C ) ( TMAX – TMIN ) 106 where: VREF (Max) = maximum VREF at TMIN, T(25°C), or TMAX. VREF (Min) = minimum VREF at TMIN, T(25°C), or TMAX. VREF (25°C) = VREF at 25°C. TMAX = +85°C. TMIN = −40°C. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) (SINAD) Ratio SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) ENOB = [(SINADdB − 1.76)/6.02] SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. Gain Error The first transition (from 100 … 000 to 100 …001) should occur at a level ½ LSB above nominal negative full scale (−4.0959375 V for the ±4.096 V range). The last transition (from 011 … 110 to 011 … 111) should occur for an analog voltage 1½ LSB below the nominal full scale (+4.0959375 V for the ±4.096 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Least Significant Bit (LSB) Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Zero Error Zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is LSB (V) VREF ( Max ) – VREF ( Min) VIN p-p 2N Rev. B | Page 12 of 24 Data Sheet AD7625 THEORY OF OPERATION IN+ GND LSB MSB 32,768C 16,384C 4C 2C C SWITCHES CONTROL SW+ C REF (4.096V) CLK+, CLK– COMP GND 4C 2C C DATA TRANSFER D+, D– OUTPUT CODE C MSB DCO+, DCO– SW– LSB CNV+, CNV– GND CONVERSION CONTROL IN– LVDS INTERFACE 07652-030 32,768C 16,384C CONTROL LOGIC Figure 18. ADC Simplified Schematic CIRCUIT INFORMATION The AD7625 is a 6 MSPS, high precision, power efficient, 16-bit ADC that uses SAR based architecture to provide performance of 93 dB SNR, ±0.45 LSB INL, and ±0.3 LSB DNL. The AD7625 is capable of converting 6,000,000 samples per second (6 MSPS). The device typically consumes 135 mW. The AD7625 offers the added functionality of a high performance on-chip reference and on-chip reference buffer. The AD7625 is specified for use with 5 V and 2.5 V supplies (VDD1, VDD2). The interface from the digital host to the AD7625 uses 2.5 V logic only. The AD7625 uses an LVDS interface to transfer data conversions. The CNV+ and CNV− inputs to the device activate the conversion of the analog input. The CNV+ and CNV− pins can be applied using a CMOS or LVDS source. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs (IN+ and IN−) captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and 4.096 V (the reference voltage), the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 … VREF/65,536). The control logic toggles these switches, MSB first, to bring the comparator back into a balanced condition. At the completion of this process, the control logic generates the ADC output code. The AD7625 digital interface uses low voltage differential signaling (LVDS) to enable high data transfer rates. CONVERTER INFORMATION The AD7625 conversion result is available for reading after tMSB (time from the conversion start until MSB is available) has elapsed. The user must apply a burst LVDS CLK± signal to the AD7625 to transfer data to the digital host. The AD7625 is a 6 MSPS ADC that uses SAR based architecture incorporating a charge redistribution DAC. Figure 18 shows a simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors that are connected to the two comparator inputs. The CLK± signal outputs the ADC conversion result onto the data output D±. The bursting of the CLK± signal is illustrated in Figure 29 and Figure 30 and is characterized as follows: The differential voltage on CLK± should be held to create logic low in the time between tCLKL and tMSB. During the acquisition phase, the terminals of the array tied to the input of the comparator are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. In this way, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. A conversion phase is initiated when the acquisition phase is complete and the CNV± input goes logic high. Note that the AD7625 can receive a CMOS (CNV+) or LVDS format (CNV±) signal. The AD7625 has two data read modes. For more information about the echoed-clock and self-clocked interface modes, see the Digital Interface section. The AD7625 is housed in a space-saving, 32-lead, 5 mm × 5 mm LFCSP. Rev. B | Page 13 of 24 AD7625 Data Sheet TRANSFER FUNCTIONS ANALOG INPUTS The AD7625 uses a 4.096 V reference. The AD7625 converts the differential voltage of the antiphase analog inputs (IN+ and IN−) into a digital output. The analog inputs, IN+ and IN−, require a 2.048 V common-mode voltage (REF/2). The analog inputs, IN+ and IN−, applied to the AD7625 must be 180° out of phase with each other. Figure 20 shows an equivalent circuit of the input structure of the AD7625. The 16-bit conversion result is in MSB first, twos complement format. 011 ... 111 011 ... 110 011 ... 101 VDD1 CNV ANALOG INPUT Figure 20. Equivalent Analog Input Circuit Figure 19. ADC Ideal Transfer Functions (FSR = Full-Scale Range) Table 7. Output Codes and Ideal Input Voltages Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR Analog Input (IN+ − IN−) REF = 4.096 V +4.0959375 V +62.5 μV 0V −62.5 μV −4.0959375 V −4.096 V Digital Output Code Twos Complement (Hex) 0x1FFF 0x0001 0x0000 0xFFFF 0x1001 0x1000 The analog input structure allows the sampling of the true differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected. The AD7625 shows some degradation in THD with higher analog input frequencies. 85 80 75 70 65 60 55 50 45 40 1 10 100 1k 10k 100k 1M INPUT COMMON-MODE FREQUENCY (Hz) Figure 21. Analog Input CMRR vs. Frequency Rev. B | Page 14 of 24 10M 07652-009 +FSR – 1LSB +FSR – 1.5LSB 07652-032 –FSR + 1LSB –FSR + 0.5LSB CMRR (dB) 100 ... 001 100 ... 000 –FSR 250Ω 25pF IN+ OR IN– 100 ... 010 07652-031 ADC CODE (TWOS COMPLEMENT) The ideal transfer functions for the AD7625 are shown in Figure 19 and Table 7. The two diodes provide ESD protection for the analog inputs, IN+ and IN−. Care must be taken to ensure that the analog input signal does not exceed the reference voltage by more than 0.3 V. If the analog input signal exceeds this level, the diodes become forward-biased and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum. However, if the supplies of the input buffer (for example, the supplies of the ADA4899-1 in Figure 24) are different from those of the reference, the analog input signal may eventually exceed the supply rails by more than 0.3 V. In such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the device. Data Sheet AD7625 TYPICAL CONNECTION DIAGRAM V+ ADR434 8 ADR444 CAPACITOR ON OUTPUT FOR STABILITY 10nF ADR280 8 10µF 10kΩ 3 VDD1 2 VDD2 3 CAP1 4 REFIN 5 EN0 10kΩ CONTROL FOR ENABLE PINS 6 EN1 7 VDD2 31 30 29 28 27 26 25 REF REF CAP2 GND CAP2 CAP2 GND 24 PADDLE IN+ 23 IN+ IN– 22 IN– SEE THE DRIVING THE AD7625 SECTION7 VCM VCM 21 AD7625 VDD1 20 100nF FERRITE BEAD 6 VDD1 (5V) VDD1 19 VDD2 18 GND DCO– DCO+ 9 10 11 12 13 14 15 CLK+ VIO 8 CLK– D+ CONVERSION4 CONTROL CMOS (CNV+ ONLY) OR LVDS CNV+ AND CNV– USING 100Ω TERMINATION RESISTOR D– 100nF CNV+ VDD2 (2.5V) 1 32 GND 100nF 100nF VIO 10µF1 CNV– VDD2 (2.5V) CREF 10µF1, 2 REF VDD1 (5V) 16 17 100nF VDD2 (2.5V) 5 100Ω 100Ω VIO (2.5V) 100Ω 100Ω DIGITAL INTERFACE SIGNALS DIGITAL HOST LVDS TRANSMIT AND RECEIVE SEE THE LAYOUT, DECOUPLING, AND GROUNDING SECTION. CREF IS USUALLY A 10µF CERAMIC CAPACITOR WITH LOW ESR AND ESL. USE PULL-UP OR PULL-DOWN RESISTORS TO CONTROL EN0, EN1 DURING POWER-UP. EN0 AND EN1 INPUTS CAN BE FIXED IN HARDWARE OR CONTROLLED USING A DIGITAL HOST (EN0 = 0 AND EN1 = 0 IS AN ILLEGAL STATE). 4 OPTION TO USE A CMOS (CNV+) OR LVDS (CNV±) INPUT TO CONTROL CONVERSIONS. 5 TO ENABLE SELF-CLOCKED MODE, TIE DCO+ TO GND USING A PULL-DOWN RESISTOR. 6 CONNECT PIN 19 AND PIN 20 TO VDD1 SUPPLY; ISOLATE FROM PIN 1 USING A FERRITE BEAD SIMILAR TO WURTH 74279266. 7 SEE THE DRIVING THE AD7625 SECTION FOR DETAILS ON AMPLIFIER CONFIGURATIONS. 8 SEE THE VOLTAGE REFERENCE OPTIONS SECTION FOR DETAILS. Figure 22. Typical Application Diagram Rev. B | Page 15 of 24 07652-027 1 2 3 AD7625 Data Sheet DRIVING THE AD7625 ADA4899-1 Differential Analog Input Source U1 ANALOG INPUT (UNIPOLAR 0V TO 4.096V) Figure 24 shows an ADA4899-1 driving each differential input to the AD7625. Single-Ended-to-Differential Driver 590Ω For applications using unipolar analog signals, a single-endedto-differential driver, as shown in Figure 23, allows for a differential input into the device. This configuration, when provided with an input signal of 0 V to 4.096 V, produces a differential ±4.096 V with midscale at 2.048 V. The one-pole filter using R = 33 Ω and C = 56 pF provides a corner frequency of 86 MHz. The VCM output of the AD7625 can be buffered and then used to provide the required 2.048 V common-mode voltage. 33Ω 56pF IN+ 590Ω AD7625 IN– VCM 33Ω U2 56pF ADA4899-1 100nF 100nF V+ V– AD8031, AD8032 Figure 23. Single-Ended-to-Differential Driver Circuit REF1 CREF 10µF2 CREF 10µF2 +VS REF1 33Ω 0V TO VREF REF 56pF REFIN IN+ ADA4899-1 –V S AD7625 +VS IN– 33Ω VREF TO 0V ADA4899-1 GND 56pF VCM 2.048V –VS +VS VCM BUFFERED VCM PIN OUTPUT GIVES THE REQUIRED 2.048V COMMON-MODE SUPPLY FOR ANALOG INPUTS. 0.1µF –VS AD8031, AD8032 THE VOLTAGE REFERENCE OPTIONS SECTION. CONNECTION TO EXTERNAL REFERENCE SIGNALS IS DEPENDENT ON THE EN1 AND EN0 SETTINGS. IS USUALLY A 10µF CERAMIC CAPACITOR WITH LOW ESL AND ESR. THE REF AND REFIN PINS ARE DECOUPLED REGARDLESS OF EN1 AND EN0 SETTINGS. 2C REF Figure 24. Driving the AD7625 from a Differential Analog Source Rev. B | Page 16 of 24 07652-025 1SEE 07652-033 50Ω Data Sheet AD7625 VOLTAGE REFERENCE OPTIONS Table 8. Voltage Reference Options1 The AD7625 allows flexible options for creating and buffering the reference voltage. The AD7625 conversions refer to 4.096 V only. The various options creating this 4.096 V reference are controlled by the EN1 and EN0 pins (see Table 8). Option A EN1 1 EN0 1 B 0 1 C 1 0 1 A V+ V+ EN1 = 0 and EN0 = 0 is an illegal state. SETTING EN1 = 1 AND EN0 = 1 ENABLES THE INTERNAL REFERENCE AND REFERENCE BUFFER. DECOUPLE THE REF AND REFIN PINS EXTERNALLY. ADR280 ADR434 ADR444 Reference Mode Use internal reference and internal reference buffer (both are enabled). Use external 1.2 V reference with internal reference buffer enabled. The internal reference is disabled. Use external 4.096 V reference with an external reference buffer. The internal reference and reference buffer are disabled. V+ 10µF 10µF V– C B IN+ REF REFIN AD7625 SETTING EN1 = 0 AND EN0 = 1 DISABLES THE INTERNAL REFERENCE AND ENABLES THE INTERNAL REFERENCE BUFFER. CONNECT A 1.2V REFERENCE TO THE REFIN PIN. THE 1.2V APPLIED TO THE REFIN PIN IS BUFFERED INTERNALLY TO CREATE A 4.096V REFERENCE FOR THE ADC. IN– Figure 25. Voltage Reference Options Rev. B | Page 17 of 24 07652-026 SETTING EN1 = 1 AND EN0 = 0 DISABLES THE INTERNAL REFERENCE AND REFERENCE BUFFER. CONNECT THE BUFFERED 4.096V SIGNAL TO THE REF PIN. AD7625 Data Sheet The AD7625 uses both 5 V (VDD1) and 2.5 V (VDD2) power supplies, as well as a digital input/output interface supply (VIO). VIO allows a direct interface with 2.5 V logic only. VIO and VDD2 can be taken from the same 2.5 V source; however, it is best practice to isolate the VIO and VDD2 pins using separate traces and also to decouple each pin separately. The 5 V and 2.5 V supplies required for the AD7625 can be generated using Analog Devices, Inc., low dropout regulators (LDOs) such as the ADP3330-2.5, ADP3330-5, ADP3334, and ADP1708. 90 After VIO is established, apply the 2.5 V VDD2 supply to the device followed by the 5 V VDD1 supply and then an external reference (depending on the reference setting being used). Finally, apply the analog inputs to the ADC. 25 VDD2 INTERNAL REF 20 CURRENT (mA) POWER SUPPLY VDD2 EXTERNAL REF 15 VIO 10 VDD1 INTERNAL REF VDD2 85 5 VDD1 0 0 1000 2000 3000 4000 5000 6000 7000 SAMPLING RATE (kSPS) 70 Figure 27. Current Consumption vs. Sampling Rate 65 60 150 140 55 1 10 100 1k SUPPLY FREQUENCY (Hz) 10k Figure 26. PSRR vs. Supply Frequency (350 mV pp Ripple on VDD2, 600 mV Ripple on VDD1) Power-Up When powering up the AD7625 device, first apply the VIO voltage to the device so that the EN1 and EN0 values can be set for the reference option in use. Connect the EN0 and EN1 pins to pull-up/pull-down resistors to ensure that one or both of these pins is set to a nonzero value. EN0 = 0 and EN1 = 0 is an illegal state that must be avoided. POWER DISSIPATION (mW) 50 07652-011 INTERNAL REFERENCE USED Rev. B | Page 18 of 24 130 INTERNAL REF 120 110 100 EXTERNAL REF 90 80 70 60 0 1000 2000 3000 4000 5000 6000 SAMPLING RATE (kSPS) Figure 28. Power Dissipation vs. Sampling Rate 7000 07652-017 PSRR (dB) 75 07652-016 VDD1 EXTERNAL REF 80 Data Sheet AD7625 The clock DCO± is a buffered copy of CLK± and is synchronous to the data, D±, which is updated on the falling edge of DCO+ (tD). By maintaining good propagation delay matching between D± and DCO± through the board and the digital host, DCO± can be used to latch D± with good timing margin for the shift register. DIGITAL INTERFACE Conversion Control All analog-to-digital conversions are controlled by the CNV signal. This signal can be applied in the form of a CNV+/CNV− LVDS signal, or it can be applied in the form of a 2.5 V CMOS logic signal to the CNV+ pin. The conversion is initiated by the rising edge of the CNV signal. Conversions are initiated by a CNV± pulse. The CNV± pulse must be returned low (≤tCNVH maximum) for valid operation. After a conversion begins, it continues until completion. Additional CNV± pulses are ignored during the conversion phase. After the time tMSB elapses, the host should begin to burst the CLK±. Note that tMSB is the maximum time for the MSB of the new conversion result and should be used as the gating device for CLK±. The echoed clock, DCO±, and the data, D±, are driven in phase, with D± being updated on the falling edge of DCO+; the host should use the rising edge of DCO+ to capture D±. The only requirement is that the 16 CLK pulses finish before the time tCLKL elapses for the next conversion phase or the data is lost. From the time tCLKL to tMSB, D± and DCO± are driven to 0s. Set CLK± to idle low between CLK± bursts. After the AD7625 is powered up, the first conversion result generated is invalid. Subsequent conversion results are valid provided that the time between conversions does not exceed the maximum specification for tCYC. The two methods for acquiring the digital data output of the AD7625 via the LVDS interface are described in the following sections. Echoed-Clock Interface Mode The digital operation of the AD7625 in echoed-clock interface mode is shown in Figure 29. This interface mode, requiring only a shift register on the digital host, can be used with many digital hosts (FPGA, shift register, microprocessor, and so on). It requires three LVDS pairs (D±, CLK±, and DCO±) between each AD7625 and the digital host. SAMPLE N SAMPLE N + 1 tCYC tCNVH CNV– CNV+ tACQ ACQUISITION ACQUISITION ACQUISITION tCLKL tCLK 15 CLK– 16 1 2 15 16 1 2 3 CLK+ 15 DCO+ D– 1 tMSB tCLKD D+ 16 D1 N–1 D0 N–1 2 15 1 16 2 3 tD 0 D15 N D14 N D1 N D0 N Figure 29. Echoed-Clock Interface Mode Timing Diagram Rev. B | Page 19 of 24 0 D15 N+1 D14 N+1 D13 N+1 07652-003 tDCO DCO– AD7625 Data Sheet Self-Clocked Interface Mode Conversions are initiated by a CNV± pulse. The CNV± pulse must be returned low (≤tCNVH maximum) for valid operation. After a conversion begins, it continues until completion. Additional CNV± pulses are ignored during the conversion phase. After the time tMSB elapses, the host should begin to burst the CLK±. Note that tMSB is the maximum time for the first bit of the header and should be used as the gating device for CLK±. CLK± is also used internally on the host to begin the internal synchronization state machine. The next header bit and conversion results are output on subsequent falling edges of CLK±. The only requirement is that the 18 CLK± pulses finish before the time tCLKL elapses for the next conversion phase or the data is lost. Set CLK± to idle high between bursts of 18 CLK± pulses. The digital operation of the AD7625 in self-clocked interface mode is shown in Figure 30. This interface mode reduces the number of wires between ADCs and the digital host to two LVDS pairs per AD7625 (CLK± and D±) or to a single pair if sharing a common CLK± using multiple AD7625 devices. Self-clocked interface mode facilitates the design of boards that use multiple AD7625 devices. The digital host can adapt the interfacing scheme to account for differing propagation delays between each AD7625 device and the digital host. The self-clocked interface mode consists of preceding the results of each ADC word with a 2-bit header on the data, D±. This header is used to synchronize D± of each conversion in the digital host. Synchronization is accomplished by one simple state machine per AD7625 device. For example, if the state machine is running at the same speed as CLK± with three phases, the state machine measures when the Logic 1 of the header occurs. SAMPLE N SAMPLE N + 1 tCYC tCNVH CNV– CNV+ tACQ ACQUISITION ACQUISITION ACQUISITION tCLK tCLKL 17 CLK– 18 1 2 3 4 17 1 18 2 3 CLK+ D+ D– D1 N–1 D0 N–1 0 1 0 D15 N D14 N D1 N Figure 30. Self-Clocked Interface Mode Timing Diagram Rev. B | Page 20 of 24 D0 N 0 1 0 D15 N+1 07652-004 tMSB tCLKD Data Sheet AD7625 APPLICATIONS INFORMATION LAYOUT, DECOUPLING, AND GROUNDING When laying out the printed circuit board (PCB) for the AD7625, follow the practices described in this section to obtain the maximum performance from the converter. supply to Pin 19 and Pin 20 using a 100 nF capacitor to GND. This GND connection can be placed a short distance away from the exposed pad. VIO Supply Decoupling Exposed Pad Decouple the VIO supply applied to Pin 12 to ground at Pin 13. The AD7625 has an exposed pad on the underside of the package. Layout and Decoupling of Pin 25 to Pin 32 Connect the outputs of Pin 25, Pin 26, and Pin 28 together and decouple them to Pin 27 using a 10 μF capacitor with low ESR and low ESL. Solder the pad directly to the PCB. Connect the pad to the ground plane of the board using multiple vias, as shown in Figure 31. Decouple all supply pins except for Pin 12 (VIO) directly to the pad, minimizing the current return path. Pin 13 and Pin 24 can be connected directly to the pad. Use vias to ground at the point where these pins connect to the pad. VDD1 Supply Routing and Decoupling The VDD1 supply is connected to Pin 1, Pin 19, and Pin 20. The supply should be decoupled using a 100 nF capacitor at Pin 1. The user can connect this supply trace to Pin 19 and Pin 20. Use a series ferrite bead to connect the VDD1 supply from Pin 1 to Pin 19 and Pin 20. The ferrite bead isolates any high frequency noise or ringing on the VDD1 supply. Decouple the VDD1 Reduce the inductance of the path connecting Pin 25, Pin 26, and Pin 28 by widening the PCB traces connecting these pins. A similar approach should be taken in the connections used for the reference pins of the AD7625. Connect Pin 29, Pin 30, and Pin 32 together using widened PCB traces to reduce inductance. In internal or external reference mode, a 4.096 V reference voltage is output on Pin 29, Pin 30, and Pin 32. Decouple these pins to Pin 31 using a 10 μF capacitor with low ESR and low ESL. Figure 31 shows an example of the recommended layout for the underside of the AD7625 device. Note the extended signal trace connections and the outline of the capacitors decoupling the signals applied to the REF pins (Pin 29, Pin 30, and Pin 32) and to the CAP2 pins (Pin 25, Pin 26, and Pin 28). 24 23 22 21 20 19 18 17 25 4.096V EXTERNAL REFERENCE (ADR434 OR ADR444) 16 Paddle 26 15 27 14 28 13 29 12 30 11 31 10 32 9 2 3 4 5 6 7 8 07652-013 1 Figure 31. PCB Layout and Decoupling Recommendations for Pin 24 to Pin 32 Rev. B | Page 21 of 24 AD7625 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 0.50 BSC TOP VIEW 0.80 0.75 0.70 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 17 0.50 0.40 0.30 PIN 1 INDICATOR 1 24 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 101515-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 32. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body and 0.75 mm Package Height (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 AD7625BCPZ AD7625BCPZRL7 EVAL-AD7625FMCZ EVAL-SDP-CH1Z 1 2 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board Controller Board Package Option CP-32-7 CP-32-7 Z = RoHS Compliant Part. The EVAL-SDP-CH1Z board allows the PC to control and communicate with all Analog Devices evaluation boards with model numbers ending with the FMC designator. Rev. B | Page 22 of 24 Data Sheet AD7625 NOTES Rev. B | Page 23 of 24 AD7625 Data Sheet NOTES ©2009–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07652-0-10/15(B) Rev. B | Page 24 of 24