ON MC100E101FNR2 5v ecl quad 4â input or/nor gate Datasheet

MC10E101, MC100E101
5VECL Quad 4-Input
OR/NOR Gate
The MC10E/100E101 is a quad 4-input OR/NOR gate.
The 100 Series contains temperature compensation.
• 500 ps Max. Propagation Delay
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
•
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with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Internal Input 50 K Pulldown Resistors
MARKING
DIAGRAMS
1 28
•
• ESD Protection: Human Body Model; > 2 KV,
•
•
•
•
MC10E101FN
Machine Model; > 200 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 115 devices
AWLYYWW
PLCC−28
FN SUFFIX
CASE 776
A
WL
YY
WW
1 28
= Assembly Location
= Wafer Lot
= Year
= Work Week
MC100E101FN
AWLYYWW
ORDERING INFORMATION
Package
Shipping†
MC10E101FN
PLCC−28
37 Units/Rail
MC10E101FNR2
PLCC−28
500 Units/Reel
MC100E101FN
PLCC−28
37 Units/Rail
MC100E101FNR2
PLCC−28
500 Units/Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
 Semiconductor Components Industries, LLC, 2003
November, 2003 − Rev. 5
1
Publication Order Number:
MC10E101/D
MC10E101, MC100E101
LOGIC DIAGRAM
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
D3a
D3b
D3c
D3d VCCO
Q3
Q3
25
24
23
22
20
19
21
D0a
D0b
Q0
D0c
D0d
Q0
D2d
26
18
Q2
D2c
27
17
Q2
D2b
28
16
VCC
D1b
Q1
D1c
Q1
15
Q1
D1d
14
Q1
D2a
VEE
1
D2a
2
Pinout: 28-Lead PLCC
(Top View)
D1d
3
13
Q0
D1c
4
12
Q0
5
D1b
6
7
D1a
8
D0d
D0c
9
10
D0b
D1a
11
D0a VCCO
D2b
Q2
D2c
D2d
Q2
D3a
D3b
Q3
D3c
Q3
D3d
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
PIN DESCRIPTION
PIN
FUNCTION
D0a − D3d
ECL Data Inputs
Q0 − Q3, Q0 − Q3
ECL Differential Outputs
VCC, VCCO
Positive Supply
VEE
Negative Supply
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
8
V
6
−6
V
V
50
100
mA
mA
0 to +85
°C
−65 to +150
°C
VCC
PECL Mode Power Supply
VEE = 0 V
VI
PECL Mode In
Input
ut Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
TA
Operating Temperature Range
Tstg
Storage Temperature Range
JA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
28 PLCC
28 PLCC
63.5
43.5
°C/W
°C/W
JC
Thermal Resistance (Junction to Case)
Standard Board
28 PLCC
22 to 26
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
1. Maximum Ratings are those values beyond which device damage may occur.
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2
VI VCC
VI VEE
MC10E101, MC100E101
10E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 2)
0°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
30
36
30
36
30
36
mA
VOH
Output HIGH Voltage (Note 3)
3980
4070
4160
4020
4105
4190
4090
4185
4280
mV
VOL
Output LOW Voltage (Note 3)
3050
3210
3370
3050
3210
3370
3050
3227
3405
mV
VIH
Input HIGH Voltage
3830
3995
4160
3870
4030
4190
3940
4110
4280
mV
VIL
Input LOW Voltage
3050
3285
3520
3050
3285
3520
3050
3302
3555
mV
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.3
A
0.2
NOTE:
Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
2. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
3. Outputs are terminated through a 50 ohm resistor to V CC − 2 volts.
10E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= −5.0 V (Note 4)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
30
36
Min
85°C
Typ
Max
30
36
Min
Typ
Max
Unit
30
36
mA
−815
−720
mV
−1773
−1595
mV
−890
−720
mV
−1950
−1698
−1445
mV
150
A
0.3
0.2
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 5)
−1020
−930
−840
−980
−895
−810
−910
VOL
Output LOW Voltage (Note 5)
−1950
−1790
−1630
−1950
−1790
−1630
−1950
VIH
Input HIGH Voltage
−1170
−1005
−840
−1130
−970
−810
−1060
VIL
Input LOW Voltage
−1950
−1715
−1480
−1950
−1715
−1480
IIH
Input HIGH Current
IIL
Input LOW Current
0.5
0.3
0.5
0.065
150
NOTE:
150
A
Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
4. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
5. Outputs are terminated through a 50 ohm resistor to V CC − 2 volts.
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3
MC10E101, MC100E101
100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE= 0.0 V (Note 6)
0°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
30
36
30
36
35
42
mA
VOH
Output HIGH Voltage (Note 7)
3975
4050
4120
3975
4050
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 7)
3190
3295
3380
3190
3255
3380
3190
3260
3380
mV
VIH
Input HIGH Voltage
3835
3975
4120
3835
3975
4120
3835
3975
4120
mV
VIL
Input LOW Voltage
3190
3355
3525
3190
3355
3525
3190
3355
3525
mV
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
A
0.2
NOTE:
Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
7. Outputs are terminated through a 50 ohm resistor to V CC − 2 volts.
100E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE = −5.0 V (Note 8)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
30
36
Min
85°C
Typ
Max
30
36
Typ
Max
Unit
35
42
mA
−1025
−950
−880
mV
−1810
−1740
−1620
mV
−880
−1165
−1025
−880
mV
−1475
−1810
−1645
−1475
mV
150
A
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 9)
−1025
−950
−880
−1025
−950
−880
VOL
Output LOW Voltage (Note 9)
−1810
−1705
−1620
−1810
−1745
−1620
VIH
Input HIGH Voltage
−1165
−1025
−880
−1165
−1025
VIL
Input LOW Voltage
−1810
−1645
−1475
−1810
−1645
IIH
Input HIGH Current
IIL
Input LOW Current
150
0.5
0.3
NOTE:
Min
150
0.5
0.25
0.5
0.2
A
Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
8. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
9. Outputs are terminated through a 50 ohm resistor to V CC − 2 volts.
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4
MC10E101, MC100E101
AC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V or VCCx= 0.0 V; VEE= −5.0 V (Note 8)
0°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
700
Typ
85°C
Max
Min
700
Typ
Max
700
Unit
fMAX
Maximum Toggle Frequency
MHz
tPLH
tPHL
Propagation Delay to Output
tSKEW
tSKEW
Within-Device Skew (Note 11)
Within-Gate Skew (Note 12)
50
25
50
25
50
25
ps
tJITTER
Random Clock Jitter (RMS)
<1
<1
<1
ps
tr
tf
Rise/Fall Time
(20 - 80%)
ps
D to Q
200
350
500
200
350
500
200
350
500
ps
300
380
575
NOTE:
300
380
575
300
380
575
Devices are designed to meet the AC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
10. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
11. Within-device skew is defined as identical transitions on similar paths through a device.
12. Within-gate skew is defined as the variation in propagation delays of a gate when driven from its different inputs.
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5
MC10E101, MC100E101
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
VTT = VCC − 2.0 V
Figure 1. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 − Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
−
ECLinPS Circuit Performance at Non−Standard VIH Levels
AN1405
−
ECL Clock Distribution Techniques
AN1406
−
Designing with PECL (ECL at +5.0 V)
AN1503
−
ECLinPS I/O SPICE Modeling Kit
AN1504
−
Metastability and the ECLinPS Family
AN1568
−
Interfacing Between LVDS and ECL
AN1596
−
ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650
−
Using Wire−OR Ties in ECLinPS Designs
AN1672
−
The ECL Translator Guide
AND8001
−
Odd Number Counters Design
AND8002
−
Marking and Date Codes
AND8020
−
Termination of ECL Logic Devices
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6
MC10E101, MC100E101
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
0.007 (0.180)
B
M
T L−M
N
S
T L−M
S
S
Y BRK
−N−
0.007 (0.180)
U
M
N
S
D
Z
−M−
−L−
W
28
D
X
0.010 (0.250)
G1
T L−M
S
N
S
S
V
1
VIEW D−D
A
0.007 (0.180)
R
0.007 (0.180)
M
T L−M
S
N
S
C
M
T L−M
S
N
0.007 (0.180)
H
Z
J
0.010 (0.250)
S
T L−M
S
N
N
S
S
K1
0.004 (0.100)
−T− SEATING
K
PLANE
F
VIEW S
G1
T L−M
S
E
G
M
S
VIEW S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
−−−
0.020
2
10
0.410
0.430
0.040
−−−
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7
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2
10
10.42
10.92
1.02
−−−
0.007 (0.180)
M
T L−M
S
N
S
MC10E101, MC100E101
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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8
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MC10E101/D
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