TI1 BQ25606 Standalone 3.0-a, single cell battery charger with 40v over voltage protection controller Datasheet

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bq25606
SLUSCK6 – MAY 2017
bq25606 Standalone 3.0-A, Single Cell Battery Charger
With 40V Over Voltage Protection Controller
1 Features
•
1
•
•
•
•
•
•
•
•
High-Efficiency, 1.5-MHz, Synchronous SwitchMode Buck Charger
– 92% Charge Efficiency at 2 A from 5-V Input
– Optimized for USB Voltage Input (5 V)
Supports USB On-The-Go (OTG)
– Boost Converter With Up to 1.2-A Output
– 92% Boost Efficiency at 1-A Output
– Accurate Constant Current (CC) Limit
– Soft-Start Up To 500-µF Capacitive Load
– Output Short Circuit Protection
Single Input to Support USB Input and High
Voltage Adapters
– Support 3.9-V to 13.5-V Input Voltage Range
With 20-V Absolute Maximum Input Voltage
Rating
– Maximum Power Tracking by Input Voltage
Limit Up to 4.6 V (VINDPM)
– VINDPM Threshold Automatically Tracks
Battery Voltage
– Auto Detect USB SDP, DCP and NonStandard Adaptors
200nS Fast Turn-Off of Optional External
OVPFET Standing Input Voltage Up to 40V
High Battery Discharge Efficiency With 19.5-mΩ
Battery Discharge MOSFET
Narrow VDC (NVDC) Power Path Management
– Instant-On Works with No Battery or Deeply
Discharged Battery
– Ideal Diode Operation in Battery Supplement
Mode
High Integration Includes All MOSFETs, Current
Sensing and Loop Compensation
58-µA Low Battery Leakage Current with System
Voltage Standby
High Accuracy
– ±0.5% Charge Voltage Regulation
– ±6% at 1.2-A and 1.8-A Charge Current
Regulation
•
– ±5% at 0.5-A, 1.2-A and 1.8-A Input Current
Regulation
Safety
– Battery Temperature Sensing for Charge and
Boost Mode
– Thermal Regulation and Thermal Shutdown
– Input UVLO and Overvoltage Protection
2 Applications
•
•
EPOS, Portable Speakers, E-Cigarette
Portable Internet Devices and Accessory
3 Description
The bq25606 device is a highly-integrated standalone
3.0-A switch-mode battery charge management and
system power path management device for single cell
Li-Ion and Li-polymer battery. The low impedance
power path optimizes switch-mode operation
efficiency, reduces battery charging time and extends
battery life during discharging phase.
Device Information(1)
PART NUMBER
bq25606
PACKAGE
VQFN (24)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
USB
Optional
VBUS
SW
ACDRV
BTST
ILIM
SYS
ICHG
BAT
CE
VSET
ICHG
REGN
+
TS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq25606
SLUSCK6 – MAY 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
8
8.3 Feature Description................................................. 16
1
1
1
2
3
4
6
9
Application and Implementation ........................ 24
9.1 Application information............................................ 24
9.2 Typical Application Diagram .................................. 25
9.3 Application Curves .................................................. 28
10 Power Supply Recommendations ..................... 33
11 Layout................................................................... 34
11.1 Layout Guidelines ................................................. 34
11.2 Layout Example .................................................... 34
Absolute Maximum Ratings ...................................... 6
Recommended Operating Conditions....................... 6
Thermal information .................................................. 6
Timing Requirements ................................................ 7
Electrical Characteristics........................................... 7
Typical Characteristics ............................................ 12
12 Device and Documentation Support ................. 36
12.1
12.2
12.3
12.4
Detailed Description ............................................ 14
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
13 Mechanical, Packaging, and Orderable
Information ........................................................... 37
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 15
4 Revision History
2
DATE
REVISION
NOTES
May 2017
*
Initial release.
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5 Description (continued)
The bq25606 is a highly-integrated standalone 3.0-A switch-mode battery charge management and system
power path management device for single cell Li-Ion and Li-polymer battery. It features fast charging with high
input voltage support for a wide range of standalone chargers and portable devices. Its low impedance power
path optimizes switch-mode operation efficiency, reduces battery charging time and extends battery life during
discharging phase. Its input voltage and current regulation deliver maximum charging power to battery. The
solution is highly integrated with input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2),
low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4) between system and battery. It also
integrates the bootstrap diode for the high-side gate drive for simplified system design.
The device supports a wide range of input sources, including standard USB host port, USB charging port, and
USB compliant high voltage adapter. The device sets default input current limit based on the built-in USB
interface. The device is compliant with USB 2.0 and USB 3.0 power spec with input current and voltage
regulation. When the device built-in USB interface identifies the input adaptor is unknown, the device's input
current limit is determined by the ILIM pin setting resistor value. The device also meets USB On-the-Go (OTG)
operation power rating specification by supplying 5.15 V on VBUS with constant current limit up to 1.2-A.
The power path management regulates the system slightly above battery voltage but does not drop below 3.5 V
minimum system voltage. With this feature, the system maintains operation even when the battery is completely
depleted or removed. When the input current limit or voltage limit is reached, the power path management
automatically reduces the charge current to zero. As the system load continues to increase, the power path
discharges the battery until the system power requirement is met. This Supplement Mode prevents overloading
the input source.
The device initiates and completes a charging cycle without software control. It senses the battery voltage and
charges the battery in three phases: pre-conditioning, constant current and constant voltage. At the end of the
charging cycle, the charger automatically terminates when the charge current is below a preset limit and the
battery voltage is higher than recharge threshold. If the fully charged battery falls below the recharge threshold,
the charger automatically starts another charging cycle.
The charger provides various safety features for battery charging and system operations, including battery
negative temperature coefficient thermistor monitoring, charging safety timer and overvoltage and overcurrent
protections. The thermal regulation reduces charge current when the junction temperature exceeds 110°C. The
STAT output reports the charging status and any fault conditions.
The device family is available in 24-pin, 4 mm x 4 mm QFN package.
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6 Pin Configuration and Functions
Terminal
Name
No.
ACDRV
BAT
2
13
14
VBUS
PMID
REGN
BTST
SW
SW
24
23
22
21
20
19
bq25606 WQFN Package
24-Pin WQFN
Top View
VAC
1
18
GND
ACDRV
2
17
GND
D+
3
16
SYS
D±
4
STAT
5
OTG
6
9
10 11 12
ILIM
CE
ICHG
15
SYS
14
BAT
13
BAT
VSET
8
TS
7
PG
Thermal
Pad
(Not to scale)
I/O
Description
AO
Charge pump output to drive external N-channel MOSFET (OVPFET). ACDRV voltage is 11 V above
VBUS when VAC voltage is below ACOV threshold and above VVAC_PRESENT. If external OVP is not
used, leave this pin floating.
P
Battery connection point to the positive terminal of the battery pack. The internal current sensing resistor
is connected between SYS and BAT. Connect a 10 µF closely to the BAT pin.
BTST
21
P
PWM high side driver positive supply. internally, the BTST is connected to the cathode of the boost-strap
diode. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
CE
9
DI
Charge enable pin. When this pin is driven low, battery charging is enabled.
D+
3
AIO
Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection
includes data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard
adaptors
D–
4
AIO
Negative line of the USB data line pair. D+/D– based USB host/charging port detection. The detection
includes data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard
adaptors
GND
ICHG
17
18
10
—
Power ground and signal ground
AI
ICHG pin sets the charge current limit. A resistor is connected from ICHG pin to ground to set charge
current limit as ICHG = KICHG/RICHG. The acceptable range for charge current is 300 mA – 3000 mA.
ILIM
8
AI
ILIM sets the input current limit. A resistor is connected from ILIM pin to ground to set the input current
limit as IINDPM = KILIM/RILIM. The acceptable range for ILIM current is 500 mA - 3200 mA.
The resistor based input current limit is effective only when the input adapter is detected as unknown.
Otherwise, the input current limit is determined by D+/D– detection outcome.
OTG
6
DI
Boost mode enable pin. When this pin is pulled HIGH, OTG is enabled. OTG cannot be floating.
PG
7
DO
Open drain active low power good indicator. Connect to the pull up rail through 10 kΩ resistor. LOW
indicates a good input if the input voltage is between UVLO and ACOV, above SLEEP mode threshold,
and input current limit is above 30 mA.
PMID
23
P
Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Put a 10 -μF
ceramic capacitor between PMID and GND.
REGN
22
P
PWM low side driver positive supply output. Internally, REGN is connected to the anode of the booststrap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to analog GND. The capacitor
should be placed close to the IC.
4
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(continued)
Terminal
Name
STAT
No.
5
I/O
Description
DO
Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin
indicates charger status.
Charge in progress: LOW
Charge complete or charger in SLEEP mode: HIGH
Charge suspend (fault response): BlinK at 1Hz
19
SW
SYS
20
15
16
P
Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel
HSFET and the drain of the n-channel LSFET. Connect the 0.047-μF bootstrap capacitor from SW to
BTST.
P
Converter output connection point. The internal current sensing resistor is connected between SYS and
BAT. Connect a 20 µF capacitor close to the SYS pin.
TS
11
AI
Temperature qualification voltage input to support JEITA profile. Connect a negative temperature
coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND.
Charge suspends when TS pin voltage is out of range. Recommend 103AT-2 thermistor.
VAC
1
AI
Input voltage sensing. When VAC voltage is below ACOV threshold and above UVLO, external OVPFET
turns on. If exteral OVP is not used, This pin must be shorted to VBUS pin.
VBUS
24
P
Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between
VBUS and PMID with VBUS on source. Place a 1-uF ceramic capacitor from VBUS to GND and place it
as close as possible to IC.
AI
VSET pin sets default battery charge voltage in bq25606. Program battery regulation voltage with a
resistor pull-down from VSET to GND.
RPD > 50kΩ (float pin) = 4.208 V
RPD < 500Ω (short to GND) = 4.352 V
5kΩ < RPD < 25kΩ = 4.400 V
P
Ground reference for the device that is also the thermal pad used to conduct heat from the device. This
connection serves two purposes. The first purpose is to provide an electrical ground connection for the
device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB.
This pad should be tied externally to a ground plane.
VSET
Thermal Pad
12
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Min
MAX
UNIT
–2
40
V
–0.3
40
V
–2
22
V
–0.3
22
V
–2
16
V
BTST to SW
–0.3
7
V
D+, D–
–0.3
7
V
Voltage Range (with respect to
GND)
REGN, TS, CE, PG, BAT, SYS (converter not switching)
–0.3
7
V
Output Sink current
STAT
6
mA
Voltage Range (with respect to
GND)
VSET, ILIM, ICHG, OTG
–0.3
7
PGND to GND (QFN package only)
–0.3
0.3
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
Voltage Range (with respect to
GND)
VAC
ACDRV
Voltage Range (with respect to
GND)
VBUS (converter not switching)
Voltage Range (with respect to
GND)
BTST, PMID (converter not switching) (2)
Voltage Range (with respect to
GND)
SW
Voltage Range (with respect to
GND)
Voltage Range (with respect to
GND)
Voltage Range (with respect to
GND)
(1)
(2)
(2)
V
Stresses beyond those listed under Absolute maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
VBUS is specified up to 22 V for a maximum of 1 hour at room temperature
7.2 Recommended Operating Conditions
Min
NOM
13.5
UNIT
(1)
V
VBUS
Input voltage
Iin
Input current (VBUS)
3.25
A
ISYSOP
Output current (SW)
3.0
A
VBATOP
Battery voltage
4.4
V
IBATOP
Fast charging current
3.0
A
IBATOP
Discharging current (continuous)
TA
Operating ambient temperature
(1)
3.9
MAX
–40
6
A
85
°C
The inherent switching noise voltage spikes should not exceed the absolute maximum voltage rating on either the BTST or SW pins. A
tight layout minimizes switching noise.
7.3 Thermal information
bq25606
THERMAL METRIC
RGE (VQFN)
UNIT
24 Pins
RθJA
Junction-to-ambient thermal resistance
31.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
27
°C/W
RθJB
Junction-to-board thermal resistance
9.2
°C/W
ΨJT
Junction-to-top characterization parameter
0.4
°C/W
ΨJB
Junction-to-board characterization parameter
9.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.8
°C/W
6
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7.4 Timing Requirements
Parameter
Additional Information
MIN
NOM
MAX
UNIT
VBUS/BAT POWER UP
tACOV
VAC OVP reaction time
VAC rising above ACOV threshold to
turn off Q2
tDEB
VAC debounce time (time before
ACDRV pulling high)
VAC rising above VVAC_PRESENT
threshold to ACDRV pulling high
tBADSRC
Bad adapter detection duration
200
ns
15
ms
30
ms
BATTERY CHARGER
tTERM_DGL
Deglitch time for charge termination
250
ms
tRECHG_DGL
Deglitch time for recharge
250
ms
tSYSOVLD_DGL
System over-current deglitch time to
turn off Q4
100
µs
tBATOVP
Battery over-voltage deglitch time to
disable charge
1
µs
tSAFETY
Typical Charge Safety Timer Range
8
10
12
hr
7.5 Electrical Characteristics
VVAC_PRESENT < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QUIESCENT CURRENTS
IBAT
Battery discharge current (BAT, SW,
SYS) in buck mode
VBAT = 4.5 V, VBUS < VAC-UVLOZ,
leakage between BAT and
VBUS, TJ< 85°C
IBAT
Battery discharge current (BAT, SW,
SYS)
VBAT = 4.5 V, No VBUS, TJ <
85°C
IVBUS
Input supply current (VBUS) in buck
mode
VVBUS = 12 V, VVBUS > VVBAT,
converter not switching
IVBUS
Input supply current (VBUS) in buck
mode
VVBUS > VUVLO, VVBUS > VVBAT,
converter switching, VBAT =
3.8V, ISYS = 0A
3
mA
IBOOST
Battery discharge current in boost mode
VBAT = 4.2 V, boost mode, IVBUS
= 0 A, converter switching
3
mA
5
µA
58
85
µA
1.5
3
mA
VBUS, VAC AND BAT PIN POWER-UP
VBUS_OP
VBUS operating range
VVBUS rising
3.9
VVAC_PRESENT
OVPFET turn-on threshold
VVAC rising
3.36
VVAC_PRESENT_H
VVAC falling
YS
3.65
13.5
V
3.97
V
mV
300
VSLEEP
Sleep mode falling threshold
(VVAC–VVBAT ), VBUSMIN_FALL ≤
VBAT ≤ VREG, VAC falling
37
76
126
mV
VSLEEPZ
Sleep mode rising threshold
(VVAC–VVBAT ), VBUSMIN_FALL ≤
VBAT ≤ VREG, VAC rising
130
220
350
mV
VVAC_OV_RISE
VAC Overvoltage rising threshold
VAC rising
13.5
14.28
14.91
VVAC_OV_HYS
VAC Overvoltage hysteresis
VAC falling
VBAT_DPL_FALL
Battery depletion falling threshold (Q4
turn-off threshold)
VBAT falling
2.15
2.6
V
VBAT_DPL_RISE
Battery Depletion rising threshold (Q4
turn-on threshold)
VBAT rising
2.35
2.82
V
VBAT_DPL_HYST
Battery Depletion rising hysteresis
VBAT rising
VBUSMIN_FALL
Bad adapter detection falling threshold
VBUS falling
VBUSMIN_HYST
Bad adapter detection hysteresis
IBADSRC
Bad adapter detection current source
Sink current from VBUS to GND
520
mV
180
3.65
3.8
V
mV
3.93
V
200
mV
30
mA
POWER-PATH
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Electrical Characteristics (continued)
VVAC_PRESENT < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.5
3.68
V
VBAT +
50 mV
V
VSYS_MIN
System regulation voltage
VVBAT < VSYS_MIN = 3.5V, charge
enabled or disabled
VSYS
System regulation voltage
ISYS = 0 A, VVBAT > VSYSMIN,
charge disabled
RON(RBFET)
Top reverse blocking MOSFET onresistance between VBUS and PMID Q1
-40°C≤ TA ≤ 125°C
45
mΩ
RON(HSFET)
Top switching MOSFET on-resistance
between PMID and SW - Q2
VREGN = 5 V , -40°C≤ TA ≤
125°C
62
mΩ
RON(LSFET)
Bottom switching MOSFET onresistance between SW and GND - Q3
VREGN = 5 V , -40°C≤ TA ≤
125°C
70
mΩ
VFWD
BATFET forward voltage in supplement
mode
30
mV
RON(BAT-SYS)
SYS-BAT MOSFET on-resistance
QFN package, Measured from
BAT to SYS, VBAT = 4.2V, TJ =
25°C
19.5
24
mΩ
RON(BAT-SYS)
SYS-BAT MOSFET on-resistance
QFN package, Measured from
BAT to SYS, VBAT = 4.2V, TJ =
–40 - 125°C
19.5
30
mΩ
BATTERY CHARGER
VBATREG
Charge voltage
RVSET > 50 kΩ, –40 ≤ TJ ≤ 85°C
4.187
4.208
4.229
V
RVSET < 500 Ω, –40 ≤ TJ ≤ 85°C
4.330
4.352
4.374
V
RVSET = 10 kΩ, –40 ≤ TJ ≤ 85°C
4.378
4.4
4.422
V
VBAT = 4.208 V or VBAT = 4.352
V, –40 ≤ TJ ≤ 85°C
–0.5%
0.5%
0
3000
mA
715
mA
VBATREG_ACC
Charge voltage setting accuracy
ICHG_REG_RANGE
Charge current regulation range
ICHG_REG
Charge current regulation
RICHG = 1100 Ω, VVBAT = 3.1 V
or VVBAT = 3.8 V
516
ICHG_REG_ACC
Charge current regulation accuracy
RICHG = 1100 Ω, VVBAT = 3.1 V
or VVBAT = 3.8 V
-16%
ICHG_REG
Charge current regulation
ICHG_REG
Charge current regulation accuracy
RICHG = 562 Ω, VBAT = 3.1 V or
VBAT = 3.8 V
ICHG_REG
Charge current regulation
RICHG = 372 Ω, VVBAT = 3.1 V or
VVBAT = 3.8 V
1.715
ICHG_REG_ACC
Charge current regulation accuracy
RICHG = 372 Ω, VVBAT = 3.1 V or
VVBAT = 3.8 V
-5%
KICHG
Charge current regulation setting ratio
RICHG = 372 Ω, 562 Ω VVBAT =
3.1 V or VVBAT = 3.8 V
639
KICHG_ACC
Charge current regulation setting ratio
accuracy
RICHG = 372Ω, 562 Ω VVBAT =
3.1 V or VVBAT = 3.8 V
-6%
VBATLOWV_FALL
Battery LOWV falling threshold
Fast charge to precharge
2.67
2.8
2.87
V
VBATLOWV_RISE
Battery LOWV rising threshold
Pre-charge to fast charge
3.0
3.1
3.24
V
IPRECHG
Precharge current regulation
RICHG = 1100 Ω, VVBAT = 2.6 V,
IPRECHG = 5% of ICHG = 615mA
21
38
IPRECHG_ACC
Precharge current regulation accuracy
Percentage of ICHG,RICHG = 1100
Ω, VVBAT = 2.6 V, ICHG = 615mA
3.4%
6.2%
IPRECHG
Precharge current regulation
RICHG = 562 Ω, VVBAT = 2.6 V,
IPRECHG = 5% of ICHG = 1.218A
48
67
IPRECHG_ACC
Precharge current regulation accuracy
Percentage of ICHG,RICHG = 562
Ω, V1330 = 2.6 V, ICHG = 1.218A
3.9%
5.5%
8
RICHG = 562 Ω, VVBAT = 3.1 V or
VVBAT = 3.8 V
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1.14
615
16%
1.218
-6%
1.28
A
6%
1.813
1.89
A
5%
677
715
A×Ω
6%
mA
mA
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Electrical Characteristics (continued)
VVAC_PRESENT < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IPRECHG
Precharge current regulation
RICHG = 372 Ω, VVBAT = 2.6 V,
IPRECHG = 5% of ICHG = 1.813A
IPRECHG_ACC
Precharge current regulation accuracy
Percentage of ICHG,RICHG = 372
Ω, VVBAT = 2.6 V, ICHG = 1.813A
ITERM
Termination current regulation
ITERM_ACC
Termination current regulation accuracy
Percentage of ICHG, RICHG = 562
Ω, VVBAT = 4.35 V, ICHG = 1.218
A
ITERM
Termination current regulation
RICHG = 372 Ω, VVBAT = 4.35 V,
ICHG = 1.813 A
ITERM_ACC
Termination current regulation accuracy
Percentage of ICHG, RICHG = 372
Ω, VVBAT = 4.35 V, ICHG = 1.813
A
VSHORT
Battery short voltage
VVBAT falling
1.85
2
2.15
V
VSHORTZ
Battery short voltage
VVBAT rising
2.05
2.25
2.35
V
ISHORT
Battery short current
VVBAT < VSHORTZ
70
90
110
mA
VRECHG
Recharge Threshold below VBAT_REG
VBAT falling
87
121
156
mV
ISYSLOAD
System discharge load current
VSYS = 4.2 V
RICHG = 562 Ω, VVBAT = 4.35V,
CHG = 1.218A
76
97
4.1%
5.4%
26
100
2.1%
8.3%
56
100
3.0%
mA
mA
126
mA
7.0%
30
mA
INPUT VOLTAGE AND CURRENT REGULATION
VDPM_VBAT
Input voltage regulation limit
VVBAT < 4.1 V (VVBAT= 3.6 V)
4.171
VDPM_VBAT_ACC
Input voltage regulation accuracy
VVBAT < 4.1 V (VVBAT = 3.6 V)
–3%
4.3
4.429
3%
V
IINDPM
USB input current regulation limit
VVBUS = 5 V, USB500 charge
port detected by DPDM , –40 ≤
TJ ≤ 85°C
448
500
mA
IINDPM
Input current regulation limit
RILIM = 910 Ω, unknown adaptor
detected by DPDM , –40 ≤ TJ ≤
85°C
505
526
550
mA
IINDPM
Input current regulation limit accuracy
RILIM = 374 Ω, unknown adaptor
detected by DPDM , –40 ≤ TJ ≤
85°C
1220
1276
1330
mA
IINDPM
Input current regulation limit
RILIM = 265 Ω, unknown adaptor
detected by DPDM , –40 ≤ TJ ≤
85°C
1.73
1.8
1.871
A
IINDPM_ACC
Input current regulation limit accuracy
RILIM = 265 Ω, 374 Ω, 910 Ω,
unknown adaptor detected by
DPDM , –40 ≤ TJ ≤ 85°C
–5%
KILIM
Input current setting ratio, ILIM = KILIM /
RILIM
RILIM = 910 Ω, 374 Ω, 265 Ω,
unknown adaptor detected by
DPDM, –40 ≤ TJ ≤ 85°C
459
KILIM_ACC
Input current setting ratio, ILIM = KILIM /
RILIM
RILIM = 910 Ω, 374 Ω, 265 Ω,
unknown adaptor detected by
DPDM, –40 ≤ TJ ≤ 85°C
–5%
IIN_START
Input current limit during system start-up
sequence
5%
478
500
A×Ω
5%
200
mA
BAT PIN OVERVOLTAGE PROTECTION
VBATOVP_RISE
Battery overvoltage threshold
VBAT rising, as percentage of
VBAT_REG
103%
104%
105%
VBATOVP_FALL
Battery overvoltage threshold
VBAT falling, as percentage of
VBAT_REG
101%
102%
103%
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Electrical Characteristics (continued)
VVAC_PRESENT < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THERMAL REGULATION AND THERMAL SHUTDOWN
TJUNCTION_REG
Junction Temperature Regulation
Threshold
TSHUT
Thermal Shutdown Rising Temperature
TSHUT_HYST
Thermal Shutdown Hysteresis
Temperature Increasing
110
°C
160
°C
30
°C
JEITA Thermistor Comparator (BUCK MODE)
VT1
T1 (0°C) threshold, Charge suspended
T1 below this temperature.
Charger suspends charge. As
Percentage to VREGN
VT1
Falling
72.4%
73.3%
74.2%
As Percentage to VREGN
69%
71.5%
74%
VT2
T2 (10°C) threshold, Charge back to
As percentage of VREGN
ICHG/2 and 4.2 V below this temperature
67.2%
68%
69%
VT2
Falling
As Percentage to VREGN
66%
66.8%
67.7%
VT3
T3 (45°C) threshold, charge back to
ICHG and 4.05V above this
temperature.
Charger suspends charge. As
Percentage to VREGN
43.8%
44.7%
45.8%
VT3
Falling
As Percentage to VREGN
45.1%
45.7%
46.2%
VT5
T5 (60°C) threshold, charge suspended
above this temperature.
As Percentage to VREGN
33.7%
34.2%
35.1%
VT5
Falling
As Percentage to VREGN
34.5%
35.3%
36.2%
COLD OR HOT THERMISTER COMPARATOR (BOOST MODE)
VBCOLD
Cold Temperature Threshold, TS pin
Voltage Rising Threshold
As Percentage to VREGN
(Approx. –20°C w/ 103AT),
–20°C ≤ TJ≤ 125°C
79.5%
80%
80.5%
VBCOLD
Falling
–20°C ≤ TJ≤ 125°C
78.5%
79%
79.5%
VBHOT
Hot Temperature Threshold, TS pin
Voltage falling Threshold
As Percentage to
VREGN (Approx. 60°C w/ 103AT),
–20°C ≤ TJ≤ 125°C
30.2%
31.2%
32.2%
VBHOT
Rising
–20°C ≤ TJ≤ 125°C
33.8%
34.4%
34.9%
10
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Electrical Characteristics (continued)
VVAC_PRESENT < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
IHSFET_OCP
HSFET cycle-by-cycle over-current
threshold
5.2
IBATFET_OCP
System over load threshold
6.0
8.0
A
A
PWM
fSW
PWM switching frequency
DMAX
Maximum PWM duty cycle (1)
Oscillator frequency, buck mode
1320
1500
1680
kHz
Oscillator frequency, boost mode
1170
1412
1500
kHz
97%
BOOST MODE OPERATION
VOTG_REG
Boost mode regulation voltage
VVBAT = 3.8 V, I(PMID) = 0 A
4.972
VOTG_REG_ACC
Boost mode regulation voltage accuracy VVBAT = 3.8 V, I(PMID) = 0 A
-3
VBATLOWV_OTG
5.126
5.280
V
3
%
Battery voltage exiting boost mode
VVBAT falling
2.6
2.8
2.9
V
Battery voltage entering boost mode
VVBAT rising
2.9
3.0
3.15
V
1.2
1.4
1.6
A
5.55
5.8
6.15
V
IOTG
OTG mode output current limit
VOTG_OVP
OTG overvoltage threshold
Rising threshold
VREGN
REGN LDO output voltage
VVBUS = 9 V, IREGN = 40 mA
5.6
6
6.65
V
VREGN
REGN LDO output voltage
VVBUS = 5 V, IREGN = 20 mA
4.6
4.7
4.9
V
0.4
V
REGN LDO
LOGIC I/O PIN CHARACTERISTICS (CE, PSEL, SCL, SDA,, INT)
VILO
Input low threshold CE
VIH
Input high threshold CE
IBIAS
High-level leakage current CE
VILO
Input low threshold OTG
VIH
Input high threshold OTG
IBIAS
High-level leakage current OTG
1.3
V
Pull up rail 1.8 V
1
µA
0.4
V
1.3
V
Pull up rail 1.8 V
1
µA
0.4
V
1.35
V
LOGIC I/O PIN CHARACTERISTICS (PG, STAT)
VOL
Low-level output voltage
D+/D– DETECTION
VD+_1P2
D+ Threshold for Non-standard adapter
(combined V1P2_VTH_LO and
V1P2_VTH_HI)
ID+_LKG
Leakage current into D+
VD–_600MVSRC
Voltage source (600 mV)
ID–_100UAISNK
D– current sink (100 µA)
RD–_19K
D– resistor to ground (19 kΩ)
VD–_0P325
D– comparator threshold for primary
detection
D– pin Rising
VD–_2P8
1.05
HiZ
-1
1
µA
700
mV
150
µA
24.8
kΩ
500
600
VD– = 500 mV,
50
100
VD– = 500 mV,
14.25
250
400
mV
D– Threshold for non-standard adapter
(combined V2P8_VTH_LO and
V2P8_VTH_HI)
2.55
2.85
V
VD–_2P0
D– Comparator threshold for nonstandard adapter (For non-standard –
same as bq2589x)
1.85
2.15
V
VD–_1P2
D– Threshold for non-standard adapter
(combined V1P2_VTH_LO and
V1P2_VTH_HI)
1.05
1.35
V
ID–_LKG
Leakage current into D–
-1
1
µA
(1)
HiZ
Specified by design. Not production tested.
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7.6 Typical Characteristics
100
100
95
95
85
Efficiency (%)
Charge Efficiency (%)
90
90
85
80
75
80
75
70
65
70
VBUS Voltage
5V
9V
12 V
65
60
VBAT = 3.2 V
VBAT = 3.8 V
VBAT = 4.1 V
55
60
50
0
0.5
1
fSW = 1.5 MHz
VBAT = 3.8 V
1.5
2
Charge Current (A)
2.5
3
0
0.2
Inductor DCR = 18 mΩ
VOTG = 5.15 V
Figure 1. Charge Efficiency vs. Charge Current
0.6
0.8
OTG Current (A)
1
1.2
1.4
D001
inductor DCR = 18 mΩ
Figure 2. Efficiency vs. OTG Current
6
3.85
5
3.8
SYSMIN Voltage (V)
OTG Output Voltage (V)
0.4
D001
4
3
2
1
3.75
3.7
3.65
3.6
3.55
0
0
0.2
0.4
0.6
0.8
1
Output Current (A)
0 A ≤ IOTG ≤1.37 A
VVBAT = 3.8 V
1.2
1.4
3.5
-40
1.6
-25
-10
D001
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
D001
VOTG = 5.15 V
Figure 4. SYSMIN Voltage vs. Junction Temperature
Figure 3. OTG Output Voltage vs. Output Current
4.5
2.75
IINDPM = 1.8 A
IINDPM = 1.28 A
IINDPM = 0.52 A
2.25
4.4
Input Current Limit (A)
BATREG Charge Voltage (V)
2.5
4.3
4.2
4.1
4
-40
-10
5
20 35 50 65 80
Junction Temperature (°C)
95
1.5
1.25
1
0.75
0.5
VBATREG = 4.208 V
VBATREG = 4.352 V
VBATREG = 4.4 V
-25
2
1.75
0.25
110 125
0
-40
D001
-25
-10
5
20
35
50
Junction Temperature (°C)
65
80
95
D001
VVBUS = 5 V
Figure 5. BATREG Charge Voltage vs. Junction
Temperature
12
Figure 6. Input Current Limit vs. Junction Temperature
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2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-40
2
ICHG = 1.8 A
ICHG = 1.2 A
ICHG = 0.68 A
1.8
1.6
Charge Current (A)
Charge Current (A)
Typical Characteristics (continued)
1.4
1.2
1
0.8
0.6
0.4
0.2
-25
-10
VVBUS = 5 V
5
20
35
50
65
Junction Temperature (°C)
80
95
0
30
110
VBAT = 3.8 V
Figure 7. Charge Current vs. Junction Temperature
60
70
80
90 100
Junction Temperature (°C)
110
120
130
D001
VBAT = 3.8V
Figure 8. Charge Current vs. Junction Temperature
705
RILIM = 265 :
RILIM = 374 :
RILIM = 910 :
484
RICHG = 372 :
RICHG = 562 :
RICHG = 1100 :
700
Charge Current Setting Ratio
Input Current Limit Setting Ratio
50
VVBUS = 5V
486
482
480
478
476
474
472
-40
40
D001
695
690
685
680
675
670
665
-25
-10
5
20
35
50
Junction Temperature (°C)
VVBUS = 5 V
65
80
95
660
-40
-25
-10
D001
VBAT = 3.8 V
Figure 9. Input Current Limit Setting Ratio vs. Junction
Temperature
VVBUS = 5 V
5
20
35
50
65
Junction Temperature (°C)
80
95
110
D001
VBAT = 3.8 V
Figure 10. Charge Current Setting Ratio vs. Junction
Temperature
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8 Detailed Description
8.1 Overview
The bq25606 device is a highly integrated 3.0-A switch-mode battery charger for single cell Li-Ion and Li-polymer
battery. It includes the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side
switching FET (LSFET, Q3), and battery FET (BATFET, Q4), and bootstrap diode for the high-side gate drive.
14
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8.2 Functional Block Diagram
VBUS
PMID
VVVAC_PRESENT
VVAC
IIN
+
RBFET (Q1)
UVLO
Q1 Gate
Control
±
VBAT + VSLEEP
+
VVAC
ACDRV
EN_REGN
VVAC
VVAC_OV
SLEEP
EN_HIZ
+
REGN
EN_REGN
±
REGN
LDO
ACOV
±
BTST
FBO
VVBUS
VIN
VAC
VBUS_OVP_BOOST
+
VOTG_OVP
±
IQ2
Q2_UCP_BOOST
+
VVBUS
VOTG_HSZCP
±
±
VOTG_BAT
CONVERTER
Control
±
+
BAT
IINDPM
+
±
SW
Q3_OCP_BOOST
+
+
IIN
HSFET (Q2)
IQ3
VINDPM
REGN
BATOVP
104% × V BAT_REG
IC TJ
LSFET (Q3)
±
+
TREG
+
±
SYS
±
±
+
+
VSYSMIN
±
BAT
ILSFET_UCP
VBAT_REG
PGND
IQ2
+
UCP
Q2_OCP
+
IHSFET_OCP
IQ3
±
ICHG
±
EN_HIZ
EN_CHARGE
EN_BOOST
ICHG_REG
VBTST - VSW
REFRESH
+
VBTST_REFRESH
±
SYS
ICHG
VBAT_REG
ICHG_REG
Q4 Gate
Control
BATFET
(Q4)
BAT
IBADSRC
REF
DAC
ILIM
ICHG
BAD_SRC
Converter
Control State
Machine
IDC
±
IC TJ
TSHUT
±
BAT_GD
'Å
+
TSHUT
VSET
D+
+
Input
Source
Detection
BAT
+
VBATGD
±
USB
Adapter
VREG -VRECHG
RECHRG
OTG
+
BAT
±
ICHG
TERMINATION
+
ITERM
STAT
CHARGE
CONTROL
STATE
MACHINE
±
VBATLOWV
BATLOWV
+
BAT
bq25606
±
VSHORT
BATSHORT
+
SUSPEND
±
BAT
/PG
Battery
Sensing
Thermistor
TS
/CE
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8.3 Feature Description
8.3.1 Device Power Up from Battery without Input Source
If only battery is present and the voltage is above depletion threshold (VBAT_DPL_RISE), the BATFET turns on and
connects battery to system. The REGN stays off to minimize the quiescent current. The low RDSON of BATFET
and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
The device always monitors the discharge current through BATFET (Supplement Mode). When the system is
overloaded or shorted (IBAT > IBATFET_OCP), the device turns off BATFET immediately until the input source plugs
in again.
8.3.2 Power Up from Input Source
When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the
bias circuits. It detects and sets the input current limit before the buck converter is started. The power up
sequence from input source is as listed:
1. Power Up OVPFET
2. Power Up REGN LDO
3. Poor Source Qualification
4. IInput Source Type Detection is based on D+/D– to set input current limit (IINDPM) .
5. Input Voltage Limit Threshold Setting (VINDPM threshold)
6. Converter Power-up
8.3.2.1 Power Up OVPFET
The external OVPFET provides an additional layer of voltage protection for the device. The external OVPFET is
enabled when all the below conditions are valid.
• VAC above VVAC_PRESENT
• VAC below VBAT + VSLEEP in boost mode
• VAC below VVAC_OV
• After tDEB (15ms nom.) delay is completed
If one of the above conditions is not valid, the device is in high impedance state (HIZ) with REGN LDO off. The
device draws less current (IVBUS_HIZ) from VBUS during a HIZ state. The battery powers the system when the
device is in a HIZ state.
As shown in Figure 11, VVAC_PRESENT(rising) < VVAC < VVAC_OV(rising) must be valid before ACDRV goes high.
VVAC_OV (rising)
VVAC_PRESENT (rising)
VAC
tON_VBUS
tDEB
ACDRV
VBUS
90%
10%
90%
10%
Time
Figure 11. OVPFET Startup Control
16
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Feature Description (continued)
8.3.2.2 Power Up REGN Regulation
The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The REGN also
provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The
REGN is enabled when all the below conditions are valid:
• VVAC above VVAC_PRESENT
• VVAC above VBAT + VSLEEPZ in buck mode or VBUS below VBAT + VSLEEP in boost mode
• After 220-ms delay is completed
If any one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off.
The device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when
the device is in HIZ.
8.3.2.3 Poor Source Qualification
After REGN LDO powers up, the device confirms the current capability of the input source. The input source
must meet both of the following requirements in order to start the buck converter.
• VAC voltage below VVAC_OV
• VBUS voltage above VVBUSMIN when pulling IBADSRC (typical 30 mA)
If the device fails the poor source detection, it repeats poor source qualification every 2 seconds.
8.3.2.4 Input Source Type Detection
After the REGN LDO is powered, the device runs input source detection through D+/D– lines. The bq25606
follows the USB Battery Charging Specification 1.2 (BC1.2) to detect input source (SDP/ DCP) and non-standard
adapter through USB D+/D– lines. The bq25606 sets input current limit through D+/D- detection and ILIM pins.
8.3.2.4.1 D+/D– detection sets input current limit in limit.bq25606
The bq25606 contains a D+/D– based input source detection to set the input current limit at VBUS plug-in. The
D+/D– detection includes standard USB BC1.2 and non-standard adapter. When input source is plugged in, the
device starts standard USB BC1.2 detections. The USB BC1.2 is capable to identify Standard Downstream Port
(SDP) and Dedicated Charging Port (DCP). When the Data Contact Detection (DCD) timer expires, the nonstandard adapter detection is applied to set the input current input current limit. The non-standard detection is
used to distinguish vendor specific adapters (Apple and Samsung) based on their unique dividers on the D+/D–
pins. If an adapter is detected as DCP, the input current limit is 2.4 A. If an adapter is detected as unknown, the
input current limit is set by ILIM pin.
Table 1. Non-Standard Adapter Detection
Non-Standard
Adapter
D+ Threshold
D– Threshold
Input Current Limit (A)
Divider 1
VD+ within V2P7_VTH
VD– within V2P0_VTH
2.1
Divider 2
VD+ within V1P2_VTH
VD– within V1P2_VTH
2
Divider 3
VD+ within V2P0_VTH
VD– within V2P7_VTH
1
Divider 4
VD+ within V2P7_VTH
VD– within V2P7_VTH
2.4
Table 2. Input Current Limit Setting from D+/D– Detection
D+/D– Detection
Input Current Limit (IINLIM)
USB SDP (USB500)
500 mA
USB DCP
2.4 A
Divider 3
1A
Divider 1
2.1 A
Divider 4
2.4 A
Divider 2
2A
Unknown 5-V Adapter
Set by ILIM pin
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8.3.2.5 Input Voltage Limit Threshold Setting (VINDPM Threshold)
The device's VINDPM is set at 4.3V. The device supports dynamic VINDPM tracking which tracks the battery
voltage. The device's VINDPM tracks battery voltage with 200mV offset such that when VBAT + 200mV is
greater than 4.3V, the VINDPM value is automatically adjusted to VBAT + 200mV.
8.3.2.6 Converter Power-Up
After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery
charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.
The device provides soft-start when system rail is ramped up. When the system rail is below 2.2 V, the input
current is limited to is to 200 mA. After the system rises above 2.2 V, the device limits input current to the value
set by ILIM pin.
As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed
frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery
voltage, charge current and temperature, simplifying output filter design.
The device switches to PFM control at light load or when battery is below minimum system voltage setting or
charging is disabled.
8.3.3 Boost Mode Operation From Battery
The device supports boost converter operation to deliver power from the battery to other portable devices
through USB port. The maximum output current is up to 1.2 A. The boost operation can be enabled if the
conditions are valid:
1. BAT above VOTG_BAT
2. VBUS less than BAT+VSLEEP (in sleep mode)
3. Boost mode operation is enabled (OTG pin HIGH)
4. Voltage at TS (thermistor) pin is within acceptable range (VBHOT < VTS < VBCOLD)
5. After 30-ms delay from boost mode enable
During boost mode, the VBUS output is 5.15 V and the output current can reach up to 1.2 A. The boost output is
maintained when BAT is above VOTG_BAT threshold.
When OTG is enabled, the device starts up with PFM and later transits to PWM to minimize the overshoot.
8.3.4 Standalone Power Management
8.3.5 Power Path Management
The device accommodates a wide range of input sources from USB, wall adapter, to car charger. The device
provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or
both.
8.3.6 Battery Charging Management
The device charges 1-cell Li-Ion battery with up to 3.0-A charge current for high capacity tablet battery. The 19.5mΩ BATFET improves charging efficiency and minimize the voltage drop during discharging.
8.3.6.1 Autonomous Charging Cycle
With battery charging is enabled (CE pin is LOW), the device autonomously completes a charging cycle. The
device default charging parameters are listed in Table 3.
Table 3. Charging Parameter Default Setting
18
Default Mode
bq25606
Charging voltage
VSET controlled
Charging current
ICHG controlled
Pre-charge current
5% of ICHG
Termination current
5% of ICHG
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Table 3. Charging Parameter Default
Setting (continued)
A
•
•
•
•
Default Mode
bq25606
Temperature profile
JEITA
Safety timer
10 hours
new charge cycle starts when the following conditions are valid:
Converter starts
Battery charging is enabled (CE is low)
No thermistor fault on TS
No safety timer fault
The charger device automatically terminates the charging cycle when the charging current is below termination
threshold, battery voltage is above recharge threshold, and device not is in DPM mode or thermal regulation.
When a fully charged battery is discharged below recharge threshold , the device automatically starts a new
charging cycle. After the charge is done, toggle CE pin can initiate a new charging cycle.
The STAT output indicates the charging status: charging (LOW), charging complete or charge disable (HIGH) or
charging fault (Blinking).
8.3.6.2 Charging Termination
The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is
below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps
running to power the system, and BATFET can turn on again to engage Supplement Mode.
8.3.6.3 Thermistor Qualification
The charger device provides a single thermistor input for battery temperature monitor.
8.3.6.4 JEITA Guideline Compliance During Charging Mode
To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline
emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high
temperature ranges.
To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds
the T1-T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5
range.
At cool temperature (T1-T2), the charge current is reduced to 20% of programmed fast charge current. At warm
temperature (T3-T5), the charge voltage is reduced to 4.1 V.
1The charger provides flexible voltage/current settings beyond the JEITA requirement. The voltage setting at
warm temperature (T3-T5) can be VREG or 4.1V (configured by JEITA_VSET). The current setting at cool
temperature (T1-T2) can be further reduced to 20% of fast charge current (JEITA_ISET).
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100
VBATREG
4.1
4
90
Charging Voltage (V)
Charging Current (%)
80
70
60
50
40
30
3
2
1
20
10
0
0
T2
T1
±5
0
5
T3
10 15 20 25 30
35 40 45 50
T2
T1
T5
55 60 65
70
±5
0
5
T3
10 15 20 25 30
35 40 45 50
T5
55 60 65
70
Battery Pack Temperature (°C)
Battery Pack Temperature (°C)
Figure 12. JEITA Profile: Charging Current
Figure 13. JEITA Profile: Charging Voltage
Equation 1 through Equation 2 describe updates to the resistor bias network.
1 ö
æ 1
VREGN ´ RTHCOLD ´ RTHHOT ´ ç
÷
VT1
VT5
è
ø
RT2 =
æ VREGN
ö
æ VREGN
ö
RTHHOT ´ ç
- 1÷ - RTHCOLD ´ ç
- 1÷
VT5
VT1
è
ø
è
ø
æ æ VREGN ö
ö
çç
÷ - 1÷
VT1
ø
èè
ø
RT1 =
æ
ö
1
1
æ
ö
÷
ç RT2 ÷ + ç RTH
è
ø è
COLD ø
(1)
(2)
Select 0°C to 60°C range for Li-ion or Li-polymer battery:
• RTHCOLD = 27.28 KΩ
• RTHHOT = 3.02 KΩ
• RT1 = 5.23 KΩ
• RT2 = 30.9 KΩ
8.3.6.5 Boost Mode Thermistor Monitor during Battery Discharge Mode
For battery protection during boost mode, the device monitors the battery temperature to be within the VBCOLD
to VBHOTthresholds. When temperature is outside of the temperature thresholds, the boost mode is suspended.
Temperature Range to Boost
VREGN
Boost Disabled
VBCOLD
(±10°C)
Boost Enabled
VBHOT
(65°C)
Boost Disabled
AGND
Figure 14. TS Pin Thermistor Sense Threshold in Boost Mode
20
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8.3.6.6 Charging Safety Timer
The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The
safety timer is 2 hours when the battery is below VBATLOWV threshold and 10 hours when the battery is higher
than VBATLOWV threshold.
During input voltage, current, JEITA cool or thermal regulation, the safety timer counts at half clock rate as the
actual charge current is likely to be below the register setting. For example, if the charger is in input current
regulation throughout the whole charging cycle, the safety timer will expire in 20 hours.
During the fault, timer is suspended. Once the fault goes away, fault resumes. If user stops the current charging
cycle, and start again, timer gets reset.
8.3.6.7 Narrow VDC Architecture
The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The
minimum system voltage is set by SYS_Min bits. Even with a fully depleted battery, the system is regulated
above the minimum system voltage.
When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),
and the system is typically 180 mV above the minimum system voltage setting. As the battery voltage rises
above the minimum system voltage, BATFET is fully on and the voltage difference between the system and
battery is the VDS of BATFET.
When the battery charging is disabled and above minimum system voltage setting or charging is terminated, the
system is always regulated at typically 50mV above battery voltage..
4.5
4.3
Charge Disabled
Charge Enabled
Minimum System Voltage
SYS (V)
4.1
3.9
3.7
3.5
3.3
3.1
2.7
2.9
3.1
3.3
3.5
3.7
BAT (V)
3.9
4.1
4.3
D002
Plot1
Figure 15. System Voltage vs Battery Voltage
8.3.6.8 Dynamic Power management
To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic
Power management (DPM), which continuously monitors the input current and input voltage. When input source
is over-loaded, either the current exceeds the input current limit (IIDPM) or the voltage falls below the input
voltage limit (VINDPM). The device then reduces the charge current until the input current falls below the input
current limit and the input voltage rises above the input voltage limit.
When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to
drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement
mode where the BATFET turns on and battery starts discharging so that the system is supported from both the
input source and battery.
Figure 16 shows the DPM response with 9-V/1.2-A adapter, 3.2-V battery, 2.8-A charge current and 3.5-V
minimum system voltage setting.
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Voltage
VBUS
9V
SYS
3.6V
3.4V
3.2V
3.18V
BAT
Current
4A
ICHG
3.2A
2.8A
ISYS
1.2A
1.0A
0.5A
IIN
-0.6A
DPM
DPM
Supplement
Figure 16. DPM Response
8.3.6.9 Supplement Mode
When the system voltage falls 180 mV (VBAT > VSYSMin) or 45 mV (VBAT < VSYSMin) below the battery
voltage, the BATFET turns on and the BATFET gate is regulated the gate drive of BATFET so that the minimum
BATFET VDS stays at 30 mV when the current is low. This prevents oscillation from entering and exiting the
supplement mode.
As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until
the BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge
current. Figure 17 shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit
supplement mode when the battery is below battery depletion threshold.
4.5
4
3.5
Current (A)
3
2.5
2
1.5
1
0.5
0
0
5
10
15
20 25 30 35
V(BAT-SYS) (mV)
40
45
50
55
D001
Plot1
Figure 17. BAFET V-I Curve
8.3.7 Status Outputs (PG, STAT)
8.3.7.1 Power Good indicator (PG Pin)
The PG pin goes LOW to indicate a good input source when:
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•
•
•
•
•
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VBUS above VVBUS_UVLO
VBUS above battery (not in sleep)
VBUS below VVAC_OV threshold
VBUS above VVBUSMin (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
Completed input Source Type Detection
8.3.7.2 Charging Status indicator (STAT)
The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED.
Table 4. STAT Pin State
CHARGING STATE
STAT INDICATOR
Charging in progress (including recharge)
LOW
Charging complete
HIGH
Sleep mode, charge disable
HIGH
Charge suspend (input overvoltage, TS fault, timer fault or system overvoltage)
Boost Mode suspend (due to TS fault)
Blinking at 1 Hz
8.3.8 Protections
8.3.8.1 Input Current Limit
The device's ILIM pin is to program maximum input current when D+/D- detection identifies an unknown adaptor
plugged in. The maximum input current is set by a resistor from ILIM pin to ground as:
K
IINMAX = ILIM
RILIM
(3)
8.3.8.2 Voltage and Current Monitoring in Converter Operation
The device closely monitors the input and system voltage, as well as internal FET currents for safe buck and
boost mode operation.
8.3.8.2.1 Voltage and Current Monitoring in Buck Mode
8.3.8.2.1.1 Input Overvoltage (ACOV)
If VAC exceeds VVAC_OV , the OVPFET turns off in 200ns to protect VBUS. In the meantiem, HSFET stops
switching immediately.
8.3.8.2.1.2 System Overvoltage Protection (SYSOVP)
The charger device clamps the system voltage during load transient so that the components connect to system
would not be damaged due to high voltage. SYSOVP threshold is 350 mV above minimum system regulation
voltage when the system is regulate at VSYSMIN. Upon SYSOVP, converter stops switching immediately to clamp
the overshoot. The charger provides 30 mA discharge current to bring down the system voltage.
8.3.8.3 Voltage and Current Monitoring in Boost Mode
The device closely monitors the VBUS voltage, as well as RBFET and LSFET current to ensure safe boost mode
operation.
8.3.8.3.1 VBUS Soft Start
When the boost function is enabled, the device soft-starts boost mode to avoid inrush current.
8.3.8.3.2 VBUS Output Protection
The device monitors boost output voltage and other conditions to provide output short circuit and overvoltage
protection. The Boost build in accurate constant current regulation to allow OTG to adaptive to various types of
load. If short circuit is detected on VBUS, the Boost turns off and retry 7 times. If retries are not successful, OTG
is disabled.
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8.3.8.3.3 Boost Mode Overvoltage Protection
When the VBUS voltage rises above regulation target and exceeds VOTG_OVP, the device stop switching.
8.3.8.4 Thermal Regulation and Thermal Shutdown
8.3.8.4.1 Thermal Protection in Buck Mode
The bq25606 monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface
temperature in buck mode. When the internal junction temperature exceeds thermal regulation limit (110°C), the
device lowers down the charge current. During thermal regulation, the actual charging current is usually below
the programmed battery charging current. Therefore, termination is disabled, the safety timer runs at half the
clock rate.
8.3.8.4.2 Thermal Protection in Boost Mode
The device monitors the internal junction temperature to provide thermal shutdown during boost mode. When IC
junction temperature exceeds TSHUT (160ºC), the boost mode is disabled and BATFET is turned off. When IC
junction temperature is below TSHUT(160ºC) - TSHUT_HYS (30ºC), the BATFET is enabled automatically to allow
system to restore .
8.3.8.5 Battery Protection
8.3.8.5.1 Battery overvoltage Protection (BATOVP)
The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage
occurs, the charger device immediately disables charging.
8.3.8.5.2 Battery Over-Discharge Protection
When battery is discharged below VBAT_DPL_FALL, the BATFET is turned off to protect battery from over discharge.
To recover from over-discharge latch-off, an input source plug-in is required at VBUS. The battery is charged
with ISHORT (typically 100 mA) current when the VBAT < VSHORT, or precharge current as set by 5% of ICHG
when the battery voltage is between VSHORTZ and VBAT_LOWV.
8.3.8.5.3 System Over-Current Protection
When the system is shorted or significantly overloaded (IBAT > IBATOP) and the current exceeds BATFET
overcurrent limit, the BATFET latches off. The BATFET latch can be reset with VBUS plug-in.
9 Application and Implementation
NOTE
information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application information
A typical application consists of the device configured as a stand-alone power path management device and a
single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of smart phones and other
portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2),
low-side switching FET (LSFET, Q3), and battery FET (BATFET Q4) between the system and battery. The
device also integrates a bootstrap diode for the high-side gate drive.
External OVPFET is optional. When external OVP is not used, short the VBUS and VAC pins and allow ACDRV
pin to float (as shown in Figure 19)
24
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9.2 Typical Application Diagram
Input:
3.9 V to 13.5 V
OVPFET
1 H
VBUS
System:
3.5 V to 4.6 V
SW
1 F
10 F
47 nF
PMID
BTST
REGN
10 F
Opt.
ACDRV
4.7 µF
GND
VAC
SYS
SYS
SYS
2.2 k
/PG
2.2 k
STAT
Host
bq25606
BAT
10 F
OTG
450
REGN
ICHG
5.23 k
/CE
TS
+
30.1 k
10 k
D+
USB
D-
ILIM
240
VSET
Float: VREG = 4.208 V
Short : VREG = 4.352 V
RPD = 10 NŸ 95(* = 4.400 V
RPD
Figure 18. bq25606 Application With OVPFET
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Typical Application Diagram (continued)
Input
3.9 V to 13.5 V
1 H
VBUS
System
3.5 V to 4.6 V
SW
1 F
10 F
47 nF
PMID
BTST
REGN
10 F
ACDRV
4.7 µF
GND
VAC
SYS
SYS
SYS
2.2 k
/PG
2.2 k
STAT
Host
bq25606
BAT
10 F
OTG
450
REGN
ICHG
5.23 k
/CE
TS
+
30.1 k
10 k
D+
USB
D-
ILIM
240
Float: VREG = 4.208 V
Short : VREG = 4.352 V
RPD=10 NŸ: VREG = 4.400 V
VSET
RPD
Figure 19. bq25606 Application Without OVPFET
9.2.1 Design Requirements
9.2.2 Detailed Design Procedure
9.2.2.1 inductor Selection
The 1.5-MHz switching frequency allows the use of small inductor and capacitor values to maintain an inductor
saturation current higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
ISAT ≥ ICHG + (1/2) IRIPPLE
(4)
The inductor ripple current depends on the input voltage (VVBUS), the duty cycle (D = VBAT/VVBUS), the switching
frequency (fS) and the inductance (L).
V ´ D ´ (1 - D)
IRIPPLE = IN
fs ´ L
(5)
The maximum inductor ripple current occurs when the duty cycle (D) is 0.5 or approximately 0.5. Usually inductor
ripple is designed in the range between 20% and 40% maximum charging current as a trade-off between
inductor size and efficiency for a practical design.
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Typical Application Diagram (continued)
9.2.2.2 input Capacitor
Design input capacitance to provide enough ripple current rating to absorb input switching ripple current. The
worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not
operate at 50% duty cycle, then the worst case capacitor RMS current ICin occurs where the duty cycle is closest
to 50% and can be estimated using Equation 6.
ICIN = ICHG ´ D ´ (1 - D)
(6)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed to the drain of the high-side MOSFET and source of the low-side MOSFET as close as possible. Voltage
rating of the capacitor must be higher than normal input voltage level. A rating of 25-V or higher capacitor is
preferred for 15 V input voltage. Capacitance of 22-μF is suggested for typical of 3A charging current.
9.2.2.3 Output Capacitor
Ensure that the output capacitance has enough ripple current rating to absorb the output switching ripple current.
Equation 7 shows the output capacitor RMS current ICOUT calculation.
I
ICOUT = RIPPLE » 0.29 ´ IRIPPLE
2´ 3
(7)
The output capacitor voltage ripple can be calculated as follows:
æ
ö
V
V
DVO = OUT2 ç 1 - OUT ÷
VIN ø
8LCfs è
(8)
At certain input and output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC.
The charger device has internal loop compensation optimized for >20μF ceramic output capacitance. The
preferred ceramic capacitor is 10V rating, X7R or X5R.
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9.3 Application Curves
VVBUS = 5 V
VVBAT = 3.2 V
VVBUS = 5 V
ICHG = 2 A
Figure 20. Power-Up with Charge Disabled
VVBUS = 5 V
ISYS = 50 mA
Figure 21. Power-Up with Charge Enabled
VVBUS = 9 V
ISYS = 50 mA
Charge Disabled
Figure 22. PFM Switching in Buck Mode
28
VVBAT = 3.2 V
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Charge Disabled
Figure 23. PFM Switching in Buck Mode
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Application Curves (continued)
VVBUS = 12 V
ISYS = 50 mA
VVBUS = 5 V
ICHG = 2 A
Charge Disabled
Figure 25. PWM Switching in Buck Mode
Figure 24. PFM Switching in Buck Mode
VVBUS = 12 V
ICHG = 2 A
VVBAT = 3.8 V
VVBAT = 3.8 V
VVBUS = 5 V
ICHG = 2 A
Figure 26. PWM Switching in Buck mode
VVBAT = 3.2 V
Figure 27. Charge Enable
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Application Curves (continued)
VVBUS = 5 V
ICHG = 2 A
VVBAT = 3.2 V
Figure 28. Charge Disable
VVBAT = 4 V
ILOAD= 50 mA
PFM Enabled
Figure 29. OTG Switching
VVBAT = 4 V
ILOAD= 1 A
PFM Enabled
VVBUS = 5 V
ISYS from 0 A to 2 A
VBAT = 3.7 V
Figure 30. OTG Switching
30
IINDPM = 1 A
ICHG = 1 A
Figure 31. System Load Transient
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Application Curves (continued)
VVBUS = 5 V
ISYS from 0 A to 4 A
VBAT = 3.7 V
IINDPM = 2 A
ICHG = 1 A
VVBUS = 5 V
ISYS from 0 A to 2 A
VBAT = 3.7 V
Figure 32. System Load Transient
VVBUS = 5 V
ISYS from 0 A to 4 A
VBAT = 3.7 V
IINDPM = 1 A
ICHG = 2 A
IINDPM = 1 A
ICHG = 2 A
Figure 33. System Load Transient
VVBUS = 5 V
ISYS from 0 A to 2 A
VBAT = 3.7 V
Figure 34. System Load Transient
IINDPM = 2 A
ICHG = 2 A
Figure 35. System Load Transient
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Application Curves (continued)
VVBUS = 5 V
ISYS from 0 A to 4 A
VBAT = 3.7 V
IINDPM = 2 A
ICHG = 2 A
VBAT = 3.8 V
CLOAD = 470 µF
Figure 37. OTG Start-Up
Figure 36. System Load Transient
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10 Power Supply Recommendations
in order to provide an output voltage on SYS, the bq25606 device requires a power supply between 3.9 V and
14.2 V input with at least 100-mA current rating connected to VBUS and a single-cell Li-Ion battery with voltage >
VBATUVLO connected to BAT. The source current rating needs to be at least 3 A in order for the buck converter of
the charger to provide maximum output power to SYS.
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11 Layout
11.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 38) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Follow this specific order carefully to achieve the
proper layout.
1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper
trace connection or GND plane.
2. Place inductor input pin to SW pin as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not
use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other
trace or plane.
3. Put output capacitor near to the inductor and the device. Ground connections need to be tied to the IC
ground with a short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together using thermal pad as the single ground
connection point. Or using a 0-Ω resistor to tie analog ground to power ground.
5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the
device. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
6. Place decoupling capacitors next to the IC pins and make trace connection as short as possible.
7. It is critical that the exposed thermal pad on the backside of the device package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on
the other layers.
8. Ensure that the number and sizes of vias allow enough copper for a given current path.
See the EVM user's guide SLUUBL3 for the recommended component placement with trace and via locations.
For the VQFN information, refer to SCBA017 and SLUA271.
11.2 Layout Example
+
+
±
Figure 38. High Frequency Current Path
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Layout Example (continued)
Figure 39. Layout Example
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
36
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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12-May-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ25606RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ25606
BQ25606RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ25606
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
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(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
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(5)
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(6)
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Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-May-2017
Addendum-Page 2
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