ISO150 ISO 15 0 www.ti.com .......................................................................................................................................... SBOS032D – SEPTEMBER 2000 – REVISED AUGUST 2008 DUAL, ISOLATED, BIDIRECTIONAL DIGITAL COUPLER FEATURES 1 • • • • • • • • • Replaces High-Performance Optocouplers Data Rate: 80 M Baud, Typ Low Power Consumption: 25 mW Per Channel, Max Two Channels, Each Bidirectional, Programmable by User Partial Discharge Tested: 2400 Vrms Creepage Distance of 7,2 mm Low Cost Per Channel Available in SO Package UL 1577 Certified APPLICATIONS • • • • • • • • Digital Isolation for A/D, D/A Conversion Isolated RS-485 Interface Multiplexed Data Transmission Isolated Parallel to Serial Interface Test Equipment Microprocessor System Interface Isolated Line Receiver Ground Loop Elimination DESCRIPTION The ISO150 is a 2-channel, galvanically-isolated data coupler capable of data rates of 80M Baud, typical. Each channel can be individually programmed to transmit data in either direction. Data is transmitted across the isolation barrier by coupling complementary pulses through high voltage 0.4 pF capacitors. Receiver circuitry restores the pulses to standard logic levels. Differential signal transmission rejects isolation-mode voltage transients up to 1.6 kV/µs The ISO150 avoids problems commonly associated with optocouplers. Optically isolated couplers require high current pulses and allowance must be made for LED aging. The ISO150's Bi-CMOS circuitry operates at 25 mW per channel. The ISO150 is available in an SO-28 and is specified for operation from –40°C to 85°C. 28 27 26 17 16 15 D2A R/T2A GA VSB R/T2B D2B Channel 2 Side A Side B Channel 1 D1A R/T1A VSA GB R/T1B D1B 1 2 3 12 13 14 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2008, Texas Instruments Incorporated ISO150 SBOS032D – SEPTEMBER 2000 – REVISED AUGUST 2008 .......................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) PRODUCT PACKAGE LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ISO150AU SO-28 DVB –40°C to 85°C ISO150AU TRANSPORT MEDIA, QUANTITY ORDERING NUMBER ISO150AU Rails, 28 ISO150AU/1K Tape and Reel, 1000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) UNIT Storage temperature –40°C to 125°C VS Supply voltage VI Transmitter input voltage –0.5 V to VS + 0.5 V –0.5 V to 6 V VO Receiver output voltage –0.5 V to VS + 0.5 V R/Tx inputs –0.5 V to VS + 0.5 V VISO Isolation voltage dV/dt 500 kV/µs Dx Short to ground Continuous TJ Junction temperature 125°C Lead temperature (soldering, 10s) 260°C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. This isolator is suitable for basic insulation applications within the safety limiting data. Maintenance of the safety data must be ensured by means of protective circuitry. REGULATORY INFORMATION UL Recognized under 1577 Component Recognition Program (1) File Number: E181974 (1) 2 Production tested at 2400 VRMS for 1 second in accordance with UL 1577. Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): ISO150 ISO150 www.ti.com .......................................................................................................................................... SBOS032D – SEPTEMBER 2000 – REVISED AUGUST 2008 ELECTRICAL CHARACTERISTICS At TA = 25°C and VS = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS ISO150AU MIN TYP MAX UNIT ISOLATION PARAMETERS Rated Voltage, Continuous 60 Hz 1500 Partial Discharge, 100% Test (1) 1s, 5pC 2400 Creepage distance (external) SO-U Package Vrms Vrms 7.2 Internal isolation distance Isolation voltage transient immunity (2) Barrier impedance Leakage current 240 Vrms, 50 Hz mm 0.10 mm 1.6 kV/µs >1014 || 7 Ω || pF 0.6 µArms DC PARAMETERS Logic output voltage HIGH, VOH IOH = 6 mA VS –1 VS LOW, VOL IOL = 6 mA 0 0.4 Logic output short-circuit current Logic input voltage Source or sink 30 mA HIGH (3) 2 VS LOW (3) 0 0.8 Logic input capacitance Logic input current Power-supply voltage range (3) 3 DC Transmit mode Power-supply current (4) Receive mode V V 5 pF <1 nA 5 5.5 0.001 100 50M Baud 14 DC 7.2 50M Baud 16 V µA mA 10 mA AC PARAMETERS Data rate Maximum (5) CL = 50 pF Minimum 50 80 M Baud DC Propagation time (6) CL = 50 pF 27 40 ns Propagation delay skew (7) CL = 50 pF 0.5 2 ns Pulse width distortion (8) CL = 50 pF 1.5 6 ns 9 14 ns Output rise-and-fall time, 10% to 90% Mode switch time CL = 50 pF Receive to Transmit 13 ns Transmit to receive (9) 75 ns TEMPERATURE RANGE Operating range –40 85 Storage –40 125 Thermal resistance, θJA (1) (2) (3) (4) (5) (6) (7) (8) (9) 75 °C °C °C/W All devices receive a 1s test. Failure criterion is ≥ 5 PULSES OF ≥5 Pc. The voltage rate-of-change across the isolation barrier that can be sustained without data errors. Logic inputs are HCT-type and thresholds are a function of power-supply voltage with approximately 0.4 V hysteresis – see text. Supply current measured with both transceivers set for the indicated mode. Supply current varies with data rate – see typical characteristics. Calculated from the maximum pulse width distortion (PWD), where Data Rate = 0.3/PWD. Propagation time measured from VIN = 1.5 V to VO = 2.5 V. The difference in propagation time of channel A and channel B in any combination of transmission directions. The difference between propagation time of a rising edge and a falling edge. When the device is powered up or direction is changed, the transceiver output is indeterminate (either high or low) and cannot be known until an input signal is applied. The output begins to track the input as soon as the input receives a change in logic state, either low to high or high to low. Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): ISO150 3 ISO150 SBOS032D – SEPTEMBER 2000 – REVISED AUGUST 2008 .......................................................................................................................................... www.ti.com PIN CONFIGURATION Top View SO D1A 1 28 D2A R/T1A 2 27 R/T2A VSA 3 26 GA GB 12 17 VSB R/T1B 13 16 R/T2B D1B 14 15 D2B TERMINAL FUNCTIONS TERMINAL NAME DESCRIPTION NO. D1A 1 Data in or data out for transceiver 1A, R/T1A held low makes D1A and input pin. R/T1A 2 Receive/transmit switch controlling transceiver 1A. VSA 3 +5V supply pin for side A, which powers transceivers 1A and 2A. GB 12 Ground pin for transceivers 1B and 2B. R/T1B 13 Receive/transmit switch controlling transceiver 1B. D1B 14 Data in or data out for transceiver 1B. R/T1B held LOW makes D1B an input pin. D2B 15 Data in or data out for transceiver 2B. R/T2B held LOW makes D2B an input pin. R/T2B 16 Receive/transmit switch controlling D2B. VSB 17 +5V supply pin for side B, which powers transceivers 1B and 2B. GA 26 Ground pin for transceivers 1A and 2A. R/T2A 27 Receive/transmit switch controlling transceiver 2A. D2A 28 Data in or data out for transceiver 2A, R/T21A held low makes D2A an input pin. 4 Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): ISO150 ISO150 www.ti.com .......................................................................................................................................... SBOS032D – SEPTEMBER 2000 – REVISED AUGUST 2008 TYPICAL CHARACTERISTICS At TA = 25°C and VS = 5 V, unless otherwise noted. SUPPLY CURRENT PER CHANNEL vs SUPPLY VOLTAGE POWER CONSUMPTION PER CHANNEL vs FREQUENCY 5 100 20 C L = 15pF 3 Receive Mode 2 80 16 60 12 NOTE: Baud Rate = 2 S Frequency 40 8 Receive Transmit 20 1 Supply Current (mA) f = 1MHz = 2MBaud Power (mW) Supply Current (mA) 4 No Load One Channel 4 Transmit Mode 0 0 0 12345 100k 6 1M 100M Frequency (Hz) Supply Voltage, V S (V) Figure 1. Figure 2. SUPPLY CURRENT PER CHANNEL vs TEMPERATURE TYPICAL RISE AND FALL TIMES vs CAPACITIVE LOAD vs SUPPLY VOLTAGE 6 100 tr tf 80 5 V S = 5.0V 4 tr, t f (ns) Supply Current (mA) 10M 3 V S = 3.0V 2 tr tf 60 V S = 3.0V 40 V S = 5.0V 20 1 0 –60 –40 –20 0 20 40 60 80 100 120 0 140 100 Temperature (5C) 200 300 400 500 Capacitive Load (pF) Figure 3. Figure 4. NORMALIZED RISE-AND-FALL TIME vs TEMPERATURE PROPAGATION DELAY vs SUPPLY VOLTAGE 45 1.6 1.5 40 C L = 50pF Propagation Delay (ns) Relative t r, t f 1.4 +1σ 1.3 1.2 1.1 Normalized to Average of Many Devices at 25° C 1.0 HIGH to LOW 35 30 LOW to HIGH 25 –1σ .9 –60 Pulse Width Distortion 20 –40 –20 0 20 40 60 80 Temperature (5C) 100 120 140 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Supply Voltage, V S (V) Figure 5. Figure 6. Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): ISO150 5 ISO150 SBOS032D – SEPTEMBER 2000 – REVISED AUGUST 2008 .......................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = 25°C and VS = 5 V, unless otherwise noted. PROPAGATION DELAY vs TEMPERATURE PULSE WIDTH DISTORTION vs TEMPERATURE 5 60 V S = 3.0V 40 30 V S = 5.0V 20 10 0 –60 –40 –20 0 20 40 VS = 5.0 V CL = 50 pF Pulse Width Distortion, PWD (ns) Propagation Delay, tPD (ns) C L = 50pF 50 60 80 100 120 4 3 2 1 0 –60 140 –40 –20 0 Temperature (5C) 20 40 60 80 100 120 140 Temperature (5C) Figure 7. Figure 8. LOGIC INPUT THRESHOLD VOLTAGE vs SUPPLY VOLTAGE OUTPUT VOLTAGE vs LOGIC INPUT VOLTAGE 2.0 1.8 V T HIGH, 125°C 1.6 5 1.4 4 V OUT(V) V IN (V) 1.2 1.0 V T LOW, –40°C 0.8 3 2 0.6 0.4 1 0.2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 6.0 0.5 Supply Voltage, V SS(V) Figure 9. 1.5 2.0 Figure 10. ISOLATION LEAKAGE CURRENT vs FREQUENCY ISOLATION VOLTAGE vs FREQUENCY 2.1k 100m Max DC Rating Peak Isolation Voltage (V) 10m Leakage Current (Arms) 1.0 V IN (V) 1m V ISO= 1500Vrms 100m 10m V ISO= 240Vrms Degraded Performance 1k 100 10 1m 100n 1 10 100 1k 10 k 100 k 1M 1 1k Figure 11. 6 10 k 100 k 1M 10 M 100 M Frequency (Hz) Frequency (Hz) Figure 12. Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): ISO150 ISO150 www.ti.com .......................................................................................................................................... SBOS032D – SEPTEMBER 2000 – REVISED AUGUST 2008 TYPICAL CHARACTERISTICS (continued) At TA = 25°C and VS = 5 V, unless otherwise noted. TYPICAL INSULATION RESISTANCE vs TEMPERATURE 1016 Isolation Resistance ( Ω) 1015 1014 1013 1012 1011 1010 0 20 40 60 80 100 120 140 160 180 Temperature (5C) Figure 13. ISOLATION BARRIER Data is transmitted by coupling complementary logic pulses to the receiver through two 0.4 pF capacitors. These capacitors are built into the ISO150 package with Faraday shielding to guard against false triggering by external electrostatic fields. The integrity of the isolation barrier of the ISO150 is verified by partial discharge testing: 2400 Vrms, 60 Hz, is applied across the barrier for one second while measuring any tiny discharge currents that might flow through the barrier. These current pulses are produced by localized ionization within the barrier; this is the most sensitive and reliable indicator of barrier integrity and longevity, and does not damage the barrier. A device fails the test if five or more current pulses of 5pC or greater are detected. Conventional isolation barrier testing applies test voltage far in excess of the rated voltage to catastrophically break down a marginal device. A device that passes the test may be weakened, and lead to premature failure. Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): ISO150 7 ISO150 SBOS032D – SEPTEMBER 2000 – REVISED AUGUST 2008 .......................................................................................................................................... www.ti.com APPLICATION INFORMATION shown. The transmission direction can be controlled by logic signals applied to the R/T pins. Channel 1 and 2 can be independently controlled for the desired transmission direction. See Figure 15 and Figure 16 for application examples using the ISO150. Figure 14 shows the ISO150 connected for basic operation; Channel 1 is configured to transmit data from side B to A, whereas Channel 2 is set for transmission from side A to B. The R/T pins for each of the four transceivers are shown connected to the required logic level for the transmission direction +5V (1) (2) (Transmit) Channel 2 Data In (1) D2A Channel 2 Data Out (1) GA R/T2A (Receive) VSB R/T2B D2B Channel 2 Side A Side B NOTES: (1) Power Supplies and grounds on side A and side B are isolated. (2) Recommended bypass: 0.1 m F in parallel with 1nF. Channel 1 D1A R/T1A VSA GB R/T1B D1B (2) Channel 1 Data Out (1) (Receive) Channel 1 Data In (1) (Transmit) +5V (1) Figure 14. Basic Operation Diagram +5V DE SN65HVD05 +5V A BUS D Data (I/O) B D 2A R/T2A GA VSB R/T2B D2B Channel 2 R Side A RE Side B Channel 1 D 1A R/T1A VSA GB R/T1B D1B DE/RE +5V ”1” (+5V) Figure 15. Isolated RS-485 Interface 8 Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): ISO150 ISO150 www.ti.com .......................................................................................................................................... SBOS032D – SEPTEMBER 2000 – REVISED AUGUST 2008 LOGIC LEVELS A single pin serves as a data input or output, depending on the mode selected. Logic inputs are CMOS with thresholds set for TTL compatibility. The logic threshold is approximately 1.3 V with 5 V supplies with approximately 400 mV of hysteresis. Input logic thresholds vary with the power-supply voltage. Drive the logic inputs with signals that swing the full logic voltage swing, note that the ISO150 will use somewhat greater quiescent current if logic inputs do not swing within 0.5 V of the power-supply rails. In receive mode, the data output can drive 15 standard LS-TTL loads. It will also drive CMOS loads. The output drive circuits are CMOS. Still, some applications with large, noisy isolationmode voltage can produce data errors by causing the receiver output to change states. After a data error, subsequent changes in input data will produce correct output data. PROPAGATION DELAY AND SKEW Logic transitions are delayed approximately 27ns through the ISO150. Some applications are sensitive to data skew—the difference in propagation delay between channel 1 and channel 2. Skew is less than 2ns between channel 1 and channel 2. Applications using more than one ISO150 must allow for somewhat greater skew from device to device. As all devices are tested for delay times of 20ns min to 40ns max, 20ns is the largest device-to-device data skew. POWER SUPPLY Separate, isolated power supplies must be connected to side A and side B to provide galvanic isolation. Nominal rated supply voltage is 5 V. Operation extends from 3 V to 5.5 V. Power supplies should be bypassed close to the device pins on both sides of the isolation barrier. The VS pin for each side powers the transceivers for both channel 1 and 2. The specified supply current is the total of both transceivers on one side, both operating in the indicated mode. Supply current for one transceiver in transmit mode and one in receive mode can be estimated by averaging the specifications for transmit and receive operation. Supply current varies with the data transmission rate — see the typical characteristics. POWER-UP STATE When the device is powered up or direction is changed, the transceiver output is indeterminate (either high or low) and cannot be known until an input signal is applied. The output begins to track the input as soon as the input receives a change in logic state, either low to high or high to low. SIGNAL LOSS The ISO150's differential-mode signal transmission and careful receiver design make it highly immune to voltage across the isolation barrier (isolation-mode voltage). Rapidly changing isolation-mode voltage can cause data errors. As the rate of change of isolation voltage is increased, there is a very sudden increase in data errors. Approximately 50% of all ISO150s will begin to produce data errors with isolation-mode transients of 1.6kV/µs. This may occur as low as 500 V/µs in some devices. In comparison, a 1000 Vrms, 60 Hz isolation-mode voltage has a rate of change of approximately 0.5V/µs. MODE CHANGES The transmission direction of a channel can be changed on the fly by reversing the logic levels at the channel's R/T pin. Note that when channel direction is changed, the output state of the channel is indeterminate (either high or low) and cannot be known until an input signal is applied. The output begins to track the input as soon as the input receives a change in logic state, either low to high or high to low. STANDBY MODE Quiescent current of each transceiver circuit is very low in transmit mode when input data is not changing (1nA typical). To conserve power when data transmission is not required, program both side A and B transceivers for transmit mode. Input data applied to either transceiver is ignored by the other side. High-speed data applied to either transceiver will increase quiescent current. CIRCUIT LAYOUT The high speed of the ISO150 and its isolation barrier require careful circuit layout. Use good high speed logic layout techniques for the input and output data lines. Power supplies should be bypassed close to the device pins on both sides of the isolation barrier. Use low inductance connections. Ground planes are recommended. Maintain spacing between side 1 and side 2 circuitry equal or greater than the spacing between the missing pins of the ISO150 (approximately 7mm). Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): ISO150 9 10 VIN 50kΩ VCC1 Submit Documentation Feedback Product Folder Link(s): ISO150 1MΩ VCC1 = VCC2 = +5V Isolated Supplies 50kΩ 100Ω 200Ω 33.2Ω D0 17 EXT/INT 8 20 TAG 23 CS SCLK 18 SDATA 19 DGND 14 9 D7 D5 11 26 REFD D4 12 SB/BTC 7 D6 10 D3 13 D2 15 D1 16 AGND2 REF 6 5 BYTE 21 R/C 22 25 PWRD +2.2µF +2.2µF CAP BUSY 24 AGND1 2 4 VANA 27 VDIG 28 R2IN R1IN 3 1 ADS7807 100Ω 100Ω BYTE 100Ω 100Ω 100nF 100nF 6.8µ F 10µ F D1A R/T1A VSA D2A R/T2A GA D1A R/T1A VSA D2A R/T2A GA 1Ω 1Ω +5V VCC1 +5V VCC1 ISO150 +5V VCC1 ISO150 +5V +5V VCC2 +5V VCC2 GB R/T1B D1B VSB R/T2B D2B R/C GB R/T1B D1B VSB R/T2B D2B BUSY U2 QA 15 High Byte Enable QH 9 QH 7 QG 6 QF 5 QE 4 QD 3 QC 2 QB 1 74LS595 QH 9 QH 7 QF 5 QG 6 12 RCLK QE 4 QD 3 13 G 10 SRCLR QC 2 QB 1 QA 15 Low Byte Enable 11 SRCLK U3 14 SER VCC2 74LS595 13 G 12 RCLK 10 SRCLR 11 SRCLK 14 SER ISO150 SBOS032D – SEPTEMBER 2000 – REVISED AUGUST 2008 .......................................................................................................................................... www.ti.com Figure 16. The ISO150 and the ADS7807 are Used to Reduce Circuit Noise in a Mixed-Signal Application Copyright © 2000–2008, Texas Instruments Incorporated ISO150 www.ti.com .......................................................................................................................................... SBOS032D – SEPTEMBER 2000 – REVISED AUGUST 2008 Revision History Changes from Original (August 1994) to Revision A ..................................................................................................... Page • • • • • • • • Changed Features Bullet - From: Plastic DIP and SOIC Packages To: Available in SO Package....................................... Changed From: ISO150 is available in a 24-pin DIP package To: The ISO150 is available in an SO-28............................ Changed From Burr-Brown To: Burr-Brown Products from Texas Instruments (New layout)............................................... Deleted the DIP Package from the Ordering Information Table ............................................................................................ Deleted DIP-P Package from Creepage distance (external) in the Electrical Characteristics Table..................................... Deleted DIP-P Package illustration from the Pin Configuration............................................................................................. Changed Pin Configuration From: SOIC Package To: SO Package..................................................................................... Changed Circuit Layout paragraph From: ISO150 (approximately 16mm for the DIP version). Sockets are not recommended. To: ISO150 (approximately 7mm)................................................................................................................. 1 1 1 2 3 4 4 9 Changes from Revision A (February 2003) to Revision B ............................................................................................. Page • • Changed Format and layout. ................................................................................................................................................. 1 Added Note 9 to the Electrical Characteristics Table ............................................................................................................ 3 Changes from Revision B (February 2005) to Revision C ............................................................................................. Page • • Added Feature: UL 1577 Certified. ........................................................................................................................................ 1 Added Table: Regulatory Information. ................................................................................................................................... 2 Changes from Revision C (October 2007) to Revision D ............................................................................................... Page • Changed Abs Max Table - Junction Temperature From: 175°C to 125°C ............................................................................ 2 Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): ISO150 11 PACKAGE OPTION ADDENDUM www.ti.com 9-Aug-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty ISO150AP OBSOLETE PDIP NVG 12 ISO150AU LIFEBUY SOP DVB 12 ISO150AU-1 OBSOLETE SOIC DVA 8 ISO150AU/1K LIFEBUY SOP DVB 12 ISO150AUG4 LIFEBUY SOP DVB 12 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) TBD Call TI Call TI Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TBD Call TI Call TI 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 20 Op Temp (°C) Device Marking (4/5) -40 to 85 ISO150AU ISO150AU -40 to 85 ISO150AU (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Aug-2016 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device ISO150AU/1K Package Package Pins Type Drawing SOP DVB 12 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 10.9 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 18.3 3.2 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO150AU/1K SOP DVB 12 1000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MPDI068 – AUGUST 2001 NVG (R-PDIP-T12/24) PLASTIC DUAL-IN-LINE 1.195 (30,35) 1.160 (29,46) D 24 13 0.280 (7,11) D 0.240 (6,10) 0.655 (16,64) 0.630 (16,00) 1 Index Area 12 0.195 (4,95) 0.115 (2,92) 0.070 (1,78) H 0.045 (1,14) Base Plane 0.210 (5,33) MAX C 0.325 (8,26) 0.300 (7,62) E –C– Seating Plane E 0.005 (0,13) MIN 1/2 Lead 4 PL D 0.150 (3,81) 0.115 (2,92) C 0.100 (2,54) 0.022 (0,56) 0.045 (1,14) 4 PL 0.030 (0,76) H 0.015 (0,38) MIN C 0.014 (0,36) 0.010 (0,25) M C 0.300 (7,62) 0.014 (0,36) 0.008 (0,20) 0.060 (1,52) 0.000 (0,00) F 0.430 (10,92) MAX F 4202644/A 08/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Dimensions are measured with the package seated in JEDEC seating plane gauge GS-3. D. Dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 (0,25). E. Dimensions measured with the leads constrained to be perpendicular to Datum C. F. Dimensions are measured at the lead tips with the leads unconstrained. G. Pointed or rounded lead tips are preferred to ease insertion. H. Maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 (0,25). POST OFFICE BOX 655303 I. Distance between leads including dambar protrusions to be 0.005 (0,13) minimum. J. A visual index feature must be located within the cross–hatched area. K. For automatic insertion, any raised irregularity on the top surface (step, mesa, etc.) shall be symmetrical about the lateral and longitudinal package centerlines. L. Controlling dimension in inches. M. Falls within JEDEC-MS-001-BE with exception of lead count. • DALLAS, TEXAS 75265 1 MECHANICAL DATA MPDS105 – AUGUST 2001 DVA (R-PDSO-G8/28) PLASTIC SMALL-OUTLINE C A 18,10 17,70 0,25 M B M 28 15 B 7,60 7,40 10,65 10,01 D Index Area 1 14 2,65 2,35 C 0,75 0,25 x 45° Seating Plane 1,27 G 0,51 0,33 0,30 0,10 0,10 0,32 0,23 0,25 M C A M B S 0°–8° F 1,27 0,40 4202103/B 08/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body length dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, and gate burrs shall not exceed 0,15 mm per side. D. Body width dimension does not include inter-lead flash or portrusions. Inter-lead flash and protrusions shall not exceed 0,25 mm per side. E. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the cross-hatched area. G. Lead width, as measured 0,36 mm or greater above the seating plane, shall not exceed a maximum value of 0,61 mm. H. Lead-to-lead coplanarity shall be less than 0,10 mm from seating plane. I. Falls within JEDEC MS-013-AE with the exception of the number of leads. F. Lead dimension is the length of terminal for soldering to a substrate. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PACKAGE OUTLINE DVB0012A SOP - 2.65 mm max height SCALE 0.900 PLASTIC SMALL OUTLINE C 10.65 10.01 SEATING PLANE PIN 1 ID AREA A 28 1 18.1 17.7 NOTE 3 0.1 C 8X 1.27 2X 16.51 14 15 B 7.6 7.4 12X 0.51 0.33 0.25 C A B 0.32 TYP 0.23 SEE DETAIL A 2.65 MAX 8 0 0.3 0.1 1.27 0.40 DETAIL A TYPICAL 4222497/A 10/2015 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MS-013. www.ti.com EXAMPLE BOARD LAYOUT DVB0012A SOP - 2.65 mm max height PLASTIC SMALL OUTLINE 12X (2) SYMM 1 28 12X (0.6) (R0.05) TYP SYMM (16.51) 8X (1.27) 14 15 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK 0.07 MAX ALL AROUND SOLDER MASK OPENING 0.07 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4222497/A 10/2015 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DVB0012A SOP - 2.65 mm max height PLASTIC SMALL OUTLINE 12X (2) 1 SYMM 28 12X (0.6) (R0.05) SYMM (16.51) 8X (1.27) 14 15 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4222497/A 10/2015 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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