Anpec APW7325KAI-TRG 5a 5v 1mhz synchronous buck converter Datasheet

APW7325
5A 5V 1MHz Synchronous Buck Converter
Features
General Description
•
High Efficiency up to 95%
APW7325 is a 5A synchronous buck converter with inte-
- Automatic PFM/PWM Mode Operation
grated 65mΩ high side and 55mΩ low side power
MOSFETs. The APW7325, design with a current-mode
•
Adjustable Output Voltage from 0.6V to VPVDD
•
Integrated 65mΩ High Side / 55mΩ Low Side
control scheme, can convert wide input voltage of 2.6V to
6V to the output voltage adjustable from 0.6V to 6V to
MOSFETs
•
Low Dropout Operation: 100% Duty Cycle
•
Stable with Low ESR Ceramic Capacitors
•
Power-On-Reset Detection on VDD and PVDD
•
Integrated Soft-Start and Soft-Stop
•
Over-Temperature Protection
•
Over-Voltage Protection
•
Under-Voltage Protection
•
High/ Low Side Current Limit
•
Power Good Indication
•
Enable/Shutdown Function
•
Small SOP-8P Package
•
Lead Free and Green Devices Available
provide excellent output voltage regulation.
The APW7325 is equipped with an automatic PFM/PWM
mode operation. At light load , the IC operates in the PFM
mode to reduce the switching losses. At heavy load, the
IC works in PWM mode. At PWM mode, the switching
frequency is set by the external resistor.
The APW7325 is also equipped with Power-on-reset, softstart, soft-stop, and whole protections (under-voltage,
over-voltage, over-temperature and current-limit) into a
single package.
This device, available SOP-8P, provides a very compact
system solution external components and PCB area.
(RoHS Compliant)
Pin Configuration
Applications
•
•
Notebook Computer & UMPC
•
Set-Top Box
•
DSL, Switch HUBr
•
Portable Instrument
APW7325
LCD Monitor/TV
NC 1
LX 2
NC 3
8 GND
9
GND
EN 4
7 PVDD
6 VDD
5 FB
SOP-8P
(Top View)
9
Exposed pad
GND
The pin 6 must be connected to the pin 9 (exposed pad)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2013
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APW7325
Ordering and Marking Information
Package Code
KA : SOP-8P
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APW7325
Assembly Material
Handling Code
Temperature Range
Package Code
APW7325 KA :
APW7325
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
VPVDD, VVDD
VLX
Input Supply Voltage
LX to GND Voltage
Power Dissipation
TJ
Junction Temperature
TSTG
Storage Temperature
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
Unit
-0.3 ~ 6.5
V
<30ns pulse width
-3 ~VPVDD+3
V
>30ns pulse width
-1 ~VPVDD+0.3
V
POK, FB, EN to GND Voltage
PD
Rating
-0.3 ~ 6.5
V
Internally Limited
W
150
o
-65 ~ 150
o
260
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
θJA
θJC
Parameter
Typical Value
Junction-to-Ambient Resistance in Free Air (Note 2)
Unit
o
SOP-8P
60
SOP-8P
20
Junction-to-Case Resistance in Free Air (Note 3)
C/W
o
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of SOP-8P is soldered directly on the PCB.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P package.
Copyright  ANPEC Electronics Corp.
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APW7325
Recommended Operating Conditions (Note 4)
Symbol
Parameter
Range
Unit
VVDD
Control and Driver Supply Voltage
2.6 ~ 6
V
VPVDD
Input Supply Voltage
2~6
V
VOUT
Converter Output Voltage
0.6~6
V
Inductance
1 ~ 3.3
µH
L
IOUT
TA
TJ
Converter Output Current
0~5
Ambient Temperature
Junction Temperature
A
-40 ~ 85
o
-40 ~ 125
o
C
C
Note 4: Refer to the typical application circuit.
Electrical Characteristics
Unless otherwise specified, these specifications apply over VVDD=VPVDD=5V, VOUT=3.3V, TA=25oC.
Symbo
Parameter
APW7325
Test Conditions
Min.
Typ.
Unit
Max.
SUPPLY CURRENT
VDD Supply Current
VFB=0.7V
-
460
-
µA
IVDD_SDH VDD Shutdown Supply Current
EN=GND
-
-
1
µA
2.3
2.4
2.5
V
-
0.2
-
V
1.5
1.7
1.9
V
-
0.2
-
V
-
0.6
-
V
IVDD
POWER-ON-RESET (POR)
VDD POR Voltage Threshold
VVDD Rising
VDD POR Hysteresis
PVDD POR Voltage Threshold
PVDD POR Hysteresis
REFERENCE VOLTAGE
VREF
Reference Voltage
All temperature
-1
-
+1
%
-1.5
-
+1.5
%
0.85
1
1.15
MHz
-
100
-
%
-
100
-
ns
-
65
80
mΩ
-
55
75
mΩ
-
-
10
µA
Error Amplifier Transconductance
-
550
-
µA/V
Error Amplifier DC Gain
-
80
-
dB
Current Sense Transresistance
-
400
-
mΩ
Dead Time
-
20
-
ns
Output Accuracy
IOUT=10mA~5A, VVDD=2.6~5V
OSCILLATOR AND DUTY CYCLE
FOSC
Oscillator Frequency
Maximum Converter’s Duty
VFB=0.7V
Minimum on Time
POWER MOSFET
High Side P-MOSFET Resistance
Low Side N-MOSFET Resistance
VVDD=5V, ILX=0.5A, TA=25oC
o
VVDD=5V, ILX=0.5A, TA=25 C
High/Low Side MOSFET Leakage
Current
CURRENT-MODE PWM CONVERTER
Gm
TD
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APW7325
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VVDD=VPVDD=5V, VOUT=3.3V, TA=25oC.
Symbo
Parameter
APW7325
Test Conditions
Min.
Unit
Typ.
Max.
PROTECTIONS
ILIM
High Side MOSFET Current-Limit
6
6.5
8
A
TOTP
Over-Temperature Trip Point
Peak Current
-
160
-
°C
Over-Temperature Hysteresis
-
50
-
°C
Over-Voltage Protection Threshold
120
-
135
%VREF
Under-Voltage Protection Threshold
45
50
55
%VREF
Soft-Start Time
-
1
-
ms
EN Enable Threshold
-
-
1.4
V
EN Shutdown Threshold
0.5
-
-
V
EN Pull Low Resistance
-
500
-
kΩ
SOFT-START, ENABLE, AND INPUT CURRENTS
Copyright  ANPEC Electronics Corp.
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APW7325
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified.
Load Transient Response
Load Transient Response
1.5A
2.5A
1A
IOUT , 1A/Div
10mA
IOUT , 1A/Div
1
1
2
2
VOUT , 100mV/Div, AC
VOUT , 100mV/Div, AC
TIME: 20µs/Div
TIME: 50µs/Div
Normal Operating Waveform
VLX , 5V/Div
1
VOUT , 20mV/Div, DC
2
IL , 1A/Div
3
TIME: 1µs/Div
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APW7325
Pin Description
PIN
FUNCTION
NO.
NAME
1,3
NC
No Connection.
2
LX
Power Switching Output. LX is the Junction of the high-side and low-side Power MOSFETs
to supply power to the output LC filter.
4
EN
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on
the regulator, drive it low to turn it off.
5
FB
Output Feedback Input. The APW7325 senses the feedback voltage via FB and regulates
the voltage at 0.6V. Connecting FB with a resistor-divider from the converter’s output sets
the output voltage.
6
VDD
Signal Input. VDD supplies the control circuitry, gate drivers. Connecting a ceramic bypass
capacitor from VDD to GND to eliminate switching noise and voltage ripple on the input to
the IC.
7
PVDD
Power Input. PVDD supplies the step-down converter switches. Connecting a ceramic
bypass capacitor from PVDD to GND to eliminate switching noise and voltage ripple on the
input to the IC.
9
GND
(Exposed Pad)
Ground and Exposed pad. Connect the exposed pad to the system ground plan with large
copper area for dissipating heat into the ambient air.
8
GND
Ground. Power and signal ground.
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APW7325
Block Diagram
PVDD
VDD
Current Sense
Amplifier
LOC
Over
Temperature
Protection
Power-OnReset
125%VREF
OTP
OVP
Current
Limit
Zero Crossing
Comparator
POR
Fault
Logics
50%VREF
UVP
Inhibit
Error
Amplifier
FB
Gate
Control
Current
Compartor
Gm
Soft-start
VREF
0.6V
Slope
Compensation
Oscillator
Shutdown
LX
Gat
Driv
e
er
Gat
e
LOC
Current Sense
Amplifier
GND
EN
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APW7325
Typical Application Circuit
L1
1µH
VIN
5V
PVDD
CIN
22µF
LX
C1
(option)
VDD
ON
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2013
R1
24k
FB
APW7325
OFF
VOUT
1.8V/5A
COUT
22µFx2
R2
12k
GND
EN
8
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APW7325
Function Description
VDD and PVDD Power-On-Reset (POR)
with a 50oC hysteresis to lower the average TJ during
The APW7325 keeps monitoring the voltage on VDD and
PVDD pins to prevent wrong logic operations which may
continuous thermal overload conditions, increasing lifetime of the APW7325.
occur when VDD or PVDD voltage is not high enough for
internal control circuitry to operate. The VDD POR rising
Current-Limit Protection
The APW7325 monitors the output current, flows through
the high-side and low-side power MOSFETs, and limits
threshold is 2.4V (typical) with 0.2V hysteresis and PVDD
POR rising threshold is 1.7V with 0.2V hysteresis.
the current peak at current-limit level to prevent the IC
from damaging during overload, short-circuit and over-
During start-up, the VDD and PVDD voltage must exceed
the enable voltage threshold. Then, the IC starts a start-
voltage conditions. Typical high side power MOSFET current limit is 6.5A, and low side MOSFET current limit is
up process and ramps up the output voltage to the voltage target.
1.9A.
Output Under-Voltage Protection (UVP)
Soft-Start
In the operational process, if a short-circuit occurs, the
output voltage will drop quickly. Before the current-limit
circuit responds, the output voltage will fall out of the re-
The APW7325 has a built-in soft-start to control the rise
rate of the output voltage and limit the input current surge
quired regulation range. The under-voltage continually
monitors the FB voltage after soft-start is completed. If a
during start-up. During soft-start, an internal voltage ramp
connected to one of the positive inputs of the error
load step is strong enough to pull the output voltage lower
than the under-voltage threshold, the IC starts soft-stop
amplifier, rises up to replace the reference voltage (0.6V)
until the voltage ramp reaches the reference voltage. Dur-
function and shuts down converter’s output.
ing soft-start without output over-voltage, the APW7325
converter’s sinking capability is disabled until the output
The under-voltage threshold is 50% of the nominal output voltage. The under-voltage comparator has a built-in
voltage reaches the voltage target.
3µs noise filter to prevent the chips from wrong UVP shutdown being caused by noise. APW7325 will be latched
Soft-Stop
after under-voltage protection.
At the moment of shutdown controlled by EN signal, under-voltage event or over-voltage event, the APW7325 ini-
Over-Voltage Protection (OVP)
tiates a soft-stop process to discharge the output voltage
in the output capacitors. Certainly, the load current also
The over-voltage function monitors the output voltage by
discharges the output voltage. During soft-stop, the internal voltage ramp (VRAMP) falls down to replace the refer-
FB pin. When the FB voltage increases over 125% of the
reference voltage due to the high-side MOSFET failure or
ence voltage. Therefore, the output voltage falls down
slowly at the light load. After the soft-stop interval elapses,
for other reasons, the over-voltage protection comparator
will trigger soft-stop function and shutdown the converter
the soft-stop process ends and the IC turns.
output.
Over-Temperature Protection (OTP)
The over-temperature circuit limits the junction temperature of the APW7325. When the junction temperature ex-
Enable and Shutdown
Driving EN to ground places the APW7325 in shutdown.
ceeds TJ=+160oC, a thermal sensor turns off the both
power MOSFETs, allowing the devices to cool. The ther-
In shutdown mode, the internal N-Channel power
MOSFET turns off, all internal circuitry shuts down and
mal sensor allows the converters to start a start-up process and to regulate the output voltage again after the
the quiescent supply current reduces to less than 1µA.
junction temperature cools by 50oC. The OTP is designed
Copyright  ANPEC Electronics Corp.
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APW7325
Application Information
shown in “Typical Application Circuits”. A suggestion of
maximum value of R2 is 20kΩ to keep the minimum cur-
Input Capacitor Selection
Because buck converters have a pulsating input current,
a low ESR input capacitor is required. This results in the
rent that provides enough noise rejection ability through
the resistor divider. The output voltage can be calculated
best input voltage filtering, minimizing the interference
with other circuits caused by high input voltage spikes.
as below:
R1 
R1 


VOUT = VREF ⋅  1 +
 = 0.6 ⋅ 1 +

R2 
R2 


Also, the input capacitor must be sufficiently large to stabilize the input voltage during heavy load transients. For
good input voltage filtering, usually a 22µF input capacitor
is sufficient. It can be increased without any limit for better
VOUT
input-voltage filtering. Ceramic capacitors show better
performance because of the low ESR value, and they are
R1≤80kΩ
less sensitive against voltage transients and spikes compared to tantalum capacitors. Place the input capacitor as
FB
R2 ≤ 20kΩ
APW7325
close as possible to the input and GND pin of the device
for better performance.
GND
Inductor Selection
Output Capacitor Selection
For high efficiencies, the inductor should have a low DC
The current-mode control scheme of the APW7325 allows the use of tiny ceramic capacitors. The higher ca-
resistance to minimize conduction losses. Especially at
high-switching frequencies, the core material has a
pacitor value provides the good load transients response.
Ceramic capacitors with low ESR values have the lowest
higher impact on efficiency. When using small chip
inductors, the efficiency is reduced mainly due to higher
output voltage ripple and are recommended. If required,
tantalum capacitors may be used as well. The output
inductor core losses. This needs to be considered when
selecting the appropriate inductor. The inductor value de-
ripple is the sum of the voltages across the ESR and the
ideal output capacitor.
termines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and the
lower the conduction losses of the converter. Conversely,
larger inductor values cause a slower load transient
∆VOUT
response. A reasonable starting point for setting ripple
current, ∆IL, is 40% of maximum output current. The rec-

V
VOUT ⋅ 1 − OUT
VIN

≅
FSW ⋅ L


 
1
 ⋅  ESR +

⋅
8
F
SW ⋅ COUT





When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
ommended inductor value can be calculated as below:
dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.


V
VOUT 1 − OUT 
VIN 

L≥
FSW ⋅ ∆IL
IL(MAX) = IOUT(MAX) + 1/2 x ∆IL
VIN
IIN
To avoid the saturation of the inductor, the inductor should
be rated at least for the maximum output current of the
IP-FET
IL
converter plus the inductor ripple current.
CIN
IOUT
P-FET
VOUT
SW
Output Voltage Setting
N-FET
In the adjustable version, the output voltage is set by a
resistive divider. The external resistive divider is con-
ESR
COUT
nected to the output, allowing remote voltage sensing as
Copyright  ANPEC Electronics Corp.
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APW7325
Application Information (Cont.)
Output Capacitor Selection (Cont.)
8
ILIM
7
6
5
1.8
0.6
IL
IPEAK
∆IL
3.45
5.3
2.95
IOUT
IP-FET
1
2
1.25
3
4
Unit : mm
Layout Consideration
For all switching power supplies, the layout is an important step in the design; especially at high peak currents
and switching frequencies. If the layout is not carefully
done, the regulator might show noise problems and duty
cycle jitter.
1. The input capacitor should be placed close to the PVDD
and GND. Connecting the capacitor and PVDD/GND
with short and wide trace without any via holes for good
input voltage filtering. The distance between VIN/GND
to capacitor less than 2mm respectively is
recommended.
2. To minimize copper trace connections that can inject
noise into the system, the inductor should be placed
as close as possible to the LX pin to minimize the
noise coupling into other circuits.
3. The output capacitor should be place closed to LX and
GND.
4. Since the feedback pin and network is a high impedance circuit the feedback network should be routed
away from the inductor. The feedback pin and feedback network should be shielded with a ground plane
or trace to minimize noise coupling into this circuit.
5. A star ground connection or ground plane minimizes
ground shifts and noise is recommended.
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APW7325
Package Information
SOP-8P
D
SEE VIEW A
h X 45o
E
E1
THERMAL
PAD
E2
D1
c
0.25
A2
A1
NX
aaa
A
b
e
c
GAUGE PLANE
SEATING PLANE
L
VIEW A
S
Y
M
B
O
L
SOP-8P
MILLIMETERS
MIN.
A
A1
INCHES
MIN.
MAX.
MAX.
1.60
0.063
0.000
0.15
0.00
0.006
0.049
A2
1.25
b
0.31
0.51
c
0.17
0.25
0.007
0.010
0.197
0.012
0.020
D
4.80
5.00
0.189
D1
2.50
3.50
0.098
0.138
E
5.80
6.20
0.228
0.244
0.157
0.118
E1
3.80
4.00
0.150
E2
2.00
3.00
0.079
e
1.27 BSC
0.050 BSC
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
0
o
o
0C
aaa
o
8C
8oC
0C
0.10
0.004
Note : 1. Followed from JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
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APW7325
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
SOP-8P
A
H
T1
C
d
D
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
5.20±0.20
2.10±0.20
4.0±0.10
8.0±0.10
W
E1
12.0±0.30 1.75±0.10
F
5.5±0.05
(mm)
Devices Per Unit
Package Type
SOP-8P
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2013
Unit
Tape & Reel
Quantity
2500
13
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APW7325
Taping Direction Information
SOP-8P
USER DIRECTION OF FEED
Classification Profile
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APW7325
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
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Description
5 Sec, 245°C
1000 Hrs, Bias @ TJ=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
www.anpec.com.tw
APW7325
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2013
16
www.anpec.com.tw
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