ICS8535-31 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8535-31 is a low skew, high performance 1-to-4 3.3V Crystal Oscillator/LVCMOS-to-3.3V HiPerClockS™ LVPECL fanout buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8535-31 has selectable single ended clock or crystal inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The output enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. • 4 differential 3.3V LVPECL outputs ICS • Selectable LVCMOS/LVTTL CLK or crystal inputs • CLK can accept the following input levels: LVCMOS, LVTTL • Maximum output frequency: 266MHz • Output skew: 30ps (maximum) • Part-to-part skew: 200ps (maximum) • Propagation delay: 1.65ns (maximum) • Additive phase jitter, RMS: 0.057ps (typical) Guaranteed output and part-to-part skew characteristics make the ICS8535-31 ideal for those applications demanding well defined performance and repeatability. • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Lead-Free package fully RoHS compliant • Industrial Temperature information available upon request • Replaces the ICS8535-11 BLOCK DIAGRAM CLK_EN Pullup PIN ASSIGNMENT D VEE CLK_EN CLK_SEL CLK nc XTAL_IN XTAL_OUT nc nc VCC Q LE CLK Pulldown 0 Q0 nQ0 XTAL_IN OSC XTAL_OUT CLK_SEL Pulldown 1 Q1 nQ1 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VCC Q1 nQ1 Q2 nQ2 VCC Q3 nQ3 ICS8535-31 Q2 nQ2 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View Q3 nQ3 8535AG-31 1 2 3 4 5 6 7 8 9 10 www.icst.com/products/hiperclocks.html 1 REV. B APRIL 29, 2005 ICS8535-31 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VEE Power Type 2 CLK_EN Input 3 CLK_SEL Input Description Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follows clock Pullup input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects XTAL inputs. Pulldown When LOW, selects CLK input. LVCMOS / LVTTL interface levels. Pulldown Clock input. LVCMOS / LVTTL interface levels. 4 CLK Input 5, 8, 9 6, 7 10, 13, 18 nc XTAL_IN, XTAL_OUT VCC Unused Power No connect. Cr ystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Positive supply pins. 11, 12 nQ3, Q3 Output Differential clock outputs. LVPECL interface levels. Input 14, 15 nQ2, Q2 Output Differential clock outputs. LVPECL interface levels. 16, 17 nQ1, Q1 Output Differential clock outputs. LVPECL interface levels. 19, 20 nQ0, Q0 Output Differential clock outputs. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 8535AG-31 www.icst.com/products/hiperclocks.html 2 REV. B APRIL 29, 2005 ICS8535-31 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs CLK_EN 0 Outputs CLK_SEL 0 Selected Source CLK Q0:Q3 Disabled; LOW nQ0:nQ3 Disabled; HIGH 0 1 XTAL_IN, XTAL_OUT Disabled; LOW Disabled; HIGH 1 0 CLK Enabled Enabled 1 1 XTAL_IN, XTAL_OUT Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock or cr ystal oscillator edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK input as described in Table 3B. Enabled Disabled CLK CLK_EN nQ0:nQ3 Q0:Q3 FIGURE 1. CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs CLK 0 1 8535AG-31 Outputs Q0:Q3 LOW HIGH nQ0:nQ3 HIGH LOW www.icst.com/products/hiperclocks.html 3 REV. B APRIL 29, 2005 ICS8535-31 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VCC Power Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 60 mA Maximum Units 2 VCC + 0.3V V -0.3 0.8 V VIN = VCC = 3.465V 150 µA VIN = VCC = 3.465V 5 µA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions CLK, CLK_SEL CLK_EN CLK, CLK_SEL CLK_EN Minimum Typical VIN = 0V, VCC = 3.465V -5 µA VIN = 0V, VCC = 3.465V -150 µA TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCC - 1.4 Typical VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. 8535AG-31 www.icst.com/products/hiperclocks.html 4 REV. B APRIL 29, 2005 ICS8535-31 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Typical Maximum Mode of Oscillation Units Fundamental Frequency 12 40 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW TABLE 6. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 Test Conditions Minimum Typical 1.45 155.52MHz, (Integration Range: 12kHz - 20MHz) Maximum Units 266 MHz 1.65 ns t jit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section t sk(o) Output Skew; NOTE 2, 4 30 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 200 ps tR / tF Output Rise/Fall Time 600 ps 20% to 80% 0.057 300 ps odc Output Duty Cycle 46 54 % All parameters measured at ƒ ≤ 266MHz unless noted otherwise. NOTE 1: Measured from the VCC/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8535AG-31 www.icst.com/products/hiperclocks.html 5 REV. B APRIL 29, 2005 ICS8535-31 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 Additive Phase Jitter, RMS -20 @ 155.52MHz (12kHz to 20MHz) = 0.057ps typical -30 -40 -50 SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 8535AG-31 vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.icst.com/products/hiperclocks.html 6 REV. B APRIL 29, 2005 ICS8535-31 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V V CC Qx SCOPE nQx Qx LVPECL nQy nQx VEE Qy t sk(o) -1.3V ± 0.165V 3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW VCC CLK 80% 80% 2 VSW I N G Clock Outputs nQ0:nQ3 20% 20% Q0:Q3 tR tF tPD PROPAGATION DELAY OUTPUT RISE/FALL TIME nQ0:nQ3 Q0:Q3 Pulse Width t odc = PERIOD t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 8535AG-31 www.icst.com/products/hiperclocks.html 7 REV. B APRIL 29, 2005 ICS8535-31 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION TERMINATION FOR LVPECL OUTPUTS 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o FOUT 50Ω VCC - 2V FIN Zo = 50Ω RTT 84Ω FIGURE 2A. LVPECL OUTPUT TERMINATION 84Ω FIGURE 2B. LVPECL OUTPUT TERMINATION CRYSTAL INPUT INTERFACE The ICS8535-31 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. These same capacitor values will tune any 18pF parallel resonant crystal over the frequency range and other parameters specified in this data sheet. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 18p X1 18pF Parallel Crystal XTAL_OUT C2 22p Figure 3. CRYSTAL INPUt INTERFACE 8535AG-31 www.icst.com/products/hiperclocks.html 8 REV. B APRIL 29, 2005 ICS8535-31 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8535-31. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8535-31 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 60mA = 207.9mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power_MAX (3.465V, with all outputs switching) = 207.9mW + 120mW = 327.9mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.328W * 66.6°C/W = 92°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8535AG-31 www.icst.com/products/hiperclocks.html 9 REV. B APRIL 29, 2005 ICS8535-31 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CC_MAX • -V OH_MAX OL_MAX CC_MAX CC_MAX – 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CC_MAX – 1.7V ) = 1.7V -V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V Pd_H = [(V – (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= OH_MAX CC_MAX CC_MAX OH_MAX OH_MAX CC_MAX OH_MAX L CC_MAX L [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 8535AG-31 www.icst.com/products/hiperclocks.html 10 REV. B APRIL 29, 2005 ICS8535-31 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8535-31 is: 428 8535AG-31 www.icst.com/products/hiperclocks.html 11 REV. B APRIL 29, 2005 ICS8535-31 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER 20 LEAD TSSOP TABLE 9. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 8535AG-31 www.icst.com/products/hiperclocks.html 12 REV. B APRIL 29, 2005 ICS8535-31 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8535AG-31 ICS8535AG-31 20 lead TSSOP tube 0°C to 70°C ICS8535AG-31T ICS8535AG-31 20 lead TSSOP 2500 tape & reel 0°C to 70°C ICS8535AG-31LF ICS8535AG31L 20 lead "Lead-Free" TSSOP tube 0°C to 70°C ICS8535AG-31LFT ICS8535AG31L 20 lead "Lead-Free" TSSOP 2500 tape & reel 0°C to 70°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8535AG-31 www.icst.com/products/hiperclocks.html 13 REV. B APRIL 29, 2005 Integrated Circuit Systems, Inc. ICS8535-31 LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER REVISION HISTORY SHEET Rev B 8535AG-31 Table Page 1 T6 5 Description of Change Features Section - corrected Par t-to-Par t Skew bullet from 100ps max. to 200ps max. AC Characteristics Table - corrected Par t-to-Par t Skew from 100ps max. to 200ps max. www.icst.com/products/hiperclocks.html 14 Date 4/29/05 REV. B APRIL 29, 2005