LE2464C 64 kb I2C CMOS Serial EEPROM Overview The LE2464C is two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). This device realizes high speed and a high level reliability by high performance CMOS EEPROM technology. This device is compatible with I2C memory protocol, therefore it is best suited for application that requires re-writable nonvolatile parameter memory. www.onsemi.com Function Capacity : 64k bits (8k 8 bits) Single supply voltage : 1.7 V to 3.6 V Operating temperature : 40ºC to +85ºC WLCSP6, 0.80x1.20 Interface : Two wire serial interface (I2C Bus*) Operating clock frequency : 400 kHz Low Power consumption : Standby : 2 µA (max.) : Active (Read) : 0.5 mA (max.) Automatic page write mode : 32 Bytes Read mode : Sequential Read and random read Slave Address : Slave address in 7 bit format is 050 or 054 depending of polarity of pin B3 (TEST) Erase/Write cycles : 106 cycles (Page Write) Data Retention : 20 years High reliability : Adopts proprietary symmetric memory array configuration (USP6947325) Hardware write protect feature Noise filters connected to SCL and SDA pins Incorporates a feature to prohibit write operations under low voltage conditions. Package : WLP6(1.200.80) 0.33mm height Specifications Absolute Maximum Ratings at Ta = 25C Parameter Symbol Conditions Supply voltage DC input voltage Over-shoot voltage Storage temperature Tstg Ratings Unit 0.5 to +4.6 V 0.5 to VCC+0.5 V 1.0 to VCC+1.0 V 65 to +150 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. * This product is licensed from Silicon Storage Technology, Inc. (USA). ORDERING INFORMATION See detailed ordering and shipping information on page 16 of this data sheet. © Semiconductor Components Industries, LLC, 2016 August 2016 - Rev. 3 1 Publication Order Number : LE2464C/D LE2464C Recommended Operating Conditions Parameter Symbol Ratings Conditions min typ Unit max Operating supply voltage 1.7 3.6 V Operating temperature 40 +85 C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC Electrical Characteristics Parameter Symbol Ratings Conditions Supply current at reading ICC1 f = 400 kHz, VCC = VCC max Supply current at writing ICC2 min typ Unit max 0.5 mA 3 mA Standby current ISB f = 400 kHz, tWC = 5 ms, VCC = VCC max VIN = VCC or GND 2 µA Input leakage current ILI VIN = GND to VCC, VCC = VCC max 2.0 +2.0 µA Output leakage current ILO VIN = GND to VCC, VCC = VCC max 2.0 +2.0 µA VCC 0.3 V Input Low voltage VIL Input High voltage VIH Output Low voltage VOL VCC 0.7 V IOL = 0.7 mA, VCC = 1.7 V 0.2 V IOL = 1.0 mA, VCC = 1.7 V 0.4 V IOL = 2.0 mA, VCC = 2.5 V 0.4 V Capacitance at Ta = 25C, f = 1 MHz Parameter Symbol Conditions max Unit In/Output pin capacitance CI/O VI/O = 0 V (SDA) 10 pF Input pin capacitance CI VIN = 0 V 10 pF AC Electric Characteristics VCC Input pulse level 0.1 × VCC to 0.9 × VCC Input pulse rise / fall time 20 ns Output detection voltage 0.5 × VCC Output load 50 pF + Pull up resistor 3.0 kΩ R=3.0kΩ SDA C=50pF Output Load Circuit Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 2 LE2464C Fast Mode Parameter Symbol Ratings min typ Unit max Slave mode SCL clock frequency fSCLS 0 SCL clock low time tLOW 1200 400 kHz SCL clock high time tHIGH 600 SDA output delay time tAA 100 SDA data output hold time tDH 100 ns Start condition setup time tSU.STA 600 ns Start condition hold time tHD.STA 600 ns Data in setup time tSU.DAT 100 ns Data in hold time tHD.DAT 0 ns Stop condition setup time tSU.STO 600 SCL SDA rise time tR 300 ns SCL SDA fall time tF 300 ns ns ns 900 ns ns Bus release time tBUF Noise suppression time tSP 1200 100 ns ns Write time tWC 5 ms Standard Mode Parameter Symbol Ratings min typ Unit max Slave mode SCL clock frequency fSCLS 0 SCL clock low time tLOW 4700 100 kHz SCL clock high time tHIGH 4000 SDA output delay time tAA 100 SDA data output hold time tDH 100 Start condition setup time tSU.STA 4700 ns Start condition hold time tHD.STA 4000 ns Data in setup time tSU.DAT 250 ns Data in hold time tHD.DAT 0 ns Stop condition setup time tSU.STO 4000 SCL SDA rise time tR 1000 ns SCL SDA fall time tF 300 ns ns ns 3500 ns ns ns Bus release time tBUF Noise suppression time tSP 100 ns Write time tWC 5 ms www.onsemi.com 3 4700 ns LE2464C Package Dimensions unit : mm WLP6(1.20.8) 0.33mm height TOP VIEW BOTTOM VIEW SIDE VIEW 1.2±0.05 A B 0.4 0.8±0.05 B 0.2 A 3 6 X φ0.20±0.05 φ0.05 M SIDE VIEW S 1 2 0.4 AB 0.2 0.08 S 0.33 MAX 0.08±0.05 S WLCSP6, 0.80x1.20 CASE 567HM ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. A B E PIN A1 REFERENCE D 0.05 C 2X 0.05 C 2X DIM A A1 b D E e TOP VIEW A 0.05 C A1 RECOMMENDED SOLDERING FOOTPRINT* 0.08 C NOTE 3 6X C SIDE VIEW SEATING PLANE 0.40 PITCH A1 PACKAGE OUTLINE e b 0.05 C A B 0.03 C MILLIMETERS MIN MAX 0.33 --0.03 0.13 0.15 0.25 0.80 BSC 1.20 BSC 0.40 BSC 6X e B 0.40 PITCH A 1 2 3 BOTTOM VIEW 0.20 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 4 LE2464C Pin Assignment Top View Ball side View A SCL WP VCC SDA GND TEST B B SDA GND TEST SCL WP VCC A 1 2 3 1 2 3 Pin Descriptions A1 SCL Serial clock input A2 WP Write protect A3 VCC Power supply B1 SDA Serial data in/output B2 GND Ground B3 TEST Slave Device Address 2 Block Diagram SDA X decoder Address generator Serial controller High voltage generator EEPROM Array Y decoder & Sense AMP I/O Buffer SCL Condition detector Write controller Input Buffer TEST WP Serial-Parallel converter www.onsemi.com 5 LE2464C Bus timing tHIGH tF tLOW tR tSP SCL tSU.STA tHD.DAT tHD.STA tSU.DAT tSU.STO tSP SDA/IN tAA tBUF tDH SDA/OUT Write timing tWC SCL D0 SDA Write Data Acknowledge Stop condition Start condition Pin Function SCL (Serial clock) The SCL signal is used to control serial input data timing. The SCL is used to latch input data synchronously at the rising edge and read output data synchronously at the falling edge. SDA (Serial input / output data) The SDA pin is bidirectional for serial data transfer. It is an open-drain structure that needs to be pulled up by resistor. TEST (Slave address) TEST pin represents S2. TEST pulled high (1.8 V) results in 7-bit device address of 0x54. TEST pulled low results in 7 bit device address of 0x50. The TEST must be tied to VCC or GND. WP (Write protect) When the WP input is high, write protection is enabled. When WP input is either low or floating, write protection is disabled. The read operation is always activated irrespective of the WP pin status. www.onsemi.com 6 LE2464C Functional Description The device supports the I2C protocol. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. 1) Start Condition A Start condition needs to start the EEPROM operation, it is to set falling edge of the SDA while the SCL is stable in the high status. 2) Stop Condition A Start condition is identified by rising edge of the SDA signal while the SCL is stable in the high status. The device becomes the standby mode from a Read operation by a Stop condition. In a write sequence, a stop condition is trigger to terminate the write data inputs and it is trigger to start the internal write cycle. After the internally write cycle time which is specified as tWC, the device enters a standby mode. tSU.STA tSU.STO tHD.STA SCL SDA Stop condition Start condition 3) Data Input During data input, the device latches the SDA on the rising edge of the SCL. For correct the operation, The SDA must be stable during the rising edge of the SCL. tSU.DAT tHD.DAT SCL SDA www.onsemi.com 7 LE2464C 4) Acknowledge Bit (ACK) The Acknowledge Bit is used to indicate a successful byte data transfer. The receiver sends a zero to acknowledge that it has received each word (Device Code, Slave Address etc) from the transmitter. SCL (From Transmitter) 8 1 9 SDA (From Transmitter) SDA (EEPROM output) Acknowledge Bit output Start condition tAA tDH 5) Device addressing To transmit between the bus master and slave device (EEPROM), the master must send a Start condition to the EEPROM. The device address word of the EEPROM consists of 4-bit Device Code, 3-bit Slave Device address code and 1-bit read/write code. By sending these, it becomes possible to communicate between the bus master and the EEPROM. The upper 4-bit of the device address word are called the Device Code, the Device Code of the EEPROM uses 1010b fixed code. This device has the 3-bit of the Slave Device address as the Slave address (S0, S1, S2). The value of S0 and S1 fixed S0 = 0, S1 = 0 internally. This device can connect up to two devices on the bus controlled by S2 value. When the Device Code is received on the SDA, the device only responds if Slave address pin tied to VCC or GND is the same as the Slave address signal input. The 8th bit is the read/write bit. The bit is set to 1 for Read operation and 0 for Write operation. If a match occurs on the Device Code, the corresponding device gives an acknowledgement on SDA during the 9th bit time. If device does not match the Device Code, it deselects itself from the bus, and goes into the Standby mode. Use the Random Read command when you execute reading after the slave device was switched. Slave Address Device Code 1 0 1 0 S2 S1 S0 R/W LSB MSB Device address word www.onsemi.com 8 LE2464C 6) EEPROM Write Operation 6)-1. Byte Write The write operation requires a 7-bit device address word with the 8th bit = 0 (write). Then the EEPROM sends acknowledgement 0 at the 9th clock cycle. After these, the EEPROM receives word address (A15 to A8), and the EEPROM outputs acknowledgement 0. And then, the EEPROM receives word address (A7 to A0), and the EEPROM outputs acknowledgement 0. Then the EEPROM receives 8-bit write data, the EEPROM outputs acknowledgement 0 after receipt of write data. If the EEPROM receives a stop condition, the EEPROM enters an internally timed (tWC) write cycle and terminates receipt of inputs until completion of the write cycle. A A A A A A A9 A8 15 14 13 12 11 10 1 0 1 0 S2 S1 S0 W ACK R/W Data A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK Stop SDA Start Word Address ACK A15 ~ A13: Don’t Care Access from master device 6)-2. Page Write The Page write allows up to 32 bytes to be written in a single write cycle. The page write is the same sequence as the byte write except for inputting the more write data. The page write is initiated by a start condition, device code, device address, memory address(n) and write data(n) with every 9th bit acknowledgement. The device enters the page write operation if this device receives more write data(n+1) instead of receiving a stop condition. The page address (A0 to A4) bits are automatically incremented on receiving write data(n+1). The device can continue to receive write data up to 32 bytes. If the page address bits reaches the last address of the page, the page address bits will roll over to the first address of the same page and previous write data will be overwritten. After these, if the device receives a stop condition, the device enters an internally timed (tWC×(n+x)) write cycle and terminates receipt of inputs until completion of the write cycle. 1 0 1 0 S2 S1 S0 W Data(n) A A A A A A A9 A8 15 14 13 12 11 10 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK ACK ACK R/W Data(n+x) Data(n+1) ····· D7 D6 ~ D1 D0 ACK ACK D7 D6 ~ D1 D0 ACK D7 D6 ~ D1 D0 D7 D6 ~ D1 D0 ACK Stop SDA Start Word Address(n) ACK A15 ~ A13: Don’t Care Access from master device www.onsemi.com 9 LE2464C 6)-3. Acknowledge Polling The Acknowledge Polling operation is used to show if the EEPROM is in an internally timed write cycle or not. This operation is initiated by the stop condition after inputting write data. This requires the 8-bit device address word with the 8th bit = 0 (write) following the start condition during an internally timed write cycle. If the EEPROM is busy with the internal write cycle, no acknowledge will be returned. If the EEPROM has terminated the internal write cycle, it responds with an acknowledge. The terminated write cycle of the EEPROM can be known by this operation. During Write 1 0 1 0 S2 S1 S0 W NO ACK NO ACK R/W No Write Start 1 0 1 0 S2 S1 S0 W Start SDA Start During Write R/W 1 0 1 0 S2 S1 S0 W ······ ACK R/W Access from master device www.onsemi.com 10 LE2464C 7) EEPROM Read Operation 7)-1. Current Address Read The device has an internal address counter. It maintains that last address during the last read or write operation, with incremented by one. The current address read accesses the address kept by the internal address counter. After receiving a start condition and the device address word with the 8th bit = 1 (Read), the EEPROM outputs the 8-bit current address data from following acknowledgement 0. If the EEPROM receives acknowledgement 1 and a following stop condition, the EEPROM stops the read operation and is returned to a standby mode. In case the EEPROM has accessed the last address of the last page at previous read operation, the current address will roll over and returns to zero address. In case EEPROM has accessed the last address of the last page at previous write operation, the current address roll over within page addressing and returns to the first address in the same page. The current address is valid while power is on. After power on, the current address will be reset (all 0). Note: After the page write operation, the current address is the specified memory address in the last page write, if the write data is more than 32-bytes. Start SDA 1 0 1 0 S2 S1 S0 R Stop Data (n+1) Device Address D7 D6 D5 D4 D3 D2 D1 D0 NO ACK ACK R/W Access from master device 7)-2. Random Read The random read requires a dummy write to set read address. The EEPROM receives a start condition and the device address word with the 8th bit = 0 (write), the memory address. The EEPROM outputs acknowledgement 0 after receiving memory address then enters a current address read with receiving a start condition. The EEPROM outputs the read data of the address which was defined in the dummy write operation. After receiving no acknowledgement and a following stop condition, the EEPROM stops the random read operation and returns to a standby mode. Word Address(n) A A A A A A A9 A8 15 14 13 12 11 10 A7 A6 A5 A4 A3 A2 A1 A0 ACK ACK ACK R/W Dummy Write Device Address Data(n) 1 0 1 0 S2 S1 S0 R ACK D7 D6 ~ D1 D0 ACK Stop 1 0 1 0 S2 S1 S0 W Start SDA Start Device Address NO ACK R/W Current Read A15 ~ A13: Don’t Care Access from master device www.onsemi.com 11 LE2464C SDA Start Device Address 1 Data(n) 0 1 0 S2 S1 S0 R D7 D6 ~ D1 D0 ACK Data(n+1) Data(n+2) Data(n+x) D7 D6 ~ D1 D0 D7 D6 ~ D1 D0 D7 D6 ~ D1 D0 ACK ACK ACK R/W Access from master device www.onsemi.com 12 Stop 7)-3. Sequential Read The sequential read operation is initiated by either a current address read or random read. If the EEPROM receives acknowledgement 0 after 8-bit read data, the read address is incremented and the next 8-bit read data outputs. The current address will roll over and returns address zero if it reaches the last address of the last page. The sequential read can be continued after roll over. The sequential read is terminated if the EEPROM receives no acknowledgement and a following stop condition. NO ACK LE2464C Application Notes 1) Software reset function Software reset (start condition + 9 dummy clock cycles + start condition), shown in the figure below, is executed in order to avoid erroneous operation after power-on and to reset while the command input sequence. During the dummy clock input period, the SDA bus must be opened (set to high by a pull-up resistor). Since it is possible for the ACK output and read data to be output from the EEPROM during the dummy clock period, forcibly entering H will result in an overcurrent flow. Note that this software reset function does not work during the internal write cycle. Dummy clock x 9 1 SCL 8 2 9 SDA Start Condition Start Condition 2) Pull-up resistor of SDA pin Due to the demands of the I2C bus protocol function, the SDA pin must be connected to a pull-up resistor (with a resistance from several k to several tens of k) without fail. The appropriate value must be selected for this resistance (RPU) on the basis of the VIL and IIL of the microcontroller and other devices controlling this product as well as the VOL – IOL characteristics of the product. Generally, when the resistance is too high, the operating frequency will be restricted; conversely, when it is too low, the operating current consumption will increase. RPU maximum value The maximum resistance must be set in such a way that the bus potential, which is determined by the sum total (IL) of the input leaks of the devices connected to the SDA bus and by RPU, can completely satisfy the input high level (VIH min) of the microcontroller and EEPROM. However, a resistance value that satisfies SDA rise time tR and fall time tF must be set. RPU Master Device IL EEPROM SDA CBUS IL RPU maximum value = (VCC VIH) / IL Example : When VCC = 3.0 V and IL = 2 A RPU maximum value = (3.0 V 3.0 V 0.8) / 2 A = 300 k RPU minimum value A resistance corresponding to the low-level output voltage (VOL max) of EEPROM must be set. RPU minimum value = (VCC VOL) / IOL Example : When VCC = 3.0 V, VOL = 0.4 V and IOL = 1 mA RPU minimum value = (3.0 V 0.4) / 1 mA = 2.6 k Recommended RPU setting RPU is set to strike a good balance between the operating frequency requirements and power consumption. If it is assumed that the SDA load capacitance is 50 pF and the SDA output data strobe time is 500 ns, RPU will be about RPU = 500 ns/50 pF = 10 k. www.onsemi.com 13 LE2464C 3) Precautions when turning on the power This product contains a power-on reset circuit for preventing the inadvertent writing of data when the power is turned on. The following conditions must be met in order to ensure stable operation of this circuit. No data guarantees are given in the event of an instantaneous power failure during the internal write operation. symbol tRISE tOFF Vbot Parameter Ratings typ – – – min – 10 – Power rise time Power off time Power bottom voltage max 100 – 0.2 Unit ms ms V tRISE VCC tOFF Vbot 0V Notes: 1) The SDA pin must be set to high and the SCL pin to low or high. 2) Steps must be taken to ensure that the SDA and SCL pins are not placed in a high-impedance state. A. If it is not possible to satisfy the instruction 1 in Note above, and SDA is set to low during power rise After the power has stabilized, the SCL and SDA pins must be controlled as shown below, with both pins set to high. VCC VCC tLOW SCL SCL SDA SDA tSU.DAT tDH tSU.DAT B. If it is not possible to satisfy the instruction 2 in Note above After the power has stabilized, software reset must be executed. C. If it is not possible to satisfy the instructions both 1 and 2 in Note above After the power has stabilized, the steps in A must be executed, then software reset must be executed. 4) Noise filter for the SCL and SDA pins This product contains a filter circuit for eliminating noise at the SCL and SDA pins. Pulses of 100 ns or less are not recognized because of this function. 5) Function to inhibit writing when supply voltage is low This product contains a supply voltage monitoring circuit that inhibits inadvertent writing below the guaranteed operating supply voltage range. The data is protected by ensuring that write operations are not started at voltages (typ.) of 1.3 V and below. www.onsemi.com 14 LE2464C 6) Notes on write protect operation This product prohibits all memory array writing when the WP pin is high. To ensure full write protection, the WP is set high for all periods from the start condition to the stop condition, and the conditions below must be satisfied. symbol tSU.WP tHD.WP WP Parameter min 600 600 WP Setup time WP Hold time Ratings typ – – max – – Unit ns ns tHD.WP tSU.WP SCL SDA Stop Condition Start Condition 7) Slave address setting This product does not have slave address pin of S0 and S1, but the information for the slave addresses, S0 and S1, are held internally. The slave addresses of this product are set to S0 = 0, and S1 = 0 when it is shipped. During device addressing, execute this slave address code after the device code. www.onsemi.com 15 LE2464C MARKING INFORMATION LE2464CXA WLP6(1.20x0.80) Part ID : 66C Lot Number : 3digits 66C Lot ORDERING INFORMATION Device LE2464CXATBG Package Shipping (Qty / Packing) WLCSP6, 0.80x1.20 (Pb-Free / Halogen Free) 5000 / Tape &Reel † For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF * I2C Bus is a trademark of Philips Corporation. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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