ispLSI 3448 ® In-System Programmable High Density PLD Functional Block Diagram J3 J2 J1 ... J0 Output Routing Pool (ORP) H3 Output Routing Pool (ORP) H1 H0 G3 D Q D Q K1 G2 OR Array D Q K2 G1 K3 D Q D Q OR Array Twin GLB G0 D Q ... • ispLSI FEATURES: — 5V In-System Programmable (ISP™) Using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging H2 K0 ... • HIGH-PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 90 MHz Maximum Operating Frequency — tpd = 12 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power Output Routing Pool (ORP) D Q D Q D3 N0 D2 N1 Global Routing Pool (GRP) N2 D1 D0 N3 A0 A1 A2 A3 Output Routing Pool (ORP) C0 ... C1 Output Routing Pool (ORP) Output Routing Pool (ORP) Boundary Scan C2 Output Routing Pool (ORP) • HIGH-DENSITY PROGRAMMABLE LOGIC — 224 I/O — 20000 PLD Gates — 672 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic AND Array Features C3 Output Routing Pool (ORP) • 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE 0139/3448 • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Five Dedicated Clock Inputs — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible I/O Placement — Optimized Global Routing Pool Provides Global Interconnectivity Description The ispLSI 3448 is a High-Density Programmable Logic Device containing 672 Registers, 224 Universal I/Os, five Dedicated Clock Inputs, 14 Output Routing Pools (ORP) and a Global Routing Pool (GRP) which allows complete inter-connectivity between all of these elements. The ispLSI 3448 features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 3448 offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 3448 device is the Twin Generic Logic Block (Twin GLB) labelled A0, A1...N3. There are a total of 56 of these Twin GLBs in the ispLSI 3448 device. Each Twin GLB has 24 inputs, a programmable AND array and two OR/Exclusive-OR Arrays, and eight outputs which can be configured to be either combinatorial or registered. All Twin GLB inputs come from the GRP. • ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 3448_06 1 February 2000 Specifications ispLSI 3448 Functional Block Diagram Input Bus Input Bus Input Bus Input Bus Output Routing Pool Output Routing Pool Output Routing Pool Output Routing Pool TOE TMS/MODE TCK/SCLK BSCAN/ispEN I/O 163 I/O 162 I/O 161 I/O 160 I/O 167 I/O 166 I/O 165 I/O 164 I/O 171 I/O 170 I/O 169 I/O 168 I/O 175 I/O 174 I/O 173 I/O 172 I/O 179 I/O 178 I/O 177 I/O 176 I/O 183 I/O 182 I/O 181 I/O 180 I/O 187 I/O 186 I/O 185 I/O 184 I/O 191 I/O 190 I/O 189 I/O 188 I/O 195 I/O 194 I/O 193 I/O 192 I/O 199 I/O 198 I/O 197 I/O 196 I/O 203 I/O 202 I/O 201 I/O 200 I/O 207 I/O 206 I/O 205 I/O 204 I/O 211 I/O 210 I/O 209 I/O 208 I/O 215 I/O 214 I/O 213 I/O 212 I/O 219 I/O 218 I/O 217 I/O 216 I/O 223 I/O 222 I/O 221 I/O 220 GOE1 GOE0 Figure 1. ispLSI 3448 Functional Block Diagram Boundary Scan TDI/SDI TRST TDO/SDO I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 Input Bus I/O 32 I/O 33 I/O 34 I/O 35 M3 M2 M1 M0 L3 L2 L1 L0 K3 K2 K1 K0 I/O 159 I/O 158 I/O 157 I/O 156 A1 J2 A2 J1 A3 J0 I/O 147 I/O 146 I/O 145 I/O 144 B0 I3 I/O 143 I/O 142 I/O 141 I/O 140 B1 I2 I1 Input Bus Global Routing Pool (GRP) B2 Input Bus J3 Output Routing Pool A0 I/O 155 I/O 154 I/O 153 I/O 152 I/O 151 I/O 150 I/O 149 I/O 148 I/O 139 I/O 138 I/O 137 I/O 136 I/O 135 I/O 134 I/O 133 I/O 132 B3 I0 I/O 131 I/O 130 I/O 129 I/O 128 C0 H3 I/O 127 I/O 126 I/O 125 I/O 124 C1 H2 C2 H1 C3 H0 D0 D1 D2 D3 E0 E1 E2 E3 F0 F1 F2 F3 G0 G1 G2 Input Bus I/O 28 I/O 29 I/O 30 I/O 31 N0 Output Routing Pool I/O 24 I/O 25 I/O 26 I/O 27 N1 Output Routing Pool I/O 20 I/O 21 I/O 22 I/O 23 Input Bus I/O 16 I/O 17 I/O 18 I/O 19 N2 G3 Output Routing Pool Output Routing Pool Output Routing Pool Output Routing Pool Input Bus Input Bus Input Bus Input Bus Y0 Y1 Y2 Y3 Y4 I/O 108 I/O 109 I/O 110 I/O 111 I/O 104 I/O 105 I/O 106 I/O 107 I/O 100 I/O 101 I/O 102 I/O 103 I/O 96 I/O 97 I/O 98 I/O 99 I/O 92 I/O 93 I/O 94 I/O 95 I/O 88 I/O 89 I/O 90 I/O 91 I/O 84 I/O 85 I/O 86 I/O 87 I/O 80 I/O 81 I/O 82 I/O 83 I/O 76 I/O 77 I/O 78 I/O 79 I/O 72 I/O 73 I/O 74 I/O 75 I/O 68 I/O 69 I/O 70 I/O 71 I/O 64 I/O 65 I/O 66 I/O 67 I/O 60 I/O 61 I/O 62 I/O 63 I/O 56 I/O 57 I/O 58 I/O 59 I/O 52 I/O 53 I/O 54 I/O 55 I/O 48 I/O 49 I/O 50 I/O 51 RESET 0130/3448 2 I/O 123 I/O 122 I/O 121 I/O 120 I/O 119 I/O 118 I/O 117 I/O 116 I/O 115 I/O 114 I/O 113 I/O 112 CLK0 CLK1 CLK2 IOCLK1 IOCLK0 I/O 12 I/O 13 I/O 14 I/O 15 Output Routing Pool I/O 8 I/O 9 I/O 10 I/O 11 Output Routing Pool I/O 4 I/O 5 I/O 6 I/O 7 Input Bus I/O 0 I/O 1 I/O 2 I/O 3 Output Routing Pool N3 Specifications ispLSI 3448 Description (continued) Clocks in the ispLSI 3448 device are provided through five dedicated signals. Three clocks are provided for the Twin GLBs and the remaining two clocks are provided for the I/O cells. All local logic block outputs are brought back into the GRP so they can be connected to the inputs of any other logic block on the device. The device also has 224 I/O cells, each of which is directly connected to an I/O ball. Each I/O cell can be individually programmed to be a combinatorial input, a registered input, a latched input, an output or a bidirectional I/O with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. The table below lists key attributes of the device along with the number of resources available. An additional feature of the ispLSI 3448 is the Boundary Scan capability, which is composed of cells connected between the on-chip system logic and the device’s inputs and outputs. All I/O have associated boundary scan registers, with 3-state I/O using three boundary scan registers and inputs using one. The 224 I/O cells are grouped into 14 sets of 16 bits. Each of these I/O groups is associated with a logic Megablock through the use of the ORP. Each Megablock is able to provide one Product Term Output Enable (PTOE) signal which is globally distributed to all I/O cells. That PTOE signal can be generated within any GLB in the Megablock. Each I/O cell can select one of 16 available OEs (two Global OEs and 14 PTOEs). The ispLSI 3448 supports all IEEE 1149.1 mandatory instructions, which include BYPASS, EXTEST and SAMPLE. Key Attributes of the ispLSI 3448 Attribute Four Twin GLBs, 16 I/O cells and one ORP are connected together to make a logic Megablock. The Megablock is defined by the resources that it shares. The outputs of the four Twin GLBs are connected to a set of 16 I/O cells by the ORP. The ispLSI 3448 device contains 14 of these Megablocks. The GRP has as its inputs the outputs from all of the Twin GLBs and all of the inputs from the bidirectional I/O cells. All of these signals are made available to the inputs of the Twin GLBs. Delays through the GRP have been equalized to minimize timing skew and logic glitching. Quantity Twin GLBs 56 Registers 672 I/O 224 Global Clocks 5 Global OE 2 Test OE 1 Table 1-0003/3448 3 Specifications ispLSI 3448 Absolute Maximum Ratings 1 Supply Voltage Vcc .................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 140°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition TA VCC VIL VIH MIN. PARAMETER SYMBOL MAX. UNITS 0 70 °C 4.75 5.25 V Input Low Voltage 0 0.8 V Input High Voltage 2.0 VCC +1 Ambient Temperature Supply Voltage V Table 2-0005/3448 Capacitance (TA=25°C,f=1.0 MHz) TYPICAL UNITS I/O Capacitance 10 pf VCC = 5.0V, VI/O = 2.0V Clock Capacitance 11 pf VCC = 5.0V, VY = 2.0V SYMBOL C1 C2 PARAMETER TEST CONDITIONS Table 2-0006/3320 Data Retention Specifications PARAMETER MINIMUM MAXIMUM UNITS 20 – Years 10000 – Cycles Data Retention ispLSI Erase/Reprogram Cycles Table 2-0008/3320 4 Specifications ispLSI 3448 Switching Test Conditions Input Pulse Levels Figure 2. Test Load GND to 3.0V + 5V ≤ 3 ns 10% to 90% Input Rise and Fall Time Input Timing Reference Levels 1.5V Ouput Timing Reference Levels 1.5V Output Load R1 Device Output See Figure 2 Table 2-0003/3448 3-state levels are measured 0.5V from steady-state active level. Test Point R2 C L* *CL includes Test Fixture and Probe Capacitance. Output Load conditions (See Figure 2) 0213A TEST CONDITION A B C R1 R2 CL 470Ω 390Ω 35pF Active High ∞ 390Ω 35pF Active Low 470Ω 390Ω 35pF Active High to Z at VOH -0.5V ∞ 390Ω 5pF Active Low to Z at VOL +0.5V 470Ω 390Ω 5pF Table 2 - 0004A DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2, 4 CONDITION PARAMETER 3 MIN. TYP. MAX. UNITS Output Low Voltage IOL= 8 mA – – 0.4 V Output High Voltage IOH = -4 mA 2.4 – – V Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (Max.) – – -10 µA Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC – – 10 µA ispEN Input Low Leakage Current 0V ≤ VIN ≤ VIL – – -150 µA I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 µA Output Short Circuit Current VCC = 5V, VOUT = 0.5V – – -200 mA Operating Power Supply Current VIL = 0.0V, VIH = 3.0V, fCLOCK = 1 MHz – 470 – mA Table 2-0007/3448 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Guaranteed but not 100% tested. 2. Measured using 28 16-bit counters. 3. Typical values are at VCC = 5V and TA= 25°C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I CC . 5 Specifications ispLSI 3448 External Switching Characteristics1, 2, 3 Over Recommended Operating Conditions 5 PARAMETER tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis ttoeen ttoedis twh twl tsu3 th3 1. 2. 3. 4. 5. TEST #2 COND. DESCRIPTION -70 -90 1 MIN. MAX. MIN. MAX. UNITS A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 12.0 – 15.0 ns A 2 Data Propagation Delay – 15.0 – 18.0 ns 90.0 – 70.0 – MHz 62.5 – 50.0 – MHz 100 – 83.0 – MHz 7.0 – 9.0 – ns A – 3 Clock Frequency with Internal Feedback 3 4 Clock Frequency with External Feedback ( 1 tsu2 + tco1 ) 4 – 5 Clock Frequency, Maximum Toggle – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass A 7 GLB Reg. Clock to Output Delay, ORP Bypass – 7.5 – 9.0 ns – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – 0.0 – ns – 9 GLB Reg. Setup Time before Clock 8.5 – 11.0 – ns – 10 GLB Reg. Clock to Output Delay – 8.0 – 10.0 ns – 11 GLB Reg. Hold Time after Clock 0.0 – 0.0 – ns A 12 Ext. Reset Pin to Output Delay – 14.0 – 15.0 ns – 13 Ext. Reset Pulse Duration 9.0 – 12.0 – ns B 14 Input to Output Enable – 25.0 – 30.0 ns C 15 Input to Output Disable – 25.0 – 30.0 ns B 16 Global OE Output Enable – 10.0 – 12.0 ns C 17 Global OE Output Disable – 10.0 – 12.0 ns B 18 Test OE Output Enable – 13.0 – 15.0 ns C 19 Test OE Output Disable – 13.0 – 15.0 ns – 20 Ext. Synchronous Clock Pulse Duration, High 5.0 – 6.0 – ns – 21 Ext. Synchronous Clock Pulse Duration, Low 5.0 – 6.0 – ns – 22 I/O Reg Setup Time before Ext. Synchronous Clock (Y3, Y4) 4.5 – 5.0 – ns – 23 I/O Reg Hold Time after Ext. Sync Clock (Y3, Y4) 0.0 – 0.0 – ns Unless noted otherwise, all parameters use 20 PTXOR path and ORP. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions section. 6 Table 2-0030/3320 Specifications ispLSI 3448 Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER 2 # DESCRIPTION -70 -90 MIN. MAX. MIN. MAX. UNITS Inputs tiobp tiolat tiosu tioh tioco tior 24 I/O Register Bypass – 2.3 – 3.2 ns 25 I/O Latch Delay – 14.0 – 18.2 ns 26 I/O Register Setup Time before Clock 7.5 – 9.0 – ns 27 I/O Register Hold Time after Clock -3.0 – -4.0 – ns 28 I/O Register Clock to Out Delay – 8.3 – 10.2 ns 29 I/O Register Reset to Out Delay – 8.3 – 10.2 ns 30 GRP Delay – 3.2 – 3.5 ns 31 Feedback Delay – 1.0 – 1.6 ns 32 4 Product Term Bypass Path Delay (Comb.) – 4.0 – 5.3 ns 33 4 Product Term Bypass Path Delay (Reg.) – 3.5 – 3.8 ns 34 1 Product Term/XOR Path Delay – 5.0 – 5.8 ns 35 20 Product Term/XOR Path Delay – 5.0 – 5.8 ns – 6.2 – 7.3 ns – 0.5 – 0.5 ns 38 GLB Register Setup Time before Clock 1.5 – 2.5 – ns 39 GLB Register Hold Time after Clock 5.4 – 6.3 – ns 40 GLB Register Clock to Output Delay – 0.5 – 1.0 ns 41 GLB Register Reset to Output Delay – 1.0 – 1.0 ns 42 GLB Product Term Reset to Register Delay – 8.9 – 10.5 ns 43 GLB Product Term Output Enable to I/O Cell Delay – 15.0 – 18.3 ns 3.7 3.7 4.5 4.5 ns 45 ORP Delay – 1.5 – 2.0 ns 46 ORP Bypass Delay – 0.0 – 0.0 ns GRP tgrp tfeedback GLB t4ptbp t4ptbr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck 36 XOR Adjacent Path Delay 3 37 GLB Register Bypass Delay 44 GLB Product Term Clock Delay ORP torp torpbp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. 7 Table 2-0036/3448 Specifications ispLSI 3448 Internal Timing Parameters1 Over Recommended Operating Conditions PARAMETER 2 # DESCRIPTION -90 -70 MIN. MAX. MIN. MAX. UNITS Outputs tob tobs toen todis 47 Output Buffer Delay – 2.5 – 3.0 ns 48 Output Buffer Delay, Slew Limited Adder – 13.0 – 13.0 ns 49 I/O Cell OE to Output Enabled – 4.5 – 5.0 ns 50 I/O Cell OE to Output Disabled – 4.5 – 5.0 ns 51 Clock Delay, Y0 or Y1 or Y2 to Global GLB Clock Line 3.5 3.5 4.0 4.0 ns 52 Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line 3.0 3.0 4.0 4.0 ns 53 Global Reset to GLB and I/O Registers – 9.0 – 9.0 ns 54 Global OE Pad Buffer – 5.5 – 7.0 ns 55 Test OE Pad Buffer – 8.5 – 10.0 ns Clocks tgy0/1/2 tioy3/4 Global Reset tgr tgoe ttoe 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 8 Table 2-0037/3448 Specifications ispLSI 3448 ispLSI 3448 Timing Model I/O Cell GRP GLB Feedback ORP I/O Cell #31 #32 I/O Reg Bypass I/O (Input) #24 #53 GRP #30 Input D Register Q RST #25 - 29 4 PT Bypass GLB Reg Bypass ORP Bypass #33 #37 #46 20 PT XOR Delays GLB Reg Delay ORP Delay D #34 - 36 Q #45 RST #53 Reset Y3,4 #38 - 41 #52 Control RE PTs OE #42 - 44 CK #51 Y0,1,2 #54 GOE0,1 #55 TOE 0902/3448 Derivations of tsu, th and tco from the Product Term Clock 1 tsu = = = 2.8 ns = Logic + Reg su - Clock (min) (tiobp + tgrp + t20ptxor) + (tgsu) - (tiobp + tgrp + tptck(min)) (#24+ #30+ #35) + (#38) - (#24+ #30+ #44) (2.3 + 3.2 + 5.0) + (1.5) - (2.3 + 3.2 + 3.7) th = = = 4.1 ns = Clock (max) + Reg h - Logic (tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor) (#24+ #30+ #44) + (#39) - (#24+ #30+ #35) (2.3 + 3.2 + 3.7) + (5.4) - (2.3 + 3.2 + 5.0) tco = = = 13.7 ns = Clock (max) + Reg co + Output (tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob) (#24 + #30 + #44) + (#40) + (#45 + #47) (2.3 + 3.2 + 3.7) + (0.5) + (1.5 + 2.5) Table 2-0042/3448 Note: Calculations are based on timing specs for the ispLSI 3448-90L. 9 #47, 48 #49, 50 I/O (Output) Specifications ispLSI 3448 Power Consumption Power consumption in the ispLSI 3448 device depends on two primary factors: the speed at which the device is operating and the number of product terms used. Figure 3 shows the relationship between power and operating speed. Figure 3. Typical Device Power Consumption vs fmax 1000 ispLSI 3448 ICC (mA) 800 600 400 200 0 30 60 90 fmax (MHz) Notes: Configuration of 28 16-bit Counters Typical Current at 5V, 25° C ICC can be estimated for the ispLSI 3448 using the following equation: ICC = 60 + (# of PTs * 0.46) + (# of nets * Max. freq * 0.01) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127A/3448 10 Specifications ispLSI 3448 Signal Description Signal Name I/O Description Input/Output – These are the general purpose I/O used by the logic array. GOE0, GOE1 Global Output Enable inputs. TOE Test Output Enable pin – This pin tristates all I/O pins when a logic low is driven. RESET Active Low (0) Reset which resets all of the GLB and I/O registers in the device. Y0, Y1, Y2 Dedicated Clock inputs connect to one of the clock inputs of all the GLBs on the device. Y3, Y4 Dedicated Clock inputs connect to one of the clock inputs of all the I/O cells on the device. BSCAN/ispEN Input – Dedicated in-system programming enable input. When this is high, the BSCAN TAP controller signals TMS, TDI, TDO and TCK are enabled. When this is brought low, the ISP State Machine control signals MODE, SDI, SDO and SLCK are enabled. High-to-low transition will put the device in the programming mode and put all I/O in the high-Z state. TDI/SDI Input – This signal performs two functions. It is the Test Data input signal when ispEN is logic high. When ispEN is logic low, it functions as an input to load programming data into the device. SDI is also used as one of the two control signals for the ISP State Machine. TCK/SCLK Input – This signal performs two functions. It is the Test Clock input signal when ispEN is logic high. When ispEN is logic low, it functions as a clock signal for the Serial Shift Register. TMS/MODE Input – This signal performs two functions. It is the Test Mode Select input signal when ispEN is logic high. When ispEN is logic low, it controls the operation of the ISP State Machine. TRST Input – Test Reset, active low to reset the Boundary Scan State Machine. TDO/SDO Output – This signal performs two functions. When ispEN is logic low, it reads the ISP data. When ispEN is high, it functions as Test Data Out. GND Ground (GND) VCC Vcc NC1 No Connect. Signal Locations Signal 432-Ball BGA GOE0, GOE1 R2, W1 TOE H3 RESET AA31 Y0, Y1, Y2, Y3, Y4 U30, N31, L1, AB3, AF1 BSCAN/ispEN AD29 TDI/SDI K29 TCK/SCLK AG29 TMS/MODE F31 TRST E3 TDO/SDO AH3 GND A1, A2, A16, A30, A31, B1, B5, B9, B13, B19, B23, B27, B31, E2, E30, J2, J30, N2, N30, T1, T31, W2, W30, AC2, AC30, AG2, AG30, AK1, AK5, AK9, AK13, AK19, AK23, AK27, AK31, AL1, AL2, AL16, AL30, AL31 VCC A3, A10, A22, A29, B14, B18, C1, C31, K1, K31, P2, P30, V2, V30, AB1, AB31, AJ1, AJ31, AK14, AK18, AL3, AL10, AL22, AL29 NC1 B2, B3, B30, C3, C7, C11, C14, C18, C21, C25, C29, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, E4, E28, F4, F28, G3, G4, G28, G29, H4, H28, J4, J28, K4, K28, L3, L4, L28, L29, M4, M28, N4, N28, P3, P4, P28, P29, R4, R28, T4, T28, U4, U28, V3, V4, V28, V29, W4, W28, Y4, Y28, AA3, AA4, AA28, AA29, AB4, AB28, AC4, AC28, AD4, AD28, AE3, AE4, AE28, AE29, AF4, AF28, AG4, AG28, AH4, AH5, AH6, AH7, AH8, AH9, AH10, AH11, AH12, AH13, AH14, AH15, AH16, AH17, AH18, AH19, AH20, AH21, AH22, AH23, AH24, AH25, AH26, AH27, AH28, AJ3, AJ7, AJ11, AJ14, AJ18, AJ21, AJ25, AJ29, AK2, AK30 1. NCs are not to be connected to any active signals, VCC or GND. 11 Specifications ispLSI 3448 I/O Locations Signal I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 BGA T30 U29 U31 V31 W31 W29 Y31 Y30 Y29 AA30 AB30 AB29 AC31 AC29 AD31 AD30 AE31 AE30 AF31 AF30 AF29 AG31 AH31 AH30 AJ30 AH29 AJ28 AK29 AK28 AJ27 AL28 AL27 AJ26 AK26 AL26 AK25 AL25 AJ24 Signal I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 I/O 64 I/O 65 I/O 66 I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 I/O 72 I/O 73 I/O 74 I/O 75 BGA AK24 AL24 AJ23 AL23 AJ22 AK22 AK21 AL21 AJ20 AK20 AL20 AJ19 AL19 AL18 AJ17 AK17 AL17 AJ16 AK16 AJ15 AK15 AL15 AL14 AL13 AJ13 AL12 AK12 AJ12 AL11 AK11 AK10 AJ10 AL9 AJ9 AL8 AK8 AJ8 AL7 Signal I/O 76 I/O 77 I/O 78 I/O 79 I/O 80 I/O 81 I/O 82 I/O 83 I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 I/O 96 I/O 97 I/O 98 I/O 99 I/O 100 I/O 101 I/O 102 I/O 103 I/O 104 I/O 105 I/O 106 I/O 107 I/O 108 I/O 109 I/O 110 I/O 111 I/O 112 I/O 113 BGA AK7 AL6 AK6 AJ6 AL5 AL4 AJ5 AK4 AK3 AJ4 AJ2 AH2 AG3 AH1 AG1 AF3 AF2 AE2 AE1 AD3 AD2 AD1 AC3 AC1 AB2 AA2 AA1 Y3 Y2 Y1 W3 V1 U3 U2 U1 T3 T2 R3 12 Signal BGA Signal BGA Signal I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 I/O 121 I/O 122 I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 I/O 128 I/O 129 I/O 130 I/O 131 I/O 132 I/O 133 I/O 134 I/O 135 I/O 136 I/O 137 I/O 138 I/O 139 I/O 140 I/O 141 I/O 142 I/O 143 I/O 144 I/O 145 I/O 146 I/O 147 I/O 148 I/O 149 I/O 150 I/O 151 R1 P1 N1 N3 M1 M2 M3 L2 K2 K3 J1 J3 H1 H2 G1 G2 F1 F2 F3 E1 D1 D2 C2 D3 C4 B4 C5 A4 A5 C6 B6 A6 B7 A7 C8 B8 A8 C9 I/O 152 I/O 153 I/O 154 I/O 155 I/O 156 I/O 157 I/O 158 I/O 159 I/O 160 I/O 161 I/O 162 I/O 163 I/O 164 I/O 165 I/O 166 I/O 167 I/O 168 I/O 169 I/O 170 I/O 171 I/O 172 I/O 173 I/O 174 I/O 175 I/O 176 I/O 177 I/O 178 I/O 179 I/O 180 I/O 181 I/O 182 I/O 183 I/O 184 I/O 185 I/O 186 I/O 187 I/O 188 I/O 189 A9 C10 B10 B11 A11 C12 B12 A12 C13 A13 A14 C15 B15 A15 C16 B16 C17 B17 A17 A18 A19 C19 A20 B20 C20 A21 B21 B22 C22 A23 C23 A24 B24 C24 A25 B25 A26 B26 I/O 190 I/O 191 I/O 192 I/O 193 I/O 194 I/O 195 I/O 196 I/O 197 I/O 198 I/O 199 I/O 200 I/O 201 I/O 202 I/O 203 I/O 204 I/O 205 I/O 206 I/O 207 I/O 208 I/O 209 I/O 210 I/O 211 I/O 212 I/O 213 I/O 214 I/O 215 I/O 216 I/O 217 I/O 218 I/O 219 I/O 220 I/O 221 I/O 222 I/O 223 BGA C26 A27 A28 C27 B28 B29 C28 D29 C30 D30 E29 D31 E31 F29 F30 G30 G31 H29 H30 H31 J29 J31 K30 L30 L31 M29 M30 M31 N29 P31 R29 R30 R31 T29 Specifications ispLSI 3448 Signal Configuration ispLSI 3448 432-Ball BGA Signal Diagram 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A GND GND VCC I/O 192 I/O 191 I/O 188 I/O 186 I/O 183 I/O 181 VCC I/O 177 I/O 174 I/O 172 I/O 171 I/O 170 GND I/O 165 I/O 162 I/O 161 I/O 159 I/O 156 VCC I/O 152 I/O 150 I/O 147 I/O 145 I/O 142 I/O 141 VCC GND GND A B GND NC1 I/O 195 I/O 194 GND I/O 189 I/O 187 I/O 184 GND I/O 179 I/O 178 I/O 175 GND VCC I/O 169 I/O 167 I/O 164 VCC GND I/O 158 I/O 155 I/O 154 GND I/O 149 I/O 146 I/O 144 GND I/O 139 NC1 NC1 GND B C VCC I/O 198 NC 1 I/O 196 I/O 193 I/O 190 NC 1 I/O 185 I/O 182 I/O 180 NC 1 I/O 176 I/O 173 NC 1 I/O 168 I/O 166 I/O 163 NC 1 I/O 160 I/O 157 NC 1 I/O 153 I/O 151 I/O 148 NC 1 I/O 143 I/O 140 I/O 138 NC 1 I/O 136 VCC C D I/O 201 I/O 199 I/O 197 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 I/O 137 I/O 135 I/O 134 D E I/O 202 GND I/O 200 NC1 NC1 TRST GND I/O 133 E F MODE/ TMS I/O 204 I/O 203 NC1 NC1 I/O 132 I/O 131 I/O 130 F G I/O 206 I/O 205 NC 1 1 1 1 I/O 129 I/O 128 G H I/O 209 I/O 208 I/O 207 NC1 NC1 TOE I/O 127 I/O 126 H J I/O 211 GND I/O 210 NC1 NC1 I/O 125 GND I/O 124 J K VCC I/O 212 TDI/ SDI NC 1 1 I/O 123 I/O 122 VCC K L I/O 214 I/O 213 NC1 NC1 NC1 NC1 I/O 121 Y2 L M I/O 217 I/O 216 I/O 215 NC1 NC1 I/O 120 I/O 119 I/O 118 M N Y1 GND I/O 218 NC1 NC1 I/O 117 GND I/O 116 N P I/O 219 VCC NC 1 1 1 1 VCC I/O 115 P R I/O 222 I/O 221 I/O 220 NC1 NC1 I/O 113 GOE 0 I/O 114 R T GND I/O 0 I/O 223 NC1 NC1 U I/O 2 Y0 I/O 1 NC V I/O 3 VCC NC1 W I/O 4 GND Y I/O 6 I/O 7 AA RESET I/O 9 NC AB VCC I/O 10 I/O 11 AC I/O 12 GND I/O 13 AD I/O 14 I/O 15 AE I/O 16 I/O 17 NC AF I/O 18 I/O 19 I/O 20 AG I/O 21 AH I/O 22 I/O 23 AJ VCC I/O 24 NC AK GND NC1 AL GND GND NC NC NC NC NC ispLSI 3448 NC NC I/O 111 I/O 112 GND T 1 I/O 108 I/O 109 I/O 110 U NC1 NC1 NC1 VCC I/O 107 V I/O 5 NC1 NC1 I/O 106 GND GOE 1 W I/O 8 NC1 NC1 I/O 103 I/O 104 I/O 105 Y 1 1 NC 1 I/O 101 I/O 102 AA NC1 NC1 Y3 I/O 100 VCC AB NC1 NC1 I/O 98 GND I/O 99 AC ispEN/ NC1 BSCAN NC 1 I/O 95 I/O 96 I/O 97 AD NC 1 I/O 93 I/O 94 AE 1 1 GND TCK/ SCLK I/O 25 NC NC Bottom View 1 NC 1 NC 1 NC1 NC1 I/O 91 I/O 92 Y4 AF NC1 NC1 I/O 88 GND I/O 90 AG TDO/ SDO AH NC1 NC1 NC1 I/O 26 I/O 29 I/O 32 NC I/O 27 I/O 28 GND I/O 33 VCC I/O 30 I/O 31 I/O 34 1 NC NC1 NC1 NC1 NC1 I/O 37 I/O 40 I/O 42 NC I/O 35 I/O 38 GND I/O 43 I/O 36 I/O 39 I/O 41 VCC 1 NC1 NC1 NC1 I/O 46 I/O 49 NC I/O 44 I/O 47 GND I/O 45 I/O 48 I/O 50 1 NC1 NC1 NC1 NC1 I/O 52 I/O 55 I/O 57 NC VCC I/O 53 I/O 56 I/O 58 I/O 51 I/O 54 GND I/O 59 1 NC1 NC1 NC1 NC1 I/O 69 I/O 71 I/O 74 NC I/O 67 I/O 68 GND I/O 73 I/O 66 VCC I/O 70 9 NC1 NC1 I/O 62 I/O 65 NC VCC GND I/O 64 I/O 60 I/O 61 I/O 63 1 NC1 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1. NCs are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package. 13 NC1 I/O 87 I/O 89 I/O 86 VCC AJ I/O 84 NC1 GND AK VCC GND GND AL 3 2 NC1 NC1 NC1 I/O 79 I/O 82 I/O 85 NC I/O 76 I/O 78 GND I/O 83 I/O 72 I/O 75 I/O 77 I/O 80 I/O 81 8 7 6 5 4 1 1 1 Specifications ispLSI 3448 Part Number Description ispLSI 3448 – XX X XXXX X Device Family Grade Blank = Commercial Device Number Package B432 = BGA Speed 90 = 90 MHz fmax 70 = 70 MHz fmax Power L = Low 0212/3448 Ordering Information COMMERCIAL FAMILY ispLSI fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE 90 12 ispLSI 3448-90LB432 432-Ball BGA 70 15 ispLSI 3448-70LB432 432-Ball BGA Table 2-0041/3448 14