E-CMOS EC24C64A 32k/64k-bit 2-wire serial cmos eeprom Datasheet

EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
General Description
Features
The EC24C32A/EC24C64A provides 32,768/65,536
bits of serial electrically erasable and programmable
read-only memory (EEPROM) organized as 4096
/8192 words of 8 bits each. The device is optimized
for use in many industrial and commercial applications where low-power and low-voltage operation are
essential.
The EC24C32A/EC24C64A is available in space saving PDIP-8,SOP-8,TSSOP-8,MSOP-8 and DFN-8
(only EC24C32A) packages and is accessed via a
two-wire serial interface.
 Wide Voltage Operation
- VCC = 1.7V to 5.5V
 Operating Ambient Temperature: -40°C to +85°C
 Internally Organized:
- EC24C32A, 4096 X 8 (32K bits)
- EC24C64A, 8192 X 8 (64K bits)
 Two-wire Serial Interface
 Schmitt Trigger, Filtered Inputs for Noise
Suppression
 Bidirectional Data Transfer Protocol
 1 MHz (5V), 400 kHz (1.7V, 2.5V, 2.7V)
Compatibility
 Write Protect Pin for Hardware Data Protection
 32-byte Page (32K, 64K) Write Modes
 Partial Page Writes Allowed
 Self-timed Write Cycle (5 ms max)
 High-reliability
- Endurance: 1 Million Write Cycles
- Data Retention: 100 Years
 PDIP-8, SOP-8, TSSOP-8, MSOP-8 and DFN-8
packages
Pin Configuration
SOP-8
TSSOP-8
DFN-8
MSOP-8
(EC24C32A/64A)
(EC24C32A/64A)
(only for EC24C32A)
(EC24C32A/64A)
Top-View
Top-View
Bottom view
Top-View
PDIP-8
Pin Name
A0 - A2
SDA
SDA
SCL
SCL
GND
WP
WP
GND
VCC
VCC
(EC24C32A/64A)
Functions
Write Protect
Address
Inputs
Address
Inputs
Serial Data
Serial
Data
Serial Clock Input
Serial
Clock
Input
Write
Protect
Ground
Ground
Power Supply
Power Supply
Top-View
E-CMOS Corp. (www.ecmos.com.tw)
Page 1 of 17
5F18N-Rev.F003
EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
Block Diagram
E-CMOS Corp. (www.ecmos.com.tw)
Page 2 of 17
5F18N-Rev.F003
EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
Pin Descriptions
DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are
hard-wired for the EC24C32A/EC24C64A. Eight 32K/64K devices may be addressed on a single bus system
(device addressing is discussed in detail under the Device Addressing section).
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and
may be wire-ORed with any number of other open-drain or open- collector devices.
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and
negative edge clock data out of each device.
WRITE PROTECT (WP): The EC24C32A/EC24C64A has a Write Protect pin that provides hardware data
protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When
the Write Protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the
following Table.
Write Protect
WP Pin Status
At VCC
At GND
Part of the Array Protected
EC24C32A
EC24C64A
Full (32K) Array
Full (64K) Array
Normal Read / Write Operations
Ordering Information
Available package types
Part Number
EC24C32A
EC24C64A
SOP-8
V
V
E-CMOS Corp. (www.ecmos.com.tw)
TSSOP-8
V
V
DFN-8
V
--
Page 3 of 17
MSOP-8
V
V
PDIP-8
V
V
5F18N-Rev.F003
EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
Marking Information
Package type
Part Number
SOP-8
EC24CXXANM1GX
TSSOP-8
EC24CXXANE1GX
MSOP-8
EC24CXXANR1GX
PDIP-8
EC24CXXANP1GX
DFN-8
EC24C32ANF2GX
Marking
24CXXA
LLLLL
YYWWT
C32A
LLLL
Marking Information
XX is the memory of production.
LLLLL is the last five numbers of wafer lot number
YYWW is Date Code.
T is tracking Code ,T=X
LLLL is the last four numbers of wafer lot number
Memory Organization
EC24C32A, 32K SERIAL EEPROM: Internally organized with 128 pages of 32 bytes each, the 32K requires an 12bit data word address for random word addressing.
EC24C64A, 64K SERIAL EEPROM: Internally organized with 256 pages of 32 bytes each, the 64K requires a 13bit data word address for random word address
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (see to Figure 1). Data changes during SCL high periods will
indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any
other command (see to Figure 2).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power mode (see to Figure2).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock
cycle (see to Figure 3).
STANDBY MODE: The EC24C32A/EC24C64A features a low-power standby mode which is enabled:
(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by
following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
E-CMOS Corp. (www.ecmos.com.tw)
Page 4 of 17
5F18N-Rev.F003
EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
Figure 1: Data Validity
Figure 2: Start and Stop Definition
E-CMOS Corp. (www.ecmos.com.tw)
Page 5 of 17
5F18N-Rev.F003
EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
Figure 3: Output Acknowledge
Device Addressing
The 32K and 64K EEPROM devices all require an 8-bit device address word following a start condition to enable
the chip for a read or write operation (see to Figure 4).
The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown.
This is common to all the Serial EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 32K/64K EEPROM. These 3 bits must compare to
their corresponding hard-wired input pins.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is
high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return
to a standby state.
DATA SECURITY: The EC24C32A /EC24C64A has a hardware data protection scheme that allows the user to
write protect the entire memory when the WP pin is at VCC.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first
8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device,
such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters
an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the
EEPROM will not respond until the write is complete (see to Figure 5).
PAGE WRITE: The 32K/64K EEPROM is capable of an 32-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the
first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the
microcontroller can transmit up to 31 (32K/64K) more data words. The EEPROM will respond with a "0" after each
data word received. The microcontroller must terminate the page write sequence with a stop condition (see to
Figure 6).
E-CMOS Corp. (www.ecmos.com.tw)
Page 6 of 17
5F18N-Rev.F003
EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
The data word address lower five (32K/64K) bits are internally incremented following the receipt of each data word.
The higher data word address bits are not incremented, retaining the memory page row location. When the word
address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same
page. If more than 32 (32K/64K) data and previous data will be overwritten. words are transmitted to the
EEPROM, the data word address will "roll over" and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are
disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device
address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has
completed will the EEPROM respond with a "0", allowing the read or write sequence to continue.
Figure 4: Device Address
Figure 5: Byte Write
Figure 6: Page Write
E-CMOS Corp. (www.ecmos.com.tw)
Page 7 of 17
5F18N-Rev.F003
EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit
in the device address word is set to "1". There are three read operations: current address read, random
address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed
during the last read or write operation, increased by one.
This address stays valid between operations as long as the chip power is maintained. The address "roll over"
during read is from the last byte of the last memory page to the first byte of the first page. The address "roll
over" during write is from the last byte of the current page to the first byte of the same page.
Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the
EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an
input "0" but does generate a following stop condition (see to Figure 7).
RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address.
Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another start condition. The microcontroller now initiates a current address read
by sending a device address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond with a "0" but does
generate a following stop condition (see to Figure 8).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address
read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the
EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out
sequential data words. When the memory address limit is reached, the data word address will "roll over" and
the sequential read will continue. The sequential read operation is terminated when the microcontroller does
not respond with a "0" but does generate a following stop condition (see to Figure 9).
E-CMOS Corp. (www.ecmos.com.tw)
Page 8 of 17
5F18N-Rev.F003
EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
Figure 7: Current Address Read
Figure 8: Random Read
Figure 9: Sequential Read
E-CMOS Corp. (www.ecmos.com.tw)
Page 9 of 17
5F18N-Rev.F003
EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
Electrical Characteristics
Absolute Maximum Stress Ratings
DC Supply Voltage ---------------------------------------------------------------------------------------- -0.3V to +6.5V
Input / Output Voltage ------------------------------------------------------------------------------------- GND-0.3V to VCC+0.3V
Operating Ambient Temperature ---------------------------------------------------------------------- -40°C to +85°C
Storage Temperature ------------------------------------------------------------------------------------- -65°C to +150°C
Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this device at these or any other conditions above those
indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics
Applicable over recommended operating range from: T A = -40°C to +85°C , VCC = +1.7V to +5.5V
(unless otherwise noted)
Parameter
Supply Voltage
Supply Current VCC = 5.0V
Supply Current VCC = 5.0V
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Level
Input High Level
Input Low Level
Input High Level
Output Low Level VCC =5.0V
Output Low Level VCC =3.0V
Output Low Level VCC =1.7V
Symbol
VCC
ICC1
ICC2
ISB
ILI
ILO
VIL1
VIH1
VIL2
VIH2
VOL3
VOL2
VOL1
Min.
1.7
Typ.
0.4
2.0
0.05
-0.3
VCC x 0.7
-0.3
VCC x 0.7
Max.
5.5
1.0
3.0
3.0
3.0
3.0
VCC x 0.3
VCC + 0.3
VCC x 0.2
VCC + 0.3
0.4
0.4
0.2
Unit
V
mA
mA
μA
μA
μA
V
V
V
V
V
V
V
Condition
READ at 400 kHz
WRITE at 400 kHz
VIN = VCC or GND
VIN = VCC or GND
VOUT = VCC or GND
VCC = 1.8V to 5.5V
VCC = 1.8V to 5.5V
VCC = 1.7V
VCC = 1.7V
IOL = 3.0 mA
IOL = 2.1 mA
IOL = 0.15 mA
Pin Capacitance
Applicable over recommended operating range from TA = 25°C , f = 1.0 MHz, VCC = +1.7V
Parameter
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
E-CMOS Corp. (www.ecmos.com.tw)
Symbol
CI/O
CIN
Min.
-
Page 10 of 17
Typ.
-
Max.
8
6
Unit
pF
pF
Condition
VI/O = 0V
VIN = 0V
5F18N-Rev.F003
EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
AC Electrical Characteristics
Applicable over recommended operating range from T A = -40°C to +85°C, VCC = +1.7V to +5.5V, CL = 1 TTL
Gate and 100 pF (unless otherwise noted)
Parameter
Symbol
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
Clock Low to Data Out Valid
Time the bus must be free before
a new transmission can start
Start Hold Time
Start Setup Time
Data In Hold Time
Data In Setup Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Setup Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Byte Mode
fSCL
tLOW
tHIGH
tI
tAA
1.7V≦VCC < 2.5V
Min.
Typ. Max.
400
1.2
0.6
50
0.05
0.9
2.5V≦VCC ≦5.5V
Min.
Typ. Max.
1000
0.6
0.4
40
0.05
0.55
tBUF
1.2
-
-
0.5
-
-
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
tWR
Endurance
0.6
0.6
0
100
0.6
50
1M
1.5
-
0.3
300
5
-
0.25
0.25
0
100
0.25
50
-
1.5
-
0.3
100
5
-
Units
kHz
μs
μs
ns
μs
μs
μs
μs
μs
ns
μs
ns
μs
ns
ms
Write Cycles
Note
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3kΩ (2.5V, 5V), 10kΩ (1.7V)
Input pulse voltages: 0.3 x VCC to 0.7 x VCC
Input rise and fall time: ≦50 ns
Input and output timing reference voltages: 0.5 x VCC
The value of RL should be concerned according to the actual loading on the user's system.
E-CMOS Corp. (www.ecmos.com.tw)
Page 11 of 17
5F18N-Rev.F003
EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
Bus Timing
Figure 10: SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
Figure 11: SCL: Serial Clock, SDA: Serial Data I/O
Note
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal
clear/write cycle.
E-CMOS Corp. (www.ecmos.com.tw)
Page 12 of 17
5F18N-Rev.F003
EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
Mechanical Dimensions
OUTLINE DRAWING PDIP - 8
Available package types : EC24C32A/64A
Top View
Side View
Section B - B
E-CMOS Corp. (www.ecmos.com.tw)
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
A1
A2
A3
b
b1
B
c
c1
D
E1
e
eA
eB
eC
L
Page 13 of 17
MIN
3.60
0.51
3.10
1.50
0.44
0.43
MAX
4.00
3.50
1.70
0.53
0.48
1.52 BSC
0.25
0.24
9.05
6.15
0.31
0.26
9.45
6.55
2.54 BSC
7.62 BSC
7.62
0
3.00
9.50
0.94
-
5F18N-Rev.F003
EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
Mechanical Dimensions
OUTLINE DRAWING SOP - 8
Available package types : EC24C32A/64A
Top View
Side View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
A1
B
C
D
E1
E
e
L
θ
E-CMOS Corp. (www.ecmos.com.tw)
Page 14 of 17
MIN
1.35
0.10
0.31
0.17
4.70
3.80
5.79
MAX
1.75
0.25
0.51
0.25
5.10
4.00
6.20
1.27 BSC
0.40
0°
1.27
8°
5F18N-Rev.F003
EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
Mechanical Dimensions
OUTLINE DRAWING TSSOP - 8
Available package types:EC24C32A/64A
Top View
Side View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
D
E
E1
A
A2
b
e
L
L1
θ
E-CMOS Corp. (www.ecmos.com.tw)
Page 15 of 17
MIN
2.80
6.20
4.20
0.80
0.19
MAX
3.20
6.60
4.60
1.20
1.15
0.30
0.65 BSC
0.45
0.75
1.00 BSC
0°
8°
5F18N-Rev.F003
EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
Mechanical Dimensions
OUTLINE DRAWING DFN - 8
Available package types: EC24C32A
Top View
End View
Side View
Bottom View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
A1
b
c
D
D2
e
Nd
E
E2
L
h
MIN
0.70
0.18
0.18
1.90
MAX
0.80
0.05
0.30
0.25
2.10
1.50 REF
0.50 BSC
1.50 BSC
2.90
3.10
1.60 BSC
0.30
0.20
E-CMOS Corp. (www.ecmos.com.tw)
0.50
0.30
Page 16 of 17
5F18N-Rev.F003
EC24C32A/64A
32K/64K-bit 2-WIRE SERIAL CMOS EEPROM
Mechanical Dimensions
OUTLINE DRAWING MSOP - 8
Available package types : EC24C32A/64A
End View
Top View
Side View
Section B -B
E-CMOS Corp. (www.ecmos.com.tw)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
A1
A2
A3
b
b1
c
c1
D
E
E1
e
L
L1
θ
Page 17 of 17
MIN
0.05
0.75
0.30
0.29
0.28
0.15
0.14
2.90
4.70
2.90
MAX
1.10
0.15
0.95
0.40
0.38
0.33
0.20
0.16
3.10
5.10
3.10
0.65 BSC
0.40
0.70
0.95 BSC
0°
8°
5F18N-Rev.F003
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