[ /Title (CD74 HC123 , CD74 HCT12 3, CD74 HC423 , CD74 HCT42 3) /Subject (High Speed CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Data sheet acquired from Harris Semiconductor SCHS142F September 1997 - Revised October 2003 High-Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets Features Ordering Information • Overriding Reset Terminates Output Pulse PART NUMBER • Triggering From the Leading or Trailing Edge TEMP. RANGE (oC) PACKAGE CD54HC123F3A -55 to 125 16 Ld CERDIP • Separate Resets CD54HCT123F3A -55 to 125 16 Ld CERDIP • Wide Range of Output-Pulse Widths CD74HC123E -55 to 125 16 Ld PDIP • Schmitt Trigger on Both A and B Inputs CD74HC123M -55 to 125 16 Ld SOIC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CD74HC123MT -55 to 125 16 Ld SOIC CD74HC123M96 -55 to 125 16 Ld SOIC • Wide Operating Temperature Range . . . -55oC to 125oC CD74HC123NSR -55 to 125 16 Ld SOP • Balanced Propagation Delay and Transition Times CD74HC123PW -55 to 125 16 Ld TSSOP • Significant Power Reduction Compared to LSTTL Logic ICs CD74HC123PWR -55 to 125 16 Ld TSSOP CD74HC123PWT -55 to 125 16 Ld TSSOP CD74HC423E -55 to 125 16 Ld PDIP CD74HC423M -55 to 125 16 Ld SOIC CD74HC423MT -55 to 125 16 Ld SOIC • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH CD74HC423M96 -55 to 125 16 Ld SOIC CD74HC423NSR -55 to 125 16 Ld SOP CD74HCT123E -55 to 125 16 Ld PDIP CD74HCT123M -55 to 125 16 Ld SOIC Description CD74HCT123MT -55 to 125 16 Ld SOIC The ’HC123, ’HCT123, CD74HC423 and CD74HCT423 are dual monostable multivibrators with resets. They are all retriggerable and differ only in that the 123 types can be triggered by a negative to positive reset pulse; whereas the 423 types do not have this feature. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of Rx and CX provides a wide range of output pulse widths from the Q and Q terminals. Pulse triggering on the A and B inputs occur at a particular voltage level and is not related to the rise and fall times of the trigger pulses. CD74HCT123M96 -55 to 125 16 Ld SOIC CD74HCT423E -55 to 125 16 Ld PDIP CD74HCT423MT -55 to 125 16 Ld SOIC CD74HCT423M96 -55 to 125 16 Ld SOIC • Q and Q Buffered Outputs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. Once triggered, the output pulse width may be extended by retriggering inputs A and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing edge triggering (A) and leading edge triggering (B) inputs are provided for triggering from either edge of the input pulse. If either Mono is not used each input on the unused device (A, B, and R) must be terminated high or low. The minimum value of external resistance, Rx is typically 5kΩ. The minimum value external capacitance, CX, is 0pF. The calculation for the pulse width is tW = 0.45 RXCX at VCC = 5V. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Pinout Functional Diagram CD54HC123, CD54HCT123 (CERDIP) CD74HC123 (PDIP, SOIC, SOP, TSSOP) CD74HC423 (PDIP, SOIC, SOP) CD74HCT123, CD74HCT423 (PDIP, SOIC) TOP VIEW 1Cx 14 13 MONO 1 1Q 2 15 1RXCX 2R 1R 3 14 1CX 2A 1Q 4 13 1Q 2Q 5 12 2Q 3 11 5 9 2Q MONO 2 10 12 2B 2Q 2Cx 2RxCx 6 7 2Cx 9 2A GND 8 4 1B 1B 2 10 2B 1Q 1 1R 2RXCX 7 1RxCx 1A 16 VCC 11 2R VCC 15 1Cx 1A 1 2CX 6 1Rx TRUTH TABLE INPUTS A OUTPUTS B R Q Q H X H L H X L H L H L ↑ H ↓ H H X X L L H L H ↑ H X H L H X L H L H L ↑ H ↓ H H X X L L H CD74HC/HCT123 CD74HC/HCT423 H = High Voltage Level, L = Low Voltage Level, X = Don’t Care. 2 VCC 2Rx CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Package Thermal Impedance, θJA (see Note 1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 3 CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V ±0.1 - ±1 - ±1 µA HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 0 5.5 - ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS All 0.35 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g. 360µA max at 25oC. Prerequisite for Switching Specifications 25oC PARAMETER SYMBOL -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS 2 100 - - 125 - - 150 - - ns 4.5 20 - - 25 - - 30 - - ns 6 17 - - 21 - - 26 - - ns 2 100 - - 125 - - 150 - - ns 4.5 20 - - 25 - - 30 - - ns 6 17 - - 21 - - 26 - - ns HC TYPES Minimum Input, Pulse Width tWL A B tWH 4 CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Prerequisite for Switching Specifications (Continued) 25oC PARAMETER R A and B Hold Time Reset Removal Time Retrigger Time Number -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS tWL 2 100 - - 125 - - 150 - 150 ns 4.5 20 - - 25 - - 30 - 30 ns 6 17 - - 21 - - 26 - 26 ns 2 50 - - 65 - - 75 - 75 ns 4.5 10 - - 13 - - 15 - 15 ns 6 9 - - 11 - - 13 - 13 ns 2 50 - - 65 - - 75 - 75 ns 4.5 10 - - 13 - - 15 - 15 ns 6 9 - - 11 - - 13 - 13 ns 5 - - - - - - - - - ns - 50 - - 63 - - 76 - ns 40 - 50 38.7 - 51.3 38.2 - 51.8 µs tH tREM trT RX = 10KΩ, CX = 0 Output Pulse Width -40oC TO 85oC tW 5 Q or Q RX = 10KΩ, CX = 10nF HCT TYPES Minimum Input, Pulse Width tWL 5 A 20 - - 25 - - 30 - - ns B tWH 20 - - 25 - - 30 - - ns R tWL 20 - - 25 - - 30 - - ns - - ns - ns A and B Hold Time tH 5 10 - - 13 - - 15 tREM 5 10 - - 13 - - 15 RX = 10KΩ, CX = 0 trT 5 - 50 - - 63 - - 76 - ns Output Pulse Width Q or Q tW 5 40 - 50 38.7 - 51.3 38.2 - 51.8 µs Reset Removal Time Retrigger Time Number (Note 3) RX = 10KΩ, CX = 10nF NOTE: 3. Time to trigger depends on the values of RX and CX. The output pulse width can only be extended when the time between the activegoing edges of the trigger input pulses meet the minimum retrigger time requirement. 5 CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Switching Specifications Input tr, tf = 6ns, RX = 10KΩ, CX = 0 -40oC TO 85oC 25oC PARAMETER -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNIT S 2 - - 300 - 375 - 450 ns 4.5 - - 60 - 75 - 90 ns CL = 15pF 5 - 25 - - - - - ns CL = 50pF 6 - - 51 - 64 - 76 ns CL = 50pF 2 - - 320 - 400 - 480 ns 4.5 - - 64 - 80 - 96 ns CL = 15pF 5 - 26 - - - - - ns CL = 50pF 6 - - 54 - 68 - 82 ns CL = 50pF 2 - - 215 - 270 - 325 ns 4.5 - - 43 - 54 - 65 ns 6 - - 37 - 46 - 55 ns 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns SYMBOL TEST CONDITIONS tPLH CL = 50pF HC TYPES Trigger Propagation Delay A, B, R to Q A, B, R to Q Reset Propagation Delay tPHL tPHL, tPLH R to Q or Q Output Transition Time tTHL, tTLH CL = 50pF Output Pulse Width RX = 10KΩ, CX = 10nF - - 5 - 45 - - - - - µs Pulse Width Match Between Circuits In the Same Package RX = 10KΩ, CX = 10pF - - 5 - ±2 - - - - - % Power Dissipation Capacitance (Note 4) CPD CL = 15pF 5 - - - - - - - pF Input Capacitance CIN CL = 50pF - 10 - 10 - 10 - 10 pF tPLH CL = 50pF 4.5 - - 60 - 75 - 90 ns CL = 15pF 5 - 25 - - - - - ns CL = 50pF 4.5 - - 68 - 85 - 102 ns CL =15pF 5 - 27 - - - - - ns HCT TYPES Trigger Propagation Delay A, B, R to Q A, B, R to Q tPHL Reset Propagation Delay R to Q or Q tPHL, tPLH CL = 50pF 4.5 - - 48 - 60 - 72 ns Output Transition Time tTHL, tTLH CL = 50pF 4.5 - - 15 - 19 - 22 ns - - 5 - 45 - - - - - µs Output Pulse Width RX = 10KΩ, CX = 10nF 6 CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Switching Specifications Input tr, tf = 6ns, RX = 10KΩ, CX = 0 (Continued) -40oC TO 85oC 25oC PARAMETER Pulse Width Match Between Circuits In the Same Package RX = 10KΩ, CX = 10pF Input Capacitance SYMBOL TEST CONDITIONS VCC (V) - - 5 CIN CL = 50pF - MIN - NOTE: 4. CPD is used to determine the dynamic power consumption, per multivibrator. PD = (CPD + CX) VCC2 fi ∑(CL VCC2 fO) Where fi = input frequency fO = Output Frequency CL = Output Load Capacitance CX = External Capacitance VCC = Supply Voltage, I assuming fi « -----tW 7 -55oC TO 125oC TYP MAX MIN MAX MIN MAX UNIT S ±2 - - - - - % - 10 - 10 - 10 pF Test Circuits and Waveforms A B = LOW A A = HIGH B = LOW A = HIGH B B R R VS VS tW tW tW VS Q VS Q tW tW tW FIGURE 1. OUTPUT PULSE CONTROL USING RESET INPUT (R) PULSE FOR 123 tW FIGURE 2. OUTPUT PULSE CONTROL USING RESET INPUT (R) FOR 423 A B tW B (R = HIGH) A trT Q VS tW tW tW NOTE: Output pulse control using retrigger pulse for 123 and 423. 8 6 4 2 0.9 EXTERNAL CAPACITANCE (CX) = 10nF 0.8 103 8 6 4 2 102 101 Ω 0k RX RX 8 6 4 2 =1 4 68 2 4 68 2 4 68 2 105 104 106 EXTERNAL CAPACITANCE (CX) - pF 0.6 HCT 0.5 0.4 0.3 DC SUPPLY VOLTAGE (VCC) = 5V AMBIENT TEMPERATURE (TA) = 25oC 2 EXTERNAL RESISTANCE (RX) = 10kΩ TO 100kΩ AMBIENT TEMPERATURE (TA) = 25oC 0.7 10 Ω 0k 8 6 4 2 103 = “K” FACTOR OUTPUT PULSE WIDTH (µs) FIGURE 3. TRIGGERING OF ONE SHOT BY INPUT A OR INPUT B FOR A PERIOD tW 0.2 0.1 4 68 107 FIGURE 4. TYPICAL OUTPUT PULSE WIDTH AS A FUNCTION OF CX FOR RX = 10kΩ AND 100kΩ 1 2 3 4 5 6 7 8 9 DC SUPPLY VOLTAGE (VCC) - VOLTS 10 11 FIGURE 5. TYPICAL “K” FACTOR AS A FUNCTION OF VCC 8 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-8684701EA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type 5962-8970001EA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) CD54HC123F ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HC123F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HCT123F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD74HC123E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC123EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC123M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC123PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD74HC123PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC423E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC423EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC423M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC423M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC423M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC423M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC423ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC423MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC423MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC423MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC423MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC423NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC423NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC423NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT123E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT123EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT123M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT123M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT123M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT123M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT123ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT123MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT123MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT123MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT123MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 2 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD74HCT423E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT423EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT423M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT423M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT423M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT423MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT423MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT423MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74HC123M96 Package Package Pins Type Drawing SOIC SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC123NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HC123PWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 CD74HC423M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC423NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HCT123M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT423M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC123M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC123NSR SO NS 16 2000 346.0 346.0 33.0 CD74HC123PWR TSSOP PW 16 2000 346.0 346.0 29.0 CD74HC423M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC423NSR SO NS 16 2000 346.0 346.0 33.0 CD74HCT123M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT423M96 SOIC D 16 2500 333.2 345.9 28.6 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. 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