TI DAC8551IDRBR 16-bit, ultra-low glitch, voltage output digital-to-analog converter Datasheet

 DAC8551
SLAS429A – APRIL 2005 – REVISED JULY 2005
16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
FEATURES
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DESCRIPTION
16-Bit Monotonic Over Temperature
Relative Accuracy: 8 LSB (Max)
Glitch Energy: 0.1 nV-s
Settling Time: 10 µs to ±0.003% FSR
Power Supply: +2.7 V to +5.5 V
MicroPower Operation: 200 µA at 5 V
Rail-to-Rail Output Amplifier
Power-On Reset to Zero
Power-Down Capability
Schmitt-Triggered Digital Inputs
SYNC Interrupt Facility
Drop-In Compatible With DAC8531/01
Operating Temperature Range: -40°C to 105°C
Available Package:
– 3 mm × 5 mm MSOP-8
APPLICATIONS
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Process Control
Data Acquisition Systems
Closed-Loop Servo-Control
PC Peripherals
Portable Instrumentation
Programmable Attenuation
The DAC8551 is a small, low-power, voltage output,
16-bit digital-to-analog converter (DAC). It is
monotonic, provides good linearity, and minimizes
undesired code-to-code transient voltages. The
DAC8551 uses a versatile 3-wire serial interface that
operates at clock rates to 30 MHz and is compatible
with standard SPI™, QSPI™, Microwire™, and digital
signal processor (DSP) interfaces.
The DAC8551 requires an external reference voltage
to set its output range. The DAC8551 incorporates a
power-on-reset circuit that ensures the DAC output
powers up at 0 V and remains there until a valid write
takes place to the device. The DAC8551 contains a
power-down feature, accessed over the serial
interface, that reduces the current consumption of the
device to 200 nA at 5 V.
The low-power consumption of this device in normal
operation makes it ideally suited for portable batteryoperated equipment. The power consumption is
1.00 mW at 5 V, reducing to 1 µW in power-down
mode.
The DAC8551 is available in an MSOP-8 package.
FUNCTIONAL BLOCK DIAGRAM
VDD
VFB
VREF
Ref (+)
VOUT
16−Bit DAC
16
DAC Register
16
SYNC
SCLK
DIN
Shift Register
Resistor
Network
PWD Control
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola.
Microwire is a trademark of National Semiconductor.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
DAC8551
www.ti.com
SLAS429A – APRIL 2005 – REVISED JULY 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
PACKAGE
LEAD
PACKAGE
DESIGNATOR (1)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
DAC8551IDGK
Tube, 80
DAC8551I
±8
±1
MSOP-8
DGK
–40°C TO 105°C
D81
DAC8551IDGKT
Tape and Reel, 250
DAC8551IDGKR
Tape and Reel, 2500
(1)
TRANSPORT
MEDIA,
QUANTITY
For the most current specifications and package information, refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
UNIT
VDD to GND
–0.3 V to 6 V
Digital input voltage to GND
–0.3 V to +VDD + 0.3 V
VOUT to GND
–0.3 V to +VDD + 0.3 V
Operating temperature range
–40°C to 105°C
Storage temperature range
–65°C to 150°C
Junction temperature range (TJ max)
150°C
Power dissipation (DGK)
(TJmax – TA)/θJA
θJA Thermal impedance
206°C/W
θJC Thermal impedance
Lead temperature, soldering
(1)
44°C/W
Vapor phase (60 s)
215°C
Infrared (15 s)
220°C
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V,– 40°C to 105°C range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE (1)
Resolution
16
Relative accuracy
Measured by line passing through codes 485 and 64741
Differential nonlinearity
16-bit Monotonic
Zero-code error
Full-scale error
Measured by line passing through codes 485 and 64741.
Gain error
Bits
±3
±8
LSB
±0.25
±1
LSB
±2
±12
mV
±0.05
±0.5
% of FSR
±0.02
±0.15
% of FSR
Zero-code error drift
±5
µV/°C
Gain temperature coefficient
±1
ppm of FSR/°C
Power supply rejection ratio
(PSRR)
8
(1)
2
RL = 2 kΩ, CL = 200 pF
Linearity calculated using a reduced code range of 485 to 64741; output unloaded.
0.75
mV
mV/V
DAC8551
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SLAS429A – APRIL 2005 – REVISED JULY 2005
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7 V to 5.5 V,– 40°C to 105°C range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VREF
V
10
µs
OUTPUT CHARACTERISTICS (2)
Output voltage range
Output voltage settling time
0
To ±0.003% FSR, 0200H to FD00H, RL = 2 kΩ, 0 pF < CL <
200 pF
8
RL = 2 kΩ, CL = 500 pF
Slew rate
Capacitive load stability
RL = ∞
RL = 2 kΩ
12
µs
1.8
V/µs
470
pF
1000
pF
Code change glitch impulse
1 LSB change around major carry
0.1
Digital feedthrough
SCLK toggling, FSYNC high
0.1
DC output impedance
At mid-code input
Short-circuit current
Power-up time
nV-s
Ω
1
VDD = 5 V
50
VDD = 3 V
20
Coming out of power-down mode VDD = 5 V
2.5
Coming out of power-down mode VDD = 3 V
5
mA
µs
AC PERFORMANCE
SNR (1st 19 harmonics removed)
THD
95
85
BW = 20 kHz, VDD = 5 V, FOUT = 1 kHz
SFDR
dB
87
SINAD
84
REFERENCE INPUT
VREF Voltage
0
Reference input range
V
µA
VREF = VDD = 5 V
50
75
VREF = VDD = 3.6 V
30
45
Reference input impedance
LOGIC INPUTS
VDD
125
µA
kΩ
(3)
±1
Input current
VINL
Logic input LOW voltage
VINH
Logic input HIGH voltage
µA
VDD = 5 V
0.8
VDD = 3 V
0.6
VDD = 5 V
2.4
VDD = 3 V
2.1
V
V
Pin capacitance
3
pF
5.5
V
POWER REQUIREMENTS
VDD
IDD (normal mode)
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
2.7
Input code = 32768, reference current included, no load
VIH = VDD and VIL = GND
200
250
180
240
0.2
1
0.05
1
µA
IDD (all power-down modes)
VDD = 3.6 V to 5.5 V
VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V
µA
POWER EFFICIENCY
IOUT/IDD
ILOAD = 2 mA, VDD = 5 V
89%
TEMPERATURE RANGE
Specified performance
(2)
(3)
–40
105
°C
Ensured by design and characterization, not production tested.
Ensured by design and characterization, not production tested.
3
DAC8551
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SLAS429A – APRIL 2005 – REVISED JULY 2005
PIN CONFIGURATION
MSOP-8
(Top View)
VDD
1
VREF
2
VFB
VOUT
8
GND
7
DIN
3
6
SCLK
4
5
SYNC
DAC8551
PIN DESCRIPTIONS
4
PIN
NAME
1
VDD
Power supply input, 2.7 V to 5.5 V.
2
VREF
Reference voltage input.
3
VFB
Feedback connection for the output amplifier. For voltage output operation, tie to VOUT externally.
4
VOUT
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
5
SYNC
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes
LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is
updated following the 24th clock (unless SYNC is taken HIGH before this edge in which case the rising edge of SYNC acts
as an interrupt and the write sequence is ignored by the DAC8551).
6
SCLK
Serial clock input. Data can be transferred at rates up to 30 MHz.
7
DIN
8
GND
DESCRIPTION
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input.
Ground reference point for all circuitry on the part.
DAC8551
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SLAS429A – APRIL 2005 – REVISED JULY 2005
TIMING REQUIREMENTS
(1) (2)
VDD = 2.7 V to 5.5 V, all specifications –40°C to 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t 1 (3) SCLK cycle time
t2
SCLK HIGH time
t3
SCLK LOW time
t4
SYNC to SCLK rising edge setup time
t5
Data setup time
t6
Data hold time
t7
SCLK falling edge to SYNC rising edge
t8
Minimum SYNC HIGH time
(1)
(2)
(3)
MIN
VDD = 2.7 V to 3.6 V
50
VDD = 3.6 V to 5.5 V
33
VDD = 2.7 V to 3.6 V
13
VDD = 3.6 V to 5.5 V
13
VDD = 2.7 V to 3.6 V
22.5
VDD = 3.6 V to 5.5 V
13
VDD = 2.7 V to 3.6 V
0
VDD = 3.6 V to 5.5 V
0
VDD = 2.7 V to 3.6 V
5
VDD = 3.6 V to 5.5 V
5
VDD = 2.7 V to 3.6 V
4.5
VDD = 3.6 V to 5.5 V
4.5
VDD = 2.7 V to 3.6 V
0
VDD = 3.6 V to 5.5 V
0
VDD = 2.7 V to 3.6 V
50
VDD = 3.6 V to 5.5 V
33
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
All input signals are specified with tR = tF = 3 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See Serial Write Operation timing diagram.
Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.
SERIAL WRITE OPERATION
t1
SCLK
t8
t3
t4
t2
t7
SYNC
t6
t5
DIN
DB23
DB0
5
DAC8551
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SLAS429A – APRIL 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS: VDD = 5 V
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
CODE
(-40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
CODE
(25°C)
6
4
2
0
−2
−4
−6
6
4
2
0
−2
VDD = 5 V, VREF = 4.99 V
LE − (LSB)
LE − (LSB)
At TA = 25°C, unless otherwise noted
−4
−6
1
DLE − (LSB)
1
DLE − (LSB)
VDD = 5 V, VREF = 4.99 V
0.5
0
−0.5
0.5
0
−0.5
−1
−1
0
8192
16384
24576
32768 40960 49152
57344 65536
0
8192
16384 24576 32768
LE − (LSB)
Figure 1.
Figure 2.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
CODE
(105°C)
ZERO-SCALE ERROR
vs
TEMPERATURE
6
4
2
0
−2
10
VDD = 5 V, VREF = 4.99 V
VDD = 5 V, VREF = 4.99 V
5
Error (mV)
−4
−6
1
DLE − (LSB)
40960 49152 57344 65536
Digital Input Code
Digital Input Code
0.5
0
0
−0.5
−5
−1
0
8192
16384 24576
32768
40960 49152 57344 65536
−40
0
Digital Input Code
40
80
120
Temperature − C
Figure 3.
Figure 4.
FULL-SCALE ERROR
vs
TEMPERATURE
IDD HISTOGRAM
0
1000
VDD = 5 V, VREF = 4.99 V
VDD = VREF = 5.5 V,
Reference Current Included
f − Frequency − Hz
Error (mV)
800
−5
600
400
200
−10
0
−40
0
40
Temperature − C
Figure 5.
6
80
120
120
140
160
180
200
220
240
IDD − Supply Current − A
Figure 6.
260
280
300
DAC8551
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SLAS429A – APRIL 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, unless otherwise noted
SOURCE AND SINK CURRENT CAPABILITY
SUPPLY CURRENT
vs
DIGITAL INPUT CODE
300
6
VDD = 5.5 V
VDD = VREF = 5.5 V
DAC Loaded With FFFFH
I DD − Supply Current − µ A
V OUT − Output Voltage − V
5
4
3
VREF = VDD −10 mV
2
1
250
200
Reference Current Included
150
100
50
DAC Loaded With 0000H
0
0
0
3
5
8
0
10
8192
16384 24576
I(SOURCE/SINK) − mA
Figure 7.
Figure 8.
POWER-SUPPLY CURRENT
vs
TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
250
300
VDD = VREF = 5.5 V
I DD − Supply Current − µ A
200
Quiescent Current −µ A
32768 40960 49152 57344 65536
Digital Input Code
150
Reference Current Included
100
50
280
VREF = VDD
260
Reference Current Include, No Load
240
220
200
180
160
140
120
0
−40
−10
20
50
80
100
2.7
110
3.1
3.4
Temperature − C
3.8
4.1
4.5
4.8
5.2
5.5
VDD − Supply Voltage − V
Figure 9.
Figure 10.
POWER-DOWN CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
1
I DD − Supply Current − µ A
− Supply Current −µ A
0.5
0.3
I
DD
0.8
0
2.7
TA = 25°C, SCL Input (All Other Inputs = GND)
VDD = VREF = 5.5 V
1700
VREF = VDD
1300
900
500
100
3.1
3.4
3.8
4.1
4.5
VDD − Supply Voltage − V
Figure 11.
4.8
5.2
5.5
0
1
2
3
4
5
V(LOGIC) − V
Figure 12.
7
DAC8551
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SLAS429A – APRIL 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, unless otherwise noted
FULL-SCALE SETTLING TIME: 5-V RISING EDGE
FULL-SCALE SETTLING TIME: 5-V FALLING EDGE
Trigger Pulse
5 V/div
Trigger Pulse
5 V/div
VDD = 5 V,
VREF = 4.096 V,
From Code: 0000
To Code: FFFF
Rising Edge
1 V/div
VDD = 5 V,
VREF = 4.096 V,
From Code: FFFF
To Code: 0000
Falling
Edge
1 V/div
Zoomed Rising Edge
1 mV/div
Zoomed Falling Edge
1 mV/div
Time (2 µs/div)
Time (2 µs/div)
Figure 13.
Figure 14.
HALF-SCALE SETTLING TIME: 5-V RISING EDGE
HALF-SCALE SETTLING TIME: 5-V FALLING EDGE
Trigger Pulse
5 V/div
Trigger Pulse
5 V/div
VDD = 5 V,
VREF = 4.096 V,
From Code: CFFF
To Code: 4000
VDD = 5 V,
VREF = 4.096 V,
From Code: 4000
To Code: CFFF
Rising
Edge
1 V/div
Falling
Edge
1 V/div
Zoomed Rising Edge
1 mV/div
Time (2 µs/div)
Time (2 µs/div)
GLITCH ENERGY: 5-V, 1-LSB STEP, RISING EDGE
GLITCH ENERGY: 5-V, 1-LSB STEP, FALLING EDGE
VDD = 5 V,
VREF = 4.096 V
From Code: 7FFF
To Code: 8000
Glitch: 0.08 nV-s
Figure 17.
VOUT(500 V/div)
Figure 16.
VOUT (500 V/div)
Figure 15.
Time 400 ns/div
8
Zoomed Falling Edge
1 mV/div
VDD = 5 V,
VREF = 4.096 V
From Code: 8000
To Code: 7FFF
Glitch: 0.16 nV-s
Measured Worst Case
Time 400 ns/div
Figure 18.
DAC8551
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SLAS429A – APRIL 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, unless otherwise noted
GLITCH ENERGY: 5-V, 16-LSB STEP, FALLING EDGE
VDD = 5 V,
VREF = 4.096 V
From Code: 8010
To Code: 8000
Glitch: 0.08 nV-s
VOUT (500 V/div)
VOUT(500 V/div)
GLITCH ENERGY: 5-V, 16-LSB STEP, RISING EDGE
VDD = 5 V,
VREF = 4.096 V
From Code: 8000
To Code: 8010
Glitch: 0.04 nV-s
Time 400 ns/div
Time 400 ns/div
Figure 19.
Figure 20.
GLITCH ENERGY: 5-V, 256-LSB STEP, RISING EDGE
GLITCH ENERGY: 5-V, 256-LSB STEP, FALLING EDGE
Time 400 ns/div
Time 400 ns/div
Figure 21.
Figure 22.
TOTAL HARMONIC DISTORTION
vs
OUTPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs
OUTPUT FREQUENCY
98
VDD = 5 V, VREF = 4.9 V
−50
SNR − Signal-to-Noise Ratio − dB
THD − Total Harmonic Distortion − dB
−40
−1dB FSR Digital Input, Fs = 1 MSPS
Measurement Bandwidth = 20 kHz
−60
−70
THD
2nd Harmonic
−80
3rd Harmonic
−90
−100
VDD = 5 V,
VREF= 4.096 V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
VOUT(5 mV/div)
VOUT(5 mV/div)
VDD = 5 V,
VREF = 4.096 V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
VDD = VREF = 5 V
96
−1 dB FSR Digital Input, Fs = 1 MSPS
Measurement Bandwidth = 20 kHz
94
92
90
88
86
84
0
1
2
3
Output Tone − kHz
Figure 23.
4
5
0
0.5
1
1.5
2
2.5
3
3.5
f − Output Frequency − kHz
4
4.5
5
Figure 24.
9
DAC8551
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SLAS429A – APRIL 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, unless otherwise noted
POWER SPECTRAL DENSITY
OUTPUT NOISE DENSITY
350
VDD = 5 V
VREF = 4.096
Code = 7FFF
No Load
−10
−50
−70
−90
−110
−130
5000
0
10000
15000
300
V n − Voltage Noise − nV/
Gain − dB
−30
Hz
VDD = 5.0 V, VREF = 4.096 V
fOUT = 1 kHz
fCLK = 1 MSPS
250
200
150
100
100
20000
1000
10000
100000
f − Frequency − Hz
f − Frequency − Hz
Figure 25.
Figure 26.
TYPICAL CHARACTERISTICS: VDD = 2.7 V
At TA = 25°C, unless otherwise noted
6
4
2
0
−2
−4
−6
6
4
VDD = 2.7 V, VREF = 2.69 V
LE − (LSB)
VDD = 2.7 V, VREF = 2.69 V
2
0
−2
1
1
0.5
0.5
0
−0.5
−4
−6
0
−0.5
−1
−1
0
8192
16384 24576 32768 40960
Digital Input Code
Figure 27.
10
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL
INPUT CODE
(25°C)
DLE − (LSB)
DLE − (LSB)
LE − (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL
INPUT CODE
(-40°C)
49152 57344 65536
0
8192
16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 28.
DAC8551
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SLAS429A – APRIL 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued)
At TA = 25°C, unless otherwise noted
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
CODE
(105°C)
LE − (LSB)
6
4
10
VDD = 2.7 V, VREF = 2.69 V
VDD = 2.7 V, VREF = 2.69 V
2
0
−2
5
Error (mV)
−4
−6
1
DLE − (LSB)
ZERO-SCALE ERROR
vs
TEMPERATURE
0.5
0
0
−0.5
−1
0
8192
16384
−5
−40
24576 32768 40960 49152 57344 65536
0
40
80
120
Digital Input Code
Temperature − C
Figure 29.
Figure 30.
FULL-SCALE ERROR
vs
TEMPERATURE
IDD HISTOGRAM
5
1500
VDD = VREF = 2.7 V
Reference Current Included
VDD = 2.7 V, VREF = 2.69 V
f − Frequency − Hz
1200
Error (mV)
0
−5
900
600
300
−10
−40
0
0
40
80
120
120
140
160
220
240
260
Figure 32.
SOURCE AND SINK CURRENT CAPABILITY
SUPPLY CURRENT
vs
DIGITAL INPUT CODE
280
300
180
VDD = 2.7 V
2.5
2
1.5
VREF = VDD − 10 mV
1
0.5
3
140
120
Reference Current Included
100
80
60
40
20
DAC Loaded With 0000H
0
VDD = VREF = 2.7 V
160
DAC Loaded With FFFFH
I DD − Supply Current − µ A
V OUT − Output Voltage − V
200
Figure 31.
3
0
180
IDD − Supply Current − A
Temperature − C
5
I(SOURCE/SINK) − mA
Figure 33.
8
10
0
0
8192
16384
24576 32768
40960
49152
57344 65536
Digital Input Code
Figure 34.
11
DAC8551
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SLAS429A – APRIL 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued)
At TA = 25°C, unless otherwise noted
POWER-SUPPLY CURRENT
vs
TEMPERATURE
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
250
TA = 25°C, SCL Input (All Other Inputs = GND)
I DD − Supply Current − µ A
VDD = VREF = 2.7 V
Quiescent Current −µ A
200
150
Reference Current Included
100
50
0
−40
−10
20
50
80
110
700
VDD = VREF = 2.7 V
500
300
100
0
0.5
1
1.5
2.5
Temperature − C
Figure 35.
Figure 36.
FULL-SCALE SETTLING TIME: 2.7-V RISING EDGE
FULL-SCALE SETTLING TIME: 2.7-V FALLING EDGE
Trigger Pulse
2.7 V/div
Trigger Pulse
2.7 V/div
VDD = 2.7 V,
VREF = 2.5 V,
From Code: FFFF
To Code: 0000
VDD = 2.7 V,
VREF = 2.5 V,
From Code: 0000
To Code: FFFF
Rising
Edge
0.5 V/div
Zoomed Rising Edge
1 mV/div
Falling
Edge
0.5 V/div
Time (2 µs/div)
Zoomed Falling Edge
1 mV/div
Time (2 µs/div)
Figure 37.
Figure 38.
HALF-SCALE SETTLING TIME: 2.7-V RISING EDGE
HALF-SCALE SETTLING TIME: 2.7-V FALLING EDGE
Trigger Pulse
2.7 V/div
Trigger Pulse
2.7 V/div
VDD = 2.7 V,
VREF = 2.5 V,
From Code: CFFF
To Code: 4000
VDD = 2.7 V
VREF = 2.5 V
From code; 4000
To code: CFFF
Rising
Edge
0.5 V/div
Zoomed Rising Edge
1 mV / div
Time − 2 s/div
Figure 39.
12
2
V(LOGIC) − V
Falling
Edge
0.5 V/div
Zoomed Falling Edge
1 mV/div
Time (2 µs/div)
Figure 40.
DAC8551
www.ti.com
SLAS429A – APRIL 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS: VDD = 2.7 V (continued)
At TA = 25°C, unless otherwise noted
VDD = 2.7 V,
VREF = 2.5 V
From Code: 7FFF
To Code: 8000
Glitch: 0.08 nV-s
GLITCH ENERGY: 2.7-V, 1-LSB STEP, FALLING EDGE
VOUT(200 V/div)
VOUT(200 V/div)
GLITCH ENERGY: 2.7-V, 1-LSB STEP, RISING EDGE
VDD = 2.7 V,
VREF = 2.5 V
From Code: 8000
To Code: 7FFF
Glitch: 0.16 nV-s
Measured Worst Case
Time 400 ns/div
Time 400 ns/div
GLITCH ENERGY: 2.7-V, 16-LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7-V, 16-LSB STEP, FALLING EDGE
VDD = 2.7 V,
VREF = 2.5 V
From Code: 8000
To Code: 8010
Glitch: 0.04 nV-s
Time 400 ns/div
VDD = 2.7 V,
VREF = 2.5 V
From Code: 8010
To Code: 8000
Glitch: 0.12 nV-s
V/div)
VOUT (200 uV/div)
Figure 42.
VOUT(200 uV/div)
Figure 41.
Time 400 ns/div
GLITCH ENERGY: 2.7-V, 256-LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7-V, 256-LSB STEP, FALLING EDGE
AVDD = 2.7 V,
Vref = 2.5 V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Time 400 ns/div
Figure 45.
VOUT (5 mV/div)
Figure 44.
VOUT(5 mV/div)
Figure 43.
VDD = 2.7 V,
VREF = 2.5 V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
Time 400 ns/div
Figure 46.
13
DAC8551
www.ti.com
SLAS429A – APRIL 2005 – REVISED JULY 2005
THEORY OF OPERATION
VREF
DAC SECTION
The architecture consists of a string DAC followed by
an output buffer amplifier. Figure 47 shows a block
diagram of the DAC architecture.
Ω
Ω
VFB
62 Ω
R Divider
V
REF
2
R
R
To Output
Amplifier
(2x Gain)
GND
Figure 47. DAC8551 Architecture
The input coding to the DAC8551 is straight binary,
so the ideal output voltage is given by:
V
OUT
X
D
IN V
REF
65536
where DIN = decimal equivalent of the binary code
that is loaded to the DAC register; it can range from 0
to 65535.
R
R
RESISTOR STRING
The resistor string section is shown in Figure 48. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier. It is
monotonic because it is a string of resistors.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, which gives an
output range of 0 V to VDD. It is capable of driving a
load of 2 kΩ in parallel with 1000 pF to GND. The
source and sink capabilities of the output amplifier
can be seen in the typical curves. The slew rate is 1.8
V/µs with a full-scale setting time of 8 µs with the
output unloaded.
The inverting input of the output amplifier is brought
out to the VFB pin. This allows for better accuracy in
critical applications by tying the VFB point and the
amplifier output together directly at the load. Other
signal conditioning circuitry may also be connected
between these points for specific applications.
14
Figure 48. Resistor String
SERIAL INTERFACE
The DAC8551 has a 3-wire serial interface ( SYNC,
SCLK, and DIN), which is compatible with SPI™,
QSPI™, and Microwire™ interface standards, as well
as most DSPs. See the Serial Write Operation timing
diagram for an example of a typical write sequence.
The write sequence begins by bringing the SYNC line
LOW. Data from the DIN line is clocked into the 24-bit
shift register on each falling edge of SCLK. The serial
clock frequency can be as high as 30 MHz, making
the DAC8551 compatible with high-speed DSPs. On
the 24th falling edge of the serial clock, the last data
bit is clocked in and the programmed function is
executed (i.e., a change in DAC register contents
and/or a change in the mode of operation).
At this point, the SYNC line may be kept LOW or
brought HIGH. In either case, it must be brought
HIGH for a minimum of 33 ns before the next write
sequence so that a falling edge of SYNC can initiate
the next write sequence. As previously mentioned, it
must be brought HIGH again just before the next
write sequence.
DAC8551
www.ti.com
SLAS429A – APRIL 2005 – REVISED JULY 2005
INPUT SHIFT REGISTER
SYNC INTERRUPT
The input shift register is 24 bits wide, as shown in
Figure 49. The first six bits are don't cares. The next
two bits (PD1 andPD0) are control bits that control
which mode of operation the part is in (normal mode
or any one of three power-down modes). A more
complete description of the various modes is located
in the Power-Down Modes section. The next 16 bits
are the data bits. These are transferred to the DAC
register on the 24th falling edge of SCLK.
In a normal write sequence, the SYNC line is kept
LOW for at least 24 falling edges of SCLK and the
DAC is updated on the 24th falling edge. However, if
SYNC is brought HIGH before the 24th falling edge, it
acts as an interrupt to the write sequence. The shift
register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents, or a change in the operating mode occurs, as
shown in Figure 50.
POWER-ON RESET
The DAC8551 contains a power-on-reset circuit that
controls the output voltage during power up. On
power up, the DAC registers is filled with zeros and
the output voltages is 0 V; it remains there until a
valid write sequence is made to the DAC. This is
useful in applications where it is important to know
the state of the output of the DAC while it is in the
process of powering up.
DB23
X
DB0
X
X
X
X
X
PD1
PD0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 49. DAC8551 Data Input Register Format
24th Falling Edge
24th Falling Edge
CLK
SYNC
DIN
DB23
DB80
DB23
DB80
Valid Write Sequence: Output Updates
on the 24th Falling Edge
Figure 50. SYNC Interrupt Facility
15
DAC8551
www.ti.com
SLAS429A – APRIL 2005 – REVISED JULY 2005
POWER-DOWN MODES
The DAC8551 supports four separate modes of
operation. These modes are programmable by setting
two bits (PD1 and PD0) in the control register.
Table 1 shows how the state of the bits corresponds
to the mode of operation of the device.
Table 1. Modes of Operation for the DAC8551
PD1
(DB17)
PD0
(DB16)
OPERATING MODE
0
0
Normal Operation
–
–
Power-down modes
0
1
Output typically 1 kΩ to GND
1
0
Output typically 100 kΩ to GND
1
1
High-Z
When both bits are set to 0, the device works
normally with its typical current consumption of 200
µA at 5 V. However, for the three power-down
modes, the supply current falls to 200 nA at 5 V (50
nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the
output of the amplifier to a resistor network of known
values. This has the advantage that the output
impedance of the device is known while it is in
power-down mode. There are three different options.
The output is connected internally to GND through a
1-kΩ resistor, a 100-kΩ resistor, or it is left
open-circuited (High-Z). The output stage is illustrated
in Figure 51.
All analog circuitry is shut down when the
power-down mode is activated. However, the contents of the DAC register are unaffected when in
power down. The time to exit power-down is typically
2.5 µs for VDD = 5 V, and 5 µs for VDD = 3 V. See the
Typical Characteristics for more information.
VFB
Amplifier
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8551, while RXD drives
the serial data line of the device. The SYNC signal is
derived from a bit-programmable pin on the port of
the 8051. In this case, port line P3.3 is used. When
data is to be transmitted to the DAC8551, P3.3 is
taken LOW. The 8051 transmits data in 8-bit bytes;
thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left
LOW after the first eight bits are transmitted, then a
second write cycle is initiated to transmit the second
byte of data. P3.3 is taken HIGH following the
completion of the third write cycle. The 8051 outputs
the serial data in a format which has the LSB first.
The DAC8551 requires its data with the MSB as the
first bit received. The 8051 transmit routine must
therefore take this into account, and mirror the data
as needed.
80C51/80L51(1)
DAC8551 (1)
P3.3
SYNC
TXD
SCLK
RXD
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 52. DAC8551 to 80C51/80L51 Interface
DAC8551 to Microwire Interface
Figure 53 shows an interface between the DAC8551
and any Microwire compatible device. Serial data is
shifted out on the falling edge of the serial clock and
is clocked into the DAC8551 on the rising edge of the
SK signal.
MicrowireTM
DAC8551(1)
CS
SYNC
SK
SCLK
SO
DIN
VOUT
Resistor
String DAC
NOTE: (1) Additional pins omitted for clarity.
Figure 53. DAC8551 to Microwire Interface
Power−Down
Circuitry
Resistor
Network
Figure 51. Output Stage During Power Down
MICROPROCESSOR INTERFACING
DAC8551 TO 8051 Interface
See Figure 52 for a serial interface between the
DAC8551 and a typical 8051-type microcontroller.
16
DAC8551 to 68HC11 Interface
Figure 54 shows a serial interface between the
DAC8551 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8551, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal is derived from a port line
(PC7), similar to the 8051 diagram.
DAC8551
www.ti.com
SLAS429A – APRIL 2005 – REVISED JULY 2005
DAC8551 (1)
68HC11(1)
PC7
SYNC
SCK
SCLK
MOSI
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 54. DAC8551 to 68HC11 Interface
valid on the falling edge of SCK. When data is being
transmitted to the DAC, the SYNC line is held LOW
(PC7). Serial data from the 68HC11 is transmitted in
8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. (Data is transmitted
MSB first.) In order to load data to the DAC8551,
PC7 is left LOW after the first eight bits are transferred, then a second and third serial write operation
is performed to the DAC. PC7 is taken HIGH at the
end of this procedure.
The 68HC11 should be configured so that its CPOL
bit is 0 and its CPHA bit is 1. This configuration
causes data appearing on the MOSI output to be
APPLICATION INFORMATION
USING THE REF02 AS A POWER SUPPLY
FOR THE DAC8551
Due to the extremely low supply current required by
the DAC8551, an alternative option is to use a REF02
+5 -V precision voltage reference to supply the required voltage to the device, as shown in Figure 55.
(2)
The load regulation of the REF02 is typically
0.005%/mA, which results in an error of 299 µV for
the 1.2-mA current drawn from it. This corresponds to
a 3.9 LSB error.
BIPOLAR OPERATION USING THE DAC8551
+15
The DAC8551 has been designed for single-supply
operation, but a bipolar output range is also possible
using the circuit in Figure 56. The circuit shown gives
an output voltage range of ±VREF. Rail-to-rail operation at the amplifier output is achievable using an
OPA703 as the output amplifier.
+5V
REF02
285µA
The output voltage for any input code can be calculated as follows:
SYNC
Three-Wire
Serial
Interface
200 A 5 V 1.2 mA
5 k
SCLK
VOUT = 0V to 5V
DAC8551
DIN
Figure 55. REF02 as a Power Supply to the
DAC8551
This is especially useful if the power supply is quite
noisy or if the system supply voltages are at some
value other than 5 V. The REF02 outputs a steady
supply voltage for the DAC8551. If the REF02 is
used, the current it needs to supply to the DAC8551
is 200 µA. This is with no load on the output of the
DAC. When a DAC output is loaded, the REF02 also
needs to supply the current to the load. The total
typical current required (with a 5-kΩ load on the DAC
output) is:
V
O
V
REF
D R1 R2 V
65536
R2
REF
R1
R1
where D represents the input code in decimal
(0–65535).
With VREF = 5 V, R1 = R2 = 10 kΩ.
V 10 D 5 V
O
65536
(4)
This is an output voltage range of ±5 V with 0000H
corresponding to a –5 V output and FFFFH corresponding to a 5 V output. Similarly, using VREF = 2.5
V, a ±2.5-V output voltage range can be achieved.
LAYOUT
A precision analog component requires careful layout,
adequate bypassing, and clean, well-regulated power
supplies.
The DAC8551 offers single-supply operation, and it
often is used in close proximity with digital logic,
17
DAC8551
www.ti.com
SLAS429A – APRIL 2005 – REVISED JULY 2005
microcontrollers, microprocessors, and digital signal
processors. The more digital logic present in the
design and the higher the switching speed, the more
difficult it is to keep digital noise from appearing at
the output.
The power applied to VDD should be well regulated
and low noise. Switching power supplies and DC/DC
converters often have high-frequency glitches or
spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes
as their internal logic switches states. This noise can
easily couple into the DAC output voltage through
various paths between the power connections and
analog output.
Due to the single ground pin of the DAC8551, all
return currents, including digital and analog return
currents for the DAC, must flow through a single
point. Ideally, GND would be connected directly to an
analog ground plane. This plane would be separate
from the ground connection for the digital
components until they were connected at the
power-entry point of the system.
As with the GND connection, VDD should be connected to a 5-V power-supply plane or trace that is
separate from the connection for digital logic until
they are connected at the power-entry point. In
addition, a 1-µF to 10-µF capacitor and 0.1-µF
bypass capacitor are strongly recommended. In some
situations, additional bypassing may be required,
such as a 100-µF electrolytic capacitor or even a Pi
filter made up of inductors and capacitors – all
designed to essentially low-pass filter the 5-V supply,
removing the high-frequency noise.
R2
10kΩ
VREF
+5V
R1
10kΩ
OPA703
VFB
VREF
10µF
DAC8551
0.1µF
–5V
Three-Wire
Serial Interface
Figure 56. Bipolar Output Range
18
5V
VOUT
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DAC8551IDGK
ACTIVE
MSOP
DGK
8
DAC8551IDGKR
ACTIVE
MSOP
DGK
DAC8551IDGKRG4
ACTIVE
MSOP
DAC8551IDGKT
ACTIVE
DAC8551IDRBR
DAC8551IDRBT
80
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU
Level-1-260C-UNLIM
8
2500 Green (RoHS &
no Sb/Br)
CU
Level-1-260C-UNLIM
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU
Level-1-260C-UNLIM
MSOP
DGK
8
250
Green (RoHS &
no Sb/Br)
CU
Level-1-260C-UNLIM
PREVIEW
SON
DRB
8
3000
TBD
Call TI
Call TI
PREVIEW
SON
DRB
8
250
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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