ICS83940D Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS83940D is a low skew, 1-to-18 LVPECLto-LVCMOS/LVTTL Fanout Buffer and a member HiPerClockS™ of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS83940D has two selectable clock inputs. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. • 18 LVCMOS/LVTTL outputs The ICS83940D is characterized at full 3.3V and 2.5V or mixed 3.3V core, 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the ICS83940D ideal for those clock distribution applications demanding well defined performance and repeatability. • Output skew: 150ps (maximum) ICS • Selectable LVCMOS_CLK or LVPECL clock inputs • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • LVCMOS_CLK accepts the following input levels: LVCMOS or LVTTL • Maximum output frequency: 250MHz • Part to part skew: 750ps (maximum) • Additive phase jitter, RMS: < 0.03ps (typical) • Full 3.3V and 2.5V or mixed 3.3V core, 2.5V output supply modes • 0°C to 70°C ambient operating temperature • Lead-Free package available • Pin compatible with the MPC940L BLOCK DIAGRAM PIN ASSIGNMENT GND Q5 Q4 Q3 VDDO 32 31 30 29 28 27 26 25 0 18 Q0:Q17 LVCMOS_CLK Q2 PCLK nPCLK Q1 Q0 CLK_SEL 1 GND 1 24 Q6 GND 2 23 Q7 LVCMOS_CLK 3 22 Q8 CLK_SEL 4 21 VDD PCLK 5 20 Q9 nPCLK 6 19 Q10 VDD 7 18 Q11 VDDO 8 17 GND ICS83940D 9 10 11 12 13 14 15 16 VDDO Q12 Q13 Q14 GND Q15 Q16 Q17 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Pacakge Top View 83940DY www.icst.com/products/hiperclocks.html 1 REV. B JUNE 15, 2004 ICS83940D Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2, 12, 17, 25 GND Power Type Description 3 LVCMOS_CLK Input 4 CLK_SEL Input 5 PCLK Input 6 nPCLK Input 7, 21 VDD Power Core supply pins. 8, 16, 29 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 VDDO Q17, Q16, Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0 Power Output supply pins. Output Clock outputs. LVCMOS / LVTTL interface levels. Power supply ground. Pulldown Clock input. LVCMOS / LVTTL interface levels. Clock select input. Selects LVCMOS / LVTTL clock Pulldown input when HIGH. Selects PCLK, nPCLK inputs when LOW. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential LVPECL clock input. Pullup/ Inver ting differential LVPECL clock input. Pulldown VDD/2 default when left floating. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN RPULLup Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ ROUT Output Impedance C PD Test Conditions Minimum Typical Maximum Units 4 pF 6 pF 18 28 Ω TABLE 3A. CLOCK SELECT FUNCTION TABLE Control Input Clock CLK_SEL PCLK, nPCLK LVCMOS_CLK 0 Selected De-selected 1 De-selected Selected TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs CLK_SEL Outputs LVCMOS_CLK PCLK nPCLK Input to Output Mode Q0:Q17 Polarity 0 — 0 1 LOW Differential to Single Ended Non Inver ting 0 — 1 HIGH Differential to Single Ended Non Inver ting 0 — 0 LOW Single Ended to Single Ended Non Inver ting 0 — 1 HIGH Single Ended to Single Ended Non Inver ting 0 — Biased; NOTE 1 0 Biased; NOTE 1 Biased; NOTE 1 0 HIGH Single Ended to Single Ended Inver ting 0 — Biased; NOTE 1 1 LOW Single Ended to Single Ended Inver ting 1 0 — — LOW Single Ended to Single Ended Non Inver ting 1 1 — — HIGH Single Ended to Single Ended Non Inver ting NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels". 83940DY www.icst.com/products/hiperclocks.html 2 REV. B JUNE 15, 2004 ICS83940D Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 3.6V Inputs, VI -0.3V to VDD + 0.3V Outputs, VO -0.3V to VDDO + 0.3V Input Current, IIN ±20mA Storage Temperature, TSTG -40°C to 125°C 83940DY NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. www.icst.com/products/hiperclocks.html 3 REV. B JUNE 15, 2004 ICS83940D Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER TABLE 4A. DC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = 0° TO 70° Symbol Parameter Test Conditions VIH Input High Voltage LVCMOS_CLK VIL Input Low Voltage LVCMOS_CLK V PP PCLK, nPCLK PCLK, nPCLK IIN Peak-to-Peak Input Voltage Input Common Mode Voltage; NOTE 1, 2 Input Current VOH Output High Voltage IOH = -20mA VOL Output Low Voltage IOL = 20mA VCMR Minimum Typical Maximum Units VDD V 0.8 V 500 1000 mV VDD - 1.4 VDD - 0.6 V ±200 µA 0.5 V 25 mA 2.4 2.4 V Core Supply Current IDD NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = 0° TO 70° Symbol Parameter fMAX Output Frequency tpLH tpLH Propagation Delay Propagation Delay Test Conditions PCLK, nPCLK; NOTE 1, 5 LVCMOS_CLK; NOTE 2, 5 PCLK, nPCLK; NOTE 1, 5 LVCMOS_CLK; NOTE 2, 5 PCLK, nPCLK Minimum Typical Maximum Units 250 MHz f ≤ 150MHz 1.6 3.0 ns f ≤ 150MHz 1.8 3.0 ns f > 150MHz 1.6 3.3 ns f > 150MHz 1.8 3.2 ns 150 ps LVCMOS_CLK Measured on rising edge @VDDO/2 150 ps Par t-to-Par t Skew; NOTE 6 PCLK, nPCLK f ≤ 150MHz 1.4 ns LVCMOS_CLK f ≤ 150MHz 1.2 ns tsk(pp) Par t-to-Par t Skew; NOTE 6 PCLK, nPCLK f > 150MHz 1.7 ns LVCMOS_CLK f > 150MHz 1.4 ns tsk(pp) Par t-to-Par t Skew; NOTE 4, 5 Measured on rising edge @VDDO/2 850 750 ps ps tsk(o) Output Skew; NOTE 3, 5 tsk(pp) tjit tR / tF odc PCLK, nPCLK LVCMOS_CLK Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 7 Output Rise/Fall Time Output Duty Cycle 0.03 0.5 to 2.4V 0.3 f < 134MHz 45 50 ps 1.1 ns 55 % 134MHz ≤ f ≤ 250MHz 40 50 60 % All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 7: Driving only one input clock. 83940DY www.icst.com/products/hiperclocks.html 4 REV. B JUNE 15, 2004 ICS83940D Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER TABLE 4B. DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0° TO 70° Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD V 0.8 V VIH Input High Voltage LVCMOS_CLK VIL Input Low Voltage LVCMOS_CLK V PP PCLK, nPCLK 300 1000 mV PCLK, nPCLK VDD - 1.4 VDD - 0.6 V IIN Peak-to-Peak Input Voltage Input Common Mode Voltage; NOTE 1, 2 Input Current ±200 µA VOH Output High Voltage IOH = -20mA VOL Output Low Voltage IOL = 20mA VCMR 2.4 1.8 V Core Supply Current IDD NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 0.5 V 25 mA TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0° TO 70° Symbol Parameter fMAX tpLH tpLH Test Conditions Minimum Typical Output Frequency Propagation Delay Propagation Delay PCLK, nPCLK; NOTE 1, 5 LVCMOS_CLK; NOTE 2, 5 PCLK, nPCLK; NOTE 1, 5 LVCMOS_CLK; NOTE 2, 5 PCLK, nPCLK Maximum Units 250 MHz f ≤ 150MHz 1.7 3.2 ns f ≤ 150MHz 1.7 3.0 ns f > 150MHz 1.6 3.4 ns f > 150MHz 1.8 3.3 ns 150 ps 150 ps tsk(o) Output Skew; NOTE 3, 5 tsk(pp) Par t-to-Par t Skew; NOTE 6 PCLK, nPCLK f ≤ 150MHz 1.5 ns LVCMOS_CLK f ≤ 150MHz 1.3 ns tsk(pp) Par t-to-Par t Skew; NOTE 6 PCLK, nPCLK f > 150MHz 1.8 ns tsk(pp) Par t-to-Par t Skew; NOTE 4, 5 tjit tR / tF LVCMOS_CLK LVCMOS_CLK PCLK, nPCLK LVCMOS_CLK Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 7 Output Rise/Fall Time Measured on rising edge @VDDO/2 f > 150MHz 1.5 ns Measured on rising edge @VDDO/2 850 750 ps ps 0.03 0.5 to 1.8V 0.3 ps 1.2 ns odc Output Duty Cycle f < 134MHz 45 50 55 % All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 7: Driving only one input clock. 83940DY www.icst.com/products/hiperclocks.html 5 REV. B JUNE 15, 2004 ICS83940D Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER TABLE 4C. DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0° TO 70° Symbol Parameter Test Conditions VIH Input High Voltage LVCMOS_CLK VIL LVCMOS_CLK IIN Input Low Voltage Peak-to-Peak Input Voltage Input Common Mode Voltage; NOTE 1, 2 Input Current VOH Output High Voltage IOH = -12mA VOL Output Low Voltage IOL = 12mA V PP VCMR Minimum Typical 2 Maximum Units VDD V 0.8 V PCLK, nPCLK 300 1000 mV PCLK, nPCLK VDD - 1.4 VDD - 0.6 V ±200 µA 1.8 V Core Supply Current IDD NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 0.5 V 25 mA Maximum 200 Units MHz TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0° TO 70° Symbol Parameter fMAX Output Frequency tpLH tpLH Propagation Delay; Propagation Delay; PCLK, nPCLK; NOTE 1, 5 LVCMOS_CLK; NOTE 2, 5 PCLK, nPCLK; NOTE 1, 5 LVCMOS_CLK; NOTE 2, 5 PCLK, nPCLK Test Conditions Minimum Typical f ≤ 150MHz 1.2 3.8 ns f ≤ 150MHz 1.5 3.2 ns f > 150MHz 1.5 3.7 ns f > 150MHz 2 3.6 ns Measured on rising edge @VDDO/2 200 ps LVCMOS_CLK 200 ps Par t-to-Par t Skew; NOTE 6 PCLK, nPCLK f ≤ 150MHz 2.6 ns LVCMOS_CLK f ≤ 150MHz 1.7 ns tsk(pp) Par t-to-Par t Skew; NOTE 6 PCLK, nPCLK f > 150MHz 2.2 ns f > 150MHz 1.7 ns tsk(pp) Par t-to-Par t Skew; NOTE 4, 5 Measured on rising edge @VDDO/2 1.2 1.0 ns ns tsk(o) Output Skew; NOTE 3, 5 tsk(pp) tjit tR / tF LVCMOS_CLK PCLK, nPCLK LVCMOS_CLK Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 7 Output Rise/Fall Time 0.03 0.5 to 1.8V 0.3 ps 1.2 ns odc Output Duty Cycle f < 134MHz 45 55 % All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 7 Driving only one input clock. 83940DY www.icst.com/products/hiperclocks.html 6 REV. B JUNE 15, 2004 ICS83940D Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 Input/Output Additive Phase Jitter -20 at 155.52MHz = 0.03ps (typical) -30 -40 SSB PHASE NOISE dBc/HZ -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 83940DY vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.icst.com/products/hiperclocks.html 7 REV. B JUNE 15, 2004 ICS83940D Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V±5% 2.05V±5% 1.25V±5% SCOPE VDD, VDDO SCOPE V DD VDDO Qx LVCMOS Qx LVCMOS GND GND -1.65V±5% -1.25V±5% 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 1.25V±5% V DD SCOPE VDD, VDDO nPCLK V Cross Points PP Qx LVCMOS V CMR PCLK GND GND -1.25V±5% 2.5V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART 1 V V DDO DDO Qx Qx 2 2 PART 2 V V DDO DDO Qy Qy 2 t sk(o) t sk(pp) PART-TO-PART SKEW 83940DY 2 OUTPUT SKEW www.icst.com/products/hiperclocks.html 8 REV. B JUNE 15, 2004 ICS83940D Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER V DD 2 LVCMOS_CLK nPCLK PCLK 2.4V 2.4V V DDO 0.5V 0.5V 2 Q0:Q17 Clock Outputs t ➤ t PD ➤ PROPAGATION DELAY R t F 3.3V OUTPUT RISE/FALL TIME 1.8V 1.8V 0.5V 0.5V Clock Outputs t R t F 2.5V OUTPUT RISE/FALL TIME 83940DY www.icst.com/products/hiperclocks.html 9 REV. B JUNE 15, 2004 Integrated Circuit Systems, Inc. ICS83940D LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 83940DY www.icst.com/products/hiperclocks.html 10 REV. B JUNE 15, 2004 ICS83940D Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V SWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested 3.3V 3.3V 3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm R2 50 Zo = 50 Ohm PCLK PCLK R1 100 Zo = 50 Ohm nPCLK nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK HiPerClockS PCLK/nPCLK CML Built-In Pullup FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 nPCLK HiPerClockS Input R5 100 - 200 R2 84 FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER R6 100 - 200 R1 125 FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 3.3V 2.5V 3.3V 3.3V 3.3V 2.5V R3 120 SSTL Zo = 50 Ohm R4 120 C1 LVDS Zo = 60 Ohm R3 1K R4 1K PCLK PCLK R5 100 Zo = 60 Ohm nPCLK R1 120 C2 nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK R1 1K R2 120 FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER 83940DY HiPerClockS PCLK/nPCLK R2 125 FIGURE 2F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER www.icst.com/products/hiperclocks.html 11 HiPerClockS PCL K/n PC LK R2 1K REV. B JUNE 15, 2004 ICS83940D Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS83940D is: 820 83940DY www.icst.com/products/hiperclocks.html 12 REV. B JUNE 15, 2004 ICS83940D Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER FOR 32 LEAD LQFP TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 83940DY www.icst.com/products/hiperclocks.html 13 REV. B JUNE 15, 2004 Integrated Circuit Systems, Inc. ICS83940D LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS83940DY ICS83940DYT ICS83940DY 32 Lead LQFP 250 per tray 0°C to 70°C ICS83940DY 32 Lead LQFP on Tape and Reel 1000 0°C to 70°C ICS83940DYLF ICS83940DYLF 32 Lead "Lead Free" LQFP 250 per tray 0°C to 70°C ICS83940DYLFT ICS83940DYLF 32 Lead "Lead Free" LQFP on Tape and Reel 1000 0°C to 70°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83940DY www.icst.com/products/hiperclocks.html 14 REV. B JUNE 15, 2004 ICS83940D Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER REVISION HISTORY SHEET Rev A Table T5A Page 4 T5B 5 3.3V/2.5V AC Characteristics table - tsk(pp) Test Conditions, replaced "<" with " ≤ "; corrected Units to read "ns" from "ps". T5C 6 T2 2 2.5V AC Characteristics table - tsk(pp) Test Conditions, replaced "<" with " ≤ "; corrected Units to "ns" from "ps". Pin Characteristics table - changed ROUT 25Ω maximum to 28Ω maximum. Delete RPULLUP row. 7 A Description of Change 3.3V AC Characteristics table • tsk(pp) Test Conditions, replaced "<" with " ≤ "; corrected Units to "ns" from "ps". • odc - corrected Test Conditions to read "134MHz ≤ f ≤ 250MHz", from "f ≤ 250MHz". 3.3V Output Load AC Test Circuit diagram - corrected GND equation to read -1.65V... from -1.165V... Date 10/11/02 12/12/02 Added LVTTL to title. T1 T2 B B 83940DY T5A T5B T5C T5A - T5C 2 2 4 5 6 7 10 11 1 4-6 11 14 Updated format. Pin Description Table - added Pullup and Pulldown to Pin 6, nPCLK. Pin Characteristics Table - added RPULLUP row. Added tjit row. Added tjit row. Added tjit row. Added Additive Phase Jitter section. Updated Single Ended Signal Driving Differential Input diagram. Added LVPECL Clock Interface section. Added "Lead-Free" bullet to Features section. Added NOTE 7. Updated LVPECL Clock Input Interface section. Ordering Information table - added "Lead-Free" par t number. www.icst.com/products/hiperclocks.html 15 10/9/03 6/15/04 REV. B JUNE 15, 2004