DS2223/DS2224 DS2223/DS2224 EconoRAM FEATURES PACKAGE OUTLINE • Low–cost, general–purpose, 256–bit memory TO–92 – DS2223 has 256–bit SRAM – DS2224 has 32–bit ROM, 224–bit SRAM • Reduces control, address and data interface to a single pin • Each DS2224 32–bit ROM is factory–lasered with a unique serial number • DS2224 portion of ROM with custom code and unique serial number available SOT–223 1 • Minimal operating power: 45 nanocoulombs per transaction @1.5V typical 1 2 3 1 2 3 • Less than 15 nA standby current at 25°C • Nonvolatile data retention easily achieved via low– cost alkaline batteries or capacitors • Directly connects to a port pin of popular microcontrol- 2 BOTTOM VIEW See Mech. Drawings Section 4 3 TOP VIEW See Mech. Drawings Section lers • Operation from 1.2 to 5.5 volts • Popular TO–92 or SOT–223 surface mount package • Operates over industrial temperature range –40°C to +85°C PIN CONNECTIONS Pin 1 Pin 2 Pin 3 Pin 4 GND DQ VCC GND – – – – Ground Data In/Out Supply Ground DESCRIPTION ORDERING INFORMATION The DS2223 and DS2224 EconoRAMs are fully static, micro–powered, read/write memories in low–cost TO–92 or SOT–223 packages. The DS2223 is organized as a serial 256 x 1 bit static read/write memory. The DS2224’s first 32 bits are lasered with a unique ID code at the time of manufacture; the remaining 224 bits are static read/write memory. Signaling necessary for reading or writing is reduced to just one interface lead. DS2223 DS2223Z DS2223T DS2223Y DS2224 DS2224Z DS2224T DS2224Y 256–bit SRAM – TO–92 Package 256–bit SRAM – SOT–223 Package 1000 piece tape–and–reel of DS2223 2500 piece tape–and–reel of DS2223Z 32–bit serial number (ROM), 224–bit SRAM – TO–92 Package 32–bit serial number (ROM), 224–bit SRAM – SOT–223 Package 1000 piece tape–and–reel of DS2224 2500 piece tape–and–reel of DS2224Z Both the DS2223 and DS2224 are not recommended for new designs. However, the parts will remain available until the year 2003, at least. 080598 1/10 DS2223/DS2224 OPERATION READ OR WRITE TRANSACTION All communications to and from the EconoRAM are accomplished via a single interface lead. EconoRAM data is read and written through the use of time slots. All data is preceded by a command byte to specify the type of transaction. Once a specific transaction has been initiated, either a read or a write, it must be completed for all memory locations before another transaction can be started. Read or write transactions are performed by initializing the EconoRAM to a known state, issuing a command byte, and then generating the time slots to either read EconoRAM contents or write new data. Each transaction consists of 264 time slots. Eight time slots transmit the command byte, the remaining 256 time slots transfer the data bits. (See Figure 5.) Once a transaction is started, it must be completed before a new transaction can begin. 1–WIRE SIGNALLING To initially set the EconoRAM into a known state, 264 Write Zero time slots must be sent by the host. These Write Zero time slots will not corrupt the data in the EconoRAM since a command byte has not been written. This operation will increment the address pointer internal to the EconoRAM to its maximum count value. Upon reaching this maximum value, the EconoRAM will ignore all additional Write Zero time slots issued to it and the internal address pointer will remain locked at the top count value. This condition is removed by the reception of a Write One time slot, typically the first bit of a command byte. The EconoRAM requires strict protocols to insure data integrity. The protocol consists of three types of signalling on one line: Write 0 time slot, Write 1 time slot and Read Data time slot. All these signals are initiated by the host. READ/WRITE TIME SLOTS The definitions of write and read time slots are illustrated in Figures 1 through 3. All time slots are initiated by the host driving the data line low. The falling edge of the data line synchronizes the EconoRAM to the host by triggering a delay circuit in the EconoRAM. During write time slots, the delay circuit determines when the EconoRAM will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit determines how long the EconoRAM will hold the data line low overriding the 1 generated by the host. If the data bit is a “1”, the EconoRAM will leave the read data time slot unchanged. COMMAND BYTE The command byte to specify the type of transaction is transmitted LSB first from the host to the EconoRAM using write time slots. The first bit of the command byte (see Figure 4) is a logic 1. This indicates to the EconoRAM that a command byte is being written. The next two bits are the select bits which denote the physical address of the EconoRAM that is to be accessed (set to 00 currently). The remaining five bits determine whether a read or a write operation is to follow. If a write operation is to be performed, all five bits are set to a logic 1 level. If a read operation is to be performed, any or all of these bits are set to a logic 0 level. All eight bits of the command byte are transmitted to the EconoRAM with a separate time slot for each bit. 080598 2/10 Once the EconoRAM has been set into a known state, the command byte is transmitted to the EconoRAM with eight write time slots. This resets the address pointer internal to the EconoRAM and prepares it for the appropriate operation, either a read or a write. After the command byte has been received by the EconoRAM, the host controls the transfer of data. In the case of a read transaction, the host issues 256 read time slots. In the case of a write transaction, the host issues 256 write time slots according to the data to be written. All data is read and written least significant bit first. Although the DS2224 has the first 32 bits replaced by lasered ROM rather than SRAM, it requires 256 write time slots for a complete write transaction. The data being sent during the first 32 write time slots has no effect on the DS2224 other than advancing the internal address pointer. As stated previously, it is not possible to change from read to write or vice versa before a transaction is completed. DS2223/DS2224 READ/WRITE TIMING DIAGRAM Write–One Time Slot Figure 1 tSLOT tREC VPULLUP VPULLUP MIN VIH MIN VIL MAX 0V DS2223/DS2224 SAMPLING WINDOW tLOW1 15 µs 60 µs 60 µs < tSLOT < 1 µs < tLOW1 < 15 µs 1 µs < tREC < Write–Zero Time Slot Figure 2 tREC tSLOT VPULLUP VPULLUP MIN VIH MIN VIL MAX 0V DS2223/DS2224 SAMPLING WINDOW 15 µs 60 µs tLOW0 60 µs < tLOW0 < tSLOT < 1 µs < tREC < Read–Data Time Slot Figure 3 tSLOT tREC VPULLUP VPULLUP MIN VIH MIN HOST SAMPLING WINDOW VIL MAX 0V tLOWR tRELEASE tRDV RESISTOR MASTER DS2223/DS2224 60 µs < tSLOT < 1 µs < tLOWR < 15 µs 0 < tRELEASE < 45 µs 1 µs < tREC < tRDV = 15 µs 080598 3/10 DS2223/DS2224 COMMAND WORD Figure 4 MSB W/R LSB W/R W/R W/R W/R 0 ALL 1s – WRITE ANY 0 – READ 0 SELECT BITS READ/WRITE TRANSACTION Figure 5 LSB DS2223 COMMAND WORD DS2224 COMMAND WORD 256–BIT SRAM ROM 224–BIT SRAM READ/WRITE FLOW RECEIVE COMMAND WORD (RESET ADDRESS POINTER) 264–BIT TRANSACTION READ/WRITE DATA BIT AND INCREMENT ADDRESS POINTER IS ADDRESS POINTER = 256? Y HOLD ADDRESS POINTER VALUE, WAIT FOR NEW COMMAND WORD TO RESET ADDRESS COUNTER 080598 4/10 8 BITS N 1 DS2223/DS2224 TYPICAL CURRENT CONSUMPTION VS. BIT RATE Figure 6 4V @ +25°C CURRENT CONSUMPTION 10 µA 1 µA 129 pC/BIT 100 nA 10 nA 5 nA 10 bps 100 bps 1 kbps 10 kbps 100 kbps BIT RATE TYPICAL LEAKAGE CURRENT VS. TEMPERATURE Figure 7 15.0 12.0 NANOAMPS LEAKAGE CURRENT VCC = 4.0V 9.0 6.0 3.0 0.0 –10 0 +10 +20 +30 +40 +50 +60 +70 TEMPERATURE (DEG. C) 080598 5/10 DS2223/DS2224 1–WIRE INTERFACE The 1–Wire interface has only a single line by definition; it is important that host and EconoRAM be able to drive it at the appropriate time. The EconoRAM is an open drain part with an internal circuit equivalent to that shown in Figure 8. The host can be the same equivalent circuit. If a bidirectional pin is not available, separate output and input pins can be tied together. The 1–Wire interface requires a pull–up resistor with a value of approximately 5 kΩ to system VCC on the data signal line. The EconoRAM has an internal open–drain driver with a 500 kΩ pull–down resistor to ground. The open–drain driver allows the EconoRAM to be powered by a small standby energy source, such as a single 1.5 volt alkaline battery, and still have the ability to produce CMOS/TTL output levels. The pull–down resistor holds the DQ pin at ground when the EconoRAM is not connected to the host. APPLICATION EXAMPLES EconoRAMs are extremely conservative with power. Data can be retained in these small memories for as long as a month using the energy stored in a capacitor. Data is retained as long as the voltage on the VCC pin of the EconoRAM (VCAP) is at least 1.2 volts. A typical circuit is shown in Figure 9. When VCC is applied, capacitor C1 is charged and the EconoRAM receives power directly from VCC. After power is removed, the diode CR1 prevents current from leaking back into the system, keeping the capacitor charged. In the standby mode, the EconoRAM typically consumes only 12 nA at 25°C. However, the power–down process of the system can cause a slightly higher current drain. This is due to the fact that as system power ramps down, the signal attached to the DQ pin of the EconoRAM transitions slowly through the linear region, while the VCAP voltage remains at its initial value. While in this region, the part draws more current as a function of the DQ pin voltage (see Figure 10). The data retention time can be estimated with the aid of Figure 11. In this figure, the vertical axis represents the value of the capacitor C1; the horizontal axis is the data retention time in hours. The two curves represent initial VCAP voltages of 3 and 5 volts. These curves are based on the assumption that the time the DQ pin is in the linear region is less than 100 ms. HOST TO ECONORAM INTERFACE Figure 8 VCC VCC 5 kΩ TX RX OPEN DRAIN 500 kΩ TX 100 OHM MOSFET RX HOST 080598 6/10 ECONORAM DS2223/DS2224 SUGGESTED CIRCUIT Figure 9 VCC VCAP + VCC C1 CR1 Econo Memory DQ GND ICC VS. DQ VOLTAGE Figure 10 SUPPLY CURRENT (µA) VCC = +5V Room Temperature 400 200 SUPPLY CURRENT <2 nA 0 0 1 2 3 4 5 DQ PIN VOLTAGE 080598 7/10 DS2223/DS2224 DATA RETENTION TIME VS. CAPACITANCE Figure 11 CAPACITANCE (µF) 10K 1K Initial VCC Voltage VCC = 3.0 VCC = 5.0 100 10 0 0.1 1 10 100 1K 10K TIME (hours) Using Battery Backup 14 mA–Hr => 144 million transactions 3 DATA PIN 2 + DS2223 DS2224 1 080598 8/10 1.5V EVEREADY NO. 321 DS2223/DS2224 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature –0.5V to +6.5V –40°C to +85°C –55°C to +125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER SYMBOL MIN Data Pin DQ Supply Voltage VCC (–40°C to +85°C) TYP MAX UNITS NOTES –0.5 6.0 V 1 1.2 5.5 V 1 DC ELECTRICAL CHARACTERISTICS PARAMETER (–40°C to +85°C; VCC=2.0V to 5.5V) SYMBOL MIN TYP MAX UNITS NOTES Input Logic Low VIL –0.5 0.4 0.8 V 1 Input Logic High VIH VCC–0.5 6.0 V 1 IL 1 mA 4 0.4 V 1 5.5 V 1, 2 kΩ 3 36 nC 5 25 nA 6 Sink Current Output Logic Low VOL Output Logic High VOH Input Resistance IR Operating Current IOP Standby Current 2 VPUP 500 ISTBY 2 (–40°C to +85°C; VCC=1.4V ± 10%) DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL MIN Input Logic Low VIL Input Logic High Sink Current MAX UNITS NOTES –0.5 0.2 V 1 VIH 1.0 6.0 V 1 IL 1 mA 7 0.4 V 4 5.5 V 1, 2 kΩ 3 36 nC 5 15 nA 6 Output Logic Low VOL Output Logic High VOH Input Resistance IR Operating Current IOP Standby Current ISTBY TYP 2 VPUP 500 2 080598 9/10 DS2223/DS2224 (–40°C to +85°C; VCC=1.4V ± 10%) AC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL MIN Time Slot tSLOT 70 Read Data Valid tRDV Release Time TYP 0 Write 1 Low Time tLOW1 1 Write 0 Low Time tLOW0 60 Data Setup Time tSU Recovery Time tREC 15 Read Data Valid Release Time NOTES µs 45 µs 15 µs µs 1 µs 8 µs 1 AC ELECTRICAL CHARACTERISTICS Time Slot UNITS µs exactly 15 tRELEASE PARAMETER MAX (–40°C to +85°C; VCC=2.0V to 5.5V) SYMBOL MIN tSLOT 60 tRDV TYP MAX 0 Write 1 Low Time tLOW1 1 Write 0 Low Time tLOW0 60 Data Setup Time tSU Recovery Time tREC NOTES µs µs exactly 15 tRELEASE UNITS 15 45 µs 15 µs µs 1 1 µs 8 µs NOTES: 1. All voltages are referenced to ground. 2. VPUP = external pull–up voltage to system sypply. 3. Input pull–down resistance to ground. 4. @ VOL=0.4V 5. 36 nanocoulombs per 264 time slots @ 1.5V (see Figure 6). 6. See Figure 7 for typical values over temperature. 7. @ VOL=0.2V 8. Read data setup time refers to the time the host must pull the 1–Wire line low to read a bit. Data is guaranteed to be valid within 1 µs of this falling edge and will remain valid for 14 µs minimum (15 µs total from falling edge on the 1–Wire line). 080598 10/10