AD ADuM3300BRWZ Triple-channel, digital isolators, enhanced system-level esd reliability Datasheet

Triple-Channel, Digital Isolators,
Enhanced System-Level ESD Reliability
ADuM3300/ADuM3301
Data Sheet
FEATURES
GENERAL DESCRIPTION
Enhanced system-level ESD performance per IEC 61000-4-x
Low power operation
5 V operation
2.0 mA per channel maximum @ 0 Mbps to 2 Mbps
4.1 mA per channel maximum @ 10 Mbps
36 mA per channel maximum @ 90 Mbps
3 V operation
1.0 mA per channel maximum @ 0 Mbps to 2 Mbps
2.8 mA per channel maximum @ 10 Mbps
17 mA per channel maximum @ 90 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics
2 ns maximum pulse width distortion
2 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body, RoHS-compliant package
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
VIORM = 560 V peak
The ADuM330x 1 are 3-channel digital isolators based on the
Analog Devices, Inc. iCoupler® technology. Combining high
speed CMOS and monolithic air core transformer technology,
these isolation components provide outstanding performance
characteristics superior to alternatives, such as optocoupler devices.
APPLICATIONS
General-purpose multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
iCoupler devices remove the design difficulties commonly
associated with optocouplers. Typical optocoupler concerns
regarding uncertain current transfer ratios, nonlinear transfer
functions, and temperature and lifetime effects are eliminated
with the simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete
components is eliminated with these iCoupler products.
Furthermore, iCoupler devices consume one-tenth to one-sixth
the power of optocouplers at comparable signal data rates.
The ADuM330x isolators provide three independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). All models operate with the supply
voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. The
ADuM330x isolators have a patented refresh feature that ensures dc
correctness in the absence of input logic transitions and during
power-up/power-down conditions.
In comparison to ADuM130x isolators, ADuM330x isolators
contain various circuit and layout changes to provide increased
capability relative to system-level IEC 61000-4-x testing (ESD,
burst, and surge). The precise capability in these tests for either
the ADuM130x or ADuM330x products is strongly determined
by the design and layout of the user’s system.
1
Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329.
VDD1 1
16
VDD2
VDD1 1
16
VDD2
GND1 2
15
GND2
GND1 2
15
GND2
ENCODE
DECODE
14
VOA
VIA 3
ENCODE
DECODE
14
VOA
VIB 4
ENCODE
DECODE
13
VOB
VIB 4
ENCODE
DECODE
13
VOB
VIC 5
ENCODE
DECODE
12
VOC
VOC 5
DECODE
ENCODE
12
VIC
NC 6
11
NC
NC 6
11
NC
NC 7
10
VE2
VE1 7
10
VE2
GND1 8
9
GND2
GND1 8
9
GND2
05984-001
VIA 3
05984-002
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. ADuM3300 Functional Block Diagram
Figure 2. ADuM3301 Functional Block Diagram
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2012 Analog Devices, Inc. All rights reserved.
Rev. B
ADuM3300/ADuM3301
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Recommended Operating Conditions .................................... 11
Applications....................................................................................... 1
Absolute Maximum Ratings ......................................................... 12
General Description ......................................................................... 1
ESD Caution................................................................................ 12
Functional Block Diagrams............................................................. 1
Pin Configurations and Function Descriptions ......................... 13
Revision History ............................................................................... 2
Typical Performance Characteristics ........................................... 15
Specifications..................................................................................... 3
Application Information................................................................ 17
Electrical Characteristics—5 V Operation................................ 3
PC Board Layout ........................................................................ 17
Electrical Characteristics—3 V Operation................................ 5
System-Level ESD Considerations and Enhancements ........ 17
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation....................................................................................... 7
Propagation Delay-Related Parameters................................... 17
Package Characteristics ............................................................. 10
Power Consumption .................................................................. 18
Regulatory Information............................................................. 10
Insulation Lifetime ..................................................................... 19
Insulation and Safety-Related Specifications.......................... 10
Outline Dimensions ....................................................................... 20
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 11
Ordering Guide .......................................................................... 20
DC Correctness and Magnetic Field Immunity........................... 17
REVISION HISTORY
2/12—Rev. A to Rev. B
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section................................................................. 1
Change to PC Board Layout Section............................................ 17
Updated Outline Dimensions ....................................................... 20
6/07—Rev. 0 to Rev. A
Updated VDE Certification Throughout ...................................... 1
Changes to Features, General Description, and Note 1............... 1
Changes to Regulatory Information Section .............................. 10
Changes to DIN V VDE V 0884-10 (VDE V 0884-10)
Insulation Characteristics.............................................................. 11
Added Table 10 ............................................................................... 12
Added Insulation Lifetime Section .............................................. 19
3/06—Revision 0: Initial Version
Rev. B | Page 2 of 20
Data Sheet
ADuM3300/ADuM3301
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.
Table 1.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM3300, Total Supply Current, Four Channels 1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM3301, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM330xARWZ
Minimum Pulse Width 2
Maximum Data Rate 3
Propagation Delay 4
Pulse Width Distortion, |tPLH − tPHL|4
Propagation Delay Skew 5
Channel-to-Channel Matching 6
Symbol
Typ
Max Unit
IDDI (Q)
IDDO (Q)
0.66
0.39
0.97
0.55
mA
mA
IDD1 (Q)
IDD2 (Q)
2.4
1.1
3.3
2.1
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
7.0
2.7
8.1
3.6
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (90)
IDD2 (90)
54
15
77
31
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
IDD1 (Q)
IDD2 (Q)
2.0
1.6
3.1
2.3
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
5.5
3.9
6.9
5.4
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (90)
IDD2 (90)
41
28
57
41
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
μA
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH,
VOCH, VODH
VOAL, VOBL,
VOCL, VODL
Min
−10
+0.01 +10
2.0
0.8
5.0
(VDD1 or
VDD2) − 0.1
4.8
(VDD1 or
VDD2) − 0.4
0.0
0.04
0.2
PW
tPHL, tPLH
PWD
tPSK
tPSKCD/OD
1
50
Rev. B | Page 3 of 20
65
0.1
0.1
0.4
Test Conditions
V
V
V
IOx = −20 μA, VIx = VIxH
V
IOx = −4 mA, VIx = VIxH
V
V
V
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
1000 ns
Mbps
100 ns
40
ns
50
ns
50
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
ADuM3300/ADuM3301
Parameter
ADuM330xBRWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
Channel-to-Channel Matching,
Opposing-Directional Channels6
ADuM330xCRWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
Channel-to-Channel Matching,
Opposing-Directional Channels6
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance-to-High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output 7
Common-Mode Transient Immunity
at Logic Low Output7
Refresh Rate
Input Dynamic Supply Current per Channel 8
Output Dynamic Supply Current per Channel8
Data Sheet
Symbol
Min
Typ
PW
Max Unit
Test Conditions
100
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
15
3
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
11.1
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
10
20
32
50
3
5
PW
tPSK
tPSKCD
10
2
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
90
18
8.3
120
27
0.5
3
32
2
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
tR/tF
|CMH|
25
2.5
35
ns
kV/μs
|CML|
25
35
kV/μs
1.2
0.20
0.05
Mbps
mA/Mbps
mA/Mbps
fr
IDDI (D)
IDDO (D)
1
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3300/ADuM3301 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. B | Page 4 of 20
Data Sheet
ADuM3300/ADuM3301
ELECTRICAL CHARACTERISTICS—3 V OPERATION
All voltages are relative to their respective ground. 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V.
Table 2.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM3300, Total Supply Current, Four Channels 1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM3301, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM330xARWZ
Minimum Pulse Width 2
Maximum Data Rate 3
Propagation Delay 4
Pulse Width Distortion, |tPLH − tPHL|4
Propagation Delay Skew 5
Channel-to-Channel Matching 6
Symbol
Typ
Max
Unit
IDDI (Q)
IDDO (Q)
0.37
0.25
0.57
0.37
mA
mA
IDD1 (Q)
IDD2 (Q)
1.4
0.7
1.9
1.2
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
3.8
1.5
5.3
2.1
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (90)
IDD2 (90)
28
8.2
41
11
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
IDD1 (Q)
IDD2 (Q)
1.1
0.9
1.6
1.4
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
IDD1 (10)
IDD2 (10)
3.0
2.2
4.1
2.9
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDD1 (90)
IDD2 (90)
22
15
31
21
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
μA
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1,VE2 ≤ VDD1 or VDD2
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH,
VOCH, VODH
VOAL, VOBL,
VOCL, VODL
Min
−10
+0.01 +10
1.6
0.4
3.0
(VDD1 or
VDD2) − 0.1
2.8
(VDD1 or
VDD2) − 0.4
0.0
0.04
0.2
PW
tPHL, tPLH
PWD
tPSK
tPSKCD/OD
1
50
Rev. B | Page 5 of 20
75
0.1
0.1
0.4
Test Conditions
V
V
V
IOx = −20 μA, VIx = VIxH
V
IOx = −4 mA, VIx = VIxH
V
V
V
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
1000 ns
Mbps
100 ns
40
ns
50
ns
50
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
ADuM3300/ADuM3301
Parameter
ADuM330xBRWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
Channel-to-Channel Matching,
Opposing-Directional Channels6
ADuM330xCRWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
Channel-to-Channel Matching,
Opposing-Directional Channels6
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance-to-High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output 7
Common-Mode Transient Immunity
at Logic Low Output7
Refresh Rate
Input Dynamic Supply Current per Channel 8
Output Dynamic Supply Current per Channel8
Data Sheet
Symbol
Min
Typ
PW
Max
Unit
Test Conditions
100
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
22
3
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
11.1
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
10
20
38
50
3
5
PW
tPSK
tPSKCD
16
2
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
90
20
8.3
120
34
0.5
3
45
2
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
tR/tF
|CMH|
25
3
35
ns
kV/μs
|CML|
25
35
kV/μs
1.1
0.10
0.03
Mbps
mA/Mbps
mA/Mbps
fr
IDDI (D)
IDDO (D)
1
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3300/ADuM3301 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. B | Page 6 of 20
Data Sheet
ADuM3300/ADuM3301
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation:
2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted. All typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.0 V.
Table 3.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current per Channel, Quiescent
5 V/3 V Operation
3 V/5 V Operation
ADuM3300, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
ADuM3301, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
Symbol
Min
Typ
Max
Unit
Test Conditions
0.66
0.37
0.97
0.57
mA
mA
0.25
0.39
0.37
0.55
mA
mA
2.4
1.4
3.3
1.9
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
0.7
1.1
1.2
2.1
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
7.0
3.8
8.1
5.3
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
1.5
2.7
2.1
3.6
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
54
28
77
41
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
8.2
15
11
31
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
2.0
1.1
3.1
1.6
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
0.9
1.6
1.4
2.3
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
5.5
3.0
6.9
4.1
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
2.2
3.9
2.9
5.4
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
IDDI (Q)
IDDO (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (10)
IDD2 (10)
IDD1 (90)
IDD2 (90)
IDD1 (Q)
IDD2 (Q)
IDD1 (10)
IDD2 (10)
Rev. B | Page 7 of 20
ADuM3300/ADuM3301
Parameter
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
For All Models
Input Currents
Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM330xARWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Propagation Delay Skew5
Channel-to-Channel Matching6
ADuM330xBRWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
Channel-to-Channel Matching,
Opposing-Directional Channels6
ADuM330xCRWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
Channel-to-Channel Matching,
Opposing-Directional Channels6
Data Sheet
Symbol
Min
Typ
Max
Unit
Test Conditions
41
22
57
31
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
15
28
21
41
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
IDD1 (90)
IDD2 (90)
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
−10
2.0
1.6
V
V
VIL, VEL
0.8
0.4
VOAH, VOBH, (VDD1 or
VOCH, VODH VDD2) − 0.1
(VDD1 or
VDD2) − 0.4
VOAL, VOBL,
VOCL, VODL
(VDD1 or VDD2)
(VDD1 or
VDD2) − 0.2
0.0
0.04
0.2
PW
tPHL, tPLH
PWD
tPSK
tPSKCD/OD
1
50
70
PW
0.1
0.1
0.4
V
V
V
IOx = −20 μA, VIx = VIxH
V
IOx = −4 mA, VIx = VIxH
V
V
V
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
1000 ns
Mbps
100 ns
40
ns
50
ns
50
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
100
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
22
3
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
11.1
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
10
15
35
50
3
5
PW
tPSK
tPSKCD
14
2
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
5
ns
tPHL, tPLH
PWD
90
20
8.3
120
30
0.5
3
Rev. B | Page 8 of 20
40
2
Data Sheet
Parameter
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance-to-High/Low)
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3 V/5 V Operation
Common-Mode Transient Immunity
at Logic High Output7
Common-Mode Transient Immunity
at Logic Low Output7
Refresh Rate
5 V/3 V Operation
3 V/5 V Operation
Input Dynamic Supply Current per Channel8
5 V/3 V Operation
3 V/5 V Operation
Output Dynamic Supply Current per Channel8
5 V/3 V Operation
3 V/5 V Operation
ADuM3300/ADuM3301
Symbol
Min
Typ
Max
Unit
Test Conditions
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
tR/tF
CL = 15 pF, CMOS signal levels
|CMH|
25
3.0
2.5
35
ns
ns
kV/μs
|CML|
25
35
kV/μs
1.2
1.1
Mbps
Mbps
0.20
0.10
mA/Mbps
mA/Mbps
0.05
0.03
mA/Mbps
mA/Mbps
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
fr
IDDI (D)
IDDO (D)
1
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3300/ADuM3301/ADuM3302 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. B | Page 9 of 20
ADuM3300/ADuM3301
Data Sheet
PACKAGE CHARACTERISTICS
Table 4.
Parameter
Resistance (Input to Output) 1
Capacitance (Input to Output)1
Input Capacitance 2
IC Junction-to-Case Thermal Resistance, Side 1
IC Junction-to-Case Thermal Resistance, Side 2
1
2
Symbol
RI-O
CI-O
CI
θJCI
θJCO
Min
Typ
1012
2.2
4.0
33
28
Max
Unit
Ω
pF
pF
°C/W
°C/W
Test Conditions
f = 1 MHz
Thermocouple located at
center of package underside
The device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM330x is approved by the organizations listed in Table 5. See Table 10 and the Insulation Lifetime section for details regarding
recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 5.
UL
Recognized under UL 1577
Component Recognition
Program 1
Double/reinforced insulation,
2500 V rms isolation voltage
File E214100
1
2
CSA
Approved under CSA Component Acceptance Notice #5A
VDE
Certified according to DIN V VDE V
0884-10 (VDE V 0884-10): 2006-12 2
Basic insulation per CSA 60950-1-03 and IEC 60950-1,
800 V rms (1131 V peak) maximum working voltage
Reinforced insulation per CSA 60950-1-03 and IEC 60950-1,
400 V rms (566 V peak) maximum working voltage
File 205078
Reinforced insulation, 560 V peak
File 2471900-4880-0001
In accordance with UL1577, each ADuM330x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 second (current leakage detection limit = 5 μA).
In accordance with DIN V VDE V 0884-10, each ADuM330x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection
limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol Value
2500
L(I01)
7.7 min
Unit Conditions
V rms 1-minute duration
mm
Measured from input terminals to output terminals,
shortest distance through air
8.1 min
mm
Measured from input terminals to output terminals,
shortest distance path along body
0.017 min mm
Insulation distance through insulation
>175
V
DIN IEC 112/VDE 0303 Part 1
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Minimum External Tracking (Creepage)
L(I02)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
Rev. B | Page 10 of 20
Data Sheet
ADuM3300/ADuM3301
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage.
Table 7.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Safety-Limiting Values
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
Symbol
Characteristic
Unit
VIORM
VPR
I to IV
I to III
I to II
40/105/21
2
560
1050
V peak
V peak
896
672
V peak
V peak
VTR
4000
V peak
TS
IS1
IS2
RS
150
265
335
>109
°C
mA
mA
Ω
VPR
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
Transient overvoltage, tTR = 10 seconds
Maximum value allowed in the event of a failure
(see Figure 3)
VIO = 500 V
350
RECOMMENDED OPERATING CONDITIONS
300
Table 8.
Parameter
Operating Temperature
Supply Voltages 1
Input Signal Rise and Fall Times
250
SIDE #2
200
Symbol
TA
VDD1, VDD2
Min Max
−40 +105
2.7 5.5
1.0
Unit
°C
V
ms
150
SIDE #1
1
100
All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section for information on immunity to external
magnetic fields.
50
0
0
50
100
150
CASE TEMPERATURE (°C)
200
05984-003
SAFETY-LIMITING CURRENT (mA)
Case Temperature
Side 1 Current
Side 2 Current
Insulation Resistance at TS
Conditions
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Rev. B | Page 11 of 20
ADuM3300/ADuM3301
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 9.
Parameter
Storage Temperature
Ambient Operating
Temperature
Supply Voltages1
Input Voltage1, 2
Output Voltage1, 2
Average Output
Current per Pin3
Side 1
Side 2
Common-Mode
Transients4
Symbol
TST
TA
Min
−65
−40
Max
+150
+105
Unit
°C
°C
VDD1, VDD2
VIA, VIB, VIC,
VID, VE1, VE2
VOA, VOB, VOC,
VOD
−0.5
−0.5
+7.0
VDDI + 0.5
V
V
−0.5
VDDO + 0.5
V
IO1
IO2
CMH, CML
−23
−30
−100
+23
+30
+100
mA
mA
kV/μs
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1
All voltages are relative to their respective ground.
VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively.
3
See Figure 3 for maximum rated current values for various temperatures.
4
Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Rating can cause latch-up
or permanent damage.
2
Table 10. Maximum Continuous Working Voltage1
Parameter
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
Basic Insulation
Reinforced Insulation
1
Max
565
Unit
V peak
Constraint
50-year minimum lifetime
1131
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1131
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 11. Truth Table (Positive Logic)
VIX Input 1
H
L
X
X
VEX Input 2
H or NC
H or NC
L
H or NC
VDDI State1
Powered
Powered
Powered
Unpowered
VDDO State1
Powered
Powered
Powered
Powered
VOX Output1
H
L
Z
H
X
X
L
X
Unpowered
Powered
Powered
Unpowered
Z
Indeterminate
Notes
Outputs return to the input state within 1 μs of VDDI power
restoration
Outputs return to the input state within 1 μs of VDDO power
restoration if VEX state is H or NC
Outputs return to high impedance state within 8 ns of VDDO
power restoration if VEX state is L
1
VIX and VOX refer to the input and output signals of a given channel (A, B, or C). VEX refers to the output enable signal on the same side as the VOX outputs. VDDI and VDDO
refer to the supply voltages on the input and output sides of the given channel, respectively.
2
In noisy environments, connecting VEX to an external logic high or low is recommended.
Rev. B | Page 12 of 20
Data Sheet
ADuM3300/ADuM3301
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1
16
VDD2
GND1* 2
15
GND2**
VIA 3
14
VOA
ADuM3300
VIB 4
TOP VIEW 13 VOB
VIC 5 (Not to Scale) 12 VOC
NC 6
11 NC
NC 7
10
VE2
GND1* 8
9
GND2**
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND
CONNECTING BOTH TO GND1 IS RECOMMENDED.
**PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND2 IS RECOMMENDED. IN NOISY ENVIRONMENTS,
CONNECTING OUTPUT ENABLES (PIN 7 FOR ADuM3301 AND PIN 10 FOR
ALL MODELS) TO AN EXTERNAL LOGIC HIGH OR LOW IS RECOMMENDED.
05984-004
NC = NO CONNECT
Figure 4. ADuM3300 Pin Configuration
Table 12. ADuM3300 Pin Function Descriptions
Pin No.
1
2, 8
3
4
5
6, 7, 11
9, 15
10
Mnemonic
VDD1
GND1
VIA
VIB
VIC
NC
GND2
VE2
12
13
14
16
VOC
VOB
VOA
VDD2
Description
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground Reference for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
No Connect.
Ground 2. Ground Reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected.
VOA, VOB, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic
high or low is recommended.
Logic Output C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. B | Page 13 of 20
ADuM3300/ADuM3301
Data Sheet
VDD1 1
16 VDD2
*GND1 2
VIA 3
15 GND2**
ADuM3301
14 VOA
VIB 4
TOP VIEW 13 VOB
VOC 5 (Not to Scale) 12 VIC
NC 6
11 NC
VE1 7
10 VE2
*GND1 8
9
GND2**
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED,
AND CONNECTING BOTH TO GND1 IS RECOMMENDED.
**PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED,
AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
05984-005
NC = NO CONNECT
Figure 5. ADuM3301 Pin Configuration
Table 13. ADuM3301 Pin Function Descriptions
Pin No.
1
2, 8
3
4
5
6, 11
7
Mnemonic
VDD1
GND1
VIA
VIB
VOC
NC
VE1
9, 15
10
GND2
VE2
12
13
14
16
VIC
VOB
VOA
VDD2
Description
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Output C.
No Connect.
Output Enable 1. Active high logic input. VOC output is enabled when VE1 is high or disconnected. VOC is
disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is
recommended.
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected.
VOA and VOB outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic
high or low is recommended.
Logic Input C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Rev. B | Page 14 of 20
Data Sheet
ADuM3300/ADuM3301
20
80
15
60
CURRENT (mA)
CURRENT/CHANNEL (mA)
TYPICAL PERFORMANCE CHARACTERISTICS
5V
10
3V
5
40
5V
20
0
20
40
60
DATA RATE (Mbps)
80
100
0
05984-006
0
0
20
80
15
60
10
40
60
DATA RATE (Mbps)
5
100
40
20
5V
5V
3V
20
40
60
DATA RATE (Mbps)
80
100
0
05984-007
0
0
80
15
60
CURRENT (mA)
20
5V
40
60
DATA RATE (Mbps)
80
100
Figure 10. Typical ADuM3300 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Figure 7. Typical Output Supply Current per Channel vs. Data Rate (No Load)
10
20
05984-010
3V
0
5
40
5V
20
3V
0
0
20
40
60
DATA RATE (Mbps)
80
100
05984-008
3V
Figure 8. Typical Output Supply Current per Channel vs. Data Rate
(15 pF Output Load)
0
0
20
40
60
DATA RATE (Mbps)
80
100
Figure 11. Typical ADuM3301 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Rev. B | Page 15 of 20
05984-011
CURRENT/CHANNEL (mA)
80
Figure 9. Typical ADuM3300 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
CURRENT (mA)
CURRENT/CHANNEL (mA)
Figure 6. Typical Input Supply Current per Channel vs. Data Rate (No Load)
20
05984-009
3V
ADuM3300/ADuM3301
Data Sheet
40
80
PROPAGATION DELAY (ns)
40
5V
20
3V
35
30
5V
0
0
20
40
60
DATA RATE (Mbps)
80
100
Figure 12. Typical ADuM3301 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
25
–50
–25
0
25
50
TEMPERATURE (°C)
75
Figure 13. Propagation Delay vs. Temperature, C Grade
Rev. B | Page 16 of 20
100
05984-019
3V
05984-012
CURRENT (mA)
60
Data Sheet
ADuM3300/ADuM3301
APPLICATION INFORMATION
The ADuM330x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 14). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for VDD1 and between Pin 15 and
Pin 16 for VDD2. The capacitor value should be between 0.01 μF
and 0.1 μF. The total lead length between both ends of the
capacitor and the input power supply pin should not exceed
20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9
and Pin 16 should be considered unless the ground pair on each
package side is connected close to the package.
VDD2
GND2
VOA
VOB
VOC/IC
NC
VE2
GND2
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation
delay to a logic high.
INPUT (VIX)
50%
tPLH
OUTPUT (VOX)
tPHL
50%
Figure 15. Propagation Delay Parameters
05984-015
VDD1
GND1
VIA
VIB
VIC/OC
NC
VE1
GND1
While the ADuM330x improve system-level ESD reliability,
they are no substitute for a robust system-level design. See
Application Note AN-793 ESD/Latch-Up Considerations with
iCoupler Isolation Products for detailed recommendations on
board layout and system-level design.
05984-016
PC BOARD LAYOUT
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Figure 14. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the
isolation barrier is minimized. Furthermore, the board layout
should be designed such that any coupling that does occur
equally affects all pins on a given component side. Failure to
ensure this could cause voltage differentials between pins
exceeding the device’s absolute maximum ratings, thereby
leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
SYSTEM-LEVEL ESD CONSIDERATIONS AND
ENHANCEMENTS
System-level ESD reliability (for example, per IEC 61000-4-x) is
highly dependent on system design, which varies widely by
application. The ADuM330x incorporate many enhancements
to make ESD reliability less dependent on system design. The
enhancements include
•
ESD protection cells added to all input/output interfaces.
•
Key metal trace resistances reduced using wider geometry
and paralleling of lines with vias.
•
The SCR effect inherent in CMOS devices minimized by
use of guarding and isolation technique between PMOS
and NMOS devices.
•
Areas of high electric field concentration eliminated using
45° corners on metal traces.
•
Supply pin overvoltage prevented with larger ESD clamps
between each supply pin and its respective ground.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM330x component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM330x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than ~1 μs, a periodic set
of refresh pulses indicative of the correct input state is sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses of more than about 5 μs, the input side is
assumed to be unpowered or nonfunctional, in which case the
isolator output is forced to a default state (see Table 11) by the
watchdog timer circuit.
The limitation on the ADuM330x’s magnetic field immunity is
set by the condition in which induced voltage in the transformer’s
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines the conditions under
which this can occur. The 3 V operating condition of the
ADuM330x is examined because it represents the most
susceptible mode of operation.
Rev. B | Page 17 of 20
ADuM3300/ADuM3301
Data Sheet
where:
β is magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM330x and
an imposed requirement that the induced voltage is at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 16.
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 17. Maximum Allowable Current
for Various Current-to-ADuM330x Spacings
100
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce error voltages sufficiently large enough to trigger
the thresholds of succeeding circuitry. Care should be taken in
the layout of such traces to avoid this possibility.
10
1
POWER CONSUMPTION
0.1
The supply current at a given channel of the ADuM330x
isolator is a function of the supply voltage, the channel’s data
rate, and the channel’s output load.
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
05984-017
0.01
0.001
1k
DISTANCE = 1m
100
05984-018
V = (−dβ/dt) ∑π rn2; n = 1, 2, … , N
1000
MAXIMUM ALLOWABLE CURRENT (kA)
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
For each input channel, the supply current is given by
Figure 16. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and was of the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V—still well above the 0.5 V
sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM330x transformers. Figure 17 expresses these allowable
current magnitudes as a function of frequency for selected
distances. The ADuM330x is extremely immune and can be
affected only by extremely large currents operated at high
frequency very close to the component (see Figure 17). For the
1 MHz example noted, a 0.5 kA current would have to be placed
5 mm away from the ADuM330x to affect the component’s
operation.
IDDI = IDDI (Q)
f ≤ 0.5 fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q)
f > 0.5 fr
For each output channel, the supply current is given by
IDDO = IDDO (Q)
f ≤ 0.5 fr
−3
IDDO = (IDDO (D) + (0.5 × 10 ) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half of the input
data rate expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
To calculate the total IDD1 and IDD2 supply current, the supply
currents for each input and output channel corresponding to
VDD1 and VDD2 are calculated and totaled. Figure 6 provides perchannel input supply current as a function of data rate. Figure 7
and Figure 8 provide per-channel output supply current as a
function of data rate for an unloaded output condition and for a
15 pF output condition, respectively. Figure 9 through Figure 12
provide total VDD1 and VDD2 supply current as a function of data
rate for ADuM3300/ADuM3301 channel configurations.
Rev. B | Page 18 of 20
Data Sheet
ADuM3300/ADuM3301
The values shown in Table 10 summarize the peak voltage for
50 years of service life for a bipolar ac operating condition, and
the maximum CSA/VDE approved working voltages. In many
cases, the approved working voltage is higher than 50-year
service life voltage. Operation at these high working voltages
can lead to shortened insulation life.
Note that the voltage presented in Figure 19 is shown as
sinusoidal for illustration purposes only. It is meant to represent
any voltage waveform varying between 0 V and some limiting
value. The limiting value can be positive or negative, but the
voltage cannot cross 0 V.
The insulation lifetime of the ADuM330x depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 18, Figure 19, and Figure 20 illustrate these
different isolation voltage waveforms.
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.
RATED PEAK VOLTAGE
05984-020
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage.
0V
Figure 18. Bipolar AC Waveform
RATED PEAK VOLTAGE
05984-021
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog
Devices executes an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM330x.
In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 10 can be applied while maintaining the
50-year minimum lifetime, provided that the voltage conforms
to either the unipolar ac or dc voltage cases. Any cross-insulation
voltage waveform that does not conform to Figure 19 or Figure 20
should be treated as a bipolar ac waveform, and its peak voltage
should be limited to the 50-year lifetime voltage value listed in
Table 10.
0V
Figure 19. Unipolar AC Waveform
RATED PEAK VOLTAGE
05984-022
INSULATION LIFETIME
0V
Figure 20. DC Waveform
Rev. B | Page 19 of 20
ADuM3300/ADuM3301
Data Sheet
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.75 (0.0295)
45°
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
8°
0°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
03-27-2007-B
1
Figure 21. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model 1, 2
ADuM3300ARWZ
ADuM3300BRWZ
ADuM3300CRWZ
ADuM3301ARWZ
ADuM3301BRWZ
ADuM3301CRWZ
1
2
3
Temperature Range (°C)
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
Number of
Inputs,
VDD1 Side
3
3
3
2
2
2
Number of
Inputs,
VDD2 Side
0
0
0
1
1
1
Maximum
Data Rate
(Mbps)
1
10
90
1
10
90
Z = RoHS Compliant Part.
Tape and reel are available. The addition of an “-RL” suffix designates a 13” (1,000 units) tape and reel option.
RW-16 = 16-lead wide body SOIC.
©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05984-0-2/12(B)
Rev. B | Page 20 of 20
Maximum
Propagation
Delay, 5 V (ns)
100
50
32
100
50
32
Maximum
Pulse Width
Distortion (ns)
40
3
2
40
3
2
Package
Option 3
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16