Data Sheet No.PD60231 revA IR3621 & (PbF) 2-PHASE / DUAL SYNCHRONOUS PWM CONTROLLER WITH OSCILLATOR SYNCHRONIZATION AND PRE-BIAS STARTUP FEATURES DESCRIPTION Dual Synchronous Controller with 180! Out of Phase Operation Configurable to 2-Independent Outputs or Current Share Single Output Voltage Mode Control Current Sharing Using Inductor's DCR Selectable Hiccup or Latched Current Limit using MOSFET's RDS(on) sensing Latched Over-Voltage Protection Pre-Bias Start Up Programmable Switching Frequency up to 500KHz Two Independent Soft-Starts/Shutdowns Precision Reference Voltage 0.8V Power Good Output External Frequency Synchronization Thermal Protection The IR3621 IC combines a dual synchronous buck controller and drivers, providing a cost-effective, high performance and flexible solution. The IR3621 operates in 2-Phase mode to produce either 2-independent output voltages or current share single output for high current application. The 180! out-of-phase operation allows the reduction of input and output capacitance. Other key features include two independently programmable soft-start functions to allow system level sequencing of output voltages in various configurations. The pre-bias protection feature prevents the discharge of the output voltage and possible damage to the load during start-up when a preexisting voltage is present at the output. Programmable switching frequency up to 500KHz per phase allows flexibility to tune the operation of the IC to meet system level requirements, and synchronization allows the simplification of system level filter design. Protection features such as selectable hiccup or latched current limit, and under voltage lock-out are provided to give required system level security in the event of a fault condition. APPLICATIONS Embedded Networking & Telecom Systems Distributed Point-of-Load Power Architectures 2-Phase Power Supply Graphics Card DDR Memory Applications Vin Vin HDrv1 Rt HDrv1 Rt OCSet1 Comp1 OCSet1 Comp1 LDrv1 PGnd1 Comp2 SS1 / SD SS2 / SD PGnd1 Vin IR3621 Vout Comp2 Vin IR3621 SS1 / SD HDrv2 OCSet2 Gnd Vout1 LDrv1 SS2 / SD HDrv2 OCSet2 Vout2 LDrv2 LDrv2 PGnd2 Gnd Current share, single output configuration PGnd2 2-independent output voltage configuration Figure 1 - Typical application of IR3621 in current share single output and 2-independent output voltage configuration ORDERING INFORMATION PKG DESIG M M F F PART NUMBER IR3621M IR3621MTR IR3621F IR3621FTR LEADFREE PART NUMBER IR3621MPbF IR3621MTRPbF N/A N/A PIN COUNT 32 32 28 28 www.irf.com PARTS PER TUBE 73 -----50 ------ PARTS PER REEL -----6000 -----2500 T&R Orientation Fig A 1 IR3621 & (PbF) ABSOLUTE MAXIMUM RATINGS Vcc, VCL Supply Voltage ........................................... VcH1 and VcH2 Supply Voltage ................................ PGOOD.................................................................... Storage Temperature Range ...................................... Junction Temperature Range ..................................... ESD Classification ................................................... -0.5V To 16V -0.5V To 25V -0.5V To 16V -55°C To 150°C -40°C To 150°C JEDEC, JESD22-A114 Caution: Stresses above those listed in “Absolute Maximum Rating” may cause permanent damage to the device. These are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to “Absolute Maximum Rating” conditions for extended periods may affect device reliability RECOMMENDED OPERATING CONDITIONS Parameter Vcc VcH1,2 Fs Tj Definition Supply Voltage Supply Voltage Operating Frequency Junction Temperature Min 5.5 10 200 -40 Max 14.5 20 500 125 Units V V kHz °C PACKAGE INFORMATION IR3621M & IR3621MPbF IR3621F 28-PIN TSSOP (F) OCSet2 9 VcH2 10 22 Fb1 21 Comp1 VP2 NC 25 EF PG ood Gn d VR 26 UT 3 Vc c 28 27 24 Hiccup VSEN2 2 23 Sync 3 4 Comp2 22 VSEN1 Fb2 SS2/SD2 21 Fb1 Pad 20 Comp1 5 20 SS1 / SD 19 OCSet1 HDrv2 11 18 VcH1 PGnd2 12 17 HDrv1 LDrv2 13 16 PGnd1 VCL 14 29 OCSet2 6 19 SS1/SD1 VCH2 7 18 OCSet1 HDrv2 8 17 9 15 LDrv1 10 11 θJA = 75.5 °C/W θJC =13.3 °C/W 12 13 14 15 VcH1 16 HD rv1 SS2 / SD 8 23 VSEN1 30 L Comp2 7 31 1 25 Hiccup 24 Sync 32 Rt LD rv1 PG nd1 NC VSEN2 5 Fb2 6 26 VP2 VC Rt 4 27 VREF VO VOUT3 3 28 Gnd NC VCC 2 NC PG nd2 LD rv2 PGood 1 32-Lead MLPQ 5mmx5mm (M) θJA = 36.0 °C/W θJC = 1.0 °C/W Exposed pad on underside is connected to a copper pad through vias for 4-layer PCB board design. 2 www.irf.com IR3621 & (PbF) ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc=12V, VcH1=VcH2=VCL=12V and 0°C<Tj<125°C. PARAMETER Output Voltage Accuracy Feedback Voltage SYMBOL TEST CONDITION MIN TYP MAX UNITS -1 -1.35 -2.5 -1.35 -1.65 -3.0 +1 +1.35 +1.35 +1.35 +1.65 +1.65 V % % % % % % 4.7 5.3 0.80 VFb1 , VFb2 MLPQ Accuracy TSSOP Tj=25°C 0°C <Tj< 125°C -40°C <Tj< 125°C Tj=25°C 0°C <Tj< 125°C -40°C <Tj< 125°C UVLO Section UVLO Threshold - Vcc UVLOVCC Supply Ramping Up Supply Ramp Up and Down UVLO Hysteresis - Vcc UVLO Threshold - VcH1,2 UVLOVCH1,2 Supply Ramping Up Supply Ramp Up and Down UVLO Hysteresis - VcH1,2 Supply Current Section Vcc Dynamic Supply Current Dyn ICC Freq=300kHz, CL=1500pF VcH1 & VcH2 Dynamic Current Dyn ICH Freq=300kHz, CL=1500pF VCL Dynamic Supply Current Dyn ICL Freq=300kHz, CL=1500pF SS=0V Vcc Static Supply Current ICCQ SS=0V VcH1/VcH2 Static Current ICHQ SS=0V VCL Static Supply Current ICLQ Soft-Start / SD Section SSIB SS=0V Charge Current SD Shutdown Threshold Power Good Section PGFB1,2L VSENS1,2 Ramping Down VSENS1,2 Lower Trip Point PG(Voltage) ISINK=2mA PGood Output Low Voltage Error Amp Section IFB1,2 SS=3V Fb Voltage Input Bias Current gm1 Transconductance 1 gm2 Transconductance 2 I(E/A)1,2 Error Amp Source/Sink Current VOS(ERR) Fb1,2 to VREF Input Offset Voltage for E/A1,2 VP2 Note2 VP2 Voltage Range Oscillator Section Freq Rt(SET) to 30.9K Frequency VRAMP Note2 Ramp Amplitude Dmin Fb=1V Min Duty Cycle Puls(ctrl) FSW=300kHz, Note2 Min Pulse Width Dmax Fb=0.6V, FSW=200kHz Max Duty Cycle Sync(Fs) 20% above free running freq Synch Frequency Range Sync(puls) Synch Pulse Duration Sync(H) Synch High Level Threshold Sync(L) Synch Low Level Threshold 1 3.5 4.0 0.75 22 V V V V 10 15 15 10 6 6 15 25 25 15 10 10 mA mA mA mA mA mA 28 35 0.25 µA V 0.8VREF 0.9VREF 0.95VREF 0.1 0.5 V V -0.1 -0.5 2500 2500 140 +4 Vcc-2 µA µmho µmho µA mV V 345 kHz V % ns % kHz ns V V 1400 1400 60 -4 0.4 100 0 255 1.25 0 150 86.5 1200 200 2 300 0.6 Note1: Cold temperature performance is guaranteed via correlation using statistical quality control. Not 100% tested in production. www.irf.com 3 IR3621 & (PbF) PARAMETER VOUT3 Internal Regulator Output Voltage Output Current Protection Section OVP Trip Threshold OVP Fault Prop Delay OCSET Current Hiccup Duty Cycle Hiccup High Level Threshold Hiccup Low Level Threshold Thermal Shutdown Trip Point Thermal Shutdown Hysteresis Output Drivers Section LO Drive Rise Time HI Drive Rise Time LO Drive Fall Time Hi Drive Fall Time Dead Band Time SYMBOL TEST CONDITION OVP Output forced to 1.25VREF OVP(delay) Note2 IOCSet Hiccup pin pulled high, Note2 Note2 Note2 Note2 Note2 Tr(LO) Tr(HI) Tf(LO) Tf(HI) TDB MIN TYP MAX UNITS 5.8 44 6.25 6.7 V mA 1.1VREF 1.15VREF 1.2VREF 5 16 20 24 5 2 0.8 140 20 V µs µA % V V !C !C 18 18 25 25 50 ns ns ns ns ns CL=1500pF,Figure 2 CL=1500pF, Figure 2 CL=1500pF,Figure 2 CL=1500pF,Figure 2 See Figure 2 Note 2: Guaranteed by design but not tested for production. Tr Tf 9V High Side Driver (HDrv) 2V Tr Tf 9V Low Side Driver (LDrv) 2V Deadband H_to_L Deadband L_to_H Figure 2 - Rise Time, Fall Time and Deadband for Driver Section 4 www.irf.com 50 50 50 50 100 IR3621 & (PbF) PIN DESCRIPTIONS TSSOP 1 2 3 4 5,23 6,22 7,21 8 20 9,19 10,18 11,17 12,16 13,15 14 24 25 26 27 28 MLPQ PIN SYMBOL PIN DESCRIPTION Power Good pin. Low when any of the outputs fall 10% below the set voltages. Supply voltage for the internal blocks of the IC. The Vcc slew rate should be <0.1V/us. Output of the internal LDO. Connect a 1.0uF capacitor from this pin to ground. VOUT3 31 Connecting a resistor from this pin to ground sets the oscillator frequency. Rt 1 Sense pins for OVP and PGood. For current share tie these pins together. VSEN2, VSEN1 2,22 Inverting inputs to the error amplifiers. In current sharing mode, Fb1 is conFb2,Fb1 3,21 nected to a resistor divider to set the output voltage and Fb2 is connected to programming resistor to achieve current sharing. In independent 2-channel mode, these pins work as feedback inputs for each channel. 4,20 Comp2, Comp1 Compensation pins for the error amplifiers. These pins provide user programmable soft-start function for each outputs. SS2 / SD 5 Connect external capacitors from these pins to ground to set the start up time SS1 / SD 19 for each output. These outputs can be shutdown independently by pulling the respective pins below 0.3V. During shutdown both MOSFETs will be turned off. For current share mode SS2 must be floating. 6,18 OCSet2,OCSet1 A resistor from these pins to switching point will set current limit threshold. VcH2, VcH1 Supply voltage for the high side output drivers. These are connected to voltages 7,17 that must be typically 6V higher than their bus voltages. A 0.1µF high frequency capacitor must be connected from these pins to PGND to provide peak drive current capability. HDrv2, HDrv1 Output drivers for the high side power MOSFETs. Note3 8,16 10,14 PGnd2, PGnd1 These pins serve as the separate grounds for MOSFET drivers and should be connected to the system’s ground plane. LDrv2, LDrv1 Output drivers for the synchronous power MOSFETs. 11,13 Supply voltage for the low side output drivers. VCL 12 The internal oscillator can be synchronized to an external clock via this pin. Sync 23 When pulled High, it puts the device current limit into a hiccup mode. When Hiccup 24 pulled Low, the output latches off, after an overcurrent event. Non-inverting input to the second error amplifier. In the current sharing mode, it VP2 26 is connected to the programming resistor to achieve current sharing. In independent 2-channel mode it is connected to VREF pin when Fb2 is connected to the resistor divider to set the output voltage. Reference Voltage. The drive capability of this pin is about 2µA. VREF 27 Analog ground for internal reference and control circuitry. Gnd 28 N/C 9,15,25.32 No Connect 29 30 PGood Vcc Note3: The negative voltage at these pins may cause instability for the gate drive circuits. To prevent this, a low forward voltage drop diode (Schottky) is required between these pins and power ground. www.irf.com 5 IR3621 & (PbF) BLOCK DIAGRAM SS2 Vcc Mode 0.3V S 28uA 28uA Mode 64uA Max SS2 / SD POR Mode Control 0.8V 3V Bias Generator Q R 0.8V 64uA UVLO SS1 / SD POR SS1 POR VcH1 HDrv1 VcH1 VcH2 POR PWM Comp1 VCL Thermal Shutdown SS1 Error Amp1 LDrv1 3uA R 0.8V PBias1 PGnd1 Q Fb1 Set1 Ramp1 Comp1 OCSet1 S 20uA Reset Dom Two Phase Oscillator Rt Set2 Ramp2 VcH2 Reset Dom Sync VREF PBias1 S PWM Comp2 0.8V HDrv2 Q R Error Amp2 SS1 SS2 Hiccup Control Hiccup Mode VP2 0.3V LDrv2 S Fb2 SS2 POR PBias2 Q Comp2 SS2 VSEN1 PGnd2 R PGood / OVP OVP HDrv OFF / LDrv ON OCSet2 3uA 20uA VSEN2 PGood Gnd Regulator Figure 3 - IR3621Block Diagram 6 www.irf.com VOUT3 IR3621 & (PbF) FUNCTIONAL DESCRIPTION Introduction The IR3621 is a versatile device for high performance buck converters. It consists of two synchronous buck controllers which can be operated either in two independent mode or in current share mode. The timing of the IC is provided by an internal oscillator circuit which generates two out-of-phase clock that can be programmed up to 500kHz per phase. Supply Voltage Vcc is the supply voltage for internal controller. The operating range is from 5.5V to 14.5V. It also is fed to the internal LDO. When Vcc is below under-voltage threshold, all MOSFET drivers will be turned off. In this mode, one control loop acts as a master and sets the output voltage as a regular Voltage Mode Buck controller and the other control loop acts as a slave and monitors the current information for current sharing. The voltage drops across the current sense resistors (or DCR of inductors) are measured and their difference is amplified by the slave error amplifier and compared with the ramp signal to generate the PWM pulses to match the output current. In this mode the SS2 pin should be floating. IR3621 Comp PWM Comp1 Internal Regulator The regulator powers directly from Vcc and generates a regulated voltage (Typ. 6.2V@40mA). The output is protected for short circuit. This voltage can be used for charge pump circuitry as shown in Figure12. Master E/A PWM Comp2 Independent Mode In this mode the IR3621 provides control to two independent output power supplies with either common or different input voltages. The output voltage of each individual channel is set and controlled by the output of the error amplifier, which is the amplified error signal from the sensed output voltage and the reference voltage. The error amplifier output voltage is compared to the ramp signal thus generating fixed frequency pulses of variable duty-cycle, which are applied to the FET drivers, Figure19 shows a typical schematic for such application. Currnt Share Mode This feature allows to connect both outputs together to increase current handling capability of the converter to support a common load. The current sharing can be done either using external resistors or sensing the DCR of inductors (see Figure 4). L1 Fb1 R1 RL1 VOUT C1 VP2 Input Supplies UnderVoltage LockOut The IR3621 UVLO block monitors three input voltages (Vcc, VcH1 and VcH2) to ensure reliable start up. The MOSFET driver output turn off when any of the supply voltages drops below set thresholds. Normal operation resumes once the supply voltages rise above the set values. Mode Selection The SS2 pin is used for mode selection. In current share mode this pin should be floating and in dual output mode a soft start capacitor must be connected from this pin to ground to program the start time for the second output. 0.8V FB2 L2 RL2 Slave E/A R2 C2 Figure 4 - Loss-less inductive current sensing and current sharing. In the diagram, L1 and L2 are the output inductors. RL1 and RL2 are inherent inductor resistances. The resistor R1 and capacitor C1 are used to sense the average inductor current. The voltage across the capacitors C1 and C2 represent the average current flowing into resistance RL1 and RL2. The time constant of the RC network should be equal or at most three times larger than the time constant L1/R . L1 R1×C1=(1~3)× L1 RL1 ---(1) Figure 5 - 30A Current Sharing using Inductor sensing www.irf.com (5A/Div) 7 IR3621 & (PbF) Dual Soft-Start The IR3621 has programmable soft-start to control the output voltage rise and limit the inrush current during start-up. It provides a separate Soft-Start function for each outputs. This will enable to sequence the outputs by controlling the rise time of each output through selection of different value soft-start capacitors. The soft-start pins will be connected together for applications where, both outputs are required to ramp-up at the same time. To ensure correct start-up, the soft-start sequence initiates when the Vcc, VcH1 and VcH2 rise above their threshold and generate the Power On Reset (POR) signal. Soft-start function operates by sourcing an internal current to charge an external capacitor to about 3V. Initially, the soft-start function clamps the E/A’s output of the PWM converter. During power up, the converter output starts at zero and thus the voltage at Fb is about 0V. A current (64µA) injects into the Fb pin and generates a voltage about 1.6V (64µA×25K) across the negative input of E/A and (see Figure6). The magnitude of this current is inversely proportional to the voltage at soft-start pin. The 28µA current source starts to charge up the external capacitor. In the mean time, the soft-start voltage ramps up, the current flowing into Fb pin starts to decrease linearly and so does the voltage at negative input of E/A. 28uA 28uA 64uA Max SS2 / SD 8 SS1 / SD 20 64uA POR Error Amp1 0.8V Fb1 22 Comp1 21 Error Amp2 VP2 26 Fb2 6 Comp2 7 Figure 6 -Soft-start circuit for IR3621 Output of POR 3V ≅1.8V When the soft-start capacitor is around 1V, the current flowing into the Fb pin is approximately 32µA. The voltage at the positive input of the E/A is approximately: Soft-Start Voltage 32µA×25K = 0.8V Current flowing into Fb pin The E/A will start to operate and the output voltage starts to increase. As the soft-start capacitor voltage continues to go up, the current flowing into the Fb pin will keep decreasing. Because the voltage at pin of E/A is regulated to reference voltage 0.8V, the voltage at the Fb is: Low Temperature Start-Up The controller is capable of starting at -40!C ambient temperature. 64uA 0uA Voltage at negative input ≅1.6V of Error Amp 0.8V 0.8V VFB = 0.8-(25K×Injected Current) The feedback voltage increases linearly as the injecting current goes down. The injecting current drops to zero when soft-start voltage is around 1.8V and the output voltage goes into steady state. Figure 7 shows the theoretical operational waveforms during soft-start. ≅1V 0V Voltage at Fb pin 0V Figure 7 - Theoretical operational waveforms during soft-start. The output start-up time is the time period when softstart capacitor voltage increases from 1V to 1.8V. The start-up time will be dependent on the size of the external soft-start capacitor. The start-up time can be estimated by: 28µA×TSTART/CSS = 1.8V-1V 8 www.irf.com IR3621 & (PbF) For a given start up time, the soft-start capacitor can be calculated by: CSS ≅ 28µA×TSTART/0.8V The soft-start is part of the Over Current Protection scheme, during the overload or short circuit condition the external soft start capacitors will be charged and discharged in certain slope rate to achieve the hiccup mode function. 28uA The internal current source develops a voltage across RSET. When the low side switch is turned on, the inductor current flows through the Q2 and results a voltage which is given by: VOCSET = IOCSET×RSET-RDS(ON)×iL ---(2) IOCSET Hiccup IR3621 Q1 L1 OCSet RSET SS1 / SD 20 Q2 Hiccup Control 3uA VOUT Figure 9 - Diagram of the over current sensing. Figure 8 - 3uA current source for discharging soft start-capacitor during Hiccup mode Out-of-Phase Operation The IR3621 drives its two output stages 180! out-of-phase. In 2-phase configuration, the two inductor ripple currents cancel each other and result in a reduction of the output current ripple and yield a smaller output capacitor for the same ripple voltage requirement. The critical inductor current can be calculated by setting: VOCSET = IOCSET×RSET - RDS(ON)×IL = 0 ISET = IL(CRITICAL)= RSET×IOCSET ---(3) RDS(ON) In single input voltage applications, the input ripple current The value of RSET should be checked in an actual reduces. This results in much smaller input capacitor's circuit to ensure that the Over Current Protection RMS current and reduces the input capacitor quantity. circuit activates as expected. The IR3621 current limit is designed primarily as disaster preventing, "no blow Over-Current Protection up" circuit, and is not useful as a precision current The IR3621 can provide two different schemes for Overregulator. Current Protection (OCP). When the Hiccup pin is pulled high, the OCP will operate in hiccup mode. In this mode, In two independent mode, the output of each channel during overload or short circuit, the outputs enter hiccup is protected independently which means if one output mode and stay in that mode until the overload or short is under overload or short circuit condition, the other circuit is removed. The converter will automatically reoutput will remain functional. The OCP set limit can be cover. programmed to different levels by using the external When the Hiccup pin is pulled low, the OCP scheme resistors. This is valid for both hiccup mode and latch will be changed to the latch up type, in this mode the up mode. converter will be turned off during Overcurrent or short In 2-phase configuration, the OCP's output depends on circuit. The power needs to be recycled for normal any one channel, which means as soon as one operation. channel goes to overload or short circuit condition the Each phase has its own independent OCP circuitry. output will enter either hiccup or latch-up, dependes on The OCP is performed by sensing current through the status of Hiccup pin. RDS(ON) of low side MOSFET. As shown in Figure 9, an external resistor (RSET) is connected between OCSet pin Pre-bias Startup and the drain of low side MOSFET (Q2) which sets the The IR3621 allows pre-bias startup without discharging current limit set point. the output capacitors. The output starts in asynchroIf using one soft start capacitor in dual configuration for a nous fashion and keeps the synchronous MOSFET off precise power up the OCP needs to be set to latch mode. until the first gate signal for control MOSFET is generated. www.irf.com 9 IR3621 & (PbF) Thermal Shutdown Temperature sensing is provided inside IR3621. The trip threshold is typically set to 140!C. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs. Thermal shutdown is not latched and automatic restart is initiated when the sensed temperature drops to normal range. There is a 20!C hysteresis in the shutdown threshold. Power Good The IR3621 provides a power good signal. The power good signal should be available after both outputs have reached regulation. This pin needs to be externally pulled high. High state indicates that outputs are in regulation. Power good will be low if either one of the output voltages is 10% below the set value. There is only one power good for both outputs. Over-Voltage Protection OVP Over-voltage is sensed through separate VOUT sense pins VSEN1 and VSEN2. A separate OVP circuit is provided for each output. Upon over-voltage condition of either one of the outputs, the OVP forces a latched shutdown on both outputs. In this mode, the upper FET drivers turn off and the lower FET drivers turn on, thus crowbaring the outputs. Reset is performed by recycling Vcc. Error Amplifier The IR3621 is a voltage mode controller. The error amplifiers are of transconductance type. In independent mode, each amplifier closes the loop around its own output voltage. In current sharing mode, amplifier 1 becomes the master which regulates the common output voltage. Amplifier 2 performs the current sharing function. Both amplifiers are capable of operating with Type III compensation control scheme. 10 Operation Frequency Selection The optimum operating frequency range for the IR3621 is 300kHz per phase, theoretically the IR3621 can be operated at higher switching frequency (e.g. 500kHz). However the power dissipation for IC, which is function of applied voltage, gate drivers load and switching frequency, will result in higher junction temperature of device. It may exceed absolute maximum rating of junction temperature, figure 18 (page 17) shows case temperature versus switching frequency with different capacitive loads for TSSOP package. This should be considered when using IR3621 for such application. The below equation shows the relationship between the IC's maximum power dissipation and Junction temperature: ΤJ-ΤA Pd = θJA Where: Tj: Maximum Operating Junction Temperature TA: Ambient Temperature θJA = Thermal Impedance of package The switching frequency is determined by an external resistor (Rt). The switching frequency is approximately inversely proportioned to resistance (see Fig 10). Per Channel Switching Frequency vs. RT 700 600 Switching Frequency (kHz) Frequency Synchronization The IR3621 is capable of accepting an external digital synchronization signal. Synchronization will be enabled by the rising edge at an external clock. Per-channel switching frequency is set by external resistor (Rt). The free running oscillator frequency is twice the per-channel frequency. During synchronization, Rt is selected such that the free running frequency is 20% below the sync frequency. Synchronization capability is provided for both 2output and 2-phase configurations. When unused, the Sync pin will remain floating and is noise immune. 500 400 300 200 100 0 0 10 20 30 40 50 60 70 RT (kohm) Figure 10- Switching Frequency versus External Resistor. Shutdown The outputs can be shutdown independently by pulling the respective soft-start pins below 0.3V. This can be easily done by using an external small signal transistor. During shutdown both MOSFETs will be turned off. During this mode the LDO will stay on. Normal operation will resume by cycling soft start pins. www.irf.com IR3621 & (PbF) APPLICATION INFORMATION Design Example: The following example is a typical application for the IR3621, the schematic is Figure19 on page18. VIN = 12V VOUT(2.5V) = 2.5V @ 10A VOUT(1.8V) = 1.8V @ 10A ∆VOUT = Output voltage ripple ≅ 3% of VOUT FS = 400kHz Output Voltage Programming Output voltage is programmed by the reference voltage and an external voltage divider. The Fb1 pin is the inverting input of the error amplifier, which is referenced to the voltage on the non-inverting pin of error amplifier. For this application, this pin (VP2) is connected to the reference voltage (VREF). The output voltage is defined by using the following equation: R6 VOUT = VP2 × 1 + ---(4) R5 ( ) VP2 = VREF = 0.8V When an external resistor divider is connected to the output as shown in Figure 11. VOUT IR3621 VREF Css ≅ 28×tSTART (µF) ---(5) Where tSTART is the desired start-up time (ms) For a start-up time of 4ms for both output, the soft-start capacitor will be 0.1µF. Connect two 0.1µFceramic capacitors from SS1 pin and SS2 pin to GND. Supply VcH1 and VcH2 To drive the high side MOSFET, it is necessary to supply a gate voltage at least 4V greater than the bus voltage. This is achieved by using a charge pump configuration as shown in Figure 12. This method is simple and inexpensive. The operation of the circuit is as follows: when the lower MOSFET is turned on, the capacitor (C1) charges up to VOUT3, through the diode (D1). The bus voltage will be added to this voltage when upper MOSFET turns on in next cycle, and providing supply voltage (VcH1) through diode (D2). VcH1 is approximately: VCH1 ≅ VOUT3 + VBUS - (VD1 + VD2) R6 Fb R5 VP2 Soft-Start Programming The soft-start timing can be programmed by selecting the soft-start capacitance value. The start-up time of the converter can be calculated by using: Figure 11 - Typical application of the IR3621 for programming the output voltage. Capacitor in the range of 0.1µF is generally adequate for most applications. The diode must be a fast recovery device to minimize the amount of charge fed back from the charge pump capacitor into VOUT3. The diodes need to be able to block the full power rail voltage, which is seen when the high side MOSFET is switched on. For low voltage application, Schottky diodes can be used to minimize forward drop across the diodes at start up. D1 Equation (4) can be rewritten as: R6 = R5 × ( VV OUT Will result to: VOUT(2.5V) = 2.5V VREF = 0.8V R9= 2.15K, R5= 1K P C3 ) VOUT3 -1 Regulator VOUT(1.8V) = 1.8V VREF = 0.8 R7= 1.24K, R8 = 1K D2 VBUS VcH1 C2 C1 Q1 L2 IR3621 If the high value feedback resistors are used, the input bias current of the Fb pin could cause a slight increase in output voltage. The output voltage can be set more accurately by using low value, precision resistors. www.irf.com HDrv Q2 Figure 12 - Charge pump circuit. 11 IR3621 & (PbF) Input Capacitor Selection The 1800 out of phase will reduce the RMS value of the ripple current seen by input capacitors. This reduces numbers of input capacitors. The input capacitors must be selected that can handle both the maximum ripple RMS at highest ambient temperature as well as the maximum input voltage. The RMS value of current ripple for duty cycles under 50% is expressed by: 2 2 2 IRMS= (I1 D1(1-D1)+I D2(1-D2)-2I1I2D1D2) --- (6) Where: IRMS is the RMS value of the input capacitor current D1 and D2 are the duty cycle for each output I1 and I2 are the current for each output For this application the IRMS =4.8A For higher efficiency, low ESR capacitors are recommended. Choose two Poscap from Sanyo 16TPB47M (16V, 47µF, 70mΩ ) with a maximum allowable ripple current of 1.4A for inputs of each channel. Inductor Selection The inductor is selected based on operating frequency, transient performance and allowable output voltage ripple. Low inductor values result in faster response to step load (high ∆i/∆t) and smaller size but will cause larger output ripple due to increased inductor ripple current. As a rule of thumb, select an inductor that produces a ripple current of 10-40% of full load DC. For the buck converter, the inductor value for desired operating ripple current can be determined using the following relation: ∆i VOUT 1 ; ∆t = D× ;D= ∆t VIN fS VOUT L = (VIN - VOUT)× ---(7) VIN×∆i×fS Where: VIN = Maximum Input Voltage VOUT = Output Voltage ∆i = Inductor Ripple Current fS = Switching Frequency ∆t = Turn On Time D = Duty Cycle VIN - VOUT = L× For ∆i(1.8V) = 35%(IO(1.8V) ), then the output inductor will be: L3 = 1.1µH Panasonic provides a range of inductors in different values and low profile for large currents. Choose ETQP6F1R1BFA (1.1µH, 16A, 2.2mΩ) both for L3 and L4. For 2-phase application, equation (7) can be used for calculating the inductors value. In such case the inductor ripple current is usually chosen to be between 1040% of maximum phase current. Output Capacitor Selection The criteria to select the output capacitor is normally based on the value of the Effective Series Resistance (ESR). In general, the output capacitor must have low enough ESR to meet output ripple and load transient requirements, yet have high enough ESR to satisfy stability requirements. The ESR of the output capacitor is calculated by the following relationship: (ESL, Equivalent Series Inductance is neglected) ∆VO ESR ≤ ---(8) ∆IO Where: ∆VO = Output Voltage Ripple ∆i = Inductor Ripple Current ∆VO = 3% of VO will result to ESR(2.5V) =16.6mΩ and ESR(1.8V) =16mΩ The Sanyo TPC series, Poscap capacitor is a good choice. The 6TPC330M, 330µF, 6.3V has an ESR 40mΩ. Selecting three of these capacitors in parallel for 2.5V output, results to an ESR of ≅ 13.3mΩ which achieves our low ESR goal. And selecting three of these capacitors in parallel for 1.8V output, results in an ESR of ≅ 13.3mΩ which achieves our low ESR goal. The capacitors value must be high enough to absorb the inductor's ripple current. Power MOSFET Selection The IR3621 uses four N-Channel MOSFETs. The selection criteria to meet power transfer requirements is based on maximum drain-source voltage (VDSS), gate-source drive voltage (VGS), maximum output current, On-resistance RDS(ON) and thermal management. For ∆i(2.5V) = 45%(IO(2.5V) ), then the output inductor will be: The both control and synchronous MOSFETs must have a maximum operating voltage (VDSS) that exceeds the maximum input voltage (VIN). L4 = 1.1µH 12 www.irf.com IR3621 & (PbF) The gate drive requirement is almost the same for both MOSFETs. Logic-level transistors can be used and caution should be taken with devices at very low VGS to prevent undesired turn-on of the complementary MOSFET, which results in a shoot-through. The total power dissipation for MOSFETs includes conduction and switching losses. For the Buck converter, the average inductor current is equal to the DC load current. The conduction loss is defined as: VDS(OFF) tr + tf ---(9) × × ILOAD T 2 Where: VDS(OFF) = Drain to Source Voltage at off time tr = Rise Time tf = Fall Time T = Switching Period ILOAD = Load Current PSW = VDS 90% 2 PCOND(Upper Switch) = ILOAD×RDS(on)×D×ϑ 2 PCOND(Lower Switch) = ILOAD×RDS(on)×(1 - D)×ϑ ϑ = RDS(on) Temperature Dependency 10% VGS The RDS(ON) temperature dependency should be considered for the worst case operation. This is typically given in the MOSFET data sheet. Ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget. Choose IRF7821 for control MOSFETs and IRF8113 for synchronous MOSFETs. These devices provide low onresistance in a compact SOIC 8-Pin package. tr td(OFF) tf Figure 13 - Switching time waveforms. From IRF7821 data sheet we obtain: IRF7821 tr = 2.7ns tf = 7.3ns These values are taken under a certain condition test. For more details please refer to the IRF7821 data sheet. The MOSFETs have the following data: IRF7821 VDSS = 30V RDS(on) = 9mΩ td(ON) IRF8113 VDSS = 30V RDS(on) = 6mΩ By using equation (9), we can calculate the total switching losses. The total conduction losses for each output will be: PCON(TOTAL, 2.5V) = PCON(UPPER) + PCON(LOWER) PCON(TOTAL, 2.5V) = 1.0W PSW(TOTAL,2.5V) = 0.18W PSW(TOTAL,1.8V) = 0.18W Programming the Over-Current Limit The over-current threshold can be set by connecting a resistor (RSET) from drain of low side MOSFET to the OCSet pin. The resistor can be calculated by using equation (3). PCON(TOTAL, 1.8V) = PCON(UPPER) + PCON(LOWER) PCON(TOTAL, 1.8V) = 1.0W The switching loss is more difficult to calculate, even though the switching transition is well understood. The reason is the effect of the parasitic components and switching times during the switching procedures such as turn-on / turnoff delays and rise and fall times. The control MOSFET contributes to the majority of the switching losses in a synchronous Buck converter. The synchronous MOSFET turns on under zero voltage conditions, therefore, the switching losses for synchronous MOSFET can be neglected. With a linear approximation, the total switching loss can be expressed as: The RDS(on) has a positive temperature coefficient and it should be considered for the worse case operation. RDS(on) = 6mΩ×1.5 = 9mΩ ISET ≅ IO(LIM) = 10A×1.5 = 15A (50% over nominal output current) This results to: RSET = R1=R6=6.75KΩ This resistor must be placed close to the IC, place a small ceramic capacitor from this pin to ground for noise rejection purposes. www.irf.com 13 IR3621 & (PbF) Feedback Compensation The IR3621 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency and adequate phase margin (greater than 45!). The ESR zero of the output capacitor is expressed as follows: FESR = 1 2π×ESR×Co VOUT R9 Fb The output LC filter introduces a double pole, –40dB/ decade gain slope above its corner resonant frequency, and a total phase lag of 180! (see Figure 14). The Resonant frequency of the LC filter is expressed as follows: 1 FLC = ---(10) 2π× LO×CO R5 Vp=VREF Comp Ve C9 CPOLE Gain(dB) H(s) dB FZ Co is the total output capacitor Gain E/A R4 Where: Lo is the output inductor For 2-phase application, the effective output inductance should be used Figure 14 shows gain and phase of the LC filter. Since we already have 180! phase shift just from the output filter, the system risks being unstable. ---(10A) Frequency Figure 15 - Compensation network without local feedback and its asymptotic gain plot. The transfer function (Ve / VOUT) is given by: Phase ( 0! 0dB H(s) = gm× -40dB/decade FLC Frequency -180! FLC Frequency R5 1 + sR4C9 × R9 + R5 sC9 ) ---(11) The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: Figure14 - Gain and phase of LC filter The IR3621’s error amplifier is a differential-input transconductance amplifier. The output is available for DC gain control or AC phase compensation. The E/A can be compensated with or without the use of local feedback. When operated without local feedback, the transconductance properties of the E/A become evident and can be used to cancel one of the output filter poles. This will be accomplished with a series RC circuit from Comp pin to ground as shown in Figure 15. Note that this method requires the output capacitor to have enough ESR to satisfy stability requirements. In general, the output capacitor’s ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin. 14 |H(s=j×2π×FO)| = gm× FZ = 1 2π×R4×C9 R5 ×R4 R9+R5 ---(12) ---(13) |H(s)| is the gain at zero cross frequency. First select the desired zero-crossover frequency (FO1): FO1 > FESR and FO1 ≤ (1/5 ~ 1/10)×fS www.irf.com IR3621 & (PbF) R4 = 1 VOSC FO1×FESR R5 + R9 × × × gm VIN FLC2 R5 ---(14) Where: VIN = Maximum Input Voltage VOSC = Oscillator Ramp Voltage FO1 = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R5 and R9 = Resistor Dividers for Output Voltage Programming gm = Error Amplifier Transconductance For V2.5V: VIN = 12V VOSC = 1.25V FO1 = 40KHz FESR = 13.3kHz For a general solution for unconditional stability for ceramic output capacitor with very low ESR or any type of output capacitors, in a wide range of ESR values we should implement local feedback with a compensation network. The typically used compensation network for a voltage-mode controller is shown in Figure 16. VOUT ZIN C12 C10 R7 R8 Zf Fb FLC = 5.06kHz R5 = 1K R9 = 2.14K gm = 1400µmho C11 R6 E/A R5 Comp Ve VP2=VREF Gain(dB) H(s) dB This results to R4=4.8K Choose R4=5K To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: FZ ≅ 75%FLC 1 FZ ≅ 0.75× ---(15) 2π LO × CO For: Lo = 1.1µH FZ = 3.61kHz Co = 990µF R4 = 5K Using equations (13) and (15) to calculate C9, we get: C9 ≅ 8.3nF; Choose C9 =8.2nF FZ1 FP2 FZ2 FP3 Frequency Figure 16- Compensation network with local feedback and its asymptotic gain plot. In such configuration, the transfer function is given by: Ve 1 - gmZf = VOUT 1 + gmZIN The error amplifier gain is independent of the transconductance under the following condition: gmZf >> 1 and gmZIN >>1 ---(16) Same calcuation For V1.8V will result to: R3 = 4.2K and C8 = 10nF By replacing ZIN and Zf according to Figure 16, the transformer function can be expressed as: One more capacitor is sometimes added in parallel with C9 and R4. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: 1 FP = C9×CPOLE 2π×R4× C9 + CPOLE H(s) = The pole sets to one half of switching frequency which results in the capacitor CPOLE: 1 1 CPOLE = ≅ π×R4×fS 1 π×R4×fS C9 fS for FP << 2 (1+sR7C11)×[1+sC10(R6+R8)] 1 × sR6(C12+C11) C12C11 1+sR7 C12+C11 ×(1+sR8C10) [ ( )] As known, transconductance amplifier has high impedance (current source) output, therefore, consider should be taken when loading the E/A output. It may exceed its source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the necessary range. The compensation network has three poles and two zeros and they are expressed as follows: www.irf.com 15 IR3621 & (PbF) FP1 = 0 FP2 = FP3 = FZ1 = 1 2π×R8×C10 1 ( ) C12×C11 2π×R7× C12+C11 ≅ 1 2π×R7×C12 1 2π×R7×C11 1 1 FZ2 = 2π×C10×(R6 + R8) ≅ 2π×C10×R6 Cross Over Frequency: VIN 1 × FO = R7×C10× VOSC 2π×Lo×Co Where: VIN = Maximum Input Voltage VOSC = Oscillator Ramp Voltage Lo = Output Inductor Co = Total Output Capacitors The transfer function of power stage is expressed by: IL2(s) VIN = Ve(s) sL2 × VOSC Where: VIN = Input Voltage L2 = Output Inductor VOSC = Oscillator Peak Voltage G(s) = ---(17) The stability requirement will be satisfied by placing the poles and zeros of the compensation network according to following design rules. The consideration has been taken to satisfy condition (16) regarding transconductance error amplifier. These design rules will give a crossover frequency approximately one-tenth of the switching frequency. The higher the band width, the potentially faster the load transient response. The DC gain will be large enough to provide high DC-regulation accuracy (typically -5dB to -12dB). The phase margin should be greater than 45! for overall stability. Based on the frequency of the zero generated by ESR versus crossover frequency, the compensation type can be different. The table below shows the compensation type and location of crossover frequency. Compensator Location of Zero Typical Type Crossover Frequency Output (FO) Capacitor Type II (PI) FLC < FESR < FO < fS/2 Electrolytic, Tantalum Type III (PID) FLC < FO < FESR < fS/2 Tantalum, Method A Ceramic Type III (PID) FLC < FO < fS/2 < FZO Ceramic Method B Table - The compensation type and location of zero crossover frequency. Details are dicussed in application Note AN-1043 which can be downloaded from the IR Web-Site. 16 Compensation for Slave Error Amplfier for 2-Phase Configuration The slave error amplifier is a differential-input transconductance amplifier, in 2-phase configuration the main goal for the slave feed back loop is to control the inductor current to match the master's inductor current as well provides highest bandwidth and adequate phase margin for overall stability. The following analysis is valid for both using external current sense resistor and using DCR of inductors. ---(18) As shown the transfer function is a function of inductor current. The transfer function for the compensation network is given by equation (19), when using a series RC circuit as shown in Figure 17: D(s) = Ve(s) = RS2 × IL2(s) (g × RR )×(1 +sCsC R ) ---(19) S1 2 m S2 2 2 IL2 L2 Fb2 RS2 Vp2 Comp2 E/A2 Ve R2 RS1 C2 L1 IL1 Figure 17 - The PI compensation network for slave channel. The loop gain function is: H(s)=[G(s) × D(s) × RS2] C × V (g × RR )×(1+sR sC ) (sL ×V ) H(s)=RS2× www.irf.com S1 2 S2 2 m 2 IN 2 OSC IR3621 & (PbF) Select a zero crossover frequency for control loop (FO2) 1.25 times larger than zero crossover frequency for voltage loop (FO1): Fo2 ≅ 1.25%xF01 H(Fo) = gm×RS1×R2× VIN =1 2π×Fo×L2×VOSC ---(20) From (20), R2 can be express as: R2 = 1 gm × RS1 × 2π × FO2 × L2 × VOSC VIN ---(21) The power stage of current loop has a dominant pole (Fp) at frequency expressed by: Req Fp = 2π×L2 Where Req is the total resistance of the power stage which includes the Rds(on) of the FET switches, the DCR of inductor and shunt resistance (if it used). Req=RDS(on)+RL+Rs Set the zero of compensator at 10 times the dominant pole frequency Fp, the compensator capacitor, C2 can be calculated as: 1 2πxR2xFz All design should be tested for stability to verify the calculated values. C2 = Fz = 10 x Fp Layout Consideration The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start by placing the power components. Make all the connections in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching. Place input capacitor near to the drain of the high-side MOSFET. The layout of driver section should be designed for a low resistance (a wide, short trace) and low inductance (a wide trace with ground return path directly beneath it), this directly affects the driver's performance. To reduce the ESR, replace the one input capacitor with two parallel ones. The feedback part of the system should be kept away from the inductor and other noise sources and must be placed close to the IC. In multilayer PCBs, use one layer as power ground plane and have a separate control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current paths to a separate loops that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. Switching Frequency vs. Case Temp Case temp (oC) 90 80 100pF 70 1000pF 60 1800pF 50 3300pF 40 30 200 300 400 500 600 700 Freq (kHz) Figure18- Case Temperature (TSSOP package) versus Switching Frequency at Room Temperature Test Condition: Vin=VcL=VcH1=VcH2=12V, Capacitors used as loads for output drivers. www.irf.com 17 IR3621 & (PbF) TYPICAL APPLICATION D1 C12 12V C11 VcH2 C1 C3 C4 VcH2 VOUT3 VcH1 Vcc HDrv1 C5 OCSet1 Hiccup Rt R3 C9 R4 U1 IR3621 Comp1 Comp2 PGood SS1 / SD C10 C15 1.8V @ 10A SS2 / SD C16 R20 D2 VSEN1 VSEN1 VSEN1 VSEN2 VSEN2 Fb1 Fb2 HDrv2 OCSet2 PGood L3 Q3 PGnd1 Sync VREF R2 Q2 R1 LDrv1 VP2 C8 C14 C13 VCL R6 LDrv2 PGnd2 Gnd R21 C20 R8 R5 C17 Q4 L4 2.5V @ 10A Q5 R22 VSEN2 R23 www.irf.com R9 C18 Figure 19 - Typical application of IR3621. 12V input and two independent outputs using type 2 compensation. 18 R7 VcH2 IR3621 & (PbF) TYPICAL APPLICATION D1 C12 12V C11 C3 C4 C13 C14 VCL VcH1 VOUT3 VcH2 HDrv1 Vcc C5 OCSet1 Hiccup Q2 L3 Q3 R5 R1 LDrv1 1.8V @ 30A PGnd1 VP2 Sync C15 R7 VREF R2 Rt C8 C9 R3 R4 C16 U1 IR3621 Comp1 VSEN1 Comp2 SS1 / SD SS2 / SD R8 R9 C18 HDrv2 OCSet2 C10 R7 VSEN2 Fb1 Fb2 C17 PGood PGood R8 VSEN1 R6 LDrv2 Q4 L4 Q5 PGnd2 Gnd Figure 20 - 2-phase operation with inductor current sensing using type 2 compensation. 12V to 1.8V @ 30A output www.irf.com 19 IR3621 & (PbF) TYPICAL OPERATING CHARACTERISTICS Vfb2 vs. Temperature 0.8060 0.8060 0.8040 0.8040 0.8020 0.8020 Vfb2 [V] Vfb1 [V] Vfb1 vs. Temperature 0.8000 0.7980 0.8000 0.7980 0.7960 0.7960 0.7940 -50 0.7940 -50 0 50 100 150 0 150 Frequency vs. Temperature (Rt=30.9kohm) 6.24 350 6.22 300 6.2 250 Frequency (kHz) VOUT3 (V) VOUT3 vs. Temperature 6.18 6.16 6.14 200 150 100 50 6.12 0 -50 6.1 -50 -25 0 25 50 75 Temperature (C) 100 -25 0 125 25 50 75 100 125 Temperature (C) Transconductance vs. Temperature SS Charge Current vs. Temperature 2500 31 29 27 25 23 21 19 17 15 Transconductance (umho) SS Charge Current (uA) 100 Temperature [C] Temperature [C] 2000 1500 SS1 SS2 Transconductance 1 1000 -50 -25 0 25 50 Temperature (C) 20 50 75 100 125 Transconductance 2 500 -50 www.irf.com -25 0 25 50 75 Temperature (C) 100 125 IR3621 & (PbF) TYPICAL OPERATING CHARACTERISTICS Dynamic Supply Current vs. Temperature (300kHz, 1500pF) Static Supply Current vs. Temperature 30 Static Supply Current (uA) 25 ICC ICH1+ICH2 Dynamic Supply Current (uA) 30 ICL 20 15 10 5 0 -50 -25 0 25 50 75 100 25 20 15 10 ICC 5 0 -50 125 -25 ICH1+ICH2 0 25 Deadband time (ns) IOCSet (uA) 25 24 23 22 21 20 19 18 17 16 15 IOCSet1 IOCSet2 0 25 50 75 100 125 100 90 80 70 60 50 40 30 20 10 0 -50 Temperature (C) 30 30 25 20 15 HI Dr1 Rise HI Dr2 Rise 10 HI Dr1 Fall HI Dr2 Fall 25 50 0 H_to_L_2 L_to_H_1 L_to_H_2 25 50 75 100 125 75 100 25 20 15 10 5 0 -25 H_to_L_1 LO Drive Rise/Fall Time vs. Temperature 35 Rise/Fall time (ns) Rise/Fall time (ns) HI Drive Rise/Fall Time vs. Temperature -25 125 Temperature (C) 35 -50 100 Deadband Time vs. Temperature IOCSet vs. Temperature -25 75 Temperature (C) Temperature (C) -50 50 ICL 125 5 -50 -25 0 LO Dr1 Rise LO Dr2 Rise LO Dr1 Fall LO Dr2 Fall 25 50 75 100 125 Temperature (C) Temperature (C) www.irf.com 21 IR3621 & (PbF) TYPICAL OPERATING WAVEFORMS Test Conditions: VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=400kHz, TA=Room Temp, No Air Flow Unless otherwise specified. Figure 21 - Start up waveforms for 2.5V output Ch1: Vin, Ch2: Vout3, Ch3: SS1, Ch4:Vo1 (2.5V) Figure 23 - Start up waveforms Ch1: Vin, Ch2: Vout3, Ch3: Vref 22 Figure 22 - Start up waveforms for 1.8V output Ch1: Vin, Ch2: Vout3, Ch3: SS2, Ch4:Vo2 (1.8V) Figure 24 - Vo1, Vo2 and PGood Ch1: Vin, Ch2: Vo1, Ch3: Vo2, Ch4: PGood www.irf.com IR3621 & (PbF) TYPICAL OPERATING WAVEFORMS Test Conditions: VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=400kHz, Ta=Room Temp, No Air Flow Unless otherwise specified. Figure 25 - 2.5V output Ch1: Vin, Ch2: SS1, Ch3: Vo1, Ch4: PGood Figure 27 - Gate waveforms with 180o out of phase Ch1: Hdrv1, Ch2: Hdrv2 Figure 26 - 1.8V output Ch1: Vin, Ch2: SS2, Ch3: Vo2, Ch4: PGood Figure 28 - 2.5V Waveforms Ch1: Hdrv1, Ch2: Ldrv1, Ch3: Lx1, Ch4: Inductor Current www.irf.com 23 IR3621 & (PbF) TYPICAL OPERATING WAVEFORMS Test Conditions: VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=400kHz, Ta=Room Temp, No Air Flow Unless otherwise specified. Figure 30 - 1.8V output shorted Ch1: Vo1, Ch2: SS2, Ch3: Inductor Current Figure 29 - 2.5V Waveforms Ch1: Hdrv2, Ch2: Ldrv2, Ch3: Lx2, Ch4: Inductor Current Figure 31 - 2.5V output shorted Ch1: Vo2, Ch2: SS1, Ch3: Inductor Current 24 Figure 32 - Prebias Start up Ch1: SS1, Ch2: Vo1, Ch3: SS2, Ch4:Vo2 www.irf.com IR3621 & (PbF) TYPICAL OPERATING WAVEFORMS Test Conditions: VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=400kHz, Ta=Room Temp, No Air Flow Unless otherwise specified. Figure 33 - SS1 pin shorted to Gnd Ch1: SS1, Ch2: Hdrv1, Ch3: Ldrv1, Ch4:Vo2 Figure 34 - SS2 pin shorted to Gnd Ch1: SS2, Ch2: Hdrv2, Ch3: Ldrv2, Ch4:Vo1 Figure 35 - External Synchronization Ch1: External Clock, Ch2: Hdrv1, Ch3: Hdrv2 www.irf.com 25 IR3621 & (PbF) TYPICAL OPERATING WAVEFORMS Test Conditions: VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=400kHz, Ta=Room Temp, No Air Flow Unless otherwise specified. Figure 37 - Load Transient Respons for Vo1 (Io=10 to 0A) Ch1: Vo1, Ch4: Io1 Figure 36 - Load Transient Respons for Vo1 (Io=0 to 10A) Ch1: Vo1, Ch4:Io1 Figure 38 - Load Transient Respons for Vo2 (Io=0 to 10A) Ch1: Vo2, Ch4: Io2 26 Figure 39 - Load Transient Respons for Vo2 (Io=10 to 0A) Ch1: Vo2, Ch4: Io2 www.irf.com IR3621 & (PbF) TYPICAL PERFORMANCE CURVES Test Conditions: VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=400kHz, Ta=Room Temp, No Air Flow Unless otherwise specified. 12V to 2.5V and 1.8V 90 85 Efficiency (%) 80 75 70 2.5V 65 1.8V 60 55 50 45 0 2 4 6 8 10 12 14 16 Io(A) Figure 40 - Efficiency for 2.5V and 1.8V outputs at room temperature and no air flow. Efficiency was measured when the other output was operating at no load. www.irf.com 27 IR3621 & (PbF) (IR3621M & IR3621MPbF) MLPQ 5x5 Package 32-Pin D D/2 D2 EXPOSED PAD PIN NUMBER 1 PIN 1 MARK AREA (See Note1) E/2 E2 E R L e TOP VIEW B BOTTOM VIEW Note 1: Details of pin #1 are optional, but must be located within the zone indicated. The identifier may be molded, or marked features. A A3 SIDE VIEW A1 SYMBOL DESIG A A1 A3 B D D2 E E2 e L R 32-PIN 5x5 NOM 0.90 0.02 0.20 REF 0.23 0.18 5.00 BSC MIN 0.80 0.00 MAX 1.00 0.05 0.30 3.45 3.55 5.00 BSC 3.45 3.30 3.55 0.50 BSC 0.40 0.30 0.50 --0.09 --3.30 NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS. 28 www.irf.com IR3621 & (PbF) (IR3621F) TSSOP Package 28-Pin A L Q R1 C B 1.0 DIA R E N M P O F PIN NUMBER 1 D DETAIL A DETAIL A G J H K SYMBOL DESIG A B C D E F G H J K L M N O P Q R R1 MIN 4.30 0.19 9.60 --0.85 0.05 0! 0.50 0.09 0.09 28-PIN MAX NOM 0.65 BSC 4.40 6.40 BSC --1.00 1.00 9.70 --0.90 --12! REF 12! REF --1.00 REF 0.60 0.20 ----- 4.50 TAPE & REEL ORIENTATION 0.30 9.80 1.10 0.95 0.15 1 1 1 Figure A : Feed Direction 8! 0.75 ----- NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Industrial market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 10/22/2005 www.irf.com 29