NTGS3136P, NVGS3136P Power MOSFET −20 V, −5.8 A, Single P−Channel, TSOP−6 Features • • • • • Low RDS(on) in TSOP−6 Package 1.8 V Gate Rating Fast Switching NV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com V(BR)DSS −20 V RDS(ON) TYP ID MAX 25 mW @ −4.5 V −5.1 A 32 mW @ −2.5 V −4.5 A 41 mW @ −1.8 V −2.5 A Applications P−Channel • Optimized for Battery and Load Management Applications in • • 1 2 5 6 Portable Equipment High Side Load Switch Switching Circuits for Game Consoles, Camera Phone, etc. 3 MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Symbol Value Unit Drain−to−Source Voltage Parameter VDSS −20 V Gate−to−Source Voltage VGS $8.0 V ID −5.1 Continuous Drain Current (Note 1) Power Dissipation (Note 1) Steady State TA = 25°C TA = 85°C −3.6 tv5s TA = 25°C −5.8 Steady State PD Continuous Drain Current (Note 2) Power Dissipation (Note 2) Pulsed Drain Current Steady State 1 TA = 85°C TA = 25°C tp = 10 ms Operating Junction and Storage Temperature Lead Temperature for Soldering Purposes (1/8” from case for 10 s) −3.7 A −2.7 February, 2015 − Rev. 2 XXX M G = Device Code = Date Code = Pb−Free Package (Note: Microdot may be in either location) PD 0.7 W PIN ASSIGNMENT IDM −20 A Drain Drain Source 6 5 4 TJ, TSTG −55 to 150 °C TL 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces) 2. Surface−mounted on FR4 board using the minimum recommended pad size (Cu area = 0.0775 in sq). © Semiconductor Components Industries, LLC, 2015 XXX MG G 1 W ID TSOP−6 CASE 318G STYLE 1 1.25 1.6 TA = 25°C MARKING DIAGRAM A TA = 25°C tv5s 4 1 1 2 3 Drain Drain Gate ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Publication Order Number: NTGS3136P/D NTGS3136P, NVGS3136P THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Junction−to−Ambient – Steady State (Note 3) Parameter RqJA 100 Junction−to−Ambient – t = 5 s (Note 3) RqJA 77 Junction−to−Ambient – Steady State (Note 4) RqJA 185 Unit °C/W 3. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces) 4. Surface−mounted on FR4 board using the minimum recommended pad size (Cu area = 0.0775 in sq). ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA −20 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate−to−Source Leakage Current ID = −250 mA, Reference 25°C IDSS VGS = 0 V, VDS = −20 V V −13 mV/°C TJ = 25°C −1.0 TJ = 85°C −5.0 IGSS VDS = 0 V, VGS = ±8.0 V VGS(TH) VGS = VDS, ID = −250 mA mA $0.1 mA −1.0 V ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance Forward Transconductance VGS(TH)/TJ −0.4 3 RDS(on) gFS mV/°C VGS = −4.5 V, ID = −5.1 A 25 33 VGS = −2.5 V, ID = −4.5 A 32 40 VGS = −1.8 V, ID = −2.5 A 41 51 VDS = −5.0 V, ID = −5.1 A 22 S 1901 pF mW CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VGS = 0 V, f = 1 MHz, VDS = −10 V 274 175 Total Gate Charge QG(TOT) 18 Threshold Gate Charge QG(TH) 0.7 Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 4.3 RG 7.6 td(ON) 9 19 Tr 9 19 99 160 48 79 TJ = 25°C −0.7 −1.2 V TJ = 125°C −0.6 60 ns Gate Resistance VGS = −4.5 V, VDS = −10 V; ID = −5.1 A 29 nC 2.4 W SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time VGS = −4.5 V, VDD = −10 V, ID = −1.0 A, RG = 6.0 W td(OFF) Tf ns DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD VGS = 0 V, IS = −1.7 A Reverse Recovery Time tRR VGS = 0 V, dIS/dt = 100 A/ms, IS = −1.7 A 37 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Pulse Test: pulse width v 300 ms, duty cycle v 2% 6. Switching characteristics are independent of operating junction temperatures www.onsemi.com 2 NTGS3136P, NVGS3136P TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 20 20 −ID, DRAIN CURRENT (A) −2.5 V 12 −1.5 V 8.0 4.0 15 10 TJ = 25°C 5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1.25 1.5 1.75 2 2.25 2.5 Figure 2. Transfer Characteristics 0.10 0.08 0.06 0.04 TJ = 125°C 0.02 TJ = 25°C 1.5 2.0 2.5 3.0 3.5 4.0 4.5 −VGS, GATE−TO−SOURCE VOLTAGE (V) 5.0 0.10 0.08 C, CAPACITANCE (pF) ID = −4.5 A VGS = −5.1 V 1.2 1.1 1.0 0.9 0.8 −25 0 25 50 75 100 125 −1.8 V 0.07 0.06 0.05 −2 V 0.04 0.03 −2.5 V 0.02 VGS = −4.5 V 0.01 0 0 4.0 8.0 12 16 20 −ID, DRAIN CURRENT (A) Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1.5 1.3 TJ = 25°C 0.09 Figure 3. On−Resistance vs. Gate−to−Source Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1 Figure 1. On−Region Characteristics 0.12 0.7 −50 0.75 −VGS, GATE−TO−SOURCE VOLTAGE (V) ID = −5.1 A 0 1.0 0.5 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.14 1.4 TJ = −55°C TJ = 125°C 0 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) VDS = −5 V −1.8 V −2 V 16 TJ = 25°C RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) −ID, DRAIN CURRENT (A) VGS = −4.5 V 150 2800 2600 2400 2200 2000 1800 1600 1400 1200 1000 800 600 400 200 0 VGS = 0 V TJ = 25°C f = 1 MHz Ciss Coss Crss 0 2 4 6 8 TJ, JUNCTION TEMPERATURE (°C) DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Capacitance Variation www.onsemi.com 3 10 12 NTGS3136P, NVGS3136P 12 QT 10 −VDS 4 8 3 −VGS 6 2 QGS QGD 4 VDS = −10 V ID = −5.1 A TJ = 25°C 1 0 0 2 4 6 8 10 12 14 16 2 0 18 30 VGS = 0 V −IS, SOURCE CURRENT (A) 5 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) −VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 10 TJ = 150°C TJ = 25°C 1.0 0 0.2 0.4 0.6 0.8 1.0 −VSD, SOURCE−TO−DRAIN VOLTAGE (V) QG, TOTAL GATE CHARGE (nC) Figure 7. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 1.2 Figure 8. Diode Forward Voltage vs. Current 0.8 80 ID = −250 mA 70 0.7 60 POWER (W) −VGS(th) (V) 0.6 0.5 0.4 50 40 30 20 0.3 0.2 −50 10 0 −25 0 25 50 75 100 125 150 1E−2 1E−1 1 1E+1 1E+2 TJ, JUNCTION TEMPERATURE (°C) SINGLE PULSE TIME (s) Figure 9. Threshold Voltage Figure 10. Single Pulse Maximum Power Dissipation R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) 100 −ID, DRAIN CURRENT (A) 1E−3 100 ms 10 1 ms 1 VGS = −8.0 V SINGLE PULSE 0.1 TC = 25°C RDS(on) LIMIT Thermal Limit Package Limit 0.01 0.1 1 10 ms dc 10 100 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.01 0.02 0.01 1E−04 1E−03 1E−02 1E−01 1 1E+01 1E+02 1E+03 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) t, TIME (s) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. FET Thermal Response www.onsemi.com 4 1E+3 NTGS3136P, NVGS3136P ORDERING INFORMATION Marking Package Shipping† NTGS3136PT1G SD NVGS3136PT1G* VSD TSOP−6 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable. www.onsemi.com 5 NTGS3136P, NVGS3136P PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE V D H ÉÉ ÉÉ 6 E1 1 NOTE 5 5 2 4 L2 GAUGE PLANE E 3 L M b SEATING PLANE DIM A A1 b c D E E1 e L L2 M DETAIL Z e 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. c A A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 6X 3.20 0.95 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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