CHA2110-98F 7-12GHz LNA GaAs Monolithic Microwave IC Description The CHA2110-98F is a monolithic two-stages wide band low noise amplifier circuit. It is self-biased. It is designed for military, space and telecommunication systems. VD1 VD2 The circuit is manufactured with a pHEMT process, 0.25µm gate length, via holes through the substrate, and air bridges. IN OUT It is available in chip form. S21 (dB) ■ Broadband performances: 7-12GHz ■ Linear gain: 19dB ■ Return Losses: 12dB ■ Noise Figure: 1.2dB ■ Output power @ 1dBcomp: 11dBm ■ DC bias: Vd=4 Volt@Id=45mA ■ Chip size 1.93x1.3x0.1mm 25 5.0 24 4.5 23 4.0 22 3.5 21 20 3.0 S21 2.5 19 2.0 18 1.5 17 NF 16 15 NF (dB) Main Features 1.0 0.5 0.0 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 Frequency (GHz) Gain and NF versus frequency Main Electrical Characteristics Tamb.= +25°C Symbol Parameter Freq Frequency range Gain Linear Gain NF Noise Figure Pout Output Power @1dB comp (f=10GHz) Ref. : DSCHA21102181 - 29 Jun 12 1/10 Min 7 Typ Max 12 19 1.2 11 Unit GHz dB dB dBm Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Bat. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHA2110-98F 7-12GHz LNA Electrical Characteristics Tamb.= +25°C Symbol Parameter Min Freq Frequency range 7 Gain Linear Gain NF Noise Figure RL_in Input return losses RL_out Output return losses P1dB Output power at 1dB comp (f=10GHz) IP3 3rd order interception point (f=10GHz) Vd Drain supply voltage (self biased) Id Drain supply current These values are representative of measurements on test fixture. Typ Max 12 19 1.2 -12 -12 11 21 4 45 Unit GHz dB dB dB dB dBm dB V mA Absolute Maximum Ratings (1) Tamb.= +25°C Symbol Parameter Values Unit Vd Drain bias voltage 5V V Id Drain bias current 70 mA Tj Junction temperature 175 °C Ta Operating temperature range -40 to +85 °C Tstg Storage temperature range -55 to +150 °C (1) Operation of this device above anyone of these parameters may cause permanent damage. (2) Duration < 1s. Typical Bias Conditions Tamb.= +25°C Symbol Pad No Vd VD1, VD2 The circuit is self-biased. Ref. : DSCHA21102181 - 29 Jun 12 Parameter Drain supply voltage 2/10 Values 4 Unit V Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHA2110-98F 7-12GHz LNA Test fixture Measurements T=[-40°C ; +25°C ; +85°C], Vd = +4V, Id = 45mA S21 versus frequency -40°C +25°C +85°C Input return loss Output Return loss -40°C +25°C +85°C -40°C +25°C Ref. : DSCHA21102181 - 29 Jun 12 +85°C 3/10 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHA2110-98F 7-12GHz LNA Test fixture Measurements T=[-40°C ; +25°C ; +85°C], Vd = +4V, Id = 45mA Noise Figure versus frequency 5.0 4.5 4.0 NF (dB) 3.5 3.0 2.5 2.0 +85°C 1.5 +25°C 1.0 -40°C 0.5 0.0 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 Frequency (GHz) P1dB versus frequency -40°C +25°C +85°C Ref. : DSCHA21102181 - 29 Jun 12 4/10 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHA2110-98F 7-12GHz LNA Test fixture Measurements Tamb=+25°C, Vd = +4V, Id = 45mA IP3 versus frequency Ref. : DSCHA21102181 - 29 Jun 12 5/10 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHA2110-98F 7-12GHz LNA Mechanical data 2 3 4 5 6 7 8 1 9 11 13 10 12 Chip thickness: 100µm. Chip size: 1300x1930 ±35µm All dimensions are in micrometers RF pads (1, 9) DC pads (2,3,4,5,6,7,8,10,11,12,13) = 100x120µm² = 100x100µm² Pin number Pin name Description 1 2 E none Input RF NC 3, 4 5 6, 7 8 9 10 11 12 13 GND none VD1 VD2 S 2B 2A 1B 1A NC NC Vd Vd Output RF NC NC NC NC Ref. : DSCHA21102181 - 29 Jun 12 6/10 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHA2110-98F 7-12GHz LNA Recommended assembly plan VD1 VD2 10nF 10nF 100pF 100pF Note: Supply feed should be bypassed. 25µm diameter gold wire is to be preferred. Recommended circuit bonding table Label E Type Input RF Decoupling N/A Vd1, Vd2 Vd 100pF & 10nF S Output RF N/A Ref. : DSCHA21102181 - 29 Jun 12 7/10 Comment Inductance (Lbonding≈750µm) = 0.6nH, 1 gold wire with diameter of 25µm Drain Supply Inductance 1nH Inductance (Lbonding≈500µm) = 0.4nH, 1 gold wire with diameter of 25µm Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHA2110-98F 7-12GHz LNA Chip biasing options This chip is self-biased, and flexibility is provided by the access to number of pads. The internal DC electrical schematic is given in order to use these pads in a safe way. VD1 GND 10Ω VD2 12Ω 15Ω OUT IN 2kΩ 1A 5.5Ω 18Ω 7Ω 5.5Ω 2A 1B 18Ω 7Ω 2B The requirement is : Not to exceed Vds = 3.5Volt (internal Drain to Source voltage). We propose three standard biasing : Low Noise and low consumption: Vd = 4V. The pads 1A, 1B, 2A and 2B are non-connected (NC). Idd = 45mA & Pout-1dB = +11dBm Typical (f=10GHz). Low Noise and higher gain: Vd = 4V and 1A or 1B grounded. All the other pads non connected (NC). Idd = 55mA & Pout-1dB = +11dBm Typical (f=10GHz) Low Noise and higher output power: Vd = 4V and 2A or 2B grounded. All the other pads non connected (NC). Idd = 55mA & Pout-1dB = +13dBm Typical (f=10GHz) Ref. : DSCHA21102181 - 29 Jun 12 8/10 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHA2110-98F 7-12GHz LNA Note Ref. : DSCHA21102181 - 29 Jun 12 9/10 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHA2110-98F 7-12GHz LNA Recommended ESD management Refer to the application note AN0020 available at http://www.ums-gaas.com for ESD sensitivity and handling recommendations for the UMS products. Recommended environmental management UMS products are compliant with the regulation in particular with the directives RoHS N°2011/65 and REACh N°1907/2006. More environmental data are available in the application note AN0019 also available at http://www.ums-gaas.com. Ordering Information Chip form: CHA2110-98F/00 Information furnished is believed to be accurate and reliable. However United Monolithic Semiconductors S.A.S. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of United Monolithic Semiconductors S.A.S.. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. United Monolithic Semiconductors S.A.S. products are not authorised for use as critical components in life support devices or systems without express written approval from United Monolithic Semiconductors S.A.S. Ref. : DSCHA21102181 - 29 Jun 12 10/10 Specifications subject to change without notice Bat. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34