ISL28138, ISL28238 ® Data Sheet February 19, 2008 4.5MHz, Single and Dual Precision Rail-to-Rail Input-Output (RRIO) Op Amps with Very Low Input Bias Current The ISL28138 and ISL28238 are 4.5MHz low-power single and dual operational amplifiers. The parts are optimized for single supply operation from 2.4V to 5.5V, allowing operation from one lithium cell or two Ni-Cd batteries. The parts feature an Input Range Enhancement Circuit (IREC) which enables them to maintain CMRR performance for input voltages greater than the positive supply. The input signal is capable of swinging 0.25V above the positive supply and to 100mV below the negative supply with only a slight degradation of the CMRR performance. The output operation is rail-to-rail. The parts draw minimal supply current (900µA per amplifier) while meeting excellent DC accuracy, AC performance, noise and output drive specifications. The ISL28138 features an enable pin that can be used to turn the device off and reduce the supply current to less than 20µA. Operation is guaranteed over -40°C to +125°C temperature range. ISL28138FHZ-T7* PART MARKING Features • 4.5MHz gain bandwidth product • 900µA supply current (per amplifier) • 300µV maximum offset voltage • 1pA typical input bias current • Down to 2.4V single supply voltage range • Rail-to-rail input and output • Output sources and sinks 60mA load current • Enable pin (ISL28138) • -40°C to +125°C operation • Pb-free (RoHS compliant) Applications • Low-end audio • 4mA to 20mA current loops • Medical devices • Sensor amplifiers Ordering Information PART NUMBER (Note) • ADC buffers PACKAGE (Pb-free) PKG. DWG. # GABR 6 Ld SOT-23 MDP0038 ISL28138FHZ-T7A* GABR 6 Ld SOT-23 MDP0038 ISL28138FBZ 28138 FBZ 8 Ld SOIC MDP0027 ISL28138FBZ-T7* 28138 FBZ 8 Ld SOIC MDP0027 Coming Soon ISL28238FBZ 28238 FBZ 8 Ld SOIC MDP0027 Coming Soon ISL28238FBZ-T7* 28238 FBZ 8 Ld SOIC MDP0027 Coming Soon ISL28238FUZ 8238Z 8 Ld MSOP MDP0043 Coming Soon ISL28238FUZ-T7* 8238Z 8 Ld MSOP MDP0043 • DAC output amplifiers Pinouts OUT 1 V- 2 + - 6 V+ NC 1 5 EN IN- 2 4 IN- IN+ 3 8 EN 7 V+ + 6 OUT V- 4 OUT_A 1 IN-_A 2 IN+_A 3 V- 4 8 V+ - + + - 5 NC ISL28238 (8 LD MSOP) TOP VIEW ISL28238 (8 LD SO) TOP VIEW *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. ISL28138 (8 LD SO) TOP VIEW ISL28138 (6 LD SOT-23) TOP VIEW IN+ 3 1 FN6336.2 OUT_A 1 7 OUT_B IN-_A 2 6 IN-_B IN+_A 3 5 IN+_B V- 4 8 V+ 7 OUT_B - + + - 6 IN-_B 5 IN+_B CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2007, 2008. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL28138, ISL28238 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/µs Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V ESD Tolerance Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Thermal Resistance θJA (°C/W) 6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 230 8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 110 8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 115 Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VOS V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. DESCRIPTION Input Offset Voltage ΔV OS --------------ΔT Input Offset Voltage vs Temperature IOS Input Offset Current IB CONDITIONS MIN (Note 1) TYP MAX (Note 1) UNIT 8 Ld SOIC -300 -650 ±6 300 650 µV 6 Ld SOT-23 -550 -750 ±6 550 750 µV 8 Ld SOIC 0.6 µV/°C -35 -80 ±5 35 80 pA TA = -40°C to +85°C -30 -80 ±1 30 80 pA TA = -40°C to +85°C 5 V Input Bias Current CMIR Common-Mode Voltage Range Guaranteed by CMRR 0 CMRR Common-Mode Rejection Ratio VCM = 0V to 5V 75 70 98 dB PSRR Power Supply Rejection Ratio V+ = 2.4V to 5.5V 80 75 98 dB AVOL Large Signal Voltage Gain VO = 0.5V to 4.5V, RL = 100kΩ to VCM 200 150 580 V/mV VO = 0.5V to 4.5V, RL = 1kΩ to VCM 50 V/mV Output low, RL = 100kΩ to VCM 3 6 8 mV Output low, RL = 1kΩ to VCM 50 70 110 mV VOUT Maximum Output Voltage Swing IS,ON Supply Current, Enabled IS,OFF Supply Current, Disabled (ISL28138) 2 Output high, RL = 100kΩ to VCM 4.994 4.99 4.998 V Output high, RL = 1kΩ to VCM 4.93 4.89 4.95 V 0.7 0.4 0.9 1.1 1.4 mA 10 14 16 µA FN6336.2 February 19, 2008 ISL28138, ISL28238 Electrical Specifications PARAMETER V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued) DESCRIPTION CONDITIONS MIN (Note 1) TYP MAX (Note 1) UNIT IO+ Short-Circuit Output Source Current RL = 10Ω 48 45 75 mA IO- Short-Circuit Output Sink Current RL = 10Ω 50 45 68 mA VSUPPLY Supply Operating Range V+ to V-, Guararteed by PSRR 2.4 VENH EN Pin High Level (ISL28138) VENL EN Pin Low Level(ISL28138) IENH EN Pin Input High Curren (ISL28138) VEN = V+ IENL EN Pin Input Low Current (ISL28138) 5.5 2 V V 0.8 V 1 1.5 1.6 µA VEN = V- 12 25 30 nA AC SPECIFICATONS GBW Gain Bandwidth Product AV = 100, RF = 100kΩ, RG = 1kΩ, RL = 10kΩ to VCM 4.5 MHz Unity Gain Bandwidth -3dB Bandwidth AV =1, RF = 0Ω, VOUT = 10mVP-P, RL = 10kΩ to VCM 13 MHz eN Input Noise Voltage Peak-to-Peak f = 0.1Hz to 10Hz 2 µVP-P Input Noise Voltage Density fO = 1kHz 26 nV/√Hz Input Noise Current Density fO = 1kHz 0.12 pA/√Hz iN CMRR @ 60Hz Input Common Mode Rejection Ratio VCM = 1VP-P, RL = 10kΩ to VCM 85 dB PSRR- @ 120Hz Power Supply Rejection Ratio (V-) V+, V- = ±1.2V and ±2.5V, VSOURCE = 1VP-P, RL = 10kΩ to VCM -82 dB PSRR+ @ 120Hz Power Supply Rejection Ratio (V+) V+, V- = ±1.2V and ±2.5V VSOURCE = 1VP-P, RL = 10kΩ to VCM -100 dB ±4.8 V/µs TRANSIENT RESPONSE SR Slew Rate tr, tf, Large Signal Rise Time, 10% to 90%, VOUT AV = +2, VOUT = 3VP-P, RG = RF = 10kΩ RL = 10kΩ to VCM 530 ns Fall Time, 90% to 10%, VOUT AV = +2, VOUT = 3VP-P, RG = RF = 10kΩ RL = 10kΩ to VCM 530 ns Rise Time, 10% to 90%, VOUT AV = +2, VOUT = 10mVP-P, RG = RF = RL = 10kΩ to VCM 50 ns Fall Time, 90% to 10%, VOUT AV = +2, VOUT = 10mVP-P, RG = RF = RL = 10kΩ to VCM 50 ns Enable to Output Turn-on Delay Time, 10% EN to 10% VOUT, (ISL28138) VEN = 5V to 0V, AV = +2, RG = RF = RL = 1k to VCM 5 µs Enable to Output Turn-off Delay Time, 10% EN to 10% VOUT, (ISL28138) VEN = 0V to 5V, AV = +2, RG = RF = RL = 1k to VCM 0.2 µs tr, tf, Small Signal tEN NOTE: 1. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. 3 FN6336.2 February 19, 2008 ISL28138, ISL28238 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, unless otherwise specified. 1 15 Rf = Rg = 100k Rf = Rg = 10k 5 0 V+ = 5V -5 RL = 1k CL = 16.3pF -10 AV = +2 VOUT = 10mVP-P -15 100 1k 10k Rf = Rg = 1k 100k 1M 10M NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0 10 100M VOUT = 100mV -1 -2 VOUT = 50mV -3 VOUT = 10mV -4 VOUT = 1V -5 -6 V = 5V + -7 RL = 1k CL = 16.3pF -8 AV = +1 -9 1k 10k FREQUENCY (Hz) 1 1 0 0 VOUT = 100mV -2 VOUT = 50mV -3 VOUT = 10mV -4 VOUT = 1V -5 -6 V+ = 5V RL = 10k CL = 16.3pF AV = +1 -7 -8 -9 1k 10k -2 VOUT = 50mV -3 VOUT = 10mV -4 10M VOUT = 1V -6 V+ = 5V RL = 100k CL = 16.3pF AV = +1 -7 1k 100M 10k FREQUENCY (Hz) AV = 101 RL = 100k -3 -4 -5 -6 -7 -8 -9 V+ = 5V VOUT = 10mVP-P CL = 16.3pF AV = +1 1k 10k 100M AV = 1, Rg = INF, Rf = 0 AV = 10, Rg = 1k, Rf = 9.09k AV = 101, Rg = 1k, Rf = 100k AV = 1001, Rg = 1k, Rf = 1M AV = 1001 50 GAIN (dB) NORMALIZED GAIN (dB) RL = 10k -2 10M 70 60 -1 1M FIGURE 4. GAIN vs FREQUENCY vs VOUT, RL = 100k RL = 1k 0 100k FREQUENCY (Hz) FIGURE 3. GAIN vs FREQUENCY vs VOUT, RL = 10k 1 100M -5 -9 1M 10M VOUT = 100mV -1 -8 100k 1M FIGURE 2. GAIN vs FREQUENCY vs VOUT, RL = 1k NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) FIGURE 1. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES Rf/Rg -1 100k FREQUENCY (Hz) 40 V+ = 5V CL = 16.3pF RL = 10k VOUT = 10mVP-P 30 AV = 10 20 10 0 100k 1M 10M FREQUENCY (Hz) FIGURE 5. GAIN vs FREQUENCY vs RL 4 100M -10 100 AV = 1 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 6. FREQUENCY RESPONSE vs CLOSED LOOP GAIN FN6336.2 February 19, 2008 ISL28138, ISL28238 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, unless otherwise specified. 1 V+ = 5V -1 -2 V+ = 2.4V -3 -4 -5 -6 -7 -8 RL = 10k CL = 16.3pF AV = +1 VOUT = 10mVP-P -9 10k 100k 1M 10M NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0 100M 8 7 6 5 4 3 2 1 0 -1 -2 -3 V+ = 5V -4 RL = 1k -5 A = +1 V -6 VOUT = 10mVP-P -7 -8 10k 100k FREQUENCY (Hz) (Continued) CL = 51.7pF CL = 43.7pF CL = 37.7pF CL = 26.7pF CL = 16.7pF CL = 4.7pF 1M 10M 100M FREQUENCY (Hz) FIGURE 8. GAIN vs FREQUENCY vs CL FIGURE 7. GAIN vs FREQUENCY vs SUPPLY VOLTAGE 20 10 0 0 -10 PSRR (dB) -40 -50 V+ = 2.4V, 5V RL = 1k CL = 16.3pF AV = +1 VCM = 1VP-P -60 -70 -80 1k 10k 100k FREQUENCY (Hz) 1M -60 PSRR+ -80 -100 10M -120 100 1k 10k 100k V+, V- = ±1.2V RL = 1k CL = 16.3pF AV = +1 VCM = 1VP-P 1M 10M FREQUENCY (Hz) FIGURE 9. CMRR vs FREQUENCY; V+ = 2.4V AND 5V FIGURE 10. PSRR vs FREQUENCY, V+, V- = ±1.2V 20 1k 0 PSRR- -20 PSRR (dB) -40 -40 -60 PSRR+ -80 -100 -120 100 1k 10k 100k V+, V- = ±2.5V RL = 1k CL = 16.3pF AV = +1 VCM = 1VP-P 1M 10M FREQUENCY (Hz) FIGURE 11. PSRR vs FREQUENCYV, V+, V- = ±2.5V 5 INPUT VOLTAGE NOISE (nV/√Hz) CMRR (dB) -30 -90 100 PSRR- -20 -20 V+ = 5V RL = 1k CL = 16.3pF AV = +1 100 10 1 10 100 1k FREQUENCY (Hz) 10k 100k FIGURE 12. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY FN6336.2 February 19, 2008 ISL28138, ISL28238 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, unless otherwise specified. 0 10 V+ = 5V RL = 1k CL = 16.3pF AV = +1 -0.5 INPUT NOISE (µV) INPUT CURRENT NOISE (pA/√Hz) (Continued) 1 -1.0 -1.5 -2.0 RL = 10k V+ = 5V CL = 16.3pF AV = 10k Rf = 100k Rg = 10 -2.5 -3.0 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k 0 1 2 3 4 5 6 TIME (s) 7 8 9 10 FIGURE 14. INPUT VOLTAGE NOISE 0.1Hz to 10Hz FIGURE 13. INPUT CURRENT NOISE DENSITY vs FREQUENCY 2.0 0.025 SMALL SIGNAL (V) 1.0 0.5 0 V+, V- = ±2.5V RL = 1k CL = 16.3pF Rg = Rf =10k AV = 2 VOUT = 3VP-P -1.0 -1.5 -2.0 0 1 2 3 4 5 6 TIME (µs) 7 8 9 0.020 0.010 10 V+, V- = ±2.5V RL = 1k CL = 16.3pF Rg= Rf = 10k AV = 2 VOUT = 10mVP-P 0.015 0 1 2 3 4 5 6 7 8 9 10 TIME (µs) FIGURE 15. LARGE SIGNAL STEP RESPONSE FIGURE 16. SMALL SIGNAL STEP RESPONSE 1.2 3.5 VOUT VEN 3.0 1.0 2.5 0.8 V+ = 5V Rg = Rf = 10k CL = 16.3pF AV = +2 VOUT = 1VP-P 2.0 1.5 1.0 0.5 0.6 0.4 0.2 RL = 10k 0 0 -0.5 OUTPUT (V) -0.5 VENABLE (V) LARGE SIGNAL (V) 1.5 0 10 20 30 40 50 60 TIME (µs) 70 80 90 -0.2 100 FIGURE 17. ISL28138 ENABLE TO OUTPUT RESPONSE 6 FN6336.2 February 19, 2008 ISL28138, ISL28238 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, unless otherwise specified. 800 100 V+ = 5V RL = OPEN Rf = 100k, Rg = 100 AV = +1k 600 400 V+ = 5V RL = OPEN Rf = 100k, Rg = 100 AV = +1k 80 60 40 200 IBIAS (pA) VOS (µV) (Continued) 0 -200 20 0 -20 -40 -400 -60 -600 -800 -1 -80 0 1 2 3 VCM (V) 4 5 6 FIGURE 18. INPUT OFFSET VOLTAGE vs COMMON MODE INPUT VOLTAGE -100 2 3 VCM (V) 4 5 6 MAX 9.5 MAX CURRENT (µA) CURRENT (µA) 1 10.5 1.1 1.0 MEDIAN 0.9 0.8 MIN 0.7 8.5 MEDIAN 7.5 6.5 MIN 5.5 4.5 -20 0 20 40 60 80 TEMPERATURE (°C) 100 3.5 -40 120 FIGURE 20. SUPPLY CURRENT ENABLED vs TEMPERATURE V+, V- = ±2.5V -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 100 120 FIGURE 21. SUPPLY CURRENT DISABLED vs TEMPERATURE V+, V- = ±2.5V 800 600 600 400 MAX MEDIAN 0 -200 MAX 400 VOS (µV) 200 VOS (µV) 0 FIGURE 19. INPUT BIAS CURRENT vs COMMON MODE INPUT VOLTAGE 1.2 0.6 -40 -1 MIN -400 200 MEDIAN 0 -200 -400 MIN -600 -800 -40 -600 -20 0 20 40 60 80 TEMPERATURE (°C) FIGURE 22. VOS (SOIC PKG) vs TEMPERATURE VIN = 0V, V+, V- = ±2.75V 7 100 120 -800 -40 -20 0 20 40 60 80 TEMPERATURE (°C) FIGURE 23. VOS (SOT PKG) vs TEMPERATURE VIN = 0V, V+, V- = ±2.75V FN6336.2 February 19, 2008 ISL28138, ISL28238 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, unless otherwise specified. 800 600 600 400 400 VOS (µV) VOS (µV) MEDIAN 0 -200 MIN -400 -20 0 20 40 60 80 TEMPERATURE (°C) 100 -200 -800 -40 120 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 100 120 1000 600 800 MAX 200 MEDIAN 0 -200 MIN 400 200 -200 -600 -400 0 20 40 60 80 TEMPERATURE (°C) 100 -600 -40 120 FIGURE 26. VOS (SOIC PKG) vs TEMPERATURE VIN = 0V, V+, V- = ±1.2V 250 250 200 IBIAS- (pA) MAX 150 MIN -20 0 MEDIAN 100 MAX 150 MEDIAN 100 50 50 20 40 60 80 TEMPERATURE (°C) FIGURE 27. VOS (SOT PKG) vs TEMPERATURE VIN = 0V, V+, V- = ±1.2V 300 200 MEDIAN 0 -400 -20 MAX 600 VOS (µV) 400 MIN MIN 0 0 -50 -40 MIN FIGURE 25. VOS (SOT PKG) vs TEMPERATURE VIN = 0V, V+, V- = ±2.5V 800 VOS (µV) MEDIAN 0 -600 FIGURE 24. VOS (SOIC PKG) vs TEMPERATURE VIN = 0V, V+, V- = ±2.5V IBIAS- (pA) 200 -400 -600 -800 -40 MAX MAX 200 -800 -40 (Continued) -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 28. IBIAS- vs TEMPERATURE V+, V- = ±2.5V 8 -50 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 29. IBIAS- vs TEMPERATURE V+, V- = ±1.2V FN6336.2 February 19, 2008 ISL28138, ISL28238 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, unless otherwise specified. 10 20 0 10 MAX -20 0 MEDIAN -30 IOS (pA) IOS (pA) -10 MIN -40 -10 MAX -20 MEDIAN -30 -50 -40 -60 -50 -70 -40 (Continued) -20 0 20 40 60 80 TEMPERATURE (°C) 100 -60 -40 120 FIGURE 30. IOS vs TEMPERATURE V+, V- = ±2.5V MIN -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 31. IOS vs TEMPERATURE V+, V- = ±1.2V 80 1750 70 1350 AVOL (V/mV) AVOL (V/mV) 1550 1150 950 MAX 750 550 MEDIAN 60 MAX 50 MEDIAN 40 30 MIN 350 150 -40 MIN -20 0 20 40 60 80 TEMPERATURE (°C) 100 20 -40 120 140 20 40 60 80 TEMPERATURE (°C) 100 120 100 120 140 MAX 130 130 MAX 120 PSRR (dB) 120 CMRR (dB) 0 FIGURE 33. AVOL vs TEMPERATURE, RL = 1k V+, V- = ±2.5V, VO = -2V TO +2V FIGURE 32. AVOL vs TEMPERATURE, RL = 100k, V+, V- = ±2.5V, VO = -2V TO +2V 110 MEDIAN 100 90 110 100 MEDIAN 90 MIN MIN 80 80 70 -40 -20 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 34. CMRR vs TEMPERATURE, VCM = +2.5V TO -2.5V, V+, V- = ±2.5V 9 70 -40 -20 0 20 40 60 80 TEMPERATURE (°C) FIGURE 35. PSRR vs TEMPERATURE, V+, V- = ±1.2V TO ±2.75V FN6336.2 February 19, 2008 ISL28138, ISL28238 Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, unless otherwise specified. 4.970 4.9994 4.965 4.9992 MAX MAX 4.9990 VOUT (V) VOUT (V) 4.960 4.955 MEDIAN 4.945 0 4.9984 20 40 60 80 TEMPERATURE (°C) 100 75 3.3 70 3.1 MEDIAN 55 MIN 100 120 MAX 2.7 2.5 2.3 MEDIAN MIN 1.9 45 1.7 0 20 40 60 80 TEMPERATURE (°C) 100 90 MAX 85 80 MEDIAN 75 70 MIN 65 0 20 40 60 80 TEMPERATURE (°C) 100 FIGURE 40. + OUTPUT SHORT CIRCUIT CURRENT vs TEMPERATURE VIN = -2.55V, RL = 10, V+, V- = ±2.5V 10 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 39. VOUT LOW vs TEMPERATURE RL=100k, V+, V- = ±2.5V 95 -20 1.5 -40 120 120 - OUTPUT SHORT CIRCUIT CURRENT (mA) -20 FIGURE 38. VOUT LOW vs TEMPERATURE RL = 1k, V+, V- = ±2.5V + OUTPUT SHORT CIRCUIT CURRENT (mA) 20 40 60 80 TEMPERATURE (°C) 2.1 50 60 -40 0 2.9 MAX 60 40 -40 -20 FIGURE 37. VOUT HIGH vs TEMPERATURE RL = 100k, V+, V- = ±2.5V VOUT (mV) VOUT (mV) 4.9982 -40 120 FIGURE 36. VOUT HIGH vs TEMPERATURE RL = 1k, V+, V- = ±2.5V 65 MEDIAN MIN MIN -20 4.9988 4.9986 4.950 4.940 -40 (Continued) -50 -55 MAX -60 MEDIAN -65 -70 MIN -75 -80 -85 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 41. - OUTPUT SHORT CIRCUIT CURRENT vs TEMPERATURE VIN = -2.55V, RL = 10, V+, V- = ±2.5V FN6336.2 February 19, 2008 ISL28138, ISL28238 Pin Descriptions ISL28138 (6 Ld SOT-23) ISL28138 (8 Ld SOIC) ISL28238 (8 Ld SOIC) (8 Ld MSOP) PIN NAME 1, 5 4 2 2 (A) 6 (B) FUNCTION NC Not connected ININ-_A IN-_B inverting input EQUIVALENT CIRCUIT V+ IN- IN+ VCircuit 1 3 2 3 (A) 5 (B) IN+ IN+_A IN+_B 4 V- 3 4 Non-inverting input Negative supply (See circuit 1) V+ CAPACITIVELY COUPLED ESD CLAMP VCircuit 2 1 6 1 (A) 7 (B) OUT OUT_A OUT_B Output V+ OUT VCircuit 3 6 7 5 8 8 V+ Positive supply EN Chip enable (See circuit 2) V+ EN VCircuit 4 Applications Information Introduction The ISL28138 and ISL28238 are single and dual channel CMOS rail-to-rail input, output (RRIO) micropower precision operational amplifiers. The parts are designed to operate from single supply (2.4V to 5.5V) or dual supply (±1.2V to ±2.75V). The parts have an input common mode range that extends 0.25V above the positive rail and 100mV below the the negative supply rail. The output operation can swing within about 3mV of the supply rails with a 100kΩ load. Rail-to-Rail Input Many rail-to-rail input stages use two differential input pairs, a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the 11 input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. The ISL28138 and ISL28238 achieve input rail-to-rail operation without sacrificing important precision specifications and degrading distortion performance. The devices’ input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. The input bias current versus the common-mode voltage range gives us an undistorted behavior from typically 100mV below the negative rail and 0.25V higher than the V+ rail. FN6336.2 February 19, 2008 ISL28138, ISL28238 Rail-to-Rail Output A pair of complementary MOS devices are used to achieve the rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. The ISL28138 and ISL28238 with a 100kΩ load will swing to within 3mV of the positive supply rail and within 3mV of the negative supply rail. Results of Over-Driving the Output Caution should be used when over-driving the output for long periods of time. Over-driving the output can occur in two ways. 1) The input voltage times the gain of the amplifier exceeds the supply voltage by a large value or, 2) the output current required is higher than the output stage can deliver. These conditions can result in a shift in the Input Offset Voltage (VOS) as much as 1µV/hr. of exposure under these conditions. IN+ and IN- Input Protection All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. They also contain back-to-back diodes across the input terminals (see “Pin Descriptions” on page 11 - Circuit 1). For applications where the input differential voltage is expected to exceed 0.5V, an external series resistor must be used to ensure the input currents never exceed 5mA (Figure 42). will be enabled by default. When not used, the EN pin should either be left floating or connected directly to the V- pin. Limitations of the Differential Input Protection If the input differential voltage is expected to exceed 0.5V, an external current limiting resistor must be used to ensure the input current never exceeds 5mA. For non-inverting unity gain applications the current limiting can be via a series IN+ resistor, or via a feedback resistor of appropriate value. For other gain configurations, the series IN+ resistor is the best choice, unless the feedback (RF) and gain setting (RG) resistors are both sufficiently large to limit the input current to 5mA. Large differential input voltages can arise from several sources: 1) During open loop (comparator) operation. Used this way, the IN+ and IN- voltages don’t track, so differentials arise. 2) When the amplifier is disabled but an input signal is still present. An RL or RG to GND keeps the IN- at GND, while the varying IN+ signal creates a differential voltage. Mux Amp applications are similar, except that the active channel VOUT determines the voltage on the IN- terminal. 3) When the slew rate of the input pulse is considerably faster than the op amp’s slew rate. If the VOUT can’t keep up with the IN+ signal, a differential voltage results, and visible distortion occurs on the input and output signals. To avoid this issue, keep the input slew rate below 4.8V/µs, or use appropriate current limiting resistors. VIN VOUT RIN RL + Large (>2V) differential input voltages can also cause an increase in disabled ICC. Using Only One Channel FIGURE 42. INPUT CURRENT LIMITING Enable/Disable Feature The ISL28138 offers an EN pin that disables the device when pulled up to at least 2.0V. In the disabled state (output in a high impedance state), the part consumes typically 10µA at room temperature. By disabling the part, multiple ISL28138 parts can be connected together as a MUX. In this configuration, the outputs are tied together in parallel and a channel can be selected by the EN pin. The loading effects of the feedback resistors of the disabled amplifier must be considered when multiple amplifier outputs are connected together. Note that feed through from the IN+ to IN- pins occurs on any Mux Amp disabled channel where the input differential voltage exceeds 0.5V (e.g., active channel VOUT = 1V, while disabled channel VIN = GND), so the mux implementation is best suited for small signal applications. If large signals are required, use series IN+ resistors, or large value RF, to keep the feed through current low enough to minimize the impact on the active channel. See “Limitations of the Differential Input Protection” on page 12 for more details.The EN pin also has an internal pull-down. If left open, the EN pin will pull to the negative rail and the device 12 If the application only requires one channel of the ISL28238, the user must configure the unused channel to prevent it from oscillating. The unused channel will oscillate if the input and output pins are floating. This will result in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation is to short the output to the negative input and ground the positive input (as shown in Figure 43). + FIGURE 43. PREVENTING OSCILLATIONS IN UNUSED CHANNELS FN6336.2 February 19, 2008 ISL28138, ISL28238 Proper Layout Maximizes Performance Power Dissipation To achieve the maximum performance of the high input impedance and low offset voltage, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. When input leakage current is a concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 44 shows a guard ring example for a unity gain amplifier that uses the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. For further reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators. It is possible to exceed the +150°C maximum junction temperatures under certain load and power-supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related in Equation 1: V+ HIGH IMPEDANCE INPUT T JMAX = T MAX + ( θ JA xPD MAXTOTAL ) (EQ. 1) where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • PDMAX for each amplifier can be calculated as shown in Equation 2: V OUTMAX PD MAX = 2*V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------RL (EQ. 2) where: IN • TMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation of 1 amplifier FIGURE 44. GUARD RING EXAMPLE FOR UNITY GAIN AMPLIFIER • VS = Supply voltage (Magnitude of V+ and V-) • IMAX = Maximum supply current of 1 amplifier Current Limiting The ISL28138 and ISL28238 have no internal current limiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device. 13 • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance FN6336.2 February 19, 2008 ISL28138, ISL28238 SOT-23 Package Family MDP0038 e1 D SOT-23 PACKAGE FAMILY A MILLIMETERS 6 N SYMBOL 4 E1 2 E 3 0.15 C D 1 2X 2 3 0.20 C 5 2X e 0.20 M C A-B D B b NX 0.15 C A-B 1 3 SOT23-5 SOT23-6 A 1.45 1.45 MAX A1 0.10 0.10 ±0.05 A2 1.14 1.14 ±0.15 b 0.40 0.40 ±0.05 c 0.14 0.14 ±0.06 D 2.90 2.90 Basic E 2.80 2.80 Basic E1 1.60 1.60 Basic e 0.95 0.95 Basic e1 1.90 1.90 Basic L 0.45 0.45 ±0.10 L1 0.60 0.60 Reference N 5 6 Reference D 2X TOLERANCE Rev. F 2/07 NOTES: C A2 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. SEATING PLANE A1 0.10 C 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. NX 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). (L1) 6. SOT23-5 version has no center lead (shown as a dashed line). H A GAUGE PLANE c L 14 0.25 0° +3° -0° FN6336.2 February 19, 2008 ISL28138, ISL28238 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 15 FN6336.2 February 19, 2008 ISL28138, ISL28238 Mini SO Package Family (MSOP) 0.25 M C A B D MINI SO PACKAGE FAMILY (N/2)+1 N E MDP0043 A E1 MILLIMETERS PIN #1 I.D. 1 B (N/2) e H C SEATING PLANE 0.10 C N LEADS SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - L 0.55 0.55 ±0.15 - L1 0.95 0.95 Basic - N 8 10 Reference - 0.08 M C A B b Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE A1 L 0.25 3° ±3° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN6336.2 February 19, 2008