ASAHI KASEI [AK4363] AK4363 96kHz 24Bit ∆Σ DAC with PLL GENERAL DESCRIPTION The AK4363 is a stereo CMOS D/A Converter and Phase Locked Loop for use in digital video broadcast set-top box applications or DVD. The DAC signal outputs are single-ended and are analog filtered to remove out of band noise. Therefore no external filters are required. The PLL provides selectable sampling clock frequencies locked to the 27MHz recovered MPEG clock. FEATURES o Stereo ∆Σ DAC o S/(N+D): 90dB@5V o DR: 102dB@5V o S/N: 102dB@5V o Multiple Sampling Frequencies: 16kHz, 22.05kHz, 24kHz (Half speed) 32kHz, 44.1kHz, 48kHz (Normal speed) 64kHz, 88.2kHz, 96kHz (Double speed) o On-Chip Low Jitter Analog PLL: Multiple Master Clock Frequencies generated from 27MHz 256fs/384fs/512fs/768fs/1024fs/1536fs for Half speed 256fs/384fs/512fs/768fs for Normal speed 128fs/192fs/256fs/384fs for Double speed o Master Clock: PLL / External o Data Input Formats: LSB justified / MSB justified / I2S selectable o Selectable Function: Soft Mute Digital Attenuator (256 Steps) Digital De-emphasis (44.1kHz/48kHz/32kHz) o Output Mode: Stereo, Mono, Reverse, Mute o Input Level:TTL/CMOS Selectable o Output Level: 3.0Vpp@5V o Control mode: 3-wire Serial / I2C Bus o Low Power Dissipation: 80mW@5V o Small 24pin VSOP Package o Power Supply: 2.7∼5.5V o Ta: -40∼85°C MS0015-E-01 2000/07 -1- ASAHI KASEI [AK4363] n Block Diagram CSN CCLK CDTI CAD1 CAD0 I2C MCKI MCKO FLT AVDD LRCK BICK SDTI Serial Input Interface AVSS PLL & Clock Generator VCOM TTL DVDD ATT 8X Interpolator ∆Σ Modulator LPF AOUTL ATT 8X Interpolator ∆Σ Modulator LPF AOUTR Mixer DVSS DZF PDN Figure 1. 3-wire Serial Control Mode (I2C = “L”) CSN CAD1 CAD0 I2C SCL SDA MCKI MCKO FLT AVDD LRCK BICK SDTI Serial Input Interface AVSS PLL & Clock Generator VCOM TTL DVDD ATT 8X Interpolator ∆Σ Modulator LPF AOUTL ATT 8X Interpolator ∆Σ Modulator LPF AOUTR Mixer DVSS DZF PDN Figure 2. I2C Bus Control Mode (I2C = “H”) MS0015-E-01 2000/07 -2- ASAHI KASEI [AK4363] n Ordering Guide AK4363VF AKD4363 -40∼+85°C Evaluation Board 24pin VSOP n Pin Layout MCKO 1 24 DZF NC 2 23 FLT DVDD 3 22 AVDD DVSS 4 21 AVSS MCKI 5 20 VCOM BICK 6 19 AOUTL SDTI 7 18 AOUTR LRCK 8 17 CAD1 PDN 9 16 CAD0 CSN 10 15 I2C SCL/CCLK 11 14 TTL SDA/CDTI 12 13 TST Top View MS0015-E-01 2000/07 -3- ASAHI KASEI [AK4363] PIN/FUNCTION No. 1 Pin Name MCKO I/O O 2 NC - 3 4 5 DVDD DVSS MCKI I 6 7 8 9 BICK SDTI LRCK PDN I I I I 10 CSN I 11 13 SCL CCLK SDA CDTI TST 14 TTL I 15 I2C I 16 17 18 19 20 CAD0 CAD1 AOUTR AOUTL VCOM I I O O O 21 22 23 AVSS AVDD FLT O 24 DZF O 12 I I I/O I I Description Master Clock Output Pin EXT = “0”: System clock is output from PLL circuit (PLL mode), EXT = “1”: Same frequency as MCKI is output (External mode) No Connect Nothing should be connected externally to this pin. Digital Power Supply Pin, +2.7∼+5.5V Digital Ground Pin, 0V System Clock Input Pin EXT = “0”: 27MHz (PLL mode), EXT = “1”: Other frequency (External mode) Serial Data Clock Pin Serial Data Input Pin Serial Input Channel Clock Pin Power-Down Pin When “L”, the circuit is in power-down mode. The AK4363 should always be reset upon power-up. Chip Select Pin at 3-wire Serial control mode This pin should be connected to DVDD at I2C Bus control mode. Control Clock Pin at I2C bus control mode Control Clock Pin at 3-wire serial control mode Control Data Input/Output Pin at I2C Bus control mode Control Data Input Pin at 3-wire serial control mode Test pin This pin should be connected to DVSS. Digital Input Level Select Pin “L”: CMOS, “H”: TTL Control Mode Select Pin “L”: 3-wire Serial, “H”: I2C Bus Chip Address Select 0 Pin Chip Address Select 1 Pin Rch Analog Output Pin Lch Analog Output Pin Common Voltage Output Pin, AVDD/2 Used for analog common voltage. Large external capacitor is used to reduce power supply noise. Analog Ground Pin Analog Power Supply Pin Output Pin for Loop Filter of PLL Circuit This pin should be connected to AVSS with one resister and one capacitor in series. ( See “SYSTEM DESIGN”.) Zero Input Detect Pin When SDTI follows a total 8192 LRCK cycles with “0” input data or RSTN = “0”, this pin goes to “H”. Note: No input pins should be left floating. MS0015-E-01 2000/07 -4- ASAHI KASEI [AK4363] ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS=0V; Note 1) Parameter Symbol min Power Supplies Analog AVDD -0.3 Digital DVDD -0.3 |AVSS-DVSS| (Note 2) ∆GND Input Current (any pins except for supplies) IIN Analog Input Voltage VINA -0.3 Digital Input Voltage VIND -0.3 Ambient Temperature Ta -40 Storage Temperature Tstg -65 max 6.0 6.0 0.3 ±10 AVDD+0.3 DVDD+0.3 85 150 Units V V V mA V V °C °C Note:1. All voltages with respect to ground. 2. AVSS and DVSS must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS=0V; Note 1) Parameter Symbol min typ Power Supplies 3V operation (TTL = “L”) (Note 3) Analog AVDD 2.7 3.0 Digital DVDD 2.7 3.0 5V operation (TTL = “H”) Analog AVDD 4.5 5.0 Digital DVDD 4.5 5.0 max Units 5.5 3.6 or AVDD V V 5.5 AVDD V V Note:1. All voltages with respect to ground. 3. The power up sequence between AVDD and DVDD is not critical. *AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0015-E-01 2000/07 -5- ASAHI KASEI [AK4363] ANALOG CHARACTERISTICS (fs=44.1kHz) (Ta=25°C; AVDD, DVDD=5V; fs=44.1kHz; EXT = “1”; FS1-0 = “00”; DFS1-0 = “00”; CKS2-0 = “000”; DIF2-0 = “101”; Signal Frequency =1kHz; Measurement frequency=20Hz∼20kHz; unless otherwise specified) Parameter min typ max Units Dynamic Characteristics Resolution 24 Bits S/(N+D) AVDD=5V 84 90 dB AVDD=3V 80 86 dB DR (-60dB input, A-weighted) AVDD=5V 94 102 dB AVDD=3V 90 97 dB S/N (A-weighted) AVDD=5V 94 102 dB AVDD=3V 90 97 dB Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 20 ppm/°C Output Voltage AOUT=0.6x(AVDD-AVSS) AVDD=5V 2.8 3.0 3.2 Vpp AVDD=3V 1.66 1.8 1.94 Vpp Load Resistance (Note 4) 10 kΩ Load Capacitance 25 pF Power Supplies Power Supply Current Normal Operation (PDN = “H”) (Note 5) AVDD 8 12 mA DVDD 8 16 mA Power-Down-Mode (PDN = “L”) AVDD+DVDD 10 100 µA Note:4. AC load. 5. AVDD is 9mA(typ) at EXT = “0”. DVDD drops to 4mA at DVDD=3V. MS0015-E-01 2000/07 -6- ASAHI KASEI [AK4363] ANALOG CHARACTERISTICS (fs=96kHz) (Ta=25°C; AVDD, DVDD=5V; fs=96kHz; EXT = “1”; FS1-0 = “01”; DFS1-0 = “01”; CKS2-0 = “001”; DIF2-0 = “101”; Signal Frequency =1kHz; Measurement frequency=20Hz∼40kHz; unless otherwise specified) Parameter min typ max Units Dynamic Characteristics Resolution 24 Bits S/(N+D) AVDD=5V 80 86 dB AVDD=3V 78 84 dB DR (-60dB input) AVDD=5V 88 96 dB AVDD=3V 84 92 dB S/N AVDD=5V 88 96 dB AVDD=3V 84 92 dB Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 20 ppm/°C Output Voltage AOUT=0.6x(AVDD-AVSS) AVDD=5V 2.8 3.0 3.2 Vpp AVDD=3V 1.66 1.8 1.94 Vpp Load Resistance (Note 4) 10 kΩ Load Capacitance 25 pF Power Supplies Power Supply Current Normal Operation (PDN = “H”) (Note 6) AVDD 8 12 mA DVDD 13 26 mA Power-Down-Mode (PDN = “L”) AVDD+DVDD 10 100 µA Note:4. AC load. 6. AVDD is 9mA(typ) at EXT = “0”. DVDD drops to 7mA at DVDD=3V. MS0015-E-01 2000/07 -7- ASAHI KASEI [AK4363] FILTER CHARACTERISTICS (fs=44.1kHz) (Ta=25°C; AVDD, DVDD=2.7∼5.5V; fs=44.1kHz; DEM=OFF) Parameter Symbol min typ Digital Filter Passband (Note 7) -0.02dB PB 0 -6.0dB 22.05 Stopband (Note 7) SB 24.1 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 8) GD 20.1 Digital Filter + Analog Filter FR Frequency Response: 0∼20.0kHz ±0.2 max Units 20.0 - - kHz kHz kHz dB dB 1/fs - dB ±0.02 Note:7. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@±0.02dB), SB=0.546*fs. 8. The calculating delay time which occurred by digital filtering. This time is from setting the 24bit data of both channels on the input register to the output of analog signal. FILTER CHARACTERISTICS (fs=96kHz) (Ta=25°C; AVDD, DVDD=2.7∼5.5V; fs=96kHz; DEM=OFF) Parameter Symbol min typ Digital Filter Passband (Note 7) -0.02dB PB 0 -6.0dB 48.0 Stopband (Note 7) SB 52.5 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 8) GD 20.1 Digital Filter + Analog Filter FR Frequency Response: 0∼20.0kHz ±0.2 40.0kHz ±0.2 max Units 43.5 - - kHz kHz kHz dB dB 1/fs - dB dB ±0.02 Note:7. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@±0.02dB), SB=0.546*fs. 8. The calculating delay time which occurred by digital filtering. This time is from setting the 24bit data of both channels on the input register to the output of analog signal. MS0015-E-01 2000/07 -8- ASAHI KASEI [AK4363] DIGITAL CHARACTERISTICS (CMOS level input) (Ta=25°C; AVDD=2.7∼5.5V; DVDD=2.7∼3.6V; TTL = “L”) Parameter Symbol min typ High-Level input voltage VIH 0.7xDVDD Low-Level input voltage VIL High-Level Output Voltage (MCKO pins: Iout=-100µA) VOH DVDD-0.5 (DZF pin: Iout=-100µA) VOH AVDD-0.5 Low-Level Output Voltage (MCKO, DZF pins: Iout= 100µA) VOL (SDA pin: Iout= 3mA) VOL Input leakage current Iin - max 0.3xDVDD Units V V - V V 0.5 0.4 ±10 V V µA DIGITAL CHARACTERISTICS (TTL level input; except for TTL pin) (Ta=25°C; AVDD, DVDD=4.5∼5.5V; TTL = “H”) Parameter Symbol min typ max Units High-Level input voltage (TTL pin) VIH 0.7xDVDD V (All pins except for TTL pin) VIH 2.2 V Low-Level input voltage (TTL pin) VIL 0.3xDVDD V (All pins except for TTL pin) VIL 0.8 V High-Level Output Voltage (MCKO pins: Iout=-100µA) VOH DVDD-0.5 V (DZF pin: Iout=-100µA) VOH AVDD-0.5 V Low-Level Output Voltage (MCKO, DZF pins: Iout= 100µA) VOL 0.5 V (SDA pin: Iout= 3mA) VOL 0.4 V Input leakage current Iin ±10 µA MS0015-E-01 2000/07 -9- ASAHI KASEI [AK4363] SWITCHING CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.7∼5.5V; CL=20pF) Parameter Symbol min 27MHz Input (PLL mode): Frequency f27M Pulse Width Low t27ML 14 Pulse Width High t27MH 14 Master Clock Input (External mode): Frequency 128fs/256fs/512fs/1024fs fCLK 4.096 192fs/384fs/768fs/1536fs fCLK 6.144 Duty Cycle dCLK 40 MCKO Output (PLL mode): Frequency fMCKO 4.096 Duty Cycle dMCKO 40 Rise time (20% to 80% DVDD) trMCKO Fall time (80% to 20% DVDD) tfMCKO LRCK: (Note 9) Frequency fsh 16 Half Speed Mode (DFS1-0 = “11”) fsn 32 Normal Speed Mode (DFS1-0 = “00”) fsd 64 Double Speed Mode (DFS1-0 = “01”) Duty 45 Duty Cycle Serial Interface Timing: BICK Period Half Speed Mode tBCK 1/128fs Normal Speed Mode tBCK 1/128fs Double Speed Mode tBCK 1/64fs BICK Pulse Width Low tBCKL 70 BICK Pulse Width High tBCKH 70 tBLR 40 BICK “↑” to LRCK Edge (Note 10) tLRB 40 LRCK Edge to BICK “↑” (Note 10) tSDH 40 SDTI Hold Time tSDS 40 SDTI Setup Time Power-down & Reset Timing PDN Pulse Width (Note 11) tPDW 150 typ max 27 Units MHz ns ns 24.576 36.864 60 MHz MHz % 36.864 60 MHz % ns ns 24 48 96 55 kHz kHz kHz % 2 2 ns ns ns ns ns ns ns ns ns ns Note: 9. If sampling speed mode (DFS0-1) changes, please reset by PDN pin or RSTN bit. 10. BICK rising edge must not occur at the same time as LRCK edge. 11. The AK4363 can be reset by PDN pin “L” upon power up. If CKS0-2 or DFS0-1 changes, the AK4363 should be reset by PDN pin or RSTN bit. MS0015-E-01 2000/07 - 10 - ASAHI KASEI [AK4363] Parameter Control Interface Timing (3-wire Serial mode): CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 12) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise suppressed by Input Filter Symbol min tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 40 40 150 50 50 fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP 4.7 4.0 4.7 4.0 4.7 0 0.25 4.0 0 typ max Units ns ns ns ns ns ns ns ns 100 1.0 0.3 50 kHz µs µs µs µs µs µs µs µs µs µs ns Note:12. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. MS0015-E-01 2000/07 - 11 - ASAHI KASEI [AK4363] n Timing Diagram 1/f27M VIH 27M VIL t27MH t27ML 1/fCLK VIH MCKI VIL tCLKH tCLKL dCLK=tCLKH*fCLK*100 =tCLKL*fCLK*100 1/fMCKO MCKO 50%DVDD 1/fs VIH LRCK VIL 1/fBCK VIH BICK VIL tBCKH tBCKL Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDS tSDH VIH SDTI VIL Serial Interface Timing tPDW PDN VIL Power-down & Reset Timing MS0015-E-01 2000/07 - 12 - ASAHI KASEI [AK4363] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 tCDH C0 R/W VIH A4 VIL WRITE Command Input Timing (3-wire Serial mode) tCSW VIH CSN VIL tCSH VIH CCLK VIL CDTI D3 D2 D1 VIH D0 VIL WRITE Data Input Timing (3-wire Serial mode) VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop I2C Bus mode Timing MS0015-E-01 2000/07 - 13 - ASAHI KASEI [AK4363] OPERATION OVERVIEW n System Clock Input 1) PLL mode (EXT = “0”) A fully integrated analog phase locked loop generates MCKO which is locked to the 27MHz reference input. The frequency of the MCKO output is selectable via register data of CKS2-0, DFS1-0 and FS1-0 as defined in Table 1-3. The PLL requires 20ms lock time whenever MCKO frequency selection changes or MCKO source changes from EXT mode to PLL mode, but 100ms upon power-up after 27MHz system clock stabilizes. Serial input data is zeroed internally while PLL is unlocked to prevent spurious output. When 27MHz clock is not present, the internal VCO frequency is pulled to its minimum value. The LRCK input must be synchronous with MCKO, however the phase is not critical. Internal timing is synchronized to LRCK input upon power-up. When MCKO frequency changes by register data of CKS2-0, DFS1-0 or FS1-0 during normal operation, the AK4363 should be reset by PDN pin “L” or RSTN bit “0”. Serial input data is zeroed internally until PLL is locked after exiting resetting. 2) External mode (EXT = “1”) When EXT bit is set to “1”, master clock can be input via MCKI pin. In this case, MCKO frequency is same as MCKI and it is not necessary to change the register data of FS1-0. The external clocks which are required to operate the AK4363 are MCKI, LRCK and BICK. The master clock (MCKI) should be synchronized with sampling clock (LRCK) but the phase is not critical. MCKI is used to operate the digital interpolation filter and the delta-sigma modulator. The frequency of MCKI can be set by CKS2-0, and can be selected to half, normal or double speed mode by DFS1-0 (See Table 2). In this case, internal VCO is powered down. Therefore, all external clocks should always be present whenever the AK4363 is in the normal operation mode (PDN = “H”). If these clock are not provided, the AK4363 may draw excess current and may not possibly operate properly because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4363 should be in the power-down mode (PDN = “L”) or in the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4363 is in the power-down mode until MCKI and LRCK are input. When the register data of CKS2-0 or DFS1-0 is changed during normal operation, the AK4363 should be reset by PDN pin “L” or RSTN bit “0”. DFS1-0 “11 “00” “01” (Half speed) (Normal speed) (Double speed) 1 0 16 32 64 0 0 22.05 88.2 default (DFS1-0 = “00”) 44.1 0 1 24 48 96 Table 1. Sampling Frequency [kHz] (FS1-0 = “11”, DFS1-0 = “10”: reserved) FS1 FS0 MS0015-E-01 2000/07 - 14 - ASAHI KASEI [AK4363] CKS2 CKS1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 fs [kHz] 16 32 64 22.05 44.1 88.2 24 48 96 Mode Half Normal Double Half Normal Double Half Normal Double DFS1-0 “11” “00” “01” (Half speed) (Normal speed) (Double speed) 0 512fs 128fs 256fs 1 256fs 256fs 256fs 0 768fs 384fs 192fs 1 384fs 384fs 384fs 0 1024fs 512fs 256fs 1 512fs 512fs N/A 0 1536fs 768fs 384fs 1 768fs 768fs N/A Table 2. System Clock (DFS1-0 = “10”: reserved) CKS0 128fs 8.1920 11.2896 12.2880 192fs 256fs 384fs 512fs 4.0960 6.1440 8.1920 8.1920 12.2880 16.3840 12.2880 16.3840 24.5760 5.6448 8.4672 11.2896 11.2896 16.9344 22.5792 16.9344 22.5792 33.8688 6.1440 9.2160 12.2880 12.2880 18.4320 24.5760 18.4320 24.5760 36.8640 Table 3. Example of System Clock [MHz] 768fs 12.2880 24.5760 16.9344 33.8688 18.4320 36.8640 - default (DFS1-0 = “00”) 1024fs 16.3840 22.5792 24.5760 - 1536fs 24.5760 33.8688 36.8640 - n Audio Serial Interface Format Data is shifted in via the SDTI pin using BICK and LRCK inputs. 6 serial data modes are supported and selected by register data of DIF2-0 as shown in Table 4. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK. Mode 4 can be used for 20, 18 and 16 MSB justified formats by zeroing the unused LSBs. Mode 0 1 2 3 4 5 6 7 DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIF0 SDTI 0 16bit, LSB justified 1 18bit, LSB justified 0 20bit, LSB justified 1 24bit, LSB justified 0 24bit, MSB justified 1 I2 S 0 Reserved 1 Reserved Table 4. Audio Data Format MS0015-E-01 L/R H/L H/L H/L H/L H/L L/H BICK ≥32fs ≥36fs ≥40fs ≥48fs ≥48fs ≥48fs default 2000/07 - 15 - ASAHI KASEI [AK4363] LRCK 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 BICK (32fs) SDTI Mode 0 15 14 6 1 0 5 14 4 15 3 16 2 1 17 0 31 15 0 14 6 5 14 1 4 15 3 16 2 1 17 0 31 15 0 14 1 BICK (64fs) SDTI Mode 0 Don’t care 15 14 0 Don’t care 15 14 0 Don’t care 15 14 0 15 14 0 15:MSB, 0:LSB SDTI Mode 1 Don’t care 17 16 17 16 17:MSB, 0:LSB 0 1 7 8 11 12 31 0 1 7 8 11 12 31 0 1 BICK (64fs) SDTI Mode 2 Don’t care SDTI Mode 3 Don’t care 19 0 Don’t care 19 0 Don’t care 19 0 19 0 19:MSB, 0:LSB 23 20 23 20 23:MSB, 0:LSB Lch Data Rch Data Figure 3. Mode 0-3 Timing LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1 BICK (64fs) SDTI 23 22 1 0 Don’t care 23 22 1 0 Don’t care 23 22 23:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 4 Timing MS0015-E-01 2000/07 - 16 - ASAHI KASEI [AK4363] LRCK 0 1 2 3 11 12 13 14 15 0 1 2 3 11 12 13 14 15 0 1 BICK (32fs) SDTI 8 0 23 1 22 2 13 3 23 12 24 11 25 10 9 31 8 0 23 1 22 2 12 13 3 23 24 11 25 10 9 31 8 0 23 1 BICK (64fs) SDTI 23 1 22 0 Don’t care 23 22 1 0 Don’t care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 5. Mode 5 Timing n De-emphasis filter A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling speed (tc=50/15µs). It is enabled or disabled with the control register data of DEM1-0 and DFS1-0. The de-emphasis filter is disabled at half/double sampling mode. DEM1 DEM0 De-emphasis 0 0 44.1kHz 0 1 OFF default 1 0 48kHz 1 1 32kHz Table 5. De-emphasis filter control with DEM1-0 (DFS1-0 = “00”) DFS1 DFS0 De-emphasis 0 0 See Table 5. default 0 1 OFF 1 0 OFF 1 1 OFF Table 6. De-emphasis filter control with DFS1-0 MS0015-E-01 2000/07 - 17 - ASAHI KASEI [AK4363] n Zero detection When the input data at both channels is continuously zeros for 8192 LRCK cycles, DZF pin goes to “H”. DZF pin immediately goes to “L” if input data is not zero after going DZF “H”. If RSTN bit becomes “0”, DZF pin goes to “H”. DZF pin goes to “L” at 4∼5/fs after RSTN bit returns to “1”. n Soft mute operation Soft mute operation is performed at digital domain. When the serial control register data of SMUTE goes “1”, the output signal is attenuated by -∞ during 1024 LRCK cycles. When SMUTE is returned to “0”, the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE bit 1024/fs 0dB 1024/fs (1) (3) Attenuation -∞ GD (2) GD AOUT DZF pin (4) 8192/fs Notes: (1) The output signal is attenuated by -∞ during 1024 LRCK cycles (1024/fs). (2) Analog output corresponding to digital input have the group delay (GD). (3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB. (4) When the input data at both channels are continuously zeros for 8192 LRCK cycles, DZF pin goes to “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”. Figure 6. Soft mute and zero detection MS0015-E-01 2000/07 - 18 - ASAHI KASEI [AK4363] n Power-down The DAC is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same time. The internal register values are initialized by PDN “L”. This reset should always be done after power-up. Because some click noise occurs at the edge of PDN, the analog output should be muted externally if the click noise influences system application. PDN Internal State Normal Operation Power-down D/A In (Digital) Normal Operation “0” data GD D/A Out (Analog) (1) GD (3) (2) (3) (1) (4) Clock In Don’t care MCKI, LRCK, BICK DZF External MUTE (6) (5) Mute ON Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs are floating (Hi -Z) at the power-down mode. (3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input. (4) The external clocks (MCKI, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”). (5) Please mute the analog output externally if the click noise (3) influences system application. The timing example is shown in this figure. (6) DZF pin is “L” in the power-down mode (PDN = “L”). Figure 7. Power-down/up sequence example MS0015-E-01 2000/07 - 19 - ASAHI KASEI [AK4363] n Reset function When RSTN = “0”, the DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage and DZF pin goes to “H”. Figure 8 shows the sequence of reset by RSTN bit. RSTN bit 2~3/fs (6) Internal RSTN bit Internal State Normal Operation D/A In (Digital) “0” data (1) D/A Out (Analog) Normal Operation Digital Block Power-down GD GD (2) (3) (3) (1) (4) Clock In Don’t care MCKI,LRCK,BICK 2/fs(5) DZF Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs go to VCOM voltage. (3) Click noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0” data is input. (4) The external clocks (MCKI, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”). (5) DZF pin goes to “H” when the RSTN bit becomes “0”, and goes to “L” at 4~5/fs after RSTN bit becomes “1”. (6) There is a delay, 2~3/fs from RSTN bit “1” to the internal RSTN “1”. Figure 8. Reset sequence example MS0015-E-01 2000/07 - 20 - ASAHI KASEI [AK4363] n Serial Control Interface The AK4363 can control its functions via registers. Internal registers may be written by 2 types of control mode. The chip address is determined by the state of the CAD0 and CAD1 inputs. PDN = “L” initializes the registers to their default values. Writing “0” to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not be initialized. (1) 3-wire Serial Control Mode (I2C = “L”) Internal registers may be written to the 3 wire µP interface pins (CSN,CCLK and CDTI). The data on this interface consists of Chip address (2bits, CAD0/1), Read/Write (1bit, Fixed to “1”; Write only), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after a low-to-high transition of CSN. The clock speed of CCLK is 5MHz(max). The CSN and CCLK pins should be held to “H” except for access. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: Chip Address (C1=CAD1, C0=CAD0) R/W: Read/Write (Fixed to “1” : Write only) A4-A0: Register Address D7-D0: Control Data (2) I2C Bus Control Mode (I2C = “H”) Internal registers may be written to I 2C Bus interface pins: SCL & SDA. The data on this interface consists of Chip address (2bits, CAD0/1), Read/Write (1bit, Fixed to “0”; Write only), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of SCL and data is clocked out on the falling edge. Data can be written after a high-to-low transition of SDA when SCL is “H”(start condition), and is latched after a low-to-high transition of SDA when SCL is “H”(stop condition). The clock speed of SCL is 100kHz(max). The CSN pin should be connected to DVDD at I 2C Bus control mode. The AK4363 does not have a register address auto increment capability. R/W ACK SDA 0 0 1 0 0 C1 C0 ACK 0 0 0 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL Stop Start C1-C0: Chip Address (C1=CAD1, C0=CAD0) R/W: Read/Write (Fixed to “0” : Write only) A4-A0: Register Address D7-D0: Control Data ACK: Acknowledge * When the AK4363 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control register is inhibited. MS0015-E-01 2000/07 - 21 - ASAHI KASEI [AK4363] n Mapping of Program Registers Addr 00H 01H 02H 03H 04H Register Name Control 1 Control 2 Control 3 Lch ATT Rch ATT D7 0 FS1 PL3 ATT7 ATT7 D6 0 FS0 PL2 ATT6 ATT6 D5 0 DFS1 PL1 ATT5 ATT5 D4 EXT DFS0 PL0 ATT4 ATT4 D3 DIF2 CKS2 DEM1 ATT3 ATT3 D2 DIF1 CKS1 DEM0 ATT2 ATT2 D1 DIF0 CKS0 ATC ATT1 ATT1 D0 RSTN RSTN SMUTE ATT0 ATT0 Note: For addresses from 05H to 1FH, data should not be written. When PDN goes to “L”, the registers are initialized to their default values. When RSTN bit goes to “0”, the internal timing is reset, DZF pin goes to “H” and registers are not initialized to their default values. MS0015-E-01 2000/07 - 22 - ASAHI KASEI [AK4363] n Register Definitions Addr 00H Register Name Control 1 Default D7 0 0 D6 0 0 D5 0 0 D4 EXT 0 D3 DIF2 1 D2 DIF1 0 D1 DIF0 1 D0 RSTN 1 RSTN: Internal timing reset 0: Reset. DZF pin goes to “H” and registers are not initialized. 1: Normal operation When the states of DIF2-0,EXT,CKS2-0,DFS1-0 or FS1-0 changes, the AK4363 should be reset by PDN pin or RSTN bit. Some click noise may occur at that timing. DIF2-0: Audio data interface modes (See Table 4.) Initial: “000”, Mode 0 EXT: Master clock select 0: PLL mode (27MHz clock input) 1: External clock mode. Internal VCO is powered down. Addr 01H Register Name Control 2 Default D7 FS1 0 D6 FS0 0 D5 DFS1 0 D4 DFS0 0 D3 CKS2 0 D2 CKS1 0 D1 CKS0 0 D0 RSTN 1 RSTN: Internal timing reset 0: Reset. DZF pin goes to “H” and registers are not initialized. 1: Normal operation When the states of DIF2-0,EXT,CKS2-0,DFS1-0 or FS1-0 changes, the AK4363 should be reset by PDN pin or RSTN bit. Some click noise may occur at that timing. CKS2-0: Clock select (See Table 2.) Initial: “000” DFS1-0: Half/Normal/Double sampling modes (See Table 1,2), De-emphasis response (See Table 6.) Initial: “00” FS1-0: Sampling frequency modes (See Table 1.) Initial: “00” MS0015-E-01 2000/07 - 23 - ASAHI KASEI Addr 02H [AK4363] Register Name Control 3 Default D7 PL3 1 D6 PL2 0 D5 PL1 0 D4 PL0 1 D3 DEM1 0 D2 DEM0 1 D1 ATC 0 D0 SMUTE 0 SMUTE: Soft Mute Enable 0: Normal operation 1: DAC outputs soft-muted ATC: Attenuation Control 0: The attenuation data for each register is applied separately to left and right channels. 1: The attenuation data loaded in addr=03H is used for both left and right channels. DEM1-0: De-emphases response (See Table 5,6.) Initial: “01”, OFF PL3-0: Mixing mode PL3 PL2 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 STEREO: REVERSE: MONO: MUTE: PL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PL0 Lch Output Rch Output Note 0 MUTE MUTE MUTE 1 MUTE R 0 MUTE L 1 MUTE (L+R)/2 0 R MUTE 1 R R 0 R L REVERSE 1 R (L+R)/2 0 L MUTE 1 L R STEREO 0 L L 1 L (L+R)/2 0 (L+R)/2 MUTE 1 (L+R)/2 R 0 (L+R)/2 L 1 (L+R)/2 (L+R)/2 MONO Table 7. Programmable Output Format default Normal stereo output L/R Reverse output Monaural output Soft mute operation MS0015-E-01 2000/07 - 24 - ASAHI KASEI Addr 03H 04H Register Name Lch ATT Rch ATT Default [AK4363] D7 ATT7 ATT7 1 D6 ATT6 ATT6 1 D5 ATT5 ATT5 1 D4 ATT4 ATT4 1 D3 ATT3 ATT3 1 D2 ATT2 ATT2 1 D1 ATT1 ATT1 1 D0 ATT0 ATT0 1 Equation of attenuation level: ATT = 20 x Log10 (Binary level / 255) [dB] FFH: 0dB : 01H: -48.1dB 00H: Mute The transition between ATT values is same as soft mute operation. When current value is ATT1 and new value is set as ATT2, ATT1 gradually becomes ATT2 with same operation as soft mute. If new value is set as ATT3 before reaching ATT2, ATT value gradually becomes ATT3 from the way of transition. Cycle time of soft mute: Ts=1024/fs When PDN pin goes to “L”, the ATT values are set to 00H. The ATT values fade to FFH(0dB) during Ts after PDN pin returns to “H”. When RSTN bit goes to “0”, the ATT values are set to 00H. The ATT values fade to their current values after RSTN bit returns to “1”. Digital attenuator is independent of soft mute function. MS0015-E-01 2000/07 - 25 - ASAHI KASEI [AK4363] SYSTEM DESIGN Figure 9 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. Condition: AVDD=DVDD=5V(TTL mode), PLL mode, I2C mode, Chip Address = “00” Analog 5V 5 1 MCKO DZF 24 2 NC FLT 23 3 DVDD AVDD 22 4 DVSS AVSS 21 5 MCKI VCOM 20 6 BICK AOUTL 19 7 SDTI AOUTR 18 8 LRCK 5.1k (Note) 10u 0.1u 27MHz Decoder Reset + 9 0.22u 0.1u 10u AK4363 Top View PDN CAD1 17 CAD0 16 10 CSN I2C 15 11 SCL TTL 14 12 SDA TST 13 + + 0.1u 10u + 10u Lch MUTE Lch Out Rch MUTE Rch Out 220 27k + 10u 220 27k uP System Ground Analog Ground Figure 9. Typical Connection Diagram Note:This resister can be changed to 10kΩ if the distortion at low frequency (around 1kHz) is critical. However the distortion at high frequency degrades in this case. MS0015-E-01 2000/07 - 26 - ASAHI KASEI [AK4363] Digital Ground Analog Ground System Controller 1 MCKO DZF 24 2 NC FLT 23 3 DVDD AVDD 22 4 DVSS AVSS 21 5 MCKI VCOM 20 6 BICK AOUTL 19 7 SDTI AOUTR 18 8 LRCK CAD1 17 9 PDN CAD0 16 10 CSN I2C 15 11 SCL TTL 14 12 SDA TST 13 AK4363 Figure 10. Ground Layout Note: AVSS and DVSS must be connected to the same analog ground plane. 1. Grounding and Power Supply Decoupling The AK4363 requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually supplied from analog supply in system. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS and DVSS of the AK4363 must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be near to the AK4363 as possible, with the small value ceramic capacitors being the nearest. 2. Voltage Reference Inputs The differential voltage between AVDD and AVSS sets the analog output range. VCOM is AVDD/2 and normally connected to AVDD with a 0.1µF ceramic capacitor. An electrolytic capacitor 10µF parallel with a 0.1µF ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from these pins. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4363. 3. Analog Outputs The analog outputs are single-ended outputs and 0.6x(AVDD-AVSS) Vpp (typ) centered around the VCOM voltage. The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. The input data format is 2’s complement. The output voltage is a positive full scale for 7FFFFF(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is 0V for 000000H(@24bit). MS0015-E-01 2000/07 - 27 - ASAHI KASEI [AK4363] PACKAGE 24pin VSOP (Unit: mm) 1.25±0.2 *7.8±0.15 13 A 7.6±0.2 *5.6±0.2 24 12 1 0.22±0.1 0.65 0.15±0.05 0.1±0.1 0.5±0.2 Detail A Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° n Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate MS0015-E-01 2000/07 - 28 - ASAHI KASEI [AK4363] MARKING AKM AK4363VF AAXXXX Contents of AAXXXX AA: Lot# XXXX: Date Code IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0015-E-01 2000/07 - 29 -