ATMEL AT60142F-DD15M-E Rad hard 512k x 8 very low power cmos sram Datasheet

Features
• Operating Voltage: 3.3V
• Access Time:
•
•
•
•
•
•
•
•
•
•
•
– 15 ns for 3.3V biased only (AT60142F)
– 17 ns for 5V Tolerant (AT60142FT)
Very Low Power Consumption
– Active: 650 mW (Max) @ 15 ns, 540 mW (Max) @ 25 ns
– Standby: 3.5 mW (Typ)
Wide Temperature Range: -55 to +125°C
TTL-Compatible Inputs and Outputs
Asynchronous
Designed on 0.25 µm Radiation Hardened Process
No Single Event Latch Up below LET Threshold of 80 MeV/mg/cm2
Tested up to a Total Dose of 300 krads (Si) according to MIL-STD-883 Method 1019
500 Mils Wide FP36 Package
ESD Better than 4000V for the AT60142F
ESD Better than 2000V for the AT60142FT
Quality Grades: ESCC, QML-Q or V with smd 5962-05208
Description
The AT60142F/FT are very low power CMOS static RAM organized as 524 288 x 8
bits.
Atmel brings the solution to applications where fast computing is as mandatory as low
consumption, such as aerospace electronics, portable instruments, or embarked
systems.
Rad Hard
512K x 8
Very Low Power
CMOS SRAM
AT60142F
AT60142FT
Utilizing an array of six transistors (6T) memory cells, the AT60142F/FT combine an
extremely low standby supply current (Typical value = 1 mA) with a fast access time at
15 ns over the full military temperature range. The high stability of the 6T cell provides
excellent protection against soft errors due to noise.
The F version is biased at 3.3 V and is not 5V tolerant: it is available to 15 ns
specification.
The FT version is a variant allowing for 5V tolerance: it is available in 17 ns
specification.
The AT60142F/FT are processed according to the methods of the latest revision of the
MIL PRF 38535 or ESCC 9000.
It is produced on a radiation hardened 0.25 µm CMOS process.
Rev. 4408A–AERO–02/05
1
AT60142F/FT
Block Diagram
Pin Configuration
A0
A1
A2
A4
CS
I/O1
I/O2
Vcc
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
36 - pin -Flatpack - 500 Mils
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
Vcc
I/O6
I/O5
A14
A13
A12
A11
A10
N/C
2
4408A–AERO–02/05
Pin Description
Table 1. Pin Names
Name
Description
A0 - A18
Address Inputs
I/O1 - I/O8
Data Input/Output
CS
Chip Select
WE
Write Enable
OE
Output Enable
Vcc
Power Supply
GND
Ground
Table 2. Truth Table(1)
CS
WE
OE
Inputs/Outputs
Mode
H
X
X
Z
Deselect/
Power-down
L
H
L
Data Out
Read
L
L
X
Data In
Write
L
H
H
Z
Output Disable
Note:
3
1. L=low, H=high, X= H or H, Z=high impedance.
AT60142F/FT
4408A–AERO–02/05
AT60142F/FT
Electrical Characteristics
Absolute Maximum Ratings*
Supply Voltage to GND Potential:.........................-0.5V + 4.6V
*NOTE:
DC Input Voltage:.....................................GND -0.5V to 4.6V(1)
DC Output Voltage High Z State: ................GND -0.5V to 4.6V
Storage Temperature: ................................... -65°C to + 150°C
Output Current Into Outputs (Low): ............................... 20 mA
Stresses beyond those listed under "Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions
beyond those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Electro Statics Discharge Voltage(2):.. .........> 4000V (MIL STD
883D Method 3015.3)
Note:
1. 7V for FT version.
2. For AT60142F. It is better than 2000V for AT60142FT.
Military Operating Range
Operating Voltage
Operating Temperature
3.3 + 0.3V
-55°C to + 125°C
Military
Recommended DC Operating Conditions
Parameter
Note:
Description
Vcc
Supply voltage
GND
Ground
Min
Typ
Max
Unit
3
3.3
3.6
V
0.0
0.0
0.0
V
VIL
Input low voltage
GND - 0.3
0.0
0.8
V
VIH
Input high voltage
2.2
–
VCC + 0.3(1)
V
Min
Typ
Max
Unit
1. FT version: 5.5V in DC, 5.8V in transient conditions.
Capacitance
Parameter
Note:
Description
Cin(1)
Input low voltage
–
–
12
pF
Cout(1)
Output high voltage
–
–
12
pF
1. Guaranteed but not tested.
4
4408A–AERO–02/05
DC Parameters
Parameter
Description
Minimum
Typical
Maximum
Unit
IIX (1)
Input leakage current
-1
–
1
µA
IOZ(1)
Output leakage
current
-1
–
1
µA
IIH(2) at 5.5V
Input Leakage
Current
-1
–
10
µA
Output Leakage
Current
-1
–
10
µA
VOL(3)
Output low voltage
–
–
0.4
V
VOH(4)
Output high voltage
2.4
–
–
V
IOZH(2) at 5.5V
1.
GND < VIN < VCC, GND < VOUT < VCC Output Disabled.
2.
FT version only: VIN = 5.5V, VOUT = 5.5V, Output Disabled.
3.
VCC min. IOL = 8 mA.
4.
VCC min. IOH = -4 mA.
Consumption
1.
2.
TAVAV/TAVAW
Test Condition
AT60142F-15
AT60142FT-17
Unit
Value
Standby Supply
Current
–
2.5
2.5
mA
max
Standby Supply
Current
–
2
2
mA
max
ICCOP(3) Read
Dynamic
Operating
Current
15 ns
17 ns
25 ns
50 ns
1 µs
180
150
75
10
170
150
75
10
mA
max
ICCOP(4) Write
Dynamic
Operating
Current
15 ns
17 ns
25 ns
50 ns
1 µs
150
130
120
100
145
130
120
100
mA
max
Symbol
Description
ICCSB (1)
ICCSB1 (2)
CS >VIH
CS > VCC - 0.3V
3. F = 1/TAVAV, Iout = 0 mA, WE = OE = VIH, VIN = GND/VCC, VCC max.
4. F = 1/TAVAW, Iout = 0 mA, W = VIL, OE = VIH , VIN = GND/VCC, VCC max.
5
AT60142F/FT
4408A–AERO–02/05
AT60142F/FT
AC Characteristics
Temperature Range:................................................ -55 +125°C
Supply Voltage:........................................................ 3.3 +0.3V
Input Pulse Levels: .................................................. GND to 3.0V
Input Rise and Fall Times:....................................... 3ns (10 - 90%)
Input and Output Timing Reference Levels: ............ 1.5V
Output Loading IOL/IOH:............................................ See Figure 1
Figure 1. AC Test Loads Waveforms
Data Retention Mode
Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage
and supply current are guaranteed over temperature. The following rules insure data
retention:
1. During data retention chip select CS must be held high within VCC to VCC -0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation.
3. During power-up and power-down transitions CS and OE must be kept between
VCC + 0.3V and 70% of VCC.
4. The RAM can begin operation > tR ns after VCC reaches the minimum operation
voltages (3V).
Figure 2. Data Retention Timing
6
4408A–AERO–02/05
Data Retention Characteristics
Parameter
Description
Min
Typ TA = 25°C
Max
Unit
VCCDR
VCC for data
retention
2.0
–
–
V
tCDR
Chip deselect
to data
retention time
0.0
–
–
ns
tR
Operation
recovery time
tAVAV
–
–
ns
ICCDR (2)
Data retention
current
–
0.700
1.5
mA
1.
2.
7
(1)
TAVAV = Read cycle time.
CS = VCC, VIN = GND/VCC.
AT60142F/FT
4408A–AERO–02/05
AT60142F/FT
Write Cycle
Symbol
Parameter
AT60142F-15
AT60142FT-17
Unit
Value
TAVAW
Write cycle time
15
17
ns
min
TAVWL
Address set-up time
0
0
ns
min
TAVWH
Address valid to end of write
8
8
ns
min
TDVWH
Data set-up time
7
7
ns
min
TELWH
CS low to write end
12
12
ns
min
6
7
ns
max
(1)
TWLQZ
Write low to high Z
TWLWH
Write pulse width
8
8
ns
min
TWHAX
Address hold from end of write
0
0
ns
min
TWHDX
Data hold time
0
0
ns
min
TWHQX
Write high to low Z(1)
3
3
ns
min
Notes:
1. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Waveforms” on page 6.)
Read Cycle
Symbol
Parameter
AT60142F-15
AT60142FT-17
Unit
Value
TAVAV
Read cycle time
15
17
ns
min
TAVQV
Address access time
15
17
ns
max
TAVQX
Address valid to low Z
5
5
ns
min
TELQV
Chip-select access time
15
17
ns
max
TELQX
CS low to low Z(1)
5
5
ns
min
TEHQZ
CS high to high Z(1)
6
7
ns
max
TGLQV
Output Enable access time
6
8
ns
max
TGLQX
OE low to low Z(1)
2
2
ns
min
TGHQZ
OE high to high Z (1)
5
6
ns
max
Notes:
1. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Waveforms” on page 6.)
8
4408A–AERO–02/05
Figure 3. Write Cycle 1. WE Controlled, OE High During Write
E
Figure 4. Write Cycle 2. WE Controlled, OE Low
E
Figure 5. Write Cycle 3. CS Controlled(1)
E
Note:
9
The internal write time of the memory is defined by the overlap of CS Low and W LOW. Both signals must be activated to initiate
a write and either signal can terminate a write by going in active mode. The data input setup and hold timing should be referenced to the active edge of the signal that terminates the write.
Data out is high impedance if OE= VIH.
AT60142F/FT
4408A–AERO–02/05
AT60142F/FT
Figure 6. Read Cycle nb 1: Address Controlled (CS = OE = VIL, WE = VIH)
Figure 7. Read Cycle nb 2: Chip Select Controlled (WE = VIH)
10
4408A–AERO–02/05
Ordering Information
Part Number
AT60142F-DC15M-E
Temperature Range
Speed
Package
Flow
25°C
15 ns/3.3V
FP36.5
Engineering Samples
5962-0520802QXC
-55° to +125°C
15 ns/3.3V
FP36.5
QML Q
5962-0520802VXC
-55° to +125°C
15 ns/3.3V
FP36.5
QML V
5962R0520802VXC
-55° to +125°C
15 ns/3.3V
FP36.5
QML V RHA
-55° to +125°C
15 ns/3.3V
FP36.5
ESCC
AT60142F-DC15SSB
(1)
AT60142F-DD15M-E
AT60142F-DD15MMQ(1) (2)
(1) (2)
AT60142F-DD15SMV
AT60142FT-DC17M-E
25°C
15 ns/3.3V
Die
Engineering Samples
-55° to +125°C
15 ns/3.3V
Die
QML Q
-55° to +125°C
15 ns/3.3V
Die
QML V
25°C
17 ns/5V tol.
FP36.5
Engineering Samples
5962-0520801QXC
-55° to +125°C
17 ns/5V tol.
FP36.5
QML Q
5962-0520801VXC
-55° to +125°C
17 ns/5V tol.
FP36.5
QML V
5962R0520801VXC
-55° to +125°C
17 ns/5V tol.
FP36.5
QML V RHA
AT60142FT-DC17SSB
-55° to +125°C
17 ns/5V tol.
FP36.5
ESCC
25°C
17 ns/5V tol.
Die
Engineering Samples
-55° to +125°C
17 ns/5V tol.
Die
QML Q
-55° to +125°C
17 ns/5V tol.
Die
QML V
AT60142FT-DD17M-E(1)
AT60142FT-DD17MMQ(1) (2)
(1) (2)
AT60142FT-DD17SMV
Note:
1. Contact Atmel for availability.
2. Will be replaced by SMD part number when available.
11
AT60142F/FT
4408A–AERO–02/05
AT60142F/FT
Package Drawings
36-lead Flat Pack (500 Mils)
12
4408A–AERO–02/05
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4408A–AERO–02/05
/xM
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