ACCUTEK MICROCIRCUIT CORPORATION AKCM6432T 512KB SECONDARY CACHE MODULE FOR THE PENTIUM CPU AND 82430 PCISETS FEATURES • • • • • • 64K x 64 Configuration 16K x 11 Tag SRAM Field Low profile card edge module with 160 leads Separate 5V and 3.3V power supplies Multiple GND pins and decoupling capacitors for maximum noise immunity. Synchronous SRAM with Burst Counter DESCRIPTION The AKCM6432T Module uses four 32K x 32 pipelined burst RAMs in surface mount packages mounted on a multi-layer FR4 board. In addition, it uses two 5V 8 -bit wide SRAMs to achieve an eleven bit tag field. Four PD (presence detect) input pins allow the system to determine the particular cache configuration. The low profile card edge package allows 160 single leads to be placed on a package 4.35” long, a maximum of 0.350” thick and a maximum of 1.14” tall. All inputs and outputs are TLLcompatible, and operate from separate 5V (+/- 5%) and 3.3V (+10/-5%) power supplies. Multiple GND pins and on-board decoupling capacitors ensure maximum protection from noise. ACCUTEK 5 New Pasture Road • Newburyport, MA 01950-4040 • Phone: 978-465-6200 • Fax: 978-462-3396 • www.accutekmicro.com PINOUT - TOP VIEW GND TIO1 TIO7 TIO5 TIO3 TIO9 VCC5 TIO10 CADV GND COE CWE5 CWE7 CWE1 VCC5 CWE3 NC NC GND NC A4 A6 A8 A10 NC A17 GND A9 A14 A15 NC PD0 PD2 LBO GND CLK0 GND D63 NC D61 D59 D57 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 GND TIO0 TIO2 TIO6 TIO4 TIO8 NC TWE CADSC GND CWE4 CWE6 CWE0 CWE2 VCC3 CS GW BWE GND A3 A7 A5 A11 A16 VCC3 A18 GND A12 A13 CADSP NC NC PD1 PD3 GND CLK1 GND D62 VCC3 D60 D58 D56 GND D55 D53 D51 D49 GND D47 D45 D43 NC D41 D39 D37 GND D35 D33 D31 NC D29 D27 D25 GND D23 D21 D19 NC D17 D15 D13 GND D11 D9 D7 NC D5 D3 D1 GND 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 GND D54 D52 D50 D48 GND D46 D44 D42 VCC3 D40 D38 D36 GND D34 D32 D30 VCC3 D28 D26 D24 GND D22 D20 D18 VCC3 D16 D14 D12 GND D10 D8 D6 VCC3 D4 D2 D0 GND PIN NAMES A5 - A18 A3 - A4 D0 - D63 TIO0 - TIO10 OE# TWE# WE#0 - WE#7 CS# CADSc# CADSp# CADV# GW# BWE# LBO# CLK0 - CLK1 PD0 - PD4 NC GND Vcc5 Vcc3 Address Inputs Address Inputs (Burst SRAMs only) Cache Data Inputs/Outputs Tag Inputs/Outputs Cache Data Output Enab led Input Tag Write Enable Input Cache Data Write Enable Inputs Cache Data Chip Enable Input (Burst only) Cache Address Status Input (Burst SRAMs only) Processor Address Status Input (Burst only) Burst Address Advance (Burst SRAMs only) Global Write Input (Burst SRAMS only) Byte Write Enable Input (Burst SRAMS only) Linear Burst Order Clock Inputs (Burst SRAMS only) Presence Detect Pins No Connect Ground 5 Volt Power Supply 3.3 Volt Power Supply PRESENCE DETECT TABLE PD4 PD3 PD2 PD1 NC GND NC GND NC NC NC GND Module NC No Cache Present GND 512KB Pipelined Burst PD0 RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Min. Typ. Max. Unit Vcc3 Vcc5 GND VIH VIL Supply Voltage Supply Voltage Supply Voltage Input High Voltage Input Low Voltage 3.146 4.75 0 2.2 -0.5(1) 3.3 5 0 - 3.6 5.25 0 Vcc + 0.3 0.8 V V V V V NOTE: 1. VIL = -1.0V for pulse width less than 5ns, once per cycle RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Power Plane Ambient Temperature 0V 3.3V +10/-5% 0 0 0V 5.0V +/- 5% Value Unit -0.5 to Vcc + 0.5 -0.5 to +4.6 V 0 C to +70 C Vcc5 VCC 0 0 C to +70 C Vcc3 GND 0 ABSOLUTE MAXIMUM RATINGS Symbol VTERM VTERM for Vcc3 TA TBIAS TSTG IOUT Rating Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND (Vcc terminals only) Operating Temperature Temperature Under Bias Storage Temperature DC Output Current V 0 to +70 0 C -10 to +85 0 C -55 to +125 50 0 C mA SRAM ACCESS TIMES Module Speed Asych Burst (1) Tag 66MHZ 15nS 8.0nS 15nS NOTE: 1. Burst SRAMS are measured by Clock to Data Out (tCD) CAPACITANCE (1,2) 0 (TA = +25 C, f = 1.0 MHZ) Symbol CIN1 CIN3 CIN4 CI/O Parameter(1 Input Capacitance (Address) Input Capacitance (OE#) Input Capacitance (WE#, TWE#) I/O Capacitance Condition Value Unit VIN = 0V 30 pF VIN = 0V 25 pF VIN = 0V 8 pF VOUT = 0V 20 pF NOTES: 1. These parameters are guaranteed by design but not tested 2. These parameters are maximum values DC ELECTRICAL CHARACTERISTICS (Vcc5 = 5.0v +/- 5%, Vcc = 3.3V + 10/-5%, TA = 00c TO 700c) Symbol ILI ILI ILO VOL VOH ICC3 ICC5 ISB3 ISB31 Parameter Input Leakage Current (Address) Input Leakage Current (Data and Control) Output Leakage Curent Output Low Voltage Output High Voltage Operating 3.3V Power Supply Curent Operating 5V Power Supply Current Standby 3.3V Power Supply Current Full Standby 3.3V Power Supply Current Min. Max. Unit Vcc = Max, VIN = GND to Vcc Test Condition - 50 µA Vcc = Max, VIN = GND to Vcc - 20 µA 2.4 - 20 0.4 620 µA V V mA - 180 mA - 120 mA - 60 mA VOUT = 0V to Vcc, Vcc = Max IOL = 8mA, Vcc = Min IOH = -4mA, Vcc = Min Vcc3 = Max, CE = VIL f = fMAX, Outputs Open Vcc5 = Max, CE = VIL f = fMAX, Outputs Open Vcc3 = Max, CE = VIH f = fMAX, Outputs Open Vcc3 = Max, CE = Vcc - 0.2V, f = 0, VIN = 0.2V or VIN = Vcc - 0.2V, Outputs Open REV1 1.130" 1 6 0 0.500" A K C M 6 4 3 2 T 4.340" 0.110" 0.074" 0.300" ACCUTEK MICROCIRCUIT CORP. NEWBURYPORT, MA 01950 CONTRACT NO. APPROVALS DRAWN DWG GN 11/21/07SIZE CHECKED ISSUED DATE A SCALE COAST MODULE FSCM NO. DWG NO. REV. AKCM6432T SHEET 1 1 of 2