ams AS8506-BQFM Battery cell monitor and balancer ic Datasheet

AS8506
Battery Cell Monitor and Balancer IC
General Description
The AS8506 is a battery management IC dedicated to support
cell voltage measurement, monitoring, cell balancing and
temperature measurement functions in Li-Ion battery stacks for
electric/hybrid electric vehicles or in other
industrial/consumer/PV battery applications.
There are two device versions available:
• The AS8506 is AEC - Q100 automotive qualified.
• The AS8506C is for industrial and other applications.
Ambient temperature range for both products is from -40°C to
+85°C.
It features cell voltage diagnosis with externally adjustable
upper and lower cell voltage limits, fast cell voltage capture on
request through 12-bit SAR ADC, passive cell balancing by
simultaneous comparison of actual cell voltages with a
reference cell voltage and temperature measurement on two
external NTC sensors through 12-bit ADC.
Cells that are above reference will sequentially be discharged
through integrated switches and one external resistor.
There is also an active balancing option through factory setting
to sequentially charge cells which are below reference from an
external DC-DC Flyback converter and an integrated low side
driver.
The device can be used flexibly for battery stacks up to 7 cells
with a minimum stack voltage of 6V and a maximum stack
voltage of 32V.
It can be chained to support battery packs of virtually any
number of cells in synchronized mode through chained clock
and trigger signal.
The status of the battery stack is communicated to outside
world through OR’d voltage_ok signal and balance ready signal.
For further understanding in regards to the contents of the
datasheet, please refer to the Reference Guide located at the end
of the document.
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 1
General Description
Key Benefits & Features
The benefits and features of AS8506, Battery Cell Monitor and
Balancer IC are listed below:
Figure 1:
Added Value of using AS8506
Benefits
Features
Reduce filter / synchronization effort. Acquired data
have same time stamp to inherently generate
accurate comparison results independent from load
transients.
Simultaneous cell voltage capture for safe operating
area (SOA) monitoring and balancing.
Strongly reduces data communication and data
processing and thereby improves EMC robustness.
Autonomous balancing and SOA monitoring.
To compensate accumulative charge differences
only. This mitigates cases of occasional wrong
balance decisions due to flat OCV characteristic or
mismatch in cell temperature
Autonomous passive balancing in the 100 mA range
Intrinsic inter module balancing through charge
redistribution, efficiency improvement in case of
leakage path due to defect induced leakage in
particular cells.
Option for active charge balancing with very few
external components.
For OCV capture, cell impedance calculation,
diagnosis
Absolute cell voltage read out, read out of two
temperature sensors.
Small form factor, low BOM
40-pin MLF (6x6) package, very low number of external
components.
Applications
The applications of AS8506 include:
• The AS8506 is ideal for simultaneous cell monitoring and
cell balancing in stacked energy storage systems. Current
levels in the 100 mA range enables to compensate
accumulative SOC mismatch over the entire cell pack.
• Typical applications are
- Li-Ion batteries up to 200 cells for electric vehicles,
- Energy storage systems to buffer energy from PV
panels or for emergency power supplies,
- Battery management for e-scooters and e-bikes,
- Li-Ion or ultra capacitor based board net battery
management systems in the 12V/48V domain, for
handheld applications like power tools, laptops and
in general all Li-Ion battery powered systems.
AS8506 – 2
ams Datasheet, Confidential:2013-Sep [1-00]
General Description
Block Diagram
The functional blocks of this device for reference are
shown below:
VCELL7
Cnt7L
comp7
DAC
VCELL7
Cnt5H
V5V_IN
WAKE_OUT
FD_IN
High
Precision
Reference
Reference &
Threshold
Generation Circuit
AS8506
VCELL5
LDO
Pre-regulator
Cnt1
Cnt2
Cnt3
Cnt4
Cnt5
Cnt7
Cnt6L
Cnt6
Cnt6H
BD_IN
Stack signals
Balance and VREF_H
Switches Level Shifters
VCELL6
CVT_NOK_IN
Level Shifters for Stack Communication / Status Signals
5V
EXT_RES_CTL
C_out7
C_out6
Temperature
Sensor /
Switch
Capacitor
Circuit
comp5
VCELL4
Cnt3H
Cnt3L
VCELL3
VCELL2
Level Shifters
VCELL3
Cnt2H
comp4
comp3
C_out5
C_out4
C_out3
C_out2
comp1
Cnt1L
C_out1
ams Datasheet, Confidential:2013-Sep [1-00]
NC_T
NC
GND
TSECH
TSECL
C-GND
FD_OUT
VCELL1
Cnt1H
RC Oscillator &
PWM Driver
comp2
VCELL1
Zero Cross
Detection Circuit
Stack
signals
CLK_IN
VCELL2
Cnt2L
TEMP_IN1
TEMP_IN2
VCELL[7:1]
FSM,
Digital Registers,
OTP Logic
TRIG_IN
CS
SCLK
SDO
SDI
BD_OUT
VCELL5
Cnt4L
MS_SL
Cnt4H
CVT_NOK_OUT
comp6
Multiplexer & SAR Logic
VCELL4
DAC_IN[11:0]
VCELL6
REF_T
CELL_THU
CELL_THL
VREF_IN
Over-temperature
Monitor
Cnt5L
V5V
WAKE_IN
Cnt7H
CLK_OUT
TRIG_OUT
VSUP
VREF_H
Figure 2:
AS8506 Block Diagram
AS8506 – 3
Pin Assignment
Pin Assignment
AS8506 – 4
VREF_H
MS_SL
VSUP
TRIG_OUT
CLK_OUT
CVT_NOK_IN
BD_IN
FD_IN
WAKE_OUT
V5V_IN
40
39
38
37
36
35
34
33
32
31
Figure 3:
Pin Diagram of AS8506
TSECH
1
30
V5V
TSECL
2
29
REF_T
VCELL7
3
28
TEMP_IN1
27
TEMP_IN2
AS8506
VCELL6
4
VCELL5
5
26
CELL_THL
VCELL4
6
25
CELL_THU
VCELL3
7
24
CS
23
SCLK
MLF 6x6
GND
(Exposed pad)
15
16
17
18
19
20
CVT_NOK_OUT
BD_OUT
FD_OUT
WAKE_IN
NC_T
SDO
CLK_IN
21
14
10
TRIG_IN
C-GND
13
SDI
GND
22
12
9
VREF_IN
VCELL1
11
8
NC
VCELL2
ams Datasheet, Confidential:2013-Sep [1-00]
Pi n A s s i g n m e n t
Figure 4:
Pin Description
Pin Number
Pin Name
1
TSECH
Flyback converter transformer secondary high side
2
TSECL
Flyback converter transformer secondary low side
3
VCELL7
Battery cell 7 high level pin
4
VCELL6
Battery cell 6 high level pin
5
VCELL5
6
VCELL4
Battery cell 4 high level pin
7
VCELL3
Battery cell 3 high level pin
8
VCELL2
Battery cell 2 high level pin
9
VCELL1
Battery cell 1 high level pin
10
C-GND
11
NC
12
VREF_IN
Analog input /
output
Cell voltage reference value (cell target voltage of
battery)
13
GND
Power supply
input
Ground to the IC
14
Pin Type
Analog input /
output
Power supply
input
16
Battery cell 5 high level pin
Battery cell 1 low level pin
Not connected
TRIG_IN
Digital input
15
Description
This pin triggers the cell balancing in the device.
Short pulse is for receiving status and continuous
‘High’ for cell balancing. It also acts as a data line
during 3-wire communication.
CLK_IN
Clock input pin in the Slave device. This pin also acts
as a clock during 3-wire communication. Scan clock
in scan mode.
CVT_NOK_OUT
This pin alerts when the cell voltage or the
device/cell temperature is not within limits. During
3-wire communication, the CRC error is indicated on
this pin. The internal device cell voltage or
temperature status is ORed with CVT_NOK_IN on
this pin.
Digital output
17
BD_OUT
The ‘device internal balance done’ and ‘balance done
from above device’ are ANDed on this pin. This pin in
Master device indicates the complete system
balance done. During address allocation process,
this pin will be ‘High’ if BD_IN is ‘High’.
18
FD_OUT
Flyback converter gate/opto coupler drive (pad is
push-pull type) can drive up to 12mA.
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 5
Pin Assignment
Pin Number
Pin Name
Pin Type
Description
19
WAKE_IN
Digital input
with pull-up
The wake pulse on this pin brings the IC into
NORMAL mode. This pin has a pull-up resistor to the
internal regulator. Should be driven with an open
drain or external NMOS.
20
NC_T
Analog input /
output
Not connected. Only used in Test mode.
21
SDO
Digital output
SPI data out
22
SDI
SPI data in
Digital input
23
SCLK
SPI clock
24
CS
25
CELL_THU
Cell voltage upper threshold
26
CELL_THL
Cell voltage lower threshold
27
TEMP_IN2
Temperature input2 to the IC (NTC input; if NTC is not
connected, then should be connected to GND with
1K resistor).
Digital input
with pull-up
Analog input /
output
SPI chip select
28
TEMP_IN1
Temperature input1 to the IC (NTC input; if NTC is not
connected, then should be connected to GND with
1K resistor).
29
REF_T
Supply to temperature sensor (Reference voltage to
DAC and ADC).
30
V5V
31
V5V_IN
32
WAKE_OUT
Digital output
open drain
Open drain o/p on the VSUP+5V domain. WAKE_IN
information will be transmitted to top device.
33
FD_IN
Digital input
Flyback converter gate drive input in daisy chain
connection. (If FD_IN is ‘high’ then FD_OUT will be
PWM o/p in balance mode).
34
Power supply
input
BD_IN
Digital input
with pull-down
35
AS8506 – 6
CVT_NOK_IN
LDO 5V output.
Supply to the bottom IC from the cascaded top IC.
In cell stack system, the device gets balance done
status of above device. During address allocation
process if this pin is ‘High’, then the device address is
decremented by ‘1’.
Indicates cell voltage or temperature status of above
device.
ams Datasheet, Confidential:2013-Sep [1-00]
Pi n A s s i g n m e n t
Pin Number
Pin Name
36
CLK_OUT
Pin Type
This pin propagates the clock to next device in the
stack system. In case of Master device internal RC
clock is transmitted on this pin to Slave device.
Digital output
37
TRIG_OUT
38
VSUP
Description
This pin transmits the data fromTRIG_IN for balance
and measurement phase. This pin is also used for
propagating the data information to next device in
stack system in SPI3.
Power supply
input
Supply to the IC.
39
MS_SL
Digital input
This pin informs the device whether it should act as
the Master or Slave. If this pin is connected to GND,
then device will act as Master. If this pin is connected
to VSUP then device will act as Slave.
40
VREF_H
Analog input /
output
High sides PMOS switch for external resistive divider.
Input to VREF_IN can be taken from external
resistive divider in one of the options.
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 7
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. These are
stress ratings only. Functional operation of the device at these
or any other conditions beyond those indicated under
“Operating Conditions” on page 10 is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
Absolute Maximum Ratings
Figure 5:
Absolute Maximum Ratings
Symbol
Parameter
Min
Typ
Max
Units
Comments
Electrical Parameters
VVSUP
Voltage at positive
supply pin
-0.3
42
V
VSUP pin
VGND
Voltage at negative
supply pin
-0.3
0
V
GND, C-GND; Reference
potential
VV5V_IN
Voltage at high side
supply
-0.3
VSUP + 0.3
V
MS_SL,VREF_H, TSECH
and TSECL
VSUP +
V5V_IN
High side supply
from top device
VSUP 0.3
VSUP + 5.5
V
TRIG_OUT, CLK_OUT,
CVT_NOK_IN, FD_IN,
BD_IN, WAKE_OUT
-0.3
7
V
V5V pin
VV5V
Voltage at on LDO
o/p pins
VESD
Voltage on 5V pins
-0.3
V5V+0.3
V
All pins expect VSUP,
VCELL1, VCELL2, VCELL3,
VCELL4, VCELL5, VCELL6,
VCELL7, MS_SL, WAKE_IN
VCELL1
to
VCELL7
Voltage on pins
VCELL1, VCELL2,
VCELL3, VCELL4,
VCELL5, VCELL6,
VCELL7
-0.3
7
V
Applied cell voltages
Latch-up Immunity
-100
+100
mA
ISCR
AS8506 – 8
AEC - Q100-004
ams Datasheet, Confidential:2013-Sep [1-00]
Absolute Maximum Ratings
Symbol
Parameter
Min
Typ
Max
Units
Comments
Electrostatic Discharge
VSUP, VREF_IN, SDI, SDO,
CS, SCLK, CELL_THU,
CELL_THL, TEMP_IN1,
TEMP_IN2, REF_T, V5V,
V5V_IN, MS_SL, VREF_H,
NC_T
±2
ESD
Electrostatic
discharge voltage
AEC - Q100-002
HBM standard (1)
kV
±4
GND, C-GND, CELL1 –
CELL7 (Cell-voltage pins,),
TSECH, TSECL, TRIG_IN,
TRIG_OUT, CLK_IN,
CLK_OUT, CVT_NOK_IN,
CVT_NOK_OUT,
WAKE_IN, WAKE_OUT,
FD_IN, FD_OUT, BD_IN
and BD_OUT
Continuous Power Dissipation
Ptot
Maximum power
dissipation
1
W
Temperature Ranges and Storage Conditions
Tstg
Storage temperature
Rthj_36
Thermal resistance
package
TBODY
Package body
temperature
MSL
-55
Moisture Sensitive
Level
150
30
ºC
ºC/W
260
ºC
Norm: IPC/JEDEC
J-STD-020 (2)
3
Note(s) and/or Footnote(s):
1. Human body model: R = 1.5kΩ; C = 100pF.
2. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity
Classification for Non-hermetic Solid State Surface Mount Devices”.
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 9
Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
All defined tolerances for external components in this
specification need to be assured over the whole operation
conditions range and also over lifetime.
Typical Operating
Characteristics
Figure 6:
Operating Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Note
VSUP
Positive supply
voltage
6
32
V
Normal operating condition
VSS
Negative supply
voltage
-0.3
0
V
With reference to all the
voltages
TAMB
Ambient temperature
-40
85
ºC
Maximum junction
temperature (TJ ) 115ºC
ISUPP, nom
ISUPP, sleep
AS8506 – 10
Supply current,
NORMAL mode
2
3
6
mA
VSUP=32V, in NORMAL mode
Supply current,
NORMAL mode, With
External Components
15
20
40
mA
VSUP=32V, in the balancing
phase with stack connection
(50% PWM duty cycle)
Supply current, SLEEP
mode
10
17
35
μA
ams Datasheet, Confidential:2013-Sep [1-00]
Electrical Characteristics
Electrical Characteristics
Device Level Specifications
-40°C < Tj < 115°C.
Figure 7:
Device Level Specifications
Symbol
Vcell_in
Parameter
Cell Input voltage
measurement
Min
Typ
1.8
Max
Unit
Note
4.5
ADC/DAC
ADC/DAC Reference
±7
DAC_error
Error of the DAC
2
mV
0.1% error because of
the DAC/Guaranteed by
design
Error because of the
comparator resolution
1
mV
Guaranteed by design
mV
Typical value is from the
lab evaluation data.
Maximum value is from
the test data.
ms
After Initialization, the
system will go to sleep
mode and waits for
wake signal.
ms
After wake signal,
device enters into wait
mode and stays for two
sec for TRIG_IN signal, if
no TRIG_IN event
occurs, device goes to
sleep mode.
ms
At10KHz clock time
Com_off
Sign_path_accuracy
T INITIALIZATION
T WAKE-UP
Tmeas
Signal path accuracy
Initialization time
Cell voltage and
Temperature
measurement time
±15
50
Wake up time from the
Wake signal to system
wait mode
75
16
mV
13.6
Tspi3_read5k
Tspi3_read20k
±5
±15
SPI3 read time for
single channel
measurement
Tspi3_read40k
ams Datasheet, Confidential:2013-Sep [1-00]
3.4
1.7
At 5KHz clock time
ms
At 20KHz clock time
At 40KHz clock time
AS8506 – 11
Electrical Characteristics
Low Dropout Regulator (5V Output LDO)
-40ºC < TJ < 115ºC; all voltages are with respect to ground (GND);
positive current flows into the pin, NORMAL operating mode, if
not otherwise mentioned. The LDO block is a linear voltage
regulator, which provides a regulated 5V.
Figure 8:
LDO Parameters
Symbol
Parameter
Min
Typ
Max
Unit
VSUP
Input supply voltage
6
12
32
V
V5V
Output voltage range
4.75
5.0
5.25
V
ILOAD
Load Current
50
mA
250
mA
ICC_SH
Output short circuit
current
85
PSRR
dB
f=1MHz / No production
test
35
CL1
2.2
10
μF
1
10
Ω
100
220
nF
0.02
1
Ω
LDO output Capacitor 1
ESR1
CL2
LDO output Capacitor 2
ESR2
NORMAL mode
f=1kHz / No production
test
60
PSRR
Note
Electrolytic
Ceramic
Note(s) and/or Footnote(s):
1. In NORMAL mode, maximum load current will be 50mA. After internal thermal shutdown, current limit is 20mA.
2. The LDO is disabled in SLEEP mode.
AS8506 – 12
ams Datasheet, Confidential:2013-Sep [1-00]
Electrical Characteristics
High-precision Bandgap Reference
-40ºC < TJ < 115ºC; all voltages are with respect to ground
(GND).
Figure 9:
Bandgap Reference Parameters
Symbol
BG_Out
BG_out_Tvar
Parameter
Reference output after
trim
Min
Typ
Max
Unit
1.2
1.235
1.27
V
±2.5
±4
mV
Reference variation with
respect to Temperature
PSRR1K
PSRR at 1KHz
20
dB
PSRRDC
PSRR at DC
80
dB
Note
After temperature trim
After trim on the absolute
No production test
Note: This bandgap output is the reference for the V5V (LDO) regulator.
Digital to Analog Converter
-40ºC < TJ < 115ºC; all voltages are with respect to ground
(GND).
Figure 10:
Digital to Analog Converter
Symbol
VSUP_DAC
VINREF
Parameter
Min
Typ
Max
Unit
Input supply voltage
4.75
5
5.25
V
LDO output as supply
Input reference voltage
4.485
4.5
4.515
V
After absolute trim
DIN
Resolution
12
bits
FDAC
Update rate
10
KHz
TSETT_DAC
Settling time
50
μs
DACINL
INL
±4
LSB
DACDNL
DNL
±0.5
LSB
Note
Guaranteed by design
No production test
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 13
Electrical Characteristics
Analog to Digital Converter
-40ºC < TJ < 115ºC; all voltages are with respect to ground
(GND).
Figure 11:
Analog to Digital Converter
Symbol
Min
Typ
Max
Unit
Input supply voltage
4.75
5
5.25
V
LDO output as supply
VINREF
Input reference voltage
4.485
4.5
4.515
V
After absolute trim
DOUT
Resolution
12
bits
Measurement time per
channel
1.4
ms
ADCINL
INL
±4
LSB
No production test.
ADCDNL
DNL
±2
LSB
No production test.
VSUP
TMEAS_ADC
Parameter
Note
Pre-Regulator
This Pre_reg is an internal regulator which provides supply to
digital and a few analog blocks..
-40ºC < TJ < 115ºC; all voltages are with respect to ground
(GND).
Figure 12:
Pre-reg Parameters
Symbol
Parameter
Min
Typ
Max
Unit
6
12
32
V
VSUP
Input supply voltage
P5V
Prereg_output voltage
range
4.3
5.0
5.5
V
3V3
3.3V_output voltage
range
2.8
3.3
3.6
V
AS8506 – 14
Note
ams Datasheet, Confidential:2013-Sep [1-00]
Electrical Characteristics
PWM Driver
40ºC < TJ < 115ºC; all voltages are with respect to ground (GND).
Figure 13:
PWM Driver
Symbol
Min
Typ
Max
Unit
Output voltage
4.5
5
5.5
V
Frequency of PWM
25
100
200
KHz
22
25
28
%
12
15
18
%
17
20
23
%
27
30
33
%
30
35
38
%
37
40
43
%
42
45
48
%
47
50
53
%
Duty cycle error
7
12
20
%
trpwm
Rise time
30
50
80
ns
tfpwm
Fall time
30
50
80
ns
CMOS load mode,
Optocoupler load mode
Guaranteed by design
Driver strength
10
12
mA
Optocoupler load mode
Driver switch load capacitance
60
100
pF
V5V
FPWM
FDuty
Fduty_error
Idriveopto
Cloadfd_out
Parameter
Duty cycle
ams Datasheet, Confidential:2013-Sep [1-00]
Note
CMOS load mode,
Optocoupler load mode
AS8506 – 15
Electrical Characteristics
PWM Oscillator
-40ºC < TJ < 115ºC; all voltages are with respect to ground
(GND).
Figure 14:
PWM Oscillator
Symbol
Parameter
fOSC
Frequency
fOSC_ACC
Accuracy
Min
90
Typ
100
Max
Unit
110
Note
• After the frequency
trim.
• Programmable
frequency options for
25KHz, 50KHz and
200KHz are available.
kHz
±15
%
Oscillator for Digital Circuit
-40ºC < TJ < 115ºC; all voltages are with respect to ground
(GND).
Figure 15:
Oscillator for Digital Circuit
Symbol
Parameter
Min
Typ
Max
Unit
fOSC-DIG
Frequency
9
10
11
kHz
fOSC_ACC
Accuracy
AS8506 – 16
±15
Note
Oscillator for Digital circuit
%
ams Datasheet, Confidential:2013-Sep [1-00]
Electrical Characteristics
External Temperature Thresholds
-40°C < TJ < 115°C; all voltages are with respect to ground (GND).
Figure 16:
External Temperature Thresholds
Symbol
Parameter
Min
Typ
Max
Code 0000
3.084
3.165
3.238
Code 0001
3.148
3.231
3.306
Code 0010
3.213
3.297
3.373
Code 0011
3.277
3.363
3.441
Code 0100
3.341
3.429
3.508
Code 0101
3.406
3.495
3.576
Code 0110
3.470
3.561
3.643
Code 0111
3.534
3.627
3.711
Ref_ext_warn/sutdown
Unit
V
Code 1000
3.599
3.693
3.779
Code 1001
3.663
3.759
3.846
Code 1010
3.727
3.825
3.914
Code 0011
3.792
3.891
3.981
Code 0100
3.856
3.957
4.049
Code 0101
3.920
4.023
4.116
Code 0110
3.984
4.089
4.184
Code 0111
4.049
4.155
4.25
ams Datasheet, Confidential:2013-Sep [1-00]
Note
16 reference
thresholds are with a
step of 66mV.
AS8506 – 17
Electrical Characteristics
Ron of the Shuttle Switches (Internal Switch for
Charging/Discharging)
-40°C < TJ < 115°C.
Figure 17:
Ron of the Shuttle Switches
Symbol
Ron_shut
Parameter
Min
Typ
Shuttle switch ON resistance
5
Max
20
Unit
Ω
Note
The maximum
charging/discharging
current limit through
shuttle switch is 100mA.
Only for Cell1 maximum
charging/discharging
current is limited to 30mA
less than 2V of cell voltage
at 115 junction of cell
voltage.
Over-Temperature Measurement
Figure 18:
OTM Parameters
Symbol
Parameter
Min
Typ
Max
Unit
Tjshut
Shut down temperature
115
135
145
ºC
Junction temperature for
Shutdown
Tjwarn
Warning temperature
100
125
140
ºC
Junction temperature for
Warning
Tjrecv
Recovery temperature
100
115
130
ºC
Junction temperature for
Recovery
AS8506 – 18
Note
ams Datasheet, Confidential:2013-Sep [1-00]
Electrical Characteristics
Weak Cell Detection (Voltage Comparator)
Figure 19:
Weak Cell Detection
Symbol
Parameter
Min
Typ
Max
Unit
3.6
4.5
V
100
mV
VCELL
Supply voltage
-0.3
VLOW
Low voltage detection
-100
Note
2
4
Tl_spike
Minimum input spike filter
No production test.
Programmable option.
μs
6
8
Power on Voltage Detection
Figure 20:
Power on Voltage Detection
Symbol
Parameter
Min
Typ
Max
Unit
Note
VSUP_POR
VSUP Power-on-Reset
threshold ON
5.2
5.5
5.8
V
Rising edge of VSUP
VSUP_RESET
VSUP Power-on-Reset
threshold OFF
4.6
4.85
5.1
V
Master reset for device
V5V_IN_POR
V5V_IN Power-on-Reset
threshold ON
3.8
4.45
4.8
V
V5V_IN_RESET
V5V_IN Power-on-Reset
threshold OFF
3.6
4.1
4.5
V
V5V_POR
V5V Power-on-Reset
threshold ON
4.1
4.5
4.7
V
Rising edge of V5V
V5V_RESET
V5V Power-on-Reset
threshold OFF
3.8
4.1
4.3
V
Falling edge of V5V
ams Datasheet, Confidential:2013-Sep [1-00]
Voltages are with respect to
VSUP measure as pass fail
test
AS8506 – 19
Electrical Characteristics
Electrical Characteristics for Digital Inputs and
Outputs
All pull-up, pull-downs have been implemented with active
devices.
Figure 21:
Digital Inputs and Outputs
Port Type
Symbol
Parameter
Min
Typ
Max
Unit
2.22
V
Note
CS
Vt-
Negative-going
threshold
Vt+
Positive-going
threshold
2.27
3.42
V
Ilil_cs
Pull-up current
-100
-30
μA
1.62
V5V=5V
INPUT
Schmitt
Trigger
In CS pad, Pulled up to
V5V. (ISUP_HV)
SDO
OUTPUT
Tristate
VOH
High level
output voltage
VOL
Low level
output voltage
VIH
High level input
voltage
VIL
Low level input
voltage
IO
Output drive
current
2.5
0.4
0.7*V5V
V
BBC4C_HV,
PPTRIM_PDIO
V
VSUP ≥ 6V
V
0.3*V5V
V
4
mA
SCLK, SDI
VIH
High level input
voltage
VIL
Low level input
voltage
0.7*V5V
V
SDI is ICC_HV
(PPRTIM_MODE)
V
SCLK is ICC_HV
(PPRTIM_PCLK)
IO Buffer
AS8506 – 20
0.3*V5V
ams Datasheet, Confidential:2013-Sep [1-00]
Electrical Characteristics
Port Type
Symbol
Parameter
Min
Typ
Max
Unit
Note
CVT_NOK_OUT, BD_OUT, TRIG_OUT, CLK_OUT
VOH
High level
output voltage
VOL
Low level
output voltage
V
BU2SC_HV for
CVT_NOK_OUT,
BU1C_HV for
BD_OUT, BU4SC_HV
for TRIG_OUT and
CLK_OUT
0.4
V
VSUP ≥ 6V
4/2/1
mA
2.4
OUTPUT
Buffer
IO
Output drive
current
FD_OUT
OUTPUT
Buffer
VOH
High level input
voltage
VOL
Low level input
voltage
Output drive
current
IO
V
BU24SC_HV for
FD_OUT
0.4
V
VSUP ≥ 6V
24
mA
2.4
MS_SL
VIH
High level input
voltage
VSUP
V
VIL
Low level input
voltage
0.3*V5V
V
High voltage input
pad
INPUT Buffer
CLK_IN, TRIG_IN
INPUT
Schmitt
Trigger
Vt-
High level input
voltage
1.62
2.22
V
Vt+
Low level input
voltage
2.27
0.3*V5V
V
ISC_V5_HV
FD_IN,BD_IN, CVT_NOK_IN
VIH
High level input
voltage
VIL
Low level input
voltage
Ipull_up
Pull-up current
0.7*V5V
V
ICC_V5_HV
INPUT Buffer
WAKE_IN
Pull up
current
-100
3.42
V
-30
μA
Internal pull
Note: Test limits for Iih and Iil are 1.0uA and -1.0uA for input pads.
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 21
Detailed Description
Detailed Description
The device consists of the following blocks:
• PWM driver
• LDO_5V with 5V / 50mA output
• Temperature monitor block
• High precision bandgap reference
• DAC for the reference voltage generation
• SAR ADC for cell voltage and external temperature
measurement
• Oscillators for PWM drive and for the digital logic
• Pre-Regulator
• SC Comparator
• Weak cell detection logic
• PORs on different supplies
Voltage Regulator (LDO_5V)
Power input to the LDO is VSUP pin. It is switched ON when the
device is in NORMAL mode and switched OFF in SLEEP mode.
The LDO takes the input from Bandgap and scales it up to the
required voltage. It starts charging only after entering NORMAL
mode. This LDO is the supply for DAC, the PWM driver and Cell
voltage comparators.It’s additional features are as follows:
• Stability is better than ±2.5% over input range.
• Load current up to 50mA.
High Precision Bandgap (HPBG)
AS8506 has a high precision bandgap to generate accurate
reference. This reference voltage is used to generate reference
for DAC and ADC.
HPBG is trimmed with respect to temperature. Variation of the
bandgap with temperature is ±3mV in the temperature range
from -40ºC to 115ºC.
External Temperature Monitor and
Measurement
Two sensor inputs TEMP_IN1 and TEMP_IN2 with a comparator
on each pin, are available. If the temperature sensor connected
to TEMP_IN1 crosses its threshold, then a warning flag is set in
the device (status can be read through SPI) and the device will
continue balancing.
If the temperature sensor connected to TEMP_IN2 crosses its
threshold, then a flag is set in the device and balancing is
stopped; but the device continues to stay in NORMAL mode for
maintaining synchronism. In both the cases, the
microcontroller will be interrupted by a pulse on
CVT_NOK_OUT pin.
AS8506 – 22
ams Datasheet, Confidential:2013-Sep [1-00]
Detailed Description
In case the external temperature sensors are not being used,
then both the inputs must be connected to GND pin through
1k resistor. In the measurement phase, external temperature is
measured through the SAR ADC. Both channels of temperature
will be measured and stored in temp_in1_lsb_reg to
temp_in2_msb_reg.
Internal Temperature Monitor
The internal temperature monitor has two thresholds at T jwarn
125ºC and T jshut 135ºC. If the internal temperature exceeds
125ºC, then a warning flag is set in the device (status can be
read through SPI) and the device will continue balancing.
If the internal temperature exceeds 135ºC, then a flag is set in
the device and balancing is stopped; but the device continues
to stay in NORMAL mode for maintaining synchronism. In both
the cases, the microcontroller will be interrupted by a pulse on
CVT_NOK_OUT pin. The balance recovery temperature is 115ºC.
PWM Generator
In the Balance phase of the AS8506, based on the decision made
during the Compare phase, some part of the cell is charged with
the Flyback converter. To drive the external Flyback converter,
AS8506 generates a PWM signal to drive external FET or
Optocoupler or Isolation device.
The frequency and of the PWM generator can be controlled by
timer_cntl_reg register.
PWM frequency is not used for the passive balancing.
RC Oscillator
The AS8506 has a trimable RC oscillator. It is designed to
generate fosc-dig clock for the digital circuit and for the clocking
of the IC. Each oscillator will be trimmed with the process to get
the accuracy to fosc-accy with 5-bit OTP Factory trim code.
DAC for the Reference Generation
AS8506 has a 12-bit DAC to generate the cell reference voltage,
cell threshold low and high voltage. The DAC code is written
into AS8506 with SPI interface from microcontroller. The output
of the DAC is given to one of the inputs of the comparators, to
compare the cell voltages synchronously. Reference for the DAC
is 4.5V, which is internally generated and is available as
reference for temperature inputs on REF_T.
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 23
Detailed Description
SAR ADC
AS8506 has a 12-bit SAR ADC to measure the cell voltage and
external temperature. The SAR ADC uses the 12-bit DAC to
generate the digital code. The SAR ADC range is 1.8V to 4.5V for
cell voltage measurement and 0.2V to 4.5V for the temperature
measurement.
Cell voltage and temperature is measured in the short trigger
phase. After the trigger goes ‘high’, compare phase starts and
then all the cell voltages and external temperature are
measured and stored in the digital registers.
Pre-Regulator
AS8506 has an internal pre-regulator, which generates supply
voltages for the internal blocks. Pre-Regulator output is used as
a supply for the oscillators. All the digital logic and the FSM will
work on the pre-regulator supply.
In SLEEP mode only the pre-regulator will be working along with
the WAKE_IN detect circuit.
Cell Threshold
AS8506 has the potential to set the two threshold levels to the
cell voltage through pins CELL_THU and CELL_THL. These
values can be set externally, (or) through OTP trim bits, (or) from
the external microcontroller by writing DAC code into the cell
threshold registers in the register space.
Weak Cell Detection
AS8506 has the ability to detect the weak cell. During load
conditions, if the cell reaches voltage of about 0.1V to -0.2V,
then this variation is detected and stored in the zero cross
detection register. This event is indicated to the master device
by a pulse on CVT_NOK_OUT pin in Compare and Balance
phase. The master device indicates the microcontroller by
setting CVT_NOK_OUT ‘high’. In WAIT mode only this will be
stored in the register; there won’t be any CVT_NOK_OUT to μC.
The register is cleared on μC reading.
External Resister Divider Control
AS8506 has the provision to enable the external divider to give
the desired cell voltage to the at VREF_IN pin. External resister
divider can be connected between VREF_H pin to ground.
Calculate the external resister divider values such that the
output of the divider will provide the desired reference value.
When comparison is not happening, this divider can be
disabled using SPI.
AS8506 – 24
ams Datasheet, Confidential:2013-Sep [1-00]
Detailed Description
PORs on Different Supplies
AS8506 has power-on-reset blocks on VSUP, V5Vand V5V_IN
supply pins. The values for POR and Reset thresholds are given
in Figure 20.
Figure 22:
Power-up Sequence of VSUP, V5V and VSUP+5V
VSUP_POR
VSUP_RESET
VSUP
VSUP_POR
V5V_5V_POR
V5V_5V_RESET
V5V_5V
V5V_5v_POR
V5V_POR
V5V_RESET
V5V
V5V_POR
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 25
Detailed Description
AS8506 System Operation
The AS8506 battery stack system can be set up by configuring
one AS8506 device as ‘Master’ and the rest as ‘Slave’ devices.
The AS8506 Master device is connected to the microcontroller,
and the Slave devices are connected to Master through a
daisy-chain of 3-wire customized SPI protocol. The
microcontroller can communicate to the Slave devices through
the Master. On power-up of the system, the microcontroller
must assign an address to all AS8506 devices including the
Master. The microcontroller can assign the address to AS8506
devices by initiating the address allocation process, by writing
a top most Slave device address into dadd_for_allc_reg register
of Master and then writing ‘07’ data into spi3_cmd_reg. Once
the address allocation process is successful, the microcontroller
can start the cell balancing. If cell balancing or check status
command is not triggered by the microcontroller, after WAIT
mode timeout period all devices enter into SLEEP mode.
The complete system communication procedure is explained
below.
• The microcontroller gives wake pulse on WAKE_IN to
bring the Master and Slaves in NORMAL mode.
• After the wake-up time period, the microcontroller (μC)
sends the reference voltage digital code to the Master
device through a 4-wire SPI.
• After receiving the digital reference code from μC, the
Master device initiates a 3-wire custom SPI operation to
send the digital reference code to the Slave devices.
• The microcontroller waits for the 3-wire SPI operation
time period. After the 3-wire SPI time period, it initiates
the cell balancing through TRIG_IN. The balancing will
continue as long as TRIG_IN is ‘High’.
• The microcontroller can change the reference value at any
time by making TRIG_IN ‘Low’ and initiating a 4-wire SPI
with new value of reference code. From here on, the
procedure is same as from point 3.
• The balance done is indicated on BD_OUT pin.
• The failure in the 3-wire SPI operation is indicated on
CVT_NOK_OUT pin.
AS8506 – 26
ams Datasheet, Confidential:2013-Sep [1-00]
Detailed Description
Figure 23:
Functional Diagram of AS8506
uC reference voltage
calculator found change in
reference (average) voltage
uC reference voltage
calculator found change in
reference (average) voltage
MICRO
PROCESSOR
4-wire SPI
write
Wake
up
pulse
by
uC
MASTER
Wake
up
pulse
by
uC
Trigger from uC
on TRIG_IN pin
for cell balancing
operation
Balance
Reference
voltage from uc
through 4 wire
SPI operation
(DAC code)
4-wire SPI
Read
Sleep
mode
4-wire SPI
write
3-wire
CUSTOM
write
MASTER module
initiates a 2 wire
SPI operation to
send the Balance
Reference voltage
from uc to slave
modules (DAC
code)
3-wire
CUSTOM
Read
SLAVES
Sleep
mode
Wake
up
pulse
by
uC
ams Datasheet, Confidential:2013-Sep [1-00]
Trigger from uC
on TRIG_IN pin
for cell balancing
operation
based on current
status of stack
voltage new
Balance
Reference
voltage from uc
through 4 wire
SPI operation
(DAC code)
CELL
Balancing
4-wire SPI
Read
3-wire
CUSTOM
write
MASTER module
initiates a 2 wire
SPI operation to
send the new
Balance
Reference
voltage from uc
to slave modules
(DAC code)
cell Balancing to
reference value
set by uC.
3-wire
CUSTOM
Read
CELL
Balancing
CELL
Balancing
cell Balancing to
reference value
set by uC.
CELL
Balancing
Normal
mode
AS8506 – 27
Detailed Description
Functional State Diagram
Figure 24:
Finite State Machine Mode
Power ON
Initialization Phase
Vsup POR
OSC clock ON
V5V LDO ON
V5V POR
OTP Load
OTP Load done
Sleep Mode
V5V LDO OFF
OSC clock OFF
Pre-reg ON
Wake_pulse
Wake Mode
V5V LDO ON
Timeout
&
No trigger
OSC clock ON
V5V_por
Wait Mode
Wait for µC Trigger
(X mS)
V5V LDO ON
OSC clock ON
No trigger
long_trigger
short_trigger
Normal Mode
Normal Mode
cell
balance
phase
Compare
phase
V5V LDO ON
OSC clock ON
AS8506 – 28
Compare phase
and
ADC Measurement phase
V5V LDO ON
OSC clock ON
ams Datasheet, Confidential:2013-Sep [1-00]
Detailed Description
Operating Modes
The AS8506 has two main operating modes NORMAL and SLEEP,
and has two transition modes WAIT and WAKE. The transition
modes are intermediate modes for switching from SLEEP to
NORMAL and vice versa. The detailed operation of each mode
is explained in subsequent sections. The initialization phase is
explained in“Initialization Sequence” on page 36.
NORMAL Mode
The device enters into NORMAL from WAKE when it receives a
short or long trigger. The NORMAL mode is a full functional
mode, where all the power supply and analog blocks are in
ON-state and the digital is fully functional.
The NORMAL mode has two phases of operation:
• Diagnosis phase
• Balance phase
Diagnosis Phase
In Diagnosis phase AS8506 detects the number of cells
connected to the device. The connected cell voltages are then
compared with upper & lower thresholds and target cell voltage
of all cells connected. Upper and lower cell voltage thresholds
as well as target cell voltages are provided from external in
analog or digital format. The Diagnosis phase sequence of
operation is explained below.
• Detects number of cells connected to the device by
comparing each cell terminals to cell detect threshold
voltage.
• Simultaneously compares each connected cell voltage
with set lower operating voltage threshold Vlimit_L. If any
of the cell voltages is less than the set lower operating
threshold, then an indication is given on CVT_NOK_OUT
pin stating that one/more cell voltages are not within the
operating voltage threshold range. Each cell status is
stored in cel_low_thsld_stat_reg register.
• Simultaneously compares each connected cell voltage
with set higher operating voltage threshold Vlimit_H. If
any of the cell voltages is greater than the set higher
operating threshold, then an indication is given on
CVT_NOK_OUT pin stating that one/more cell voltages
are not within the operating voltage threshold range. Each
cell status is stored in cel_high_thsld_stat_reg register.
• Simultaneously compares each connected cell voltage
with reference value. This result is stored in
cel_ref_stat_reg register and used in balance phase. Cell
reference can be provided by microcontroller by writing
into register or by providing input at external pin
VREF_IN.
• Enables the SAR ADC and measures each cell voltage and
two temperature inputs sequentially. The 12 bits cell
voltage and temperature inputs information is stored in
respective registers.
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 29
Detailed Description
At the end of the Diagnosis phase, if trigger signal is ‘High’ then
it enters into Balance phase. If trigger signal is ‘Low’ it enters
into WAIT mode.
The Diagnosis phase without the cell voltage measurement
with SAR ADC is called Compare phase.
Balance Phase
The Balance phase is basically a charging cycle in case of active
balancing and a discharging cycle in case of passive balancing.
The Balance phase is divided into 7 time slots. The device will
move through all 7 time slots irrespective of number of cells
connected to the device. This is done to keep synchronization
between each module in case of battery stack system. One time
slot is assigned to each cell (sequential order) for charging or
discharging. The period of time slots is programmable (see
“Status Registers” on page 52).
In each time slot, following operations are done.
• Check CVT_NOK flag status. If CVT_NOK flag is set, then
no operation is done till time slot is over. If CVT_NOK flag
is not set, then move to the next step.
• Based on Diagnosis phase results, shuttle switch
corresponding to current time slot cell is switched ON for
charging that cell in case of active balancing, and
discharging in case of passive balancing.
• The PWM generator is enabled and PWM driver start
driving the Flyback converter FET (external component)
in case of active balancing. The PWM frequency and duty
cycles are factory programmable and also register
controllable. In case of stack system, the bottom module
PWM driver is enabled when there is a request of charging
or discharging from top module on FD_OUT pin.
• At the end of the current time slot, stop the PWM
generator and then open the corresponding shuttle
switches. The device moves to the next time slot.
In the Balance phase, at any point, if the trigger input goes ‘Low’,
then the device suspends balancing operation and enters into
WAIT mode.
Sleep Mode
This is the least power consumption mode of AS8506. In this
mode only pre-reg is ON, rest all analog blocks are OFF and
digital clock is disabled. Only a digital wake detection circuit is
active. The device enters into this mode when there is no trigger
from microcontroller for time greater than WAIT mode timeout
period.
Wait Mode
This mode is a transition mode, where the device waits for
command on TRIG_IN pin either from microcontroller, (or) from
below module in case of stack system. The device will be in this
state for T WMODE_TOUT period. After the timeout, the device
AS8506 – 30
ams Datasheet, Confidential:2013-Sep [1-00]
Detailed Description
enters into SLEEP mode. In the WAIT period all power blocks are
ON, all analog blocks are ON and digital is also functional. In
this mode, power consumption is lesser than NORMAL mode
because there are no charge balancing activities being carried
out.
Wake Mode
This is also a transition mode, where the device does
initialization after exiting SLEEP mode. In the SLEEP mode if
AS8506 receives a wake pulse of width T WAKE, the device enters
into WAKE mode. In the WAKE mode device enables the V5V LDO
and waits for V5V_por_n signal. Once V5V_por_n signal
becomes ‘High’, the device enters into WAIT mode.
An example of Compare and Balance (active balance) phase
sequence with respect to time is given in Figure 25. In this
example it is assumed that only 6 cells are connected to AS8506
and comparators’ outputs at Diagnosis phase is “010010X”;
Where:
‘0’ indicates respective cell voltage is less than target voltage
and needs charging.
‘1’ indicates respective cell voltage is more than target voltage
and needs charging.
‘X’ indicates no cell is connected to respective comparator and
output is neglected.
Tc_slot
Compare Phase
ams Datasheet, Confidential:2013-Sep [1-00]
Tc_slot
Tc_slot
Balance Phase
Tc_slot
Cell
Connected
Vcell6 < Vrdiv
Need
Charging
Cell
Not
Connected
Tc_slot
Tc_slot
Cell reference comparision
Idle
Time
Cell Higher Threshold comparision
PWM
Cell Detection Comparision
Idle
Time
Cell Lower Threshold comparision
Charging
Cell
Cell
Cell
Cell
Connected
Connected
Connected
Connected
Vcell2 > Vrdiv Vcell3 < Vrdiv Vcell4 < Vrdiv Vcell5 > Vrdiv
Don’t Need
Need
Need
Don’t Need
Charging
Charging
Charging
Charging
Tc_slot
CELL7 TIME SLOT
PWM
CELL6 TIME SLOT
PWM
Idle
Time
CELL5 TIME SLOT
Charging
000000X
Cell
Connected
Vcell1 < Vrdiv
Need
Charging
Charging
Cell7 not connected
PWM
CELL4 TIME SLOT
Charging
CELL3 TIME SLOT
CELL2 TIME SLOT
CELL1 TIME SLOT
Cell Higher Threshold comparision
Cell reference comparision
010010X
Cell Detection Comparision
Cell7 not connected
Cell Lower Threshold comparision
Figure 25:
Diagnosis and Balance Phase with Time Sequence for AS8506
Compare Phase
AS8506 – 31
Detailed Description
Wake-up Event
The AS8506 device comes out of SLEEP mode by a wake pulse
on the WAKE_IN pin. To avoid false wake by noises on the
WAKE_IN, the wake signal (Low pulse) is taken through a
low-pass filter from WAKE_IN pin. When a pulse of width
Twake_pulse is given on the WAKE_IN by the microcontroller, the
device wakes up and enters into WAKE mode. The low-pass filter
discards all signals having width less than Tfilter_min and allows
all signals with width greater than Tfilter_max. The filter is
uncertain in Tuncertain region. The negative edge which is
passing through the filter will wake the device from SLEEP
mode. In chain of AS8506 devices, to propagate the negative
edge the microcontroller has to give minimum low pulse of
width Twake_pulse. Before entering into SLEEP mode the wake
pin must be ‘High’.
Figure 26:
WAKE-UP Signaling
WAKE_IN
Tuncertain
Tfilter_min
Tuncertain
Tfilter_max
Twake_pulse
wake_in_fltrd
Tfilter_delay
AS8506 – 32
ams Datasheet, Confidential:2013-Sep [1-00]
Detailed Description
Trigger Event
The AS8506 device enters into NORMAL mode only when a valid
command is present on the TRIG_IN pin. There are two
commands in the device.
• Diagnosis command
• Cell balance command
When a high pulse of width Tdiag_cmd as shown in Figure 27, is
given on TRIG_IN pin, the device performs the following
operations.
• Compares all connected cell voltages with the set lower
operating voltage threshold, and if any of the cell voltage
is less than lower threshold, then sets a corresponding flag
in the cel_low_thsld_stat_reg register. This is indicated by
high pulse on CVT_NOK_OUT pin.
• Compares all connected cell voltages with the set higher
operating voltage threshold, and if any of the cell voltage
is more than higher threshold, then sets a corresponding
flag in the cel_high_thsld_stat_reg register. This is
indicated by high pulse on CVT_NOK_OUT pin.
• Sets a corresponding flag in the temp_stat_reg register if
ambient temperature or internal chip temperature is
higher than respective thresholds. This is indicated by
high pulse on CVT_NOK_OUT pin.
• It will enable SAR ADC and starts measuring each cell
voltage, and then measures temperature channel
measurement. The 12 bits digital value will be stored in
corresponding registers.
Thus, on diagnosis command the device gives the cell operating
voltage, ambient temperature and internal temperature status
with respect to its safe operating range.
When the TRIG_IN pin is ‘High’ for longer than the status
command, the device enters into Balance phase. Depending
upon cell voltage status, the device starts balancing the cell
voltages. The cell voltage balancing is continued till the high
voltage on the TRIG_IN pin. As soon as TRIG_IN goes ‘Low’, the
device stops balancing and enters into WAIT mode. Thus, the
microcontroller has full control over the balancing time and
stop balancing whenever required.
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 33
Detailed Description
Figure 27:
TRIG_IN Command Signaling
Cell Balance
Command
Diagnosis
Command
TRIG_IN
Tstatus_cmd
Device
State
AS8506 – 34
WAIT
MODE
NORMAL MODE
(Diagnosis phase)
Tbal_cmd
WAIT
MODE
NORMAL MODE
(Compare + Balance phase)
WAIT
MODE
ams Datasheet, Confidential:2013-Sep [1-00]
Detailed Description
Balancing Algorithm
Figure 28:
Cell Balancing Algorithm
Trigger
BD_IN
compare all
connected cells with
reference voltage
BD_OUT
identify and store
toggle of connected cell
comparator outputs
generate Internal
Balance done
YES
All
connected
cell comp
toggle?
NO
Active – balancing
Charge cells with comp
o/p = 0.
Passive – balancing
discharge cell with
comp o/p = 1
NO
ams Datasheet, Confidential:2013-Sep [1-00]
7 Time slot
Over ?
YES
AS8506 – 35
Detailed Description
Initialization Sequence
The power-up initialization sequence diagram for AS8506 is
shown in Figure 29.
• When the power supply is switched ON, initially VSUP POR
output Vsup_por_n is ‘Low’; hence all the digital logic will
be in reset state.
• Once the VSUP crosses the Vsup_por_th, the VSUP POR
output becomes ‘High’ enabling the oscillator and
high-precision bandgap (HPBG) block.
• The digital block is now operational. It will now enable the
V5V LDO and waits for V5V_por_n high signal from the
V5V POR block.
• Once the V5V crosses V5V_por_th, the V5V_por_n will be
‘High’. The OTP auto load command is generated by ‘High’
on otp_por_n signal. Now the device waits for T auto_load
period for OTP contents to load into digital local registers.
• After the OTP contents are loaded into digital local
registers, the device power-up sequence is completed.
The device enters into SLEEP mode. In SLEEP mode, the
LDO, oscillator and HPBG are disabled.
• The wake-up circuit monitors the WAKE_IN pin for
wake-up pulse. When a wake-up pulse is received, the
oscillator and HPBG block are enabled and device enters
into WAKE mode. In the WAKE mode, the device enables
V5V LDO and waits for V5V_por_n high signal.
• Once the V5V crosses V5V_por_th, the V5V_por_n will be
‘High’ and the device enters into WAIT mode. In WAIT
mode the device waits for trigger pulse on TRIG_IN pin
from microcontroller. In this state, if a short or long pulse
trigger signal is received on TRIG_IN within Twmode_tout
period, the AS8506 enters into NORMAL mode and
performs required operations based on trigger pulse.
AS8506 – 36
ams Datasheet, Confidential:2013-Sep [1-00]
Detailed Description
Figure 29:
Power-up Initialization Sequence
Vsup_por_th
VSUP
Vsup_por_n
Wake Pulse
WAKE_IN
TRIG_IN
osc_en
hp_bg_en
ldo_en
Thp_bg_stl
Thp_bg_stl
V5V_por_th
V5V_bor_th
V5V_por_th
V5V
V5V_por_n
otp_por_n
Tauto_laod
otp_load
wait_timer
Continue
INITIALIZATION
TINITIALIZATION
ams Datasheet, Confidential:2013-Sep [1-00]
SLEEP MODE
WAKE MODE
WAIT MODE
NORMAL
WAIT MODE
TWAKE-UP
AS8506 – 37
Device Inter face
Device Interface
A 4-wire SPI is used to communicate with the device. Pins CS,
SCLK, SDI, and SDO are used for SPI interface.
Serial Peripheral Interface
The Serial Peripheral Interface (SPI) provides the
communication link with the microcontroller. The SPI is
configured for half-duplex data transfer. The SPI in AS8506
provides access to the status registers, control registers and test
registers. The SPI is also used to enter into test and OTP modes.
This interface is only Slave interface and only Master can initiate
the SPI operation. The SPI also supports block data transfer
where sequential register data can be accessed with single SPI
command.
The SPI can work on both the clock polarities. The polarity of
the clock is dependent on the value of SCLK at the falling edge
of CS.
At the falling edge of CS,
• If SCLK is “1”, then the SPI is negative edge triggered.
• If the SCLK is “0”, then SPI is positive edge triggered logic.
see Figure 30 for more details.
Figure 30:
SPI Clock Polarity Table
CS
SCLK
Description
↓
Low
Serial data is transferred at rising edge and sampled at falling edge of SCLK.
↓
High
Serial data is transferred at falling edge and sampled at rising edge of SCLK.
AS8506 – 38
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
The SPI protocol frame is divided into two fields.
• The header field
• The data field
The header field is 1 byte long; containing a read/write
command bit, 1 reserved bit, and 6 address bits. The SPI frame
format is shown in Figure 31. In the data phase MSB is sent first
and LSB is sent last.
Figure 31:
SPI Frame Format
R/W
0
Header Field
Data Field
1 byte
Integer Multiple of Bytes
A5
Reserved
Bit
A4
A3
A2
A1
A0
DATA
6 bits
Address
0 – WRITE
1 – READ
SPI Write Operation
The SPI write operation begins with clock polarity selection at
negative edge of CS (see Figure 30). Once the clock polarity is
selected, the SPI write command is given by providing ‘0’ in R/W
bit of the header field in first sampling edge at SDI pin. The next
bit in header field is reserved and set to ‘0’. The 6 bits address
of register to be written is provided at SDI pin in next six
consecutive sampling edges of SCLK. The data to be written is
followed by last bit of header field. With each sampling edge a
bit is sampled starting from MSB to LSB. During complete SPI
write operation the SCSN has to be ‘Low’. The SPI write
operation ends with positive edge of SCSN. The waveform for
SPI write operation with single data byte is shown in Figure 32
and Figure 33.
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 39
Device Inter face
Figure 32:
SPI Write Operation with Negative Clock Polarity and 1 Byte of Data Field
SCSN
SCLK
R0
A5
SDI
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDO
Figure 33:
SPI Write Operation with Positive Clock Polarity and 1 Byte of Data Field
SCSN
SCLK
SDI
R0
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDO
Sampling Edge
High Impedance Sate
In case of SPI block write operation, first data byte is written
into addressed register same as single byte write operation.
After first data byte, Master can send next data byte by keeping
CS ‘Low’ and giving clock on SCLK as per polarity selection. At
the end of every eighth data bit, the byte is written into next
consecutive address location (internally address is incremented
by one location). In this way, Master can continue writing into
consecutive address locations. The waveform is shown in
Figure 34.
AS8506 – 40
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
Figure 34:
SPI Block Write Operation with Negative Clock Polarity
CS
SCLK
SDI
0
A
0 5
A
4
A
3
A
2
A
1
A
0
D D
7 6
D
5
D D D
4 3 2
D D D D
1 0 7 6
D
5
D D D
4 3 2
D
1
D
0
D D
7 6
D
5
D D D
4 3 2
D
1
D D D
0 7 6
D
5
D D D
4 3 2
D
1
D
0
D D
7 6
D
5
D D D
4 3 2
D
1
D
0
SDO
Data D7-D0 is
moved to Address
A5-A0 here
Data D7-D0 is
moved to Address
A5-A0 +1 here
Data D7-D0 is
moved to Address
Data D7-D0 is
moved to Address
A5-A0 +3 here
A5-A0 +2 here
Data D7-D0 is
moved to Address
A5-A0 +4 here
SPI Read Operation
The SPI read operation also begins with clock polarity selection
at negative edge of SCSN (see Figure 30). Once the clock
polarity is selected, the SPI read command is given by providing
‘1’ in R/W bit of the header field in first sampling edge at SDI
pin. The next bit in header fields is reserved and set to ‘0’. The
6 bits address of register to be read is provided at SDI pin in
next six consecutive sampling edges of SCLK. The read data is
followed by last bit of header field on SDO pin. With each
sampling edge a bit can be read on SDO pin starting from MSB
to LSB. In case of multi-data bytes, MSB of next data byte can
be read after the LSB of previous data byte. During complete
SPI read operation the SCSN has to be ‘Low’. The SPI read
operation ends with positive edge of SCSN. The wave form for
SPI read operation with single data byte is shown in Figure 35
and Figure 36.
Figure 35:
SPI Read Operation with Negative Clock Polarity and 1 Byte of Data Field
SCSN
SCLK
SDI
R0
A5
A4
SDO
ams Datasheet, Confidential:2013-Sep [1-00]
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
AS8506 – 41
Device Inter face
Figure 36:
SPI Read Operation with Positive Clock Polarity and 1 Byte of Data Field
SCSN
SCLK
SDI
SDO
R0
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Sampling Edge
High Impedance Sate
AS8506 – 42
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
In case of SPI block read operation, first data byte is read from
addressed register same as single byte read operation. After
first data byte read, Master can read next consecutive addressed
data by keeping CS ‘Low’ and giving clock on SCLK as per clock
polarity selection. At the end of every eighth data bit, the
address pointer is incremented to next consecutive address
location. In this way Master can continue reading from
consecutive register address locations. The waveform is shown
in Figure 37.
Figure 37:
SPI Block Read Operation with Negative Clock Polarity
CS
SCLK
SDI
SDIO
1
0
A
5
A A A
A
A
4
1
0
3
2
D
D
D D D
D D D
D D
D
D D D
D D
D D
D D D D
D D
D D
D
D D
D D
D
D D
D D D
D D
D
7
6
5
2
7
5
4
1
7
5
1
7
5
4 3
2
0
7
5
2
0
Data D7-D0 at
Address A5-A0
is read here
4
3
1
0
6
3
2
0
6
4
3
2
0
6
1
6
Data D7-D0 at
Data D7-D0 at
Data D7-D0 at
Data D7-D0 at
Address A5-A0 +1
is read here
Address A5-A0 +2
is read here
Address A5-A0 +3
is read here
Address A5-A0 +4
is read here
4
3
1
Address Allocation Process
During the system configuration the microcontroller has to
allocate a unique address to each of the AS8506 devices
including the Master to communicate with SPI3. The
microcontroller before initiating the address allocation process,
it writes top most device address into allcd_dev_add_reg of the
Master through 4-wire SPI. The microcontroller can initiate the
address allocation process by writing ‘100’ command code and
setting D0 to 1 in spi3_cmd_reg register. By sighting ‘1’ at
spi3_cmd_reg [0], the Master initiates a SPI3 address allocation
write with top most device address as data. The address
“000000” is reserved as broadcast address visible to all devices.
The address allocation process is explained for six AS8506
devices (including Master) stack system in Figure 38.
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 43
Device Inter face
Figure 38:
Address Allocation Process
SPI3 address allocation write
operation
Address allocation process
STOP
CLK-IN/OUT
TRIG-IN/OUT
C1
C0
TST
CVT_NOK_IN
Address of
6th Device
Address = X
New
Address = 6
Address = X
New
Address = 6
Address = X
New
Address = 6
6-1=5 5-1=4
Address = X
New
Address = 6
6-1=5 5-1=4 4-1=3
Final Address
Address = X
New
Address = 6
6-1=5 5-1=4 4-1=3
3-1=2
Address = X
New
Address = 6
6-1=5 5-1=4 4-1=3
3-1=2 2-1=1
CVT_NOK_OUT6
CVT_NOK_IN5
Address of
5th Device
6 -1 = 5
Final Address
CVT_NOK_OUT5
CVT_NOK_IN4
Address of
4th Device
Final Address
CVT_NOK_OUT4
CVT_NOK_IN3
Address of
3rd Device
CVT_NOK_OUT3
CVT_NOK_IN2
Address of
2nd Device
Final Address
CVT_NOK_OUT2
CVT_NOK_IN1
Address of
1st Device
(Master)
Final Address
CVT_NOK_OUT1
(Master)
AS8506 – 44
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
In the address allocation process, the
CVT_NOK_IN/CVT_NOK_OUT pins of AS8506 are used. After
the successful SPI3 address allocation write operation, all
AS8506 devices including Master will store the top device
address (sent by Master in SPI3 address allocation write) as its
address. The top device identifies itself as top most device and
registers the address as its final address and at first rising edge
of clock all devices force ‘High’ on its CVT_NOK_OUT pin. The
concept of address allocation is: after the STOP of SPI3, at every
falling edge of the clock each device will sample its
CVT_NOK_IN pin. If CVT_NOK_IN pin is ‘High’, the device will
decrement the assigned address by ‘1’ and continue to force
‘High’ on its CVT_NOK_OUT pin at rising edge of clock. If
CVT_NOK_IN is sampled to be ‘Low’, then the address value at
register will be stored as its final device address and it stops
forcing ‘High’ on its CVT_NOK_OUT pin and makes it ‘Low’ at
next rising edge of clock.
In Figure 38, top most device pins are suffixed with ‘6’ down to
lower most device (Master) pins suffixed with ‘1’ in descending
order. There is no device above topmost device, CVT_NOK_IN6
is always ‘Low’; therefore the address sent by Master is final
address for the top device. For the fifth device the
CVT_NOK_IN5 is ‘Low’ for one clock cycle, the address is
decremented once. For the fourth device CVT_NOK_IN4 is ‘Low’
for two clock cycles, the address is decremented twice before
registering it as final address. This procedure is continued and
finally the Master device CVT_ONK_IN1 is ‘Low’ for 5 clock
cycles, the address is decremented five times and finally
address register will have value of “000001” as its final address.
The microcontroller can identify the end of address allocation
procedure in two ways:
• One way is by probing CVT_NOK_OUT of Master after
initiating address allocation process for a pulse.
• The other method is by polling bit0 of spi3_cmd_reg
register for ‘0’ (Low) and no CRC errors.
During SPI3 address allocation write operation, if a CRC error
occurs in the any of the Slaves, the Master indicates this failure
of SPI3 transaction to all Slaves by driving TST bit ‘High’. All
Slaves should terminate the address allocation process if a
‘High’ TST bit is seen during start address allocation process
SPI3 write operation. The Master will indicate the failure of
address allocation process to μC by asserting a flag in the
spi3_sts_reg register and sending interrupt pulse on its
CVT_NOK_OUT pin.
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 45
Device Inter face
Communication to Slaves
There are two modes of communication between the Master
and Slaves in the AS8506 stack system:
• Broadcast Communication
• Communication with Individual Slave
Broadcast Communication
The Broadcast of communication is used to send the reference,
lower, upper threshold limit codes and timer control register
values for all the slaves.
Reference and thresholds can be set by one of the two methods:
• Through the external pins
• Through the Internal DAC
In case of the stacked system, reference and thresholds can be
set by writing DAC values though broadcast SPI command.
Write the corresponding data in the registers of timer_cntl_reg,
ref_dcod_lsb_reg/ref_dcod_msb_reg,
hlmt_dcod_lsb_reg/hlmt_dcod_msb_reg and
llmt_dcod_lsb_reg/llmt_dcod_msb_reg and command in the
Command Registers spi3_cmd_reg and spop_dadd_bcmd_reg.
Example:
To write DAC code of 0x0666 in the lower threshold register of
all the devices, initiate a broadcast command as given in the
below sequence.
Figure 39:
Threshold Setting through Broadcast Command to Slaves
Command
Register Name
Address
Data
llmt_dcod_lsb_reg
0x23
0x66
llmt_dcod_msb_reg
0x24
0x06
spop_dadd_bcmd_reg
0x25
0x03
spi3_cmd_reg
0x28
0x09
To set low threshold
Broadcast the cell lower limit DAC code
Broadcast communication command
Each broadcast write operation takes 35 clock cycles of the
communication frequency. The default communication
frequency is 5KHz.
Broadcast slave register write is also possible other than above
registers.
If there any specific register of all the slaves to be written with
the same content of Master then this feature is useful.
Write register address in the spop_reg_add_reg.
AS8506 – 46
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
Example:
To set the external temperature thresholds to 4.15V, initiate a
broadcast command as given in the below sequence.
Figure 40:
External Temperature Threshold Setting through Broadcast Command to Slaves
Command
Register Name
Address
Data
To set the external temperature threshold
tflg_tshld_setg_reg
0x1D
0xFF
Address of the register to broadcast
spop_reg_add_reg
0x26
0x1D
Broadcast communication command
spi3_cmd_reg
0x28
0x0B
Communication with Individual Slave
Communication with an individual slave is done as SPI write or
read.
Write operation.
To perform the write operation to one of the slave device,
corresponding data should be written in these registers
spop_dadd_bcmd_reg, spop_reg_add_reg, wrop_data_reg
and spi3_cmd_reg.
Example:
To set the external temperature threshold of the slave device
address 0x06 to 4.15V, initiate a broadcast command as given
in the below sequence.
Figure 41:
Write Operation to the Individual Slave
Command
Register Name
Address
Data
spop_dadd_bcmd_reg
0x25
0x06
spop_reg_add_reg
0x26
0x1D
To set the external temperature threshold
wrop_data_reg
0x27
0xFF
Slave write command
spi3_cmd_reg
0x28
0x05
Slave device address
Address of the slave register
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 47
Device Inter face
Read operation.
To perform the read operation to one of the slave device,
corresponding data should be written in these registers
spop_dadd_bcmd_reg, spop_reg_add_reg and spi3_cmd_reg.
Data from the slave device will be written in the register
rdop_data_reg.
Example:
To read the temperature status register of the slave device
address 0x06, initiate a broadcast command as given in the
below sequence.
Figure 42:
Read Operation to the Individual Slave
Command
Slave device address Slave
Address of the slave register
write command
AS8506 – 48
Register Name
Address
Data
spop_dadd_bcmd_reg
0x25
0x06
spop_reg_add_reg
0x26
0x05
spi3_cmd_reg
0x28
0x03
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
SPI Timing Diagrams
Figure 43:
Timing Diagram for Write Operation
SCS
...
tCPS
SCLK
tCPHD
tSCLKH
tSCLKL
t CSH
CLK
polarity
...
tDIS
SDI
tDIH
DATAI
DATAI
...
DATAI
...
SDO
Figure 44:
Timing Diagram for Read Operation
SCS
tSCLKH
tSCLKL
SCLK
SDI
DATAI
DATAI
t DOD
SDO
ams Datasheet, Confidential:2013-Sep [1-00]
DATAO (D7N )
t DOHZ
DATAO (D00 )
AS8506 – 49
Device Inter face
SPI Protocol
Figure 45:
SPI Timing Parameters
Symbol
Parameter
Min
Typ
Max
Unit
1
Mbps
Note
General
BRSPI
Bit rate
TSCLKH
Clock high time
400
ns
TSCLKL
Clock low time
400
ns
Write Operation Parameters
tDIS
Data in setup
time
20
ns
tDIH
Data in hold time
20
ns
TCSH
SCSN hold time
20
ns
Read Operation Parameters
tDOD
Data out delay
80
ns
tDOHZ
Data out to high
impedance delay
80
ns
Time for the SPI to release
the SDO bus
Timing Parameters for SCLK Polarity Identification
tCPS
Clock setup time
(CLK polarity)
20
ns
Setup time of SCLK with
respect to SCSN falling
edge.
tCPHD
Clock hold time
(CLK polarity)
20
ns
Hold time of SCLK with
respect to SCSN falling
edge.
AS8506 – 50
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
System Timings
Figure 46:
System Timings
Symbol
Parameter
Min
Typ
Max
Unit
Note
Wake-up Timing
Twake_pulse
Wake pulse width
Tfilter_delay
Time between edge on TRIG_IN pin
to trig_in_fltrd signal
Tfilter
100
WAKE_IN pin filter specification
μs
1
4
μs
4
μs
1000
μs
Trigger Timing
Tstatus_cmd
Tbal_cmd
Status request command pulse
500
Cell balance command pulse
7000
μs
Wait Mode Timing
Twmode_tout
WAIT mode timeout
ams Datasheet, Confidential:2013-Sep [1-00]
2000
ms
AS8506 – 51
Device Inter face
Register Space Description
The AS8506 register space is divided into control registers and
test registers. All of these registers are accessed through SPI.
Status Registers
Figure 47:
Cell Detection Status Register
Address
Register Name
Features and Bit Description
SPI
4
SPI
3
POR
Value
R
R
0000_0000
POR_V5V
Indicates the detected cells.
0x00
AS8506 – 52
cel_det_stat_reg
D0
0 → Cell 1 is not detected
1 → Cell 1 is detected
D1
0 → Cell 2 is not detected
1 → Cell 2 is detected
D2
0 → Cell 3 is not detected
1 → Cell 3 is detected
D3
0 → Cell 4 is not detected
1→ Cell 4 is detected
D4
0 → Cell 5 is not detected
1 → Cell 5 is detected
D5
0 → Cell 6 is not detected
1 → Cell 6 is detected
D6
0 → Cell 7 is not detected
1 → Cell 7 is detected
D7
Reserved
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
Figure 48:
Diagnostic Status Register
Address
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
Diagnostic register. μC can read this
register if pulse is detected on
CVT_NOK_OUT pin, to diagnose cause
of indication.
0x01
diag_sts_reg
D0
1 → Low Threshold limit cross
Indicator
D1
1 → High Threshold limit
cross indicator
D2
1 → Over-temperature
indicator
D3
1 → Address allocation
procedure fail
D4
1 → SPI3 read operation fail
D5
1 → SPI3 write operation fail
D6
1 → SPI3 Broadcast operation
fail
D7
Reserved
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 53
Device Inter face
Figure 49:
Cell Lower Threshold Status Register
Address
Features and Bit
Description
Register Name
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
Indicates if a cell voltage crossed
the lower threshold limit set by μC.
0x02
AS8506 – 54
cel_low_thsld_stat_reg
D0
0 → Cell 1 voltage is more
than Low Threshold limit
set
1 → Cell 1 voltage is less
than Low Threshold limit
set
D1
0 → Cell 2 voltage is more
than Low Threshold limit
set
1 → Cell 2 voltage is less
than Low Threshold limit
set
D2
0 → Cell 3 voltage is more
than Low Threshold limit
set
1 → Cell 3 voltage is less
than Low Threshold limit
set
D3
0 → Cell 4 voltage is more
than Low Threshold limit
set
1 → Cell 4 voltage is less
than Low Threshold limit
set
D4
0 → Cell 5 voltage is more
than Low Threshold limit
set
1 → Cell 5 voltage is less
than Low Threshold limit
set
D5
0 → Cell 6 voltage is more
than Low Threshold limit
set
1 → Cell 6 voltage is less
than Low Threshold limit
set
D6
0 → Cell 7 voltage is more
than Low Threshold limit
set
1 → Cell 7 voltage is less
than Low Threshold limit
set
D7
Reserved
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
Figure 50:
Cell Higher Threshold Status Register
Address
Features and Bit
Description
Register Name
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
Indicates if a cell voltage crossed
the lower threshold limit set by μC.
0x03
cel_high_thsld_stat_reg
ams Datasheet, Confidential:2013-Sep [1-00]
D0
0 → Cell 1 voltage is less
than High Threshold limit
set
1 → Cell 1 voltage is more
than High Threshold limit
D1
0 → Cell 2 voltage is less
than High Threshold limit
set
1 → Cell 2 voltage is more
than High Threshold limit
D2
0 → Cell 3 voltage is less
than High Threshold limit
set
1 → Cell 3 voltage is more
than High Threshold limit
D3
0 → Cell 4 voltage is less
than High Threshold limit
set
1 → Cell 4 voltage is more
than High Threshold limit
D4
0 → Cell 5 voltage is less
than High Threshold limit
set
1 → Cell 5 voltage is more
than High Threshold limit
D5
0 → Cell 6 voltage is less
than High Threshold limit
set
1 → Cell 6 voltage is more
than High Threshold limit
D6
0 → Cell 7 voltage is less
than High Threshold limit
set
1 → Cell 7 voltage is more
than High Threshold limit
D7
Reserved
AS8506 – 55
Device Inter face
Figure 51:
Cell Reference Status Register
Address
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
Indicates which cell has reached the
reference value at least once. This
status is cleared when new reference is
selected.
0x04
AS8506 – 56
D0
0 → Cell 1 voltage is less than
reference voltage
1 → Cell 1 voltage is more
than reference voltage
D1
0 → Cell 2 voltage is less than
reference voltage
1 → Cell 2 voltage is more
than reference voltage
D2
0 → Cell 3 voltage is less than
reference voltage
1 → Cell 3 voltage is more
than reference voltage
D3
0 → Cell 4 voltage is less than
reference voltage
1 → Cell 4 voltage is more
than reference voltage
D4
0 → Cell 5 voltage is less than
reference voltage
1 → Cell 5 voltage is more
than reference voltage
D5
0 → Cell 6 voltage is less than
reference voltage
1 → Cell 6 voltage is more
than reference voltage
D6
0 → Cell 7 voltage is less than
reference voltage
1 → Cell 7 voltage is more
than reference voltage
D7
Reserved
cel_ref_stat_reg
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
Figure 52:
Temperature Status Register
Address
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
Indicates the status of temperature
monitors.
0x05
D0
0 → Ambient temperature is
less than warning threshold
1 → Ambient temperature is
more than warning threshold
D1
0 → Internal temperature is
less than warning threshold
1 → Internal temperature is
more than warning threshold
D2
0 → Ambient temperature is
less than maximum
threshold
1 → Ambient temperature is
more than maximum
threshold
D3
0 → Internal temperature is
less than maximum
threshold
1 → Internal temperature is
more than maximum
threshold
temp_stat_reg
D7:D4
ams Datasheet, Confidential:2013-Sep [1-00]
Reserved
AS8506 – 57
Device Inter face
Figure 53:
Zero Cross Status Register
Address
Register Name
Features and Bit Description
SPI4
SPI3
R
R
POR
Value
Indicates which cell voltage has crossed
zero voltage and reached negative
during sudden loading condition. This
indirectly indicates the increasing status
of cell internal impedance.
0x06
AS8506 – 58
D0
0 → Cell 1 voltage is normal
1 → Cell 1 voltage has
crossed zero voltage towards
negative direction
D1
0 → Cell 2 voltage is normal
1 → Cell 2 voltage has
crossed zero voltage towards
negative direction
D2
0 → Cell 3 voltage is normal
1 → Cell 3 voltage has
crossed zero voltage towards
negative direction
D3
0 → Cell 4 voltage is less than
reference voltage
1 → Cell 4 voltage is more
than reference voltage
D4
0 → Cell 5 voltage is normal
1 → Cell 5 voltage has
crossed zero voltage towards
negative direction
D5
0 → Cell 6 voltage is normal
1 → Cell 6 voltage has
crossed zero voltage towards
negative direction
D6
0 → Cell 7 voltage is normal
1 → Cell 7 voltage has
crossed zero voltage towards
negative direction
D7
Reserved
zero_crs_stat_reg
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
Figure 54:
Cell1 Voltage LSB Register
Address
0x07
Register Name
cell1_volt_lsb_reg
Features and Bit Description
Cell1 voltage measured. 8 least
significant bits of 12-bit ADC code of
Cell1
D7:D0
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
Bit7 to Bit0 of ADC code
Figure 55:
Cell1 Voltage MSB Register
Address
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
Cell1 voltage measured. 4 most
significant bits of 12-bit ADC code of
Cell1
0x08
cell1_volt_msb_reg
D3:D0
Bit11 to Bit8 of ADC code
D7:D4
Reserved
Figure 56:
Cell2 Voltage LSB Register
Address
0x09
Register Name
Cell2_volt_lsb_reg
Features and Bit Description
Cell2 voltage measured. 8 least
significant bits of 12-bit ADC code of
Cell2
D7:D0
ams Datasheet, Confidential:2013-Sep [1-00]
Bit7 to Bit0 of ADC code
AS8506 – 59
Device Inter face
Figure 57:
Cell2 Voltage MSB Register
Address
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
Cell2 voltage measured. 4 most
significant bits of 12-bit ADC code of
Cell2
0x0A
cell2_volt_msb_reg
D3:D0
Bit11 to Bit8 of ADC code
D7:D4
Reserved
Figure 58:
Cell3 Voltage LSB Register
Address
0x0B
Register Name
cell3_volt_lsb_reg
Features and Bit Description
Cell3 voltage measured. 8 least
significant bits of 12-bit ADC code of
Cell3
D7:D0
Bit7 to Bit0 of ADC code
Figure 59:
Cell3 Voltage MSB Register
Address
Register Name
Features and Bit Description
Cell3 voltage measured. 4 most
significant bits of 12-bit ADC code of
Cell3
0x0C
cell3_volt_msb_reg
D3:D0
Bit11 to Bit8 of ADC code
D7:D4
Reserved
Figure 60:
Cell4 Voltage LSB Register
Address
0x0D
Register Name
cell4_volt_lsb_reg
Features and Bit Description
Cell4 voltage measured. 8 least
significant bits of 12-bit ADC code of
Cell4
D7:D0
AS8506 – 60
Bit7 to Bit0 of ADC code
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
Figure 61:
Cell4 Voltage MSB Register
Address
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
Cell4 voltage measured. 4 most
significant bits of 12-bit ADC code of
Cell4
0x0E
cell4_volt_msb_reg
D3:D0
Bit11 to Bit8 of ADC code
D7:D4
Reserved
Figure 62:
Cell5 Voltage LSB Register
Address
0x0F
Register Name
cell5_volt_lsb_reg
Features and Bit Description
Cell5 voltage measured. 8 least
significant bits of 12-bit ADC code of
Cell5
D7:D0
Bit7 to Bit0 of ADC code
Figure 63:
Cell5 Voltage MSB Register
Address
Register Name
Features and Bit Description
Cell5 voltage measured. 4 most
significant bits of 12-bit ADC code of
Cell5
0x10
cell5_volt_msb_reg
D3:D0
Bit11 to Bit8 of ADC code
D7:D4
Reserved
Figure 64:
Cell6 Voltage LSB Register
Address
0x11
Register Name
cell6_volt_lsb_reg
Features and Bit Description
Cell6 voltage measured. 8 least
significant bits of 12-bit ADC code of
Cell6
D7:D0
ams Datasheet, Confidential:2013-Sep [1-00]
Bit7 to Bit0 of ADC code
AS8506 – 61
Device Inter face
Figure 65:
Cell6 Voltage MSB Register
Address
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
Cell6 voltage measured. 4 most
significant bits of 12-bit ADC code of
Cell6
0x12
cell6_volt_msb_reg
D3:D0
Bit11 to Bit8 of ADC code
D7:D4
Reserved
Figure 66:
Cell7 Voltage LSB Register
Address
0x13
Register Name
cell7_volt_lsb_reg
Features and Bit Description
Cell7 voltage measured. 8 least
significant bits of 12-bit ADC code of
Cell7
D7:D0
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
Bit7 to Bit0 of ADC code
Figure 67:
Cell7 Voltage MSB Register
Address
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
Cell7 voltage measured. 4 most
significant bits of 12-bit ADC code of
Cell7
0x14
cell7_volt_msb_reg
D3:D0
Bit11 to Bit8 of ADC code
D7:D4
Reserved
Figure 68:
Temperature Input1 LSB Register
Address
0x15
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
temp_in1_lsb_reg
Temperature sensor input1 measured.
8 least significant bits of 12-bit ADC
code of temperature input1.
R
R
0000_0000
POR_V5V
D7:D0
AS8506 – 62
Bit7 to Bit0 of ADC code
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
Figure 69:
Temperature Input1 MSB Register
Address
0x16
Register Name
temp_in1_msb_reg
Features and Bit Description
Temperature sensor input1
measured. 4 most significant bits of
12-bit ADC code of temperature
input1.
D3:D0
Bit11 to Bit8 of ADC code
D7:D4
Reserved
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
Figure 70:
Temperature Input2 LSB Register
Address
0x17
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
temp_in2_lsb_reg
Temperature sensor input2 measured.
8 least significant bits of 12-bit ADC
code of temperature input1.
R
R
0000_0000
POR_V5V
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
D7:D0
Bit7 to Bit0 of ADC code
Figure 71:
Temperature Input2 MSB Register
Address
Register Name
Features and Bit Description
Temperature sensor input2 measured.
4 most significant bits of 12-bit ADC
code of temperature input2.
0x18
temp_in2_msb_reg
D3:D0
Bit11 to Bit8 of ADC code
D7:D4
Reserved
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 63
Device Inter face
Figure 72:
SPI3 Status Register
Address
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
This register has status of the latest SPI3
operation.
0x19
spi3_sts_reg
D0
0 → No CRC error.
1 → CRC error for data from
Master to Slave
D1
0 → No CRC error.
1 → CRC error for data from
Slave to Master
D2
0 → Start address allocation
process write pass
1 → Start address allocation
process write fail
D7:D3
AS8506 – 64
Reserved
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
Configuration and 3-Wire SPI Interface Related
Registers
Figure 73:
Device Address for Address Allocation Register
Address
0x1A
Register Name
dadd_for_allc_reg
Features and Bit Description
The device address for address
allocation. In the address allocation
process the μC writes top device
address in this register. Address
“00000” is reserved as broadcast
address.
D5:D0
Device address
D7:D6
Reserved
SPI4
SPI3
POR
Value
R/W
R/W
0000_0000
POR_VSUP
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_VSUP
SPI4
SPI3
POR
Value
R/W
-
0000_0000
POR_VSUP
Figure 74:
Allocated Device Address Register
Address
Register Name
Features and Bit Description
Final device address after address
allocation process is completed
0x1B
allcd_dev_add_reg
D5:D0
Device address
D7:D6
Reserved
Figure 75:
Device Configuration Setting Register
Address
Register Name
Features and Bit Description
Selects SPI3 frequency of operation.
0x1C
dev_cnfg_setg_reg
D1:D0
00 → 5 KHz
01 → 20 KHz
10 → 40 KHz
11 → Reserved
D7:D2
Reserved
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 65
Device Inter face
Figure 76:
Temperature Threshold Setting Register
Address
Register
Name
Features and Bit Description
SPI4
SPI3
POR
Value
R/W
XXXX_
XXXX
POR_
VSUP
Sets over-temperature warning flag and
shutdown flag threshold.
D3:D0
Over temperature warning flag
threshold selection
Code Value Code Value Code Value
0x1D
0000
0001
0010
0011
0100
0101
tflg_tshld_setg
_reg
D7:D4
3.165
3.231
3.297
3.363
3.429
3.495
0110
0111
1000
1001
1010
1011
3.561
3.627
3.693
3.759
3.825
3.891
1100
1101
1110
1111
-
3.957
4.023
4.089
4.155
-
R/W
Over temperature shutdown flag
threshold selection
Code Value Code Value Code Value
0000
0001
0010
0011
0100
0101
AS8506 – 66
3.165
3.231
3.297
3.363
3.429
3.495
0110
0111
1000
1001
1010
1011
3.561
3.627
3.693
3.759
3.825
3.891
1100
1101
1110
1111
-
3.957
4.023
4.089
4.155
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
Figure 77:
Timer Control Register
Address
0x1E
Register Name
timer_cntl_reg
Features and Bit Description
D2:D0
000 → 25% duty cycle
001 → 15% duty cycle
010 → 20% duty cycle
011 → 30% duty cycle
100 → 35% duty cycle
101 → 40% duty cycle
110 → 45% duty cycle
111 → 50% duty cycle
D4:D3
00 → 1s time slot
01 → 8s time slot
10 → 16s time slot
11 → 32s time slot
D6:D5
00 → 100 KHz
01 → 25 KHz
10 → 50 KHz
11 → 200 KHz
D7
SPI4
SPI3
POR
Value
R/W
R/W
0000_0000
POR_VSUP
SPI4
SPI3
POR
Value
R/W
R/W
0000_0000
POR_VSUP
0 → 5 clock cycles for
comparator
1 → 15 clock cycles for
comparator
Figure 78:
Reference DAC Code LSB Register
Address
Register Name
Features and Bit Description
Least Significant byte of 12-bit DAC
code for setting reference voltage.
0x1F
ref_dcod_lsb_reg
D7:D0
ams Datasheet, Confidential:2013-Sep [1-00]
Bit7 to Bit0 of DAC
code
AS8506 – 67
Device Inter face
Figure 79:
Reference DAC Code MSB Register
Address
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
R/W
R/W
0000_0000
POR_VSUP
SPI4
SPI3
POR
Value
R/W
R/W
0000_0000
POR_VSUP
SPI4
SPI3
POR
Value
R/W
R/W
0000_0000
POR_VSUP
SPI4
SPI3
POR
Value
R/W
R/W
0000_0000
POR_VSUP
Most Significant byte of 12-bit DAC
code for setting reference voltage.
0x20
ref_dcod_msb_reg
D3:D0
Bit11 to Bit8 of DAC
code
D7:D4
Reserved
Figure 80:
Higher Limit DAC Code LSB Register
Address
Register Name
Features and Bit Description
Least Significant byte of 12-bit DAC
code for setting high limit voltage.
0x21
hlmt_dcod_lsb_reg
D7:D0
Bit7 to Bit0 of DAC
code
Figure 81:
Higher Limit DAC Code MSB Register
Address
Register Name
Features and Bit Description
Most Significant byte of 12-bit DAC
code for setting high limit voltage.
0x22
hlmt_dcod_msb_reg
D3:D0
Bit11 to Bit8 of DAC
code
D7:D4
Reserved
Figure 82:
Lower Limit DAC Code LSB Register
Address
Register Name
Features and Bit Description
Least Significant byte of 12-bit DAC
code for setting low limit voltage.
0x23
llmt_dcod_lsb_reg
D7:D0
AS8506 – 68
Bit7 to Bit0 of DAC
code
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
Figure 83:
Lower Limit DAC Code MSB Register
Address
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
R/W
R/W
0000_0000
POR_VSUP
SPI4
SPI3
POR
Value
R/W
-
0000_0000
POR_V5V
Most Significant byte of 12-bit DAC
code for setting low limit voltage.
0x24
llmt_dcod_msb_reg
D3:D0
Bit11 to Bit8 of DAC
code
D7:D4
Reserved
Figure 84:
Device Address and Broadcast Command SPI Operation Register
Address
Register Name
Features and Bit Description
Device address/ broadcast command
register
If spi3_cmd_reg [D3-D1] =
001/010
Address of Device to be
accessed.
(000000 address is broadcast
address)
0x25
spop_dadd_bcmd
_reg
D5:D0
If spi3_cmd_reg [D3-D1] =
100
Broadcast communication
commands.
000000 → No operation
000001 → Timer control
register write
000010 → Cell reference DAC
code write
000011 Cell lower limit DAC
code write
000100 → Cell higher limit
DAC code write
If spi3_cmd_reg [D3-D1] =
101
000000 → Data of register
wrop_data_reg is written to
address stored in
spop_reg_add_reg in all
devices.
D7:D6
ams Datasheet, Confidential:2013-Sep [1-00]
Reserved
(accessible only in Master
mode)
AS8506 – 69
Device Inter face
Figure 85:
SPI Operation Register Address Register
Address
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
R/W
-
0000_0000
POR_V5V
SPI4
SPI3
POR
Value
R/W
-
0000_0000
POR_V5V
Address of register to be accessed
during 3-wire read/write operation in
the device selected in
spop_dadd_bcmd_reg
0x26
spop_reg_add_reg
D6:D0
Address of Register to
be accessed (R/W)
D7:D4
Reserved
(accessible only in
Master mode)
Figure 86:
SPI Write Operation Data Register
Address
0x27
Register Name
wrop_data_reg
Features and Bit Description
Data to be written in the register
addressed by spop_reg_add_reg of
device selected in
spop_dadd_bcmd_reg during SPI3
write operation.
D7:D0
AS8506 – 70
Bit7 to Bit0 of accessed
register
(accessible only in
Master mode)
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
Figure 87:
SPI3 Command Register
Address
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
R/W
-
0000_0000
POR_V5V
SPI4
SPI3
POR
Value
R/W
R/W
0000_0000
POR_VSUP
3-wire SPI command register. Register is
cleared once the SPI3 transaction is
done.
D0
0x28
0 → No SPI3 operation
1 → Start SPI3 operation
corresponding to
command code
D3:D1
000 → Reserved
001 → Slave register Read
010 → Slave register Write
011 → Start address
allocation process
100 → Broadcast
configuration command
101 → Broadcast Slave
register Write
110 → Reserved
111 → Reserved
D7:D4
Reserved
spi3_cmd_reg
Figure 88:
SPI Read Operation Data Register
Address
0x29
Register Name
rdop_data_reg
Features and Bit Description
Read data from the register
addressed by spop_reg_add_reg of
device selected in
spop_dadd_bcmd_reg during SPI3
read operation.
D7:D0
ams Datasheet, Confidential:2013-Sep [1-00]
Bit7 to Bit0 of accessed
register
(accessible only in
Master mode)
AS8506 – 71
Device Inter face
Figure 89:
Feature Selection Register 1
Address
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
R/W
R/W
0000_0000
POR_VSUP
Feature selection register1.
D0
D2:D1
0x2A
AS8506 – 72
1 → Zero cross
detection enable
Zero cross detection
filter setting
00 → 8μs
01 → 6μs
10 → 4μs
11 → 2μs
D3
Reserved
D4
1 → External resistor
divider enable
feat_sel_reg_1
D5
0 → Cell reference is
generated from DAC
1 → Cell reference is
supplied externally on
VREF_IN pin
D6
0 → Cell Lower/Higher
limit is generated from
DAC
1 → Cell Lower/Higher
limit is supplied
externally on CELL_THL
and CELL_THU pins
D7
Reserved
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
Figure 90:
Feature Selection Register 2
Address
Register Name
Features and Bit Description
SPI4
SPI3
POR
Value
R/W
-
0000_0010
POR_V5V
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
Feature selection register2.
0x2B
feat_sel_reg_2
D1:D0
FD_OUT pad
configuration
10 → Optocoupler
driver
11 → Normal Pad
D7:D2
Reserved
Note: Registers from address 0x2C to 0x2F are ‘Reserved’.
OTP Reflection Registers
Figure 91:
OTP Reflection Register 1
Address
Register Name
Features and Bit Description
0x30
otp_refln_reg_1
D7:D0
OTP bits [0:7]
Chip ID [0:7]
Figure 92:
OTP Reflection Register 2
Address
Register Name
Features and Bit Description
0x31
otp_refln_reg_2
D7:D0
ams Datasheet, Confidential:2013-Sep [1-00]
OTP bits [8:15]
Chip ID [8:15]
AS8506 – 73
Device Inter face
Figure 93:
OTP Reflection Register 3
Address
Register Name
Features and Bit Description
0x32
otp_refln_reg_3
D7:D0
OTP bits [16:23]
Chip ID [16:18], OTP bits
[19:23]
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
Figure 94:
OTP Reflection Register 4
Address
Register Name
Features and Bit Description
0x33
otp_refln_reg_4
D7:D0
OTP bits [24:31]
Figure 95:
OTP Reflection Register 5
Address
Register Name
Features and Bit Description
0x34
otp_refln_reg_5
D7:D0
OTP bits [32:39]
Figure 96:
OTP Reflection Register 6
Address
Register Name
Features and Bit Description
0x35
otp_refln_reg_6
D7:D0
AS8506 – 74
OTP bits [40:47]
ams Datasheet, Confidential:2013-Sep [1-00]
Device Inter face
Figure 97:
OTP Reflection Register 7
Address
Register Name
Features and Bit Description
0x36
otp_refln_reg_7
D7:D0
OTP bits [48:55]
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
SPI4
SPI3
POR
Value
R
R
0000_0000
POR_V5V
Figure 98:
OTP Reflection Register 8
Address
Register Name
Features and Bit Description
0x37
otp_refln_reg_8
D7:D0
OTP bits [56:63]
Note(s) and/or Footnote(s):
1. Registers from address 0x38 to 0x39 are ‘Reserved’.
2. Registers from address 0x3A to 0x4E are OTP and Test registers. These are for factory use.
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 75
Application Information
Application Information
Figure 99:
Application Schematic with Single Device
3
37
36
35
34
33
32
BD_IN
FD_IN
WAKE_OUT
100nF
31
V5V_IN
TSECL
38
CVT_NOK_IN
2
39
CLK_OUT
VREF_H
TSECH
VSUP
TSECL
1
MS_SL
40
TSECH
TRIG_OUT
VSUP
V5V
REF_T
VREF_T
29
TEMP_IN1
28
VCELL6
TEMP_IN2
27
VCELL5
CELL_THL
26
CELL_THU
25
VCELL7
2-5uF
30
TL1
NTC
TL2
Optional fixed
reference
5
6
VCELL4
AS8506
VCELL1
SDI
22
NC
11
12
13
14
15
16
17
18
R
6R
RF
2
TH
U
R2
SCLK
TSECH
R3
SDI
SDO
21
R
1
CS
Note: Max current on REF_T is 900uA
including the Temperature sensors
20
CS
SCLK
SDI
SDO
Note: Open drain on
WAKE_IN pin in the µC
or Transistor as shown
above.
Passive balancing
TSECL
SDO
R
1
THL
BD
CVT_NOK
CLK
TRIG
VREF_IN
19
NC_T
C-GND
WAKE_IN
10
RF
1
FD_OUT
9
BD_OUT
23
CVT_NOK_OUT
24
SCLK
CLK_IN
CS
VCELL2
TRIG_IN
VCELL3
8
GND
7
VREF_IN
VREF_T
4
WAKE
BD
Microcontroller
CVT_NOK
CLK
TRIG
RLoad
Supply from Stack
TSECH
100 mA load
TSECL
Optional factory setting for
Active balancing
AS8506 – 76
ams Datasheet, Confidential:2013-Sep [1-00]
Application Information
Passive balance
Passive balance is to dissipate the energy from the cell with the
higher cell voltage to the reference value (average of the stack
e.g. max cell voltage in constant voltage charge phase or mean
cell voltage as genertaed by resitor divider).
Resistor value should be selected based on the cell chemistry
and voltage limits. Maximum current capability of internal
shuttle switch is 100mA. Internal resistance of the shuttle
switch typically is 5Ω..
Active balance
In the active balance device charge the cells which are lower
than the reference voltage. This is a method of charge transfer
from the stack to the cell.
Flyback converter is used for this charge transfer. Active
balancing mode need to be enabled by factory setting. It is not
available for the default ASSP.
Flyback Converter (with external Transformer)
The high-efficiency, high-voltage, DC-DC Flyback converter
delivers current of 100mA to the lithium ion cell when the
secondary side of the Flyback transformer is connected to the
cell terminals. This also gives the isolation between the primary
supply and the load cell. The Flyback converter is designed to
charge the lithium-ion battery cells during the balancing mode
of the IC. It consists of a PWM waveform generator with variable
duty cycle and a driver. This driver can drive an external
MOSFET, (or) the optocoupler, (or) an isolation device based on
the requirement. During the ON-state of the PWM waveform,
the primary side of the Flyback transformer conducts and stores
the energy. In the other phase the stored energy in the
secondary is transferred to the cell which will be connected to
the secondary side of the transformer. The converter always
works in discontinuous current mode (DCM).
The advantages of this type of control system can be
summarized as following:
• High-efficiency even at light load
• Intrinsically stable
• Simplicity
Figure 100:
External Components
Component
Manufacturer Part Number
Manufacturer
Transformer
WE-FLEX 749196111
WURTH ELECTRONICS
Optocoupler
ACPL-M72T-000E
AVAGO TECHNOLOGIES
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 77
Application Information
Figure 101:
Application with Opto-Coupler/ Isolation Device
VREF_H2
VCELL7
4
VCELL6
5
35
34
33
32
31
V5V_U
V5V_IN
3
36
WAKE_OUT
TSECL
37
FD_IN
2
38
BD_IN
TSECL2
39
CVT_NOK_IN
7
TSECH
CLK_OUT
VREF_H
1
TRIG_OUT
40
TSECH2
VSUP
VSUP2
MS_SL
VSUP2
V5V
REF_T
30
29
100nF
2-5uF
TU1
6
5
TEMP_IN1
28
TEMP_IN2
27
VCELL5
CELL_THL
26
6
VCELL4
CELL_THU
25
7
VCELL3
CS
24
8
VCELL2
SCLK
23
9
VCELL1
SDI
22
SDO
21
AS8506
MLF 6x6
VSUP1
TU2
NTC
TU1
GND
(Exposed Pad)
17
18
39
38
37
36
35
34
VSUP
TRIG_OUT
CLK_OUT
CVT_NOK_IN
BD_IN
19
20
33
32
31
WAKE_OUT
16
FD_IN
15
TU2
VSUP1
VSUP1
Note: If slave has to drive
FD pin then SDI has to be
connected local ground
R
FD_OUT2
6R
FD_OUT
14
VREF_IN2
BD_OUT
13
NC_T
CVT_NOK_OUT
12
WAKE_IN
CLK_IN
VSUP1
TRIG_IN
NC
11
GND
C-GND
VREF_IN
10
MS_SL
1
NTC
VREF_H1
VREF_H
1
TSECH
TSECL1
2
TSECL
3
VCELL7
4
VCELL6
5
V5V
V5V_IN
40
TSECH1
V5V
REF_T
30
6
100nF
29
2-5uF
7
TL1
TEMP_IN1
28
TEMP_IN2
27
VCELL5
CELL_THL
26
6
VCELL4
CELL_THU
25
7
VCELL3
CS
24
CS
SCLK
23
SCLK
SDI
22
SDI
SDO
21
SDO
AS8506
MLF 6x6
TL2
NTC
TL2
TL1
5
15
16
17
18
NC_T
14
WAKE_IN
13
FD_OUT
12
BD_OUT
NC
11
CVT_NOK_OUT
C-GND
CLK_IN
10
TRIG_IN
VCELL1
GND
VCELL2
9
VREF_IN
1
8
GND
(Exposed Pad)
19
NTC
20
R
6R
WAKE_IN
BD
CVT_NOK
CLK
TRIG
VREF_IN1
CS
SCLK
SDI
SDO
WAKE
BD
CVT_NOK
Micro
controller
CLK
TRIG
Optional Factory Setting for Active Balancing
TSECH1
Supply from Stack
100 mA load
TSECH2
Note: Open drain on WAKE_IN
pin in the µC or Transistor as
shown above.
TSECL1
100 mA load
TSECL2
100 V device
Non-inverting
Optocoupler/
isolation device
FD_OUT2
100 V device
Converter
for active
balancing
Caution: In the application it’s recommended to connect the AS8506 devices stacked first and connect the
battery stack from bottom to top in sequence to avoid any possible damage of the system. While removing
the battery pack its strictly recommended to remove the battery pack from the top. Removing the battery
pack from bottom will damage the system.
AS8506 – 78
ams Datasheet, Confidential:2013-Sep [1-00]
Application Information
Figure 102:
Application Schematic
VREF_H2
6
5
36
35
34
33
32
31
V5V_U
V5V_IN
TSECL
37
WAKE_OUT
2
38
FD_IN
TSECL2
39
BD_IN
TSECH
CVT_NOK_IN
1
CLK_OUT
VREF_H
TSECH2
TRIG_OUT
40
7
VSUP
VSUP2
MS_SL
VSUP2
V5V
30
REF_T
29
TEMP_IN1
28
VCELL6
TEMP_IN2
27
5
VCELL5
CELL_THL
26
6
VCELL4
CELL_THU
25
7
VCELL3
8
VCELL2
9
VCELL1
10
C-GND
3
VCELL7
4
AS8506
MLF 6x6
GND
(Exposed Pad)
1
NTC
24
23
SDI
22
CVT_NOK_OUT
BD_OUT
FD_OUT
15
16
17
18
19
SDO
NTC
TU2
VSUP1
Note: If slave has to
drive FD pin then SDI
has to be connected
local ground
21
20
R
CLK_IN
14
6
R
CS
NC_T
TRIG_IN
13
WAKE_IN
GND
NC
12
VREF_IN2
TU2
TU1
SCLK
2-5uF
VSUP1
V5V_U
VREF_IN
11
VSUP1
100nF
TU1
6
33
32
31
V5V_IN
34
WAKE_OUT
4
35
FD_IN
VCELL7
36
BD_IN
TSECL
3
37
CVT_NOK_IN
2
38
CLK_OUT
TSECL1
39
TRIG_OUT
TSECH
VSUP
7
VREF_H
1
MS_SL
VREF_H1
40
TSECH1
V5V
V5V
30
REF_T
29
TEMP_IN1
28
VCELL6
TEMP_IN2
27
5
VCELL5
CELL_THL
26
6
VCELL4
CELL_THU
25
7
VCELL3
AS8506
MLF 6x6
100nF
TL2
NTC
15
16
17
18
R
19
24
CS
23
SCLK
SDI
22
SDI
SDO
21
SDO
20
WAKE_IN
BD
CVT_NOK
CLK
TRIG
6
14
R
VREF_IN1
13
CS
SCLK
NC_T
FD_OUT
12
WAKE_IN
BD_OUT
NC
11
CVT_NOK_OUT
C-GND
CLK_IN
10
1
TRIG_IN
VCELL1
GND
VCELL2
9
GND
(Exposed Pad)
VREF_IN
8
NTC
TL2
TL1
5
2-5uF
TL1
CS
SCLK
SDI
SDO
WAKE
BD
CVT_NOK
Micro
Controller
CLK
Optional Factory Setting for Active Balancing
TSECH1
Supply from Stack
Note: Open drain on
WAKE_IN pin in the µC or
Transistor as shown
above.
TRIG
100 mA load
TSECL1
TSECH2
100 mA load
TSECL2
100 V device
Converter
for active
balancing
Caution: In the application it’s recommended to connect the AS8506 devices stacked first and connect the
battery stack from bottom to top in sequence to avoid any possible damage of the system. While removing
the battery pack its strictly recommended to remove the battery pack from the top. Removing the battery
pack from bottom will damage the system.
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 79
Application Information
Figure 103:
Application with Opto-Coupler Device Stackable to Higher Numbers
12V / 5V
Vcc / V Auxiliary
Stack n+1
AS8506
Cellx of
stackn
Optocoupler
VCC
Vb
RL
Vo
Stack n
Stack
Ground
AS8506
100KHz
12V / 5V
Vcc / V Auxiliary
Cellx of
stack2
Optocoupler
VCC
RL
Vb
Vo
Stack2
AS8506
Stack
Ground
FDRIVE_OUT
Vcc
Cellx of
stack1
Stack1
AS8506
FDRIVE_OUT(100KHz
Stack
Ground
Caution:: In the application it’s recommended to connect the AS8506 devices stacked first and connect the
battery stack from bottom to top in sequence to avoid any possible damage of the system. While removing the
battery pack its strictly recommended to remove the battery pack from the top. Removing the battery pack
from bottom will damage the system.
AS8506 – 80
ams Datasheet, Confidential:2013-Sep [1-00]
Pa c k a g e D r a w i n g s & M a r k i n g s
Package Drawings & Markings
The AS8506 device is available in a 40-pin MLF (6x6) package.
Figure 104:
AS8506 Package Drawings and Dimensions
AS8506
YYWWIZZ
(A)
Note: ‘A’ is for active balancing and default is Passive Balancing.
Symbol
Min
Nom
Max
Symbol
A
A1
A2
A3
L
L1
L2
Θ
b
b1
D
E
0.80
0
-
0.90
0.02
0.65
0.20 REF
0.40
0.15
0.10
0.25
0.15
6.00 BSC
6.00 BSC
1.00
0.05
1.00
e
D1
E1
D2
E2
aaa
bbb
ccc
ddd
eee
fff
N
0.30
0.05
0.05
0º
0.20
0.10
ams Datasheet, Confidential:2013-Sep [1-00]
0.50
0.25
0.15
14º
0.30
0.20
Min
4.40
4.40
-
Nom
0.50 BSC
5.75 BSC
5.75 BSC
4.50
4.50
0.15
0.10
0.10
0.05
0.08
0.10
40
Max
4.60
4.60
-
AS8506 – 81
Pack age Drawings & Mark ings
Note(s) and/or Footnote(s):
1. Dimensions and toleranceing conform to ASME Y14.5M. - 1994.
2. All dimensions are in millimeters (angles in degrees).
3. Bilateral coplanarity zone applies to the exposed pad as well as the terminal.
4. Radius on terminal is optional.
5. N is the number of terminals.
Figure 105:
AS8506 Packaging Code YYWWXZZ
YY
WW
I
ZZ
Last two digits of the year
Manufacturing week
Plant identifier
Assembly traceability code
AS8506 – 82
ams Datasheet, Confidential:2013-Sep [1-00]
Pa c k a g e D r a w i n g s & M a r k i n g s
The AS8506C device is available in a 40-pin MLF (6x6) package.
Figure 106:
AS8506C Package Drawings and Dimensions
AS8506C
YYWWIZZ
(A)
Note: ‘A’ is for active balancing and default is Passive Balancing.
Symbol
Min
Nom
Max
Symbol
A
A1
A2
A3
L
L1
L2
Θ
b
b1
D
E
0.80
0
-
0.90
0.02
0.65
0.20 REF
0.40
0.15
0.10
0.25
0.15
6.00 BSC
6.00 BSC
1.00
0.05
1.00
e
D1
E1
D2
E2
aaa
bbb
ccc
ddd
eee
fff
N
0.30
0.05
0.05
0º
0.20
0.10
ams Datasheet, Confidential:2013-Sep [1-00]
0.50
0.25
0.15
14º
0.30
0.20
Min
4.40
4.40
-
Nom
0.50 BSC
5.75 BSC
5.75 BSC
4.50
4.50
0.15
0.10
0.10
0.05
0.08
0.10
40
Max
4.60
4.60
-
AS8506 – 83
Pack age Drawings & Mark ings
Note(s) and/or Footnote(s):
1. Dimensions and toleranceing conform to ASME Y14.5M. - 1994.
2. All dimensions are in millimeters (angles in degrees).
3. Bilateral coplanarity zone applies to the exposed pad as well as the terminal.
4. Radius on terminal is optional.
5. N is the number of terminals.
Figure 107:
AS8506C Packaging Code YYWWXZZ
YY
WW
I
ZZ
Last two digits of the year
Manufacturing week
Plant identifier
Assembly traceability code
AS8506 – 84
ams Datasheet, Confidential:2013-Sep [1-00]
RoHS Compliant & ams Green Statement
RoHS Compliant & ams Green
Statement
RoHS: The term RoHS compliant means that ams products fully
comply with current RoHS directives. Our semiconductor
products do not contain any chemicals for all 6 substance
categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, RoHS compliant products are
suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br): ams Green
defines that in addition to RoHS compliance, our products are
free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous
material).
Important Information: The information provided in this
statement represents ams knowledge and belief as of the date
that it is provided. ams bases its knowledge and belief on
information provided by third parties, and makes no
representation or warranty as to the accuracy of such
information. Efforts are underway to better integrate
information from third parties. ams has taken and continues to
take reasonable steps to provide representative and accurate
information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. ams
and ams suppliers consider certain information to be
proprietary, and thus CAS numbers and other limited
information may not be available for release.
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 85
Ordering & Contact Information
Ordering & Contact Information
The devices are available as the standard products shown in
Ordering Information.
Figure 108:
Ordering Information
Ordering Code
Description
Delivery Form
Package
Reel Size
AS8506-BQFP
Monitor and balancer IC
Tape and reel
40-pin MLF (6x6)
4000
AS8506-BQFM
Monitor and Balancer IC
Tape and Reel
40-Pin MLF (6x6)
1000
AS8506C-BQFP (1)
Monitor and Balancer IC
Tape and Reel
40-Pin MLF (6x6)
4000
AS8506C-BQFM (1)
Monitor and Balancer IC
Tape and Reel
40-Pin MLF (6x6)
1000
Note(s) and/or Footnote(s):
1. Non-automotive Version without AECQ 100 Qualification.
Buy our products or get free samples online at:
www.ams.com/ICdirect
Technical Support is available at:
www.ams.com/Technical-Support
For further information and requests, e-mail us at:
[email protected]
For sales offices, distributors and representatives, please visit:
www.ams.com/contact
Headquarters
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
AS8506 – 86
ams Datasheet, Confidential:2013-Sep [1-00]
Copyrights & Disclaimer
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141
Unterpremstaetten, Austria-Europe. Trademarks Registered. All
rights reserved. The material herein may not be reproduced,
adapted, merged, translated, stored, or used without the prior
written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent
indemnification provisions appearing in its Term of Sale. ams
AG makes no warranty, express, statutory, implied, or by
description regarding the information set forth herein. ams AG
reserves the right to change specifications and prices at any
time and without notice. Therefore, prior to designing this
product into a system, it is necessary to check with ams AG for
current information. This product is intended for use in
commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or
high reliability applications, such as military, medical
life-support or life-sustaining equipment are specifically not
recommended without additional processing by ams AG for
each application. This Product is provided by ams “AS IS” and
any express or implied warranties, including, but not limited to
the implied warranties of merchantability and fitness for a
particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out
of ams AG rendering of technical or other services.
ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 87
Reference Guide
Reference Guide
AS8506 – 88
1
2
2
3
General Description
Key Benefits & Features
Applications
Block Diagram
4
8
10
Pin Assignment
Absolute Maximum Ratings
Typical Operating Characteristics
11
11
12
13
13
14
14
15
16
16
17
18
18
19
19
20
Electrical Characteristics
Device Level Specifications
Low Dropout Regulator (5V Output LDO)
High-precision Bandgap Reference
Digital to Analog Converter
Analog to Digital Converter
Pre-Regulator
PWM Driver
PWM Oscillator
Oscillator for Digital Circuit
External Temperature Thresholds
Ron of the Shuttle Switches (Internal Switch for
Charging/Discharging)
Over-Temperature Measurement
Weak Cell Detection (Voltage Comparator)
Power on Voltage Detection
Electrical Characteristics for Digital Inputs and Outputs
22
22
22
22
23
23
23
23
24
24
24
24
24
25
26
28
29
29
29
30
30
30
31
32
33
35
36
Detailed Description
Voltage Regulator (LDO_5V)
High Precision Bandgap (HPBG)
External Temperature Monitor and Measurement
Internal Temperature Monitor
PWM Generator
RC Oscillator
DAC for the Reference Generation
SAR ADC
Pre-Regulator
Cell Threshold
Weak Cell Detection
External Resister Divider Control
PORs on Different Supplies
AS8506 System Operation
Functional State Diagram
Operating Modes
NORMAL Mode
Diagnosis Phase
Balance Phase
Sleep Mode
Wait Mode
Wake Mode
Wake-up Event
Trigger Event
Balancing Algorithm
Initialization Sequence
ams Datasheet, Confidential:2013-Sep [1-00]
Reference Guide
38
38
39
41
43
46
46
47
47
48
49
50
51
52
52
65
ams Datasheet, Confidential:2013-Sep [1-00]
73
Device Interface
Serial Peripheral Interface
SPI Write Operation
SPI Read Operation
Address Allocation Process
Communication to Slaves
Broadcast Communication
Communication with Individual Slave
Write operation.
Read operation.
SPI Timing Diagrams
SPI Protocol
System Timings
Register Space Description
Status Registers
Configuration and 3-Wire SPI Interface
Related Registers
OTP Reflection Registers
76
77
77
77
Application Information
Passive balance
Active balance
Flyback Converter (with external Transformer)
81
85
86
87
Package Drawings & Markings
RoHS Compliant & ams Green Statement
Ordering & Contact Information
Copyrights & Disclaimer
AS8506 – 89