White Electronic Designs EDI2GG464128V 4MB SYNCHRONOUS CARD EDGE DIMM FEATURES DESCRIPTION 4x128Kx64 Synchronous Access Speed(s): TKHQV = 9.5, 10, 11, 12, 15ns Flow-Through Architecture Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#) Clock Controlled Registered Address The EDI2KG64128VxxD is a Synchronous SRAM, 60 position Card Edge DIMM (120 contacts) Module, organized as 4x128Kx64. The Module contains eight (8) Synchronous Burst Ram Devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The module architecture is defined as a Synchronous Only, Flow-Through, Early Write Device. This module provides High Performance, Ultra Fast access times at a cost per bit benefit over BiCMOS Asynchronous SRAM based devices. As well as improved cost per bit, the use of Synchronous or Synchronous Burst devices or modules can ease the memory subsystem design by reducing or easing the memory controller requirement. Clock Controlled Registered Global Write (GW#) Aysnchronous Output Enable (G#) Internally self-timed Write Gold Lead Finish 3.3V +10%, -5% Operation Access Speed(s): tKHQV = 9.5, 10, 11, 12, 15ns Common Data I/O High Capacitance (30pf) drive, at rated Access Speed Single total array Clock Multiple Vcc and GND Synchronous operations are in relation to an externally supplied clock, Registered Address, Registered Global Write, Registered Enables as well as an Asynchronous Output enable. All read and write operations to this module are performed on Quad Words (64 bit operations). Write cycles are internally self timed and are initiated by a rising clock edge. This feature relieves the designer the task of developing external write pulse width circuitry. *This product is subject to change without notice. PIN NAMES October 2004 Rev. 1 DQ0-DQ63 Input/Output Bus A015 Address Bus E1#, E2#, E3#, E4# Synchronous Bank Enables CK Array Clock GW# Synchronous Global Write Enable G# Asynchronous Output Enable Vcc 3.3V Power Supply Vss Ground NC No Connect 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI2GG464128V PIN CONFIGURATION October 2004 Rev. 1 VSS A0 A1 A2 A3 VCC A4 A5 A6 A7 VSS A8 VSS CK VSS E4# VCC E3# G# VSS DQ0 DQ1 DQ2 DQ3 VCC DQ8 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 VSS A16 A15 A14 A13 VCC A12 A11 A10 A9 VSS RFU VSS NC VSS E2# VCC E1# GW# VSS DQ7 DQ6 DQ5 DQ4 VCC DQ15 DQ9 DQ10 DQ11 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ24 DQ25 DQ26 DQ27 VSS DQ32 DQ33 DQ34 DQ35 VCC DQ40 DQ41 DQ42 DQ43 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ56 DQ57 DQ58 DQ59 VSS 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 DQ14 DQ13 DQ12 VSS DQ23 DQ22 DQ21 DQ20 VCC DQ31 DQ30 DQ29 DQ28 VSS DQ39 DQ38 DQ34 DQ37 VCC DQ47 DQ46 DQ45 DQ44 VSS DQ55 DQ54 DQ53 DQ52 VCC DQ63 DQ62 DQ61 DQ60 VSS 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI2GG464128V FUNCTIONAL BLOCK DIAGRAM A0-16 GW# G# 128Kx32 GW# DQ G# E# CLK 128Kx32 GW# DQ G# E# CLK E1# 128Kx32 GW# DQ G# E# CLK 128Kx32 GW# DQ G# E# CLK E2 # 128Kx32 GW# DQ G# E# CLK 128Kx32 GW# DQ G# E# CLK E3# 128Kx32 GW DQ G# E# CLK 128Kx32 GW DQ G# E# CLK E4# DQ0-63 CLK October 2004 Rev. 1 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI2GG464128V PIN DESCRIPTIONS DIMM Pins Symbol Type 3, 5, 7, 9, 13, 15, 17, 19, 20, 23, 18, 16, 14, 10, 8, 6 A0-A15 Input Synchronous Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CK. The burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle. 38 GW# Input Synchronous Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CK. 27 CK Input Synchronous Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge. 36, 32, 35, 31 E1#, E2# E3#, E4# Input Synchronous Bank Enables: These active LOW inputs are used to enable each individual Synchronous bank and to gate ADSP#. 37 G# Input Various DQ0-63 Input/Output Various Vcc Supply Core power supply: +3.3V -5%/+10% Various Vss Ground Ground October 2004 Rev. 1 Description Output Enable: This active LOW asynchronous input enables the data output drivers. Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64. 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI2GG464128V SYNCHRONOUS ONLY – TRUTH TABLE Operation Synchronous Write-Bank 1 Synchronous Read-Bank 1 Synchronous Write-Bank 2 Synchronous Read-Bank 2 Synchronous Write-Bank 3 Synchronous Read-Bank 3 Synchronous Write-Bank 4 Synchronous Read-Bank 4 Snooze Mode E1# L L H H H H H H X E2# H H L L H H H H X E3# H H H H L L H H X ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Relative to Vss VIN Storage Temperature Operating Temperature (Commercial) Operating Temperature (Industrial) Short Circuit Output Current E4# H H H H H H L L X GW# L H L H L H L H X G# H L H L H L H L X CK DQ High-Z High-Z High-Z High-Z X High-Z RECOMMENDED DC OPERATING CONDITIONS -0.5V to +4.6V -0.5V to Vcc +0.5V -55°C to +125°C 0°C to +70°C -40°C to +85°C 20 mA * Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Supply Voltage Supply Voltage Input High Input Low Input Leakage Output Leakage Output High IOH = -4ma Sym VCC VSS VIH VIL ILI ILO VOH Min 3.14 0.0 2.2 -0.3 -2 -2 2.4 Typ 3.3 0.0 3.0 0.0 1 1 - Max 3.6 0.0 VCC + 0.3 0.8 2 2 - Units V V V V µA µA V Output Low IOL = 8ma VOL - - 0.4 V DC ELECTRICAL CHARACTERISTICS – READ CYCLE Symbol Typ 9.5 10 Max 11 12 15 Units Power Supply Current Icc1 1.55 2.8 2.2 2.2 2.7 2.0 A Power Supply Current Device Selected, No Operation Icc .75 1.8 1.5 1.3 1.3 1.0 A Snooze Mode IccZZ 200 300 300 300 300 300 mA CMOS Standby Icc3 400 500 500 500 500 500 mA Clock Running-Deselect IccK 600 900 900 900 900 900 mA Description *TBD AC TEST LOAD DQ AC TEST CONDITIONS Parameter Z0 Z0==50W 50Ω Input Pulse Levels Input and Output Timing Ref. Output Test Equivalencies 50Ω I/O Unit Vss to 3.0V 1.25 See figure at left V V V Vt = 1.25V Figure 1 – Output Load Equivalent October 2004 Rev. 1 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI2GG464128V READ CYCLE TIMING PARAMETERS 9.5ns 10ns 11ns 12ns 15ns Description Sym Min Max Min Clock Cycle Time tKHKH * * 12 12 15 20 ns Clock High Time tKHKL * * 5 5 5 6 ns Clock Low Time tKLKH * * 5 5 5 6 Clock to Output Valid tKHQV * * Clock to Output Invalid tKHQX1 * * 3 3 3 3 ns Clock to Output Low-Z tKHQX * * 2 2 2 2 ns Output Enable to Output Valid tGLQV * * Output Enable to Output Low-Z tGLQX * * Output Enable to Output High-Z tGHQZ * * Address Setup tAVKH * * 2.5 2.5 2.5 2.5 ns Bank Enable Setup tEVKH * * 2.5 2.5 2.5 2.5 ns Address Hold tKHAX * * 1.0 1.0 1.0 1.0 ns Bank Enable Hold tKHEX * * 1.0 1.0 1.0 1.0 ns Max Min Max 10 Max 11 4 0 Min 6 0 5 Units ns 15 5 0 4 Max 12 5 0 Min ns ns ns 5 5 ns *TBD WRITE CYCLE TIMING PARAMETERS 9.5ns 10ns 11ns 12ns 15ns Description Sym Min Max Min Clock Cycle Time tKHKH * * 12 12 15 20 ns Clock High Time tKHKL * * 5 5 5 6 ns Clock Low Time tKLKH * * 5 5 5 6 ns Address Setup tAVKH * * 2.5 2.5 2.5 2.5 ns Address Hold tKHAX * * 1.0 1.0 1.0 1.0 ns Bank Enable Setup tEVKH * * 2.5 2.5 2.5 2.5 ns Bank Enable Hold tKHEX * * 1.0 1.0 1.0 1.0 ns Global Write Enable Setup tWVKH * * 2.5 2.5 2.5 2.5 ns Global Write Enable Hold tKHWX * * 1.0 1.0 1.0 1.0 ns Data Setup tDVKH * * 2.5 2.5 2.5 2.5 ns Data Hold tKHDX * * 1.0 1.0 1.0 1.0 ns Max Min Max Min Max Min Max Units *TBD October 2004 Rev. 1 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI2GG464128V ORDERING INFORMATION Part Number Organization Voltage Speed (ns) Package Height* EDI2GG464128V95D* 4x128Kx64 3.3 9.5 120 Card Edge DIMM 28.58 (1.125”) EDI2GG464128V10D* 4x128Kx64 3.3 10 120 Card Edge DIMM 28.58 (1.125”) EDI2GG464128V11D 4x128Kx64 3.3 11 120 Card Edge DIMM 28.58 (1.125”) EDI2GG464128V12D 4x128Kx64 3.3 12 120 Card Edge DIMM 28.58 (1.125”) EDI2GG464128V15D* 4x128Kx64 3.3 15 120 Card Edge DIMM 28.58 (1.125”) *Consult Factory for Availability PACKAGE DESCRIPTION: 120 LEAD CARD EDGE DIMM 5.33 (0.210) MAX. 89.23 (3.513) MAX. 28.58 (1.125) MAX. 4.95 (0.195) 1.04 ± 0.05 (0.041 ± 0.002) 1.27 (0.050) TYP. 1.88 ±0.08 (0.074 ± 0.003) 31.75 (1.250) 34.54 ± 0.08 (1.360 ± 0.003) 3.81 (0.150) 5.08 (0.200) TYP. 41.91 (1.650) 5.08 (0.200) MIN. 44.70 ± 0.05 (1.760 ± 0.002) R 0.78 (0.031) (2x) R6 R3 R5 R2 ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES). October 2004 Rev. 1 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI2GG464128V Document Title 4MB SYNCHRONOUS CARD EDGE DIMM Revision History Rev # History Release Date Rev 0 Created July 1999 Rev 1 Corrected block diagram specs 10-25-04 October 2004 Rev. 1 8 Status White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com