BUZ71A Data Sheet June 1999 13A, 50V, 0.120 Ohm, N-Channel Power MOSFET Features This is an N-Channel enhancement mode silicon gate power field effect transistor designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. • rDS(ON) = 0.120Ω File Number 2419.2 • 13A, 50V • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance Formerly developmental type TA9770. • Majority Carrier Device Ordering Information PART NUMBER BUZ71A PACKAGE TO-220AB • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” BRAND BUZ71A NOTE: When ordering, use the entire part number. Symbol D G S Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) 4-17 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 BUZ71A TC = 25oC, Unless Otherwise Specified Absolute Maximum Ratings Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current, TC = 55oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSTG, TJ DIN Humidity Category - DIN 40040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEC Climatic Category - DIN IEC 68-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg BUZ71A 50 50 13 48 ±20 40 100 0.32 -55 to 150 E 55/150/56 UNITS V V A A V W mJ W/oC oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V 50 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 1mA (Figure 9) 2.1 3 4 V IDSS TJ = 25oC, VDS = 50V, VGS = 0V - 20 250 µA TJ = 125oC, VDS = 50V, VGS = 0V - 100 1000 µA VGS = 20V, VDS = 0V - 10 100 nA rDS(ON) ID = 9A, VGS = 10V (Figure 8) - 0.11 0.12 Ω gfs VDS = 25V, ID = 9A (Figure 11) 3.0 5.2 - S - 20 30 ns Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 2) IGSS Forward Transconductance (Note 2) Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time VCC = 30V, ID ≈ 3A, VGS = 10V, RGS = 50Ω, RL = 10Ω - 55 85 ns td(OFF) - 70 90 ns tf - 80 110 ns - 480 650 pF pF Fall Time Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 10) Output Capacitance COSS - 280 450 Reverse Transfer Capacitance CRSS - 160 280 pF Thermal Resistance Junction to Case RθJC ≤ 3.1 oC/W Thermal Resistance Junction to Ambient RθJA ≤ 75 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulsed Source to Drain Current ISDM Source to Drain Diode Voltage VSD Reverse Recovery Time trr Reverse Recovery Charge QRR TEST CONDITIONS TC = 25oC TC = 25oC TJ = 25oC, TJ = 25oC, VR = 30V MIN TYP MAX UNITS - - 13 A - - 52 A ISD = 26A, VGS = 0V, (Figure 12) - 1.6 2.2 V ISD = 13, dISD/dt = 100A/µs, - 120 - ns - 0.15 - µC NOTES: 2. Pulse Test: Pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 10V, TJ = 25oC, L = 820µH, IPEAK = 14A. (See Figures 14 and 15). 4-18 BUZ71A Typical Performance Curves Unless Otherwise Specified 15 POWER DISSIPATION MULTIPLIER 1.2 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 VGS ≥ 10V 10 5 0.2 0 0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 0 150 125 ZθJC, TRANSIENT THERMAL IMPEDANCE FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 50 100 TC, CASE TEMPERATURE (oC) 150 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 0.5 1 0.2 0.1 0.1 0.05 0.02 0.01 PDM SINGLE PULSE t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC 0.01 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101 FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE 102 30 101 TJ = MAX RATED TC = 25oC SINGLE PULSE 100µs 1ms 100 10-1 100 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms 100ms DC 101 102 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 4-19 103 PD = 40W VGS = 20V 10V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 5µs 10µs PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 8.0V 20 VGS = 7.5V VGS = 7.0V VGS = 6.5V VGS = 6.0V 10 VGS = 5.5V 0 VGS = 5.0V VGS = 4.5V VGS = 4.0V 0 4 6 2 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. OUTPUT CHARACTERISTICS 8 BUZ71A Unless Otherwise Specified (Continued) 15 0.4 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS = 25V TJ = 25oC VGS = 5V 5.5V 6V 6.5V 7V 7.5V 8V NORMALIZED ON RESISTANCE IDS(ON), DRAIN TO SOURCE CURRENT (A) Typical Performance Curves 10 5 0 0 5 VGS, GATE TO SOURCE VOLTAGE (V) 0.20 0.10 40 10V 80 20V 0.1 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0 0 4 VGS(TH), GATE THRESHOLD VOLTAGE (V) rDS(ON), DRAIN TO SOURCE ON RESISTANCE (Ω) VGS = 10V, ID = 9A PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0 9V 120 30 2 1 0 -50 0 50 100 150 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 6 VGS = 0, f = 1MHz CISS = CGS +CGD CRSS = CGD COSS ≈ CDS + CGS gfs, TRANSCONDUCTANCE (S) C, CAPACITANCE (nF) 25 3 160 FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 100 CISS COSS CRSS 10-1 10-2 10 15 20 ID, DRAIN CURRENT (A) VDS = VGS ID = 1mA TJ , JUNCTION TEMPERATURE (oC) 101 5 FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 0.30 -40 0.2 10 FIGURE 6. TRANSFER CHARACTERISTICS 0 0.3 0 10 20 30 VDS, DRAIN TO SOURCE VOLTAGE (V) 40 FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 4-20 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX o 5 VDS = 25V, TJ = 25 C 4 3 2 1 0 0 5 10 ID, DRAIN CURRENT (A) FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT 15 BUZ71A Typical Performance Curves 15 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 101 TJ = 150oC TJ = 25oC 100 10-1 0 ID = 18A VGS, GATE TO SOURCE VOLTAGE (V) ISD, SOURCE TO DRAIN CURRENT (A) 102 Unless Otherwise Specified (Continued) 0.5 1.0 1.5 2.0 2.5 VSD, SOURCE TO DRAIN VOLTAGE (V) VDS = 10V 10 VDS = 40V 5 0 3.0 0 5 15 10 20 25 Qg, GATE CHARGE (nC) FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 16. SWITCHING TIME TEST CIRCUIT 4-21 10% 50% 50% PULSE WIDTH FIGURE 17. RESISTIVE SWITCHING WAVEFORMS BUZ71A Test Circuits and Waveforms (Continued) VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 0.2µF VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd 0.3µF VGS Qgs D VDS DUT G 0 Ig(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 18. GATE CHARGE TEST CIRCUIT Ig(REF) 0 FIGURE 19. GATE CHARGE WAVEFORMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. 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