AVAGO HCPL-260L High speed lvttl compatible 3.3 volt optocouplers low power consumption Datasheet

HCPL-260L/060L/263L/063L
High Speed LVTTL Compatible 3.3 Volt Optocouplers
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The HCPL-260L/060L/263L/063L are optically coupled
gates that combine a GaAsP light emitting diode and
an integrated high gain photo detector. An enable input allows the detector to be strobed. The output of
the detector IC is an open collector Schottky-clamped
transistor. The internal shield provides a guaranteed
common mode transient immunity specification of
15 kV/µs at 3.3V.
• 3.3V/5V Dual Supply Voltages
This unique design provides maximum AC and DC circuit
isolation while achieving LVTTL/LVCMOS compati-bility. The optocoupler AC and DC operational parameters
are guaranteed from –40°C to +85°C allowing troublefree system performance.
• Low power consumption
• 15 kV/µs minimum Common Mode Rejection (CMR) at
VCM = 1000 V
• High speed: 15 MBd typical
• LVTTL/LVCMOS compatible
• Low input current capability: 5 mA
• Guaranteed AC and DC performance over temperature: –40°C to +85°C
• Available in 8-pin DIP, SOIC-8
• Strobable output (single channel products only)
These optocouplers are suitable for high speed logic
interfacing, input/output buffering, as line receivers in
environments that conventional line receivers cannot
tolerate and are recommended for use in extremely high
ground or induced noise environments.
• Safety approvals: UL, CSA, IEC/EN/DIN EN 60747-5-5
Functional Diagram
• Computer-peripheral interfaces
HCPL-260L/060L
1
8
VCC
ANODE
2
7
CATHODE
3
NC
4
SHIELD
ANODE 1
1
8
VCC
VE
CATHODE 1
2
7
VO1
6
VO
CATHODE 2
3
6
VO2
5
GND
ANODE 2
4
5
GND
TRUTH TABLE
(POSITIVE LOGIC)
LED
ENABLE
ON
OFF
ON
OFF
ON
OFF
H
H
L
L
NC
NC
OUTPUT
L
H
H
H
L
H
SHIELD
TRUTH TABLE
(POSITIVE LOGIC)
LED
OUTPUT
ON
OFF
L
H
• Isolated line receiver
• Microprocessor system interfaces
HCPL-263L/063L
NC
Applications
• Digital isolation for A/D, D/A conversion
• Switching power supply
• Instrument input/output isolation
• Ground loop elimination
• Pulse transformer replacement
• Field buses
A 0.1 µF bypass capacitor must be
connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
HCPL-xxxx is UL Recognized with 3750 Vrms for 1 minute per UL1577
Option
Part number
HCPL-260L
HCPL-263L
HCPL-060L
HCPL-063L
RoHS
Compliant
Non RoHS
Compliant
-000E
No option
-300E
-300
X
X
-500E
#500
X
X
-020E
-020
-320E
-320
-520E
-520
-060E
#060
-560E
#560
-000E
No option
-300E
Package
Surface
Mount
Gull
Wing
Tape
& Reel
UL 5000
Vrms/ 1 Minute rating
IEC/EN/DIN
EN 60747-5-5 Quantity
50 per tube
300mil
DIP-8
X
X
X
X
X
X
#300
X
X
-500E
#500
X
X
-020E
#020
-320E
-320
X
X
-520E
#520
X
X
-060E
-060
50 per tube
X
X
1000 per reel
X
50 per tube
X
50 per tube
X
X
1000 per reel
X
50 per tube
X
1000 per reel
50 per tube
300mil
DIP-8
-560E
-560
X
-000E
No option
X
-500E
#500
-060E
#060
-560E
-560
X
-000E
No option
X
-500E
#500
-060E
-060
-560E
-560
SO-8
SO-8
X
X
50 per tube
X
X
X
50 per tube
X
50 per tube
X
1000 per reel
X
50 per tube
X
1000 per reel
X
X
1500 per reel
X
100 per tube
X
1500 per reel
100 per tube
X
X
X
X
100 per tube
X
X
1000 per reel
X
1500 per reel
X
100 per tube
X
1500 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry. Combination of Option 020 and Option 060 is not available.
Example 1:
HCPL-260L-560E to order product of 300mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with
IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant.
Example 2:
HCPL-263L to order product of 300mil DIP package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use ‘-XXXE‘.
2
Schematic
HCPL-260L/060L
IF
HCPL-263L/063L
ICC
8
2+
IO
6
VF
VCC
VO
1
ICC
8
IF1
IO1
+
7
VF1
VCC
VO1
–
–
3
SHIELD
IE
5
7
GND
2
SHIELD
3
VE
IO2
–
USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED
BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5).
6
VF2
VO2
+
4
IF2
SHIELD
5
HCPL-260L Schematic a
HCPL-260L Schematic b
Package Outline Drawings
8-Pin DIP Package
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
TYPE NUMBER
8
7
6
5
OPTION CODE*
6.35 ± 0.25
(0.250 ± 0.010)
DATE CODE
A XXXXZ
YYWW RU
1
1.19 (0.047) MAX.
2
3
4
UL
RECOGNITION
1.78 (0.070) MAX.
5 TYP.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
0.65 (0.025) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
DIMENSIONS IN MILLIMETERS AND (INCHES).
* MARKING CODE LETTER FOR OPTION NUMBERS
"V" = OPTION 060
OPTION NUMBER 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
3
GND
8-Pin DIP Package with Gull Wing Surface Mount in Option 500
(HCPL-260L, HCPL-263L)
LAND PATTERN RECOMMENDATION
9.65 ± 0.25
(0.380 ± 0.010)
6
7
8
1.016 (0.040)
5
6.350 ± 0.25
(0.250 ± 0.010)
1
3
2
10.9 (0.430)
4
2.0 (0.080)
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
0.254
3.56 ± 0.13
(0.140 ± 0.005)
(0.010
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.130
(0.025 ± 0.005)
2.54
(0.100)
BSC
0.635 ± 0.25
(0.025 ± 0.010)
0.076
0.051
0.003
0.002)
12 NOM.
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
Small Outline SO-8 Package
LAND PATTERN RECOMMENDATION
8
7
6
5
XXXV
YWW
3.937 ± 0.127
(0.155 ± 0.005)
5.994 ± 0.203
(0.236 ± 0.008)
TYPE NUMBER
(LAST 3 DIGITS)
7.49 (0.295)
DATE CODE
PIN ONE 1
2
3
4
0.406 ± 0.076
(0.016 ± 0.003)
1.9 (0.075)
1.270 BSC
(0.050)
0.64 (0.025)
* 5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005)
7
1.524
(0.060)
0.228 ± 0.025
(0.009 ± 0.001)
0.203 ± 0.102
(0.008 ± 0.004)
0.305 MIN.
(0.012)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
OPTION NUMBER 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
4
0.432
(0.017)
0~7
* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
45 X
Reflow Soldering Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The HCPL-260L/060L/263L/063L have been approved by the following organizations:
UL
Approval under UL 1577, Component Recognition Program, File E55361.
CSA
Approval under CSA Component Acceptance Notice #5, File CA 88324.
IEC/EN/DIN EN 60747-5-5
Insulation and Safety Related Specifications
Parameter
Symbol
8-Pin DIP
(300 Mil)
Value
SO-8
Value
Units
Conditions
Minimum External Air
L (101)
7.1
4.9
mm
Gap (External Clearance)
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External Tracking
L (102)
7.4
4.8
mm
(External Creepage)
Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic
0.08
0.08
mm
Gap (Internal Clearance)
Through insulation distance, conductor
to conductor, usually the direct distance
between the photoemitter and
photodetector inside the optocoupler cavity.
Tracking Resistance
(Comparative Tracking Index)
DIN IEC 112/VDE 0303 Part 1
CTI
Isolation Group
5
200
200
Volts
IIIa
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics*
Description
Symbol
PDIP Option 060
SO-8 Option 060
Installation classification per DIN VDE 0110, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
I – IV
I – IV
I – III
I – IV
I – IV
I – III
Climatic Classification
40/85/21
40/85/21
Pollution Degree (DIN VDE 0110/39)
2
2
Unit
Maximum Working Insulation Voltage
VIORM
630
567
Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm=1 sec,
Partial discharge < 5 pC
VPR
1181
1063
Vpeak
Input to Output Test Voltage, Method a*
VIORM x 1.6 = VPR, Type and Sample Test, tm=10 sec, Partial
discharge < 5 pC
VPR
1008
907
Vpeak
Highest Allowable Overvoltage
(Transient Overvoltage tini = 60 sec)
VIOTM
6000
6000
Vpeak
Case Temperature
TS
175
150
°C
Input Current
IS, INPUT
230
150
mA
Output Power
PS, OUTPUT
600
600
mW
RS
≥109
≥109
W
Safety-limiting values
– maximum values allowed in the event of a failure.
Insulation Resistance at TS, VIO = 500 V
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-5, for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
6
HCPL-060L/HCPL-063L
800
PS (mW)
IS (mA)
700
600
500
400
300
200
100
0
0
25
50
75 100 125 150 175 200
TS – CASE TEMPERATURE – C
OUTPUT POWER – PS, INPUT CURRENT – IS
OUTPUT POWER – PS, INPUT CURRENT – IS
Thermal Derating Curve Figures
HCPL-260L/HCPL-263L
800
PS (mW)
IS (mA)
700
600
500
400
300
200
100
0
0
25
50
75 100 125 150 175 200
TS – CASE TEMPERATURE – C
Absolute Maximum Ratings (No Derating Required up to 85˚C)
Parameter
Symbol
Package**
Storage Temperature
TS
Operating Temperature†
TA
Min.
Max.
Units
–55
125
˚C
–40
85
˚C
mA
Note
Average Forward Input Current
IF
Single 8-Pin DIP
Single SO-8
20
Dual 8-Pin DIP
Dual SO-8
15
1, 3
Reverse Input Voltage
VR
8-Pin DIP, SO-8
5
V
1
Input Power Dissipation
PI
40
mW
Supply Voltage (1 Minute Maximum)
VCC 7
Enable Input Voltage (Not to Exceed
VE
VCC by more than 500 mV)
Single 8-Pin DIP
Single SO-8
VCC + 0.5
2
V
V
Enable Input Current
IE 5
mA
Output Collector Current
IO
mA
1
Output Collector Voltage
VO 7
V
1
50
Output Collector Power Dissipation
PO
Single 8-Pin DIP
Single SO-8
85
Dual 8-Pin DIP
Dual SO-8
60
**Ratings apply to all devices except otherwise noted in the Package column.
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Input Current, Low Level
IFL*
0
250
µA
Input Current, High Level[1]
IFH**
5
15
mA
Power Supply Voltage
VCC
2.7
4.5
3.6
5.5
V
Low Level Enable Voltage
VEL
0
0.8
V
High Level Enable Voltage
VEH
2.0
VCC
V
Operating Temperature
TA
–40
85
˚C
Fan Out (at RL = 1 kΩ)[1]
N
5
TTL Loads
Output Pull-up Resistor
RL
4k
Ω
330
*The off condition can also be guaranteed by ensuring that VFL ≤ 0.8 volts.
**The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be
used for best performance and to permit at least a 20% LED degradation guardband.
7
mW
1, 4
Electrical Specifications
Over Recommended Operating Conditions (TA = –40°C to +85°C , 2.7V ≤ VCC ≤ 3.6V) unless otherwise specified.
All Typicals at VCC = 3.3 V, TA = 25°C. All enable test conditions apply to single channel products only. See Note 5.
Parameter
Fig.
Note
High Level
IOH* 4.5
50
µA
VCC = 3.3 V, VE = 2.0 V,
Output Current VO = 3.3 V, IF = 250 µA
1
1, 15
Input Threshold
ITH 3.0
5.0
mA
VCC = 3.3 V, VE = 2.0 V,
Current VO = 0.6 V,
IOL (Sinking) = 13 mA
2
15
Low Level
VOL*
0.35
0.6
V
VCC = 3.3 V, VE = 2.0 V,
Output Voltage IF = 5 mA,
IOL (Sinking) = 13 mA
3
15
High Level
Sym.
ICCH
Supply Current
Low Level
ICCL
Device
Min.
Typ.
Max.
Units
mA
Test Conditions
Single
4.7
7.0
Dual
6.9
10.0
VCC = 3.3 V
VE = 0.5 V IF = 10 mA
mA
VE = 0.5 V IF = 0 mA
Single
7.0
10.0
Supply Current
Dual
8.7
15.0
VCC = 3.3 V
High Level
Enable Current
IEH
Single
–0.5
–1.2
mA
VCC = 3.3 V, VE = 2.0 V
Low Level
Enable Current
IEL*
Single
–0.5
–1.2
mA
VCC = 3.3 V, VE = 0.5 V
High Level
Enable Voltage
VEH
Single
Low Level
Enable Voltage
VEL
Single0.8
Input Forward
Voltage
VF
2.0V
1.4
1.5
1.75*
15
V
V
TA = 25˚C, IF = 10 mA
5
1
Input Reverse
BVR* 5V
IR = 10 µA
1
Breakdown
Voltage
Input Diode
Temperature
Coefficient
∆VF/–1.6mV˚C
IF = 10 mA
1
∆TA
Input
Capacitance
CIN
60
pF
*The JEDEC Registration specifies 0˚C to +70˚C. Avago specifies –40˚C to +85˚C.
8
f = 1 MHz, VF = 0 V
1
Electrical Specifications (DC)
Over recommended operating conditions (TA = -40°C to +85°C, 4.5V ≤ VDD ≤ 5.5V) unless otherwise specified.
All typicals at VCC = 5 V, TA = 25 °C.
Parameter
Symbol
High Level Output
Current
IOH
Input Threshold
Current
ITH
Low Level Output
Voltage
VOL
High Level Supply
Current
ICCH
Channel
Min.
Typ.*
Max.
Units
Test Conditions
Fig.
Note
5.5
100
mA
VCC = 5.5 V,
VO = 5.5 V,
IFL = 250 mA
1
1,15
Single
2.0
5.0
mA
2
15
Dual
2.5
VCC = 5.5 V, VO = 0.6 V,
IOL > 13 mA
0.35
0.6
V
VCC = 5.5 V, IF = 5 mA,
IOL(Sinking) = 13 mA
3
15
7.0
10.0
mA
VE =0.5V, VCC = 5.5 V,
IF = 0 mA
mA
VE =VCC, VCC = 5.5 V,
IF = 0 mA
Single
6.5
Low Level Supply
Current
ICCL
Dual
10.0
15.0
Single
9.0
13.0
8.5
9
VCC = 5.5 V, IF = 0 mA
mA
VE =0.5V, VCC = 5.5 V,
IF = 0 mA
mA
VE =VCC, Vv = 5.5 V,
IF = 0 mA
Dual
13.0
21.0
mA
VCC = 5.5 V, IF = 0 mA
High Level Enable
Current
IEH
Single
-0.7
-1.6
mA
VCC = 5.5 V, VE = 2.0V
Low Level Enable
Current
IEL
Single
-0.9
-1.6
mA
VCC = 5.5 V, VE = 0.5V
High Level Enable
Voltage
VEH
Single
Low Level Enable
Voltage
VEL
Single
Input Forward
Voltage
VF
Input Reverse
Breakdown Voltage
BVR
Input Diode
Temperature
Coefficient
ΔVF/ΔTA
Input Capacitance
CIN
2.0
1.4
15
V
0.8
V
1.75
V
TA = 25 °C, IF = 10 mA
1.8
V
IF=10mA
V
IR = 10 μA
1
-1.6
mV/°C
IF = 10 mA
1
60
pF
f = 1 MHz, VF = 0 V
1
1.5
1.3
5
5
Switching Specifications
Over Recommended Operating Conditions (TA = –40°C to +85°C, 2.7V ≤ VCC ≤ 3.6V), IF = 7.5 mA unless otherwise
specified. All Typicals at TA = 25°C, VCC = 3.3 V.
Parameter
Symbol
Max.
Units
Test Conditions
Fig.
Note
Propagation Delay
Time to High Output
Level
tPLH
Min.
Typ.
90
ns
RL = 350 Ω
CL = 15 pF
6, 7
1, 6, 15
Propagation Delay
Time to Low Output
Level
tPHL
75
ns
RL = 350 Ω
CL = 15 pF
Pulse Width
Distortion
|tPHL –
tPLH|
25
ns
RL = 350 Ω
CL = 15 pF
Propagation Delay
Skew
tPSK
40
ns
RL = 350 Ω
CL = 15 pF
8, 9, 15
Output Rise Time
(10-90%)
tr
45
ns
RL = 350 Ω
CL = 15 pF
1, 15
Output Fall Time
(90-10%)
tf
20
ns
RL = 350 Ω
CL = 15 pF
1, 15
Propagation Delay
Time of Enable from
VEH to VEL
tELH
45
ns
RL = 350 Ω,
CL = 15 pF,
VEL = 0 V, VEH = 3 V
9
10
Propagation Delay
Time of Enable from
VEL to VEH
tEHL
30
ns
RL = 350 Ω,
CL = 15 pF,
VEL = 0 V, VEH = 3 V
9
11
1, 7, 15
8
9, 15
Switching Specifications (AC)
Over recommended operating conditions TA = -40°C to 85°C, 4.5 ≤ Vcc ≤ 5.5V, IF = 7.5 mA unless otherwise specified.
All typicals at VCC = 5 V, TA = 25 °C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Propagation Delay Time
to High Output Level
tPLH
20
48
75
ns
TA = 25°C,
RL = 350W,
CL = 15 pF
6,7
1,6,15
Propagation Delay Time
to Low Output Level
tPHL
ns
TA = 25°C,
RL = 350W,
CL = 15 pF
6, 7
1,7, 15
Pulse Width Distortion
|tPHL - tPLH|
35
ns
RL = 350W,
CL = 15 pF
8
9, 15
Propagation Delay
Skew
TPSK
40
ns
RL = 350W,
CL = 15 pF
8,9, 15
Output Rise Time
(10%-90%)
tr
24
ns
RL = 350W,
CL = 15 pF
1,15
Output Fall Time
(10%-90%)
tf
10
ns
RL = 350W,
CL = 15 pF
1, 15
Propagation Delay
Time of Enable from
VEH to VEL
tELH
30
ns
RL = 350W, CL = 15 pF,
VEL=0V, VEH=3V
9
10
Propagation Delay
Time of Enable from
VEL to VEH
tEHL
20
ns
RL = 350W, CL = 15 pF,
VEL=0V, VEH=3V
9
11
10
100
25
50
75
100
3.5
Parameter
Sym.
Device
Min.
Typ.
Units
Test Conditions
Fig.
Note
Output High Level
Common Mode
Transient Immunity
|CMH|
HCPL-263L
HCPL-063L
HCPL-260L
HCPL-060L
15
25
kV/ms
VCC = 3.3 V, IF = 0 mA,
VO(MIN) = 2 V, RL = 350 W,
TA = 25°C, VCM = 1000 V
and VCM = 10V
10
12,
14,
15
Output Low Level
Common Mode
Transient Immunity
|CML|
HCPL-263L
HCPL-063L
HCPL-260L
HCPL-060L
15
25
kV/ms
VCC = 3.3 V, IF = 7.5 mA,
VO(MAX) = 0.8 V, RL = 350 W,
TA = 25°C, VCM = 1000 V
and VCM = 10V
10
13,
14,
15
Output High Level
Common Mode
Transient Immunity
|CMH|
HCPL-263L
HCPL-063L
HCPL-260L
HCPL-060L
10
15
kV/ms
VCC = 5 V, IF = 0 mA,
VO(MIN) = 2 V, RL = 350 W,
TA = 25°C, VCM = 1000 V
10
12,
14,
15
Output Low Level
Common Mode
Transient Immunity
|CML|
HCPL-263L
HCPL-063L
HCPL-260L
HCPL-060L
10
15
kV/ms
VCC = 5 V, IF = 7.5 mA,
VO(MAX) = 0.8 V, RL = 350 W,
TA = 25°C, VCM = 1000 V
10
13,
14,
15
11
Package Characteristics
All Typicals at TA = 25˚C.
Parameter
Sym.
Package
Min.
Typ.
Max
Units
Test Conditions
Fig.
Note
Input-Output
II-O*
Single 8-Pin DIP
1
µA
45% RH, t = 5 s,
Insulation Single SO-8 VI-O = 3 kV DC, TA = 25˚C
16, 17
Input-Output
VISO
8-Pin DIP, SO-8
3750
V rms
RH ≤ 50%, t = 1 min,
Momentary TA = 25˚C
Withstand
Voltage**
16, 17
Input-Output
Resistance
RI-O
8-Pin, SO-8
1012
Ω
VI-O =500 V dc
1, 16, 19
Input-Output
Capacitance
CI-O
8-Pin DIP, SO-8
0.6
pF
f = 1 MHz, TA = 25˚C
1, 16, 19
Input-Input
II-I
Dual Channel
0.005
µA
RH ≤ 45%, t = 5 s,
Insulation VI-I = 500 V
Leakage
Current
Resistance
RI-I
Dual Channel
1011
Ω
(Input-Input)
20
Capacitance
CI-I
(Input-Input)
20
Dual 8-Pin Dip
Dual SO-8
0.03
0.25
pG
f = 1 MHz
20
*The JEDEC Registration specifies 0˚C to +70˚C. Avago specifies –40˚C to +85˚C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable), your equipment level safety specification or Avago Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage."
Notes:
1. Each channel.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 20 mA.
3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 15 mA.
4. Derate linearly above +80˚C free-air temperature at a rate of 2.7 mW/˚C for the SOIC-8 package.
5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in
Figure 11. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
6. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge
of the output pulse.
7. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge
of the output pulse.
8. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified test
conditions.
9. See test circuit for measurement details.
10. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the
rising edge of the output pulse.
11. The tEHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the
falling edge of the output pulse.
12. CMH is the maximum tolerable rate of rise on the common mode voltage to assure that the output will remain in a high logic state
(i.e., Vo > 2.0 V).
13. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state
(i.e., Vo < 0.8 V).
14. For sinusoidal voltages, (|dVCM | / dt)max = πfCMVCM (p-p).
15. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in improved
CMR performance. For single channel products only. See application information provided.
16. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
17. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V rms for one second (leakage
detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/
EN/DIN EN 60747-5-5 Insulation Characteristics Table, if applicable.
18. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for one second (leakage
detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/
EN/DIN EN 60747-5-5 Insulation Characteristics Table, if applicable.
19. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only.
20. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only.
12
VCC = 3.3 V
VO = 3.3 V
VE = 2.0 V*
IF = 250 µA
10
* FOR SINGLE
CHANNEL
PRODUCTS
ONLY
5
0
-60 -40 -20
20
0
40
80 100
60
IOH – HIGH LEVEL OUTPUT CURRENT – µA
IOH – HIGH LEVEL OUTPUT CURRENT – µA
15
15
VCC = 5.5 V
VO = 5.5 V
VE = 2.0 V*
IF = 250 µA
10
* FOR SINGLE
CHANNEL
PRODUCTS
ONLY
5
0
-60 -40 -20
TA – TEMPERATURE – C
20
0
40
80 100
60
TA – TEMPERATURE – C
Figure 1. Typical high level output current vs. temperature.
12
10
6N137 fig 1
8-PIN DIP, SO-8
VCC = 3.3 V
VO = 0.6 V
8
6
RL = 350 KΩ
RL = 1 KΩ
4
2
RL = 4 KΩ
0
-60 -40 -20
0
20
40
60
80 100
ITH – INPUT THRESHOLD CURRENT – mA
ITH – INPUT THRESHOLD CURRENT – mA
HCPL-260L fig 1
6
5
8-PIN DIP, SO-8
VCC = 5.0 V
VO = 0.6 V
4
3
RL = 350 Ω
RL = 1 KΩ
2
1
RL = 4 KΩ
0
-60 -40 -20
TA – TEMPERATURE – C
20
0
40
60
80 100
TA – TEMPERATURE – C
Figure 2. Typical output voltage vs. forward input current.
0.8
0.7
0.6
8-PIN DIP, SO-8
VCC = 3.3 V
VE = 2.0 V*
IF = 5.0 mA
* FOR SINGLE
CHANNEL
PRODUCTS ONLY
0.5
0.4
IO = 13 mA
0.3
0.2
0.1
0
-60 -40 -20
0
20
40
60
80 100
VOL – LOW LEVEL OUTPUT VOLTAGE – V
VOL – LOW LEVEL OUTPUT VOLTAGE – V
HCPL-260L fig 3
0.8
0.7
8-PIN DIP, SO-8
VCC = 5.5 V
VE = 2.0 V*
IF = 5.0 mA
* FOR SINGLE
CHANNEL
PRODUCTS ONLY
0.6
0.5
IO = 16 mA
IO = 12.8 mA
0.4
0.3
0.2
IO = 9.6 mA
IO = 6.4 mA
0.1
TA – TEMPERATURE – C
0
-60 -40 -20
0
20
40
13
80 100
TA – TEMPERATURE – C
Figure 3. Typical low level output voltage vs. temperature.
HCPL-260L fig 4
60
6N137 fig 4a
60
VCC = 3.3 V
VE = 2.0 V*
VOL = 0.6 V
IOL – LOW LEVEL OUTPUT CURRENT – mA
IOL – LOW LEVEL OUTPUT CURRENT – mA
70
* FOR SINGLE
CHANNEL
PRODUCTS ONLY
50
IF = 5.0 mA
40
20
-60 -40 -20
0
20
40
80 100
60
70
VCC = 5.0 V
VE = 2.0 V*
VOL = 0.6 V
* FOR SINGLE
CHANNEL
PRODUCTS ONLY
60
IF = 10-15 mA
50
IF = 5.0 mA
40
20
-60 -40 -20
TA – TEMPERATURE – C
0
40
20
60
80 100
TA – TEMPERATURE – C
Figure 4. Typical low level output current vs. temperature.
HCPL-260L fig 5
IF – FORWARD CURRENT – mA
6N137 fig 5
8-PIN DIP, SO-8
1000
TA = 25 C
100
IF
+
VF
–
10
1.0
0.1
0.01
0.001
1.1
1.2
1.3
1.4
1.6
1.5
VF – FORWARD VOLTAGE – V
Figure 5. Typical input diode forward characteristic.
HCPL-260L fig 6
3.3V or 5V
SINGLE CHANNEL
PULSE GEN.
ZO = 50 Ω
t f = t r = 5 ns
IF
INPUT
MONITORING
NODE
RM
1
VCC 8
2
7
3
6
4
5
GND
PULSE GEN.
ZO = 50 Ω
tf = tr = 5 ns
0.1 µF
BYPASS
RL
IF
*CL
RM
2
7
3
6
4
5
GND
*CL IS APPRO IMATELY 15 F HICH INCLUDES
PROBE AND STRAY IRING CAPACITANCE.
INPUT
IF
tPHL
A
IF = 3.75
A
1.5 V
Figure 6. Test circuit for tPHL and tPLH.
HCPL 260L f
14
IF = 7.50
tPLH
OUTPUT
VO
7
3.3V or 5V
VCC 8
RL
INPUT
MONITORING
NODE
OUTPUT VO
MONITORING
NODE
DUAL CHANNEL
1
0.1 µF
BYPASS
CL*
OUTPUT VO
MONITORING
NODE
120
90
100
VCC = 3.3 V
IF = 7.5 mA
tP - PROPAGATION DELAY - ns
tP – PROPAGATION DELAY – ns
150
tPLH , RL = 350 Ω
60
30
tPHL , RL = 350 Ω
0
-60 -40 -20
0
20
40
60
VCC = 5.0 V
IF = 7.5 mA
80
tPLH , RL = 4 KΩ
tPHL , RL = 350 Ω
1 KΩ
60
4 KΩ
tPLH , RL = 1 KΩ
40
20
tPLH , RL = 350 Ω
0
-60 -40 -20
80 100
TA – TEMPERATURE – C
20
0
40
80 100
60
TA - TEMPERATURE - ¡C
50
40
HCPL-260L fig 8
VCC = 3.3 V
IF = 7.5 mA
30
20
RL = 350 Ω
10
0
-60 -40 -20
0
20
40
60
80 100
PWD - PULSE WIDTH DISTORTION - ns
PWD – PULSE WIDTH DISTORTION – ns
Figure 7. Typical propagation delay vs. temperature.
TA – TEMPERATURE – C
Figure8. Typical pulse width distortion vs. temperature.
6N137 fig 11
15
40
6N137 fig 9
RL = 4 kΩ
30
VCC = 5.0 V
IF = 7.5 mA
20
10
RL = 350Ω
0
RL = 1 kΩ
-10
-60 -40 -20
0
20
40
80 100
60
o
TA - TEMPERATURE - C
PULSE GEN.
ZO = 50 Ω
tf = tr = 5 ns
INPUT VE
MONITORING NODE
3.3V or 5V
7.5 mA
IF
1
VCC 8
2
7
3
6
4
5
0.1 µF
BYPASS
RL
OUTPUT VO
MONITORING
NODE
*CL
GND
3.0 V
INPUT
VE
1.5 V
tEHL
tELH
OUTPUT
VO
1.5 V
*CL IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
Figure 9. Test circuit for tEHL and tELH.
IF
SINGLE CHANNEL
IF
1
3.3V or 5V
VFF
2
7
3
6
4
GND
1
A
HCPL-260L fig 9
0.1 µF
RL
BYPASS
B
A
DUAL CHANNEL
B
VCC 8
5
VCM
7
3
6
GND
VCM
VCM
VCM
0V
5V
VO
VO
S ITCH AT A
IF = 0
S ITCH AT B
VO MIN.
IF = 7.5 A
VO MA .
0.5 V
A
HCPL 260L
VCC BUS (FRONT)
NC
ENABLE
0.1µF
OUTPUT
10 mm MAX.
(SEE NOTE 5)
Figure 11. Recommended printed circuit board layout.
HCPL-260L fig 12
CMH
CML
GND BUS (BACK)
NC
–
+
PULSE
GENERATOR
ZO = 50 Ω
PEA
Figure 10. Test circuit for common mode transient immunity and typical waveforms.
16
2
4
–
+
PULSE
GENERATOR
ZO = 50 Ω
SINGLE CHANNEL
DEVICE ILLUSTRATED.
11
3.3V or 5V
RL
VFF
OUTPUT VO
MONITORING
NODE
VCC 8
5
0.1 µF
BYPASS
OUTPUT VO
MONITORING
NODE
SINGLE CHANNEL DEVICE
VCC1
3.3 V or 5V
3.3 V or 5V
VCC2
8
220 Ω
RL
IF
+
D1*
2
6
VF
–
GND 1
0.1 µF
BYPASS
3
5
SHIELD
GND 2
VE 7
1
2
*DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT.
DUAL CHANNEL DEVICE
CHANNEL 1 SHOWN
VCC1
3.3 V or 5V
220 Ω
IF
+
D1*
RL
1
7
0.1 µF
BYPASS
VF
–
GND 1
2
SHIELD
1
Figure 12. Recommended LVTTL interface circuit.
17
3.3 V or 5V
VCC2
8
5
GND 2
2
HCPL-260L fig 13
Application Information
Common-Mode Rejection for HCPL-260L Families:
Also, common-mode transients can capacitively couple from the LED anode (or cathode) to the output-side
ground causing current to be shunted away from the
LED (which can be bad if the LED is on) or conversely
cause current to be injected into the LED (bad if the LED
is meant to be off ). Figure 14 shows the parasitic capacitances which exists between LED anode/cathode and
output ground (CLA and CLC). Also shown in Figure 14 on
the input side is an AC-equivalent circuit.
Figure 13 shows the recom­mended drive circuit for optimal common-mode rejection performance. Two main
points to note are:
1. The enable pin is tied to VCC rather than floating (this
applies to single-channel parts only).
2. Two LED-current setting resistors are used instead of
one. This is to balance ILED variation during commonmode transients.
If the enable pin is left floating, it is possible for commonmode transients to couple to the enable pin, resulting in
common-mode failure. This failure mechanism only occurs when the LED is on and the output is in the Low
State. It is identified as occurring when the transient output voltage rises above 0.8 V. Therefore, the enable pin
should be connected to either VCC or logic-level high for
best common-mode performance with the output low
(CMRL ). This failure mechanism is only present in singlechannel parts which have the enable function.
*
VCC
220 Ω
220 Ω
74LS04
OR ANY TOTEM-POLE
OUTPUT LOGIC GATE
For transients occurring when the LED is on, commonmode rejec­tion (CMRL, since the output is in the “low”
state) depends upon the amount of LED current drive
(IF). For conditions where IF is close to the switching
threshold (ITH), CMRL also depends on the extent which
ILP and ILN balance each other. In other words, any condition where common-mode transients cause a momentary decrease in IF will cause common-mode failure for
transients which are fast enough.
HCPL-260L
1
8
2
7
3
6
VO
5
GND
4
SHIELD
*
VCC+
0.01 µF
350 Ω
GND2
GND1
* HIGHER CMR MAY BE OBTAINABLE BY CONNECTING PINS 1, 4 TO INPUT GROUND (GND1).
Figure 13. Recommended drive circuit for High-CMR.
HCPL-261A fig 19
1/2 RLED
1/2 RLED
1
8
2
7
0.01 µF
350 Ω
ILP
3
4
CLA
ILN
CLC
VCM
6
VO
15 pF
5
SHIELD
+
–
Figure 14. AC equivalent circuit.
HCPL- 261A fig 20
18
VCC+
GND
Likewise for common-mode transients which occur
when the LED is off (i.e. CMRH, since the output is “high”),
if an imbalance between ILP and ILN results in a transient
IF equal to or greater than the switching threshold of the
optocoupler, the transient “signal” may cause the output
to spike below 2 V (which consti­tutes a CMRH failure).
By using the recommended circuit in Figure 13, good
CMR can be achieved. The balanced ILED-setting resistors
help equalize ILP and ILN to reduce the amount by which
ILED is modulated from transient coupling through CLA
and CLC.
VCC
HCPL-260L
420 Ω
(MAX)
2N3906
(ANY PNP)
74L504
(ANY
TTL/CMOS
GATE)
1
2
LED
3
4
CMR with Other Drive Circuits
CMR performance with drive circuits other than that
shown in Figure 13 may be enhanced by following these
guidelines:
1. Use of drive circuits where current is shunted from the
LED in the LED “off” state (as shown in Figures 15 and
16). This is beneficial for good CMRH.
2. Use of IFH > 3.5 mA. This is good for high CMRL.
Figure 15 shows a circuit which can be used with any
totem-pole-output TTL/LSTTL/HCMOS logic gate. The
buffer PNP transistor allows the circuit to be used with
logic devices which have low current-sinking capability.
It also helps maintain the driving-gate power-supply current at a constant level to minimize ground shifting for
other devices connected to the input-supply ground.
When using an open-collector TTL or open-drain CMOS
logic gate, the circuit in Figure 16 may be used. When
using a CMOS gate to drive the optocoupler, the circuit
shown in Figure 17 may be used. The diode in parallel
with the RLED speeds the turn-off of the optocoupler
LED.
Figure 15. TTL interface circuit.
VCC
HCPL-260L
HCPL- 261A fig 21
1
R
2
74HC00
(OR ANY
OPEN-COLLECTOR/
OPEN-DRAIN
LOGIC GATE)
LED
3
4
Figure 16. TTL open-collector/open drain gate drive circuit.
VCC
HCPL- 261A fig 22
1
1N4148
74HC04
(OR ANY
TOTEM-POLE
OUTPUT LOGIC
GATE)
220 Ω
2
LED
3
4
Figure 17. CMOS gate drive circuit.
HCPL- 261A fig 23
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved. Obsoletes AV01-0581EN
AV02-0616EN - May 13, 2013
HCPL-260L