Maxim MAX9374ESA Differential lvpecl-to-lvds translator Datasheet

19-2326; Rev 0; 1/02
Differential LVPECL-to-LVDS Translators
Features
♦ Guaranteed 2.0GHz Operating Frequency
♦ 250ps (typ) Propagation Delay
♦ 1.0ps RMS Jitter (typ)
♦ 2.375V to 2.625V Low-Voltage Supply Range
(MAX9374)
♦ On-Chip VBB Reference for Single-Ended Input
♦ Output Low for Open Inputs
♦ Output Conforms to ANSI TIA/EIA-644 LVDS
Standard
♦ ESD Protection >2.0kV (Human Body Model)
♦ Available in Small 8-Pin SOT23 Package
Ordering Information
Applications
Precision Clock Buffer
PART
Low-Jitter Data Repeater
TEMP
RANGE
PINPACKAGE
TOP
MARK
-40°C to +85°C
8 SOT23-8
AAKU
Central Office Clock Distribution
MAX9374EKA-T
DSLAM/DLC
MAX9374ESA
-40°C to +85°C
8 SO
MAX9374AEKA-T
-40°C to +85°C
8 SOT23-8
MAX9374AESA
-40°C to +85°C
8 SO
Base Station
Mass Storage
—
AAKV
—
Pin Configurations/Functional Diagrams appear at end of
data sheet.
Typical Application Circuit
LVDS RECEIVER
MAX9374/MAX9374A
Z0 = 50Ω
D
Q
LVPECL
INPUT
100Ω
D
Q
Z0 = 50Ω
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9374/MAX9374A
General Description
The MAX9374 and MAX9374A are 2.0GHz differential
LVPECL-to-LVDS translators and are designed for telecom applications. They feature 250ps propagation
delay. The differential output conforms to the ANSI
TIA/EIA-644 LVDS standard. The inputs are biased with
internal resistors such that the output is differential low
when inputs are open. An on-chip VBB reference output
is available for single-ended operation.
The MAX9374 is designed for low-voltage operation
from a 2.375V to 2.625V power supply for use in 2.5V
systems. The MAX9374A is designed for 3.0V to 3.6V
operation in systems with a nominal 3.3V supply. Both
devices are offered in industry-standard 8-pin SOT23
and SO packages.
MAX9374/MAX9374A
Differential LVPECL-to-LVDS Translators
ABSOLUTE MAXIMUM RATINGS
VCC to GND...........................................................................4.0V
VD, VD to GND ..............................................-0.3V to VCC + 0.3V
VD to VD ................................................................................3.0V
VBB Sink/Source Current.......................................................1mA
Short-Circuit Duration (Q, Q to GND).........................Continuous
Short-Circuit Duration (Q to Q)...................................Continuous
Continuous Power Dissipation (TA = +70°C)
8-Pin SOT23 (derate 8.9mW/°C above +70°C)............714mW
8-Pin SO (derate 5.9mW/°C above +70°C)..................470mW
Junction-to-Ambient Thermal Resistance
8-Pin SOT23.............................................................+112°C/W
8-Pin SO...................................................................+170°C/W
Junction-to-Ambient Thermal Resistance with
500 LFPM Airflow
8-Pin SOT23...............................................................+78°C/W
8-Pin SO.....................................................................+99°C/W
Junction-to-Case Thermal Resistance
8-Pin SOT23...............................................................+80°C/W
8-Pin SO.....................................................................+40°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (D, D, Q, Q) .......................................2kV
Soldering Temperature (10s) ...........................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.375V to 2.625V for MAX9374, VCC = 3.0V to 3.6V for MAX9374A, 100Ω ±1% across outputs, VID = 0.095V to VCC or 3V,
whichever is less, VIHD = 1.2V to VCC, VILD = GND to VCC - 0.095V, unless otherwise noted. Typical values are at VIHD = 2.0V, VILD =
1.85V, VCC = 3.3V for MAX9374A, VCC = 2.5V for MAX9374.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
-40°C
MIN
TYP
+25°C
MAX
MIN
VCC
1.2
TYP
+85°C
MAX
MIN
VCC
1.2
TYP
MAX
UNITS
DIFFERENTIAL INPUT (D, D)
High Voltage of
Differential Input
VIHD
Figure 1
1.2
Low Voltage of
Differential Input
VILD
Figure 1
GND
VIH
VBB connected
to D (VIL for
VBB connected
to D), Figure 1
VCC 1.165
VCC
VCC 1.165
VCC
VIL
VBB connected
to D (VIH for
VBB connected
to D), Figure 1
VEE
VCC 1.475
VEE
VCC < 3.0V
VCC ≥ 3.0V
0.1
0.1
VCC
3.0
-150
150
Single-Ended Input
High Voltage
Single-Ended Input
Low Voltage
Differential Input Voltage
Input Current
VIHD VILD
IIN
VIHMAX, VILMIN
(Note 3)
VCC
V
VCC 0.095
V
VCC 1.165
VCC
V
VCC 1.475
VEE
VCC 1.475
V
0.1
0.1
VCC
3.0
0.1
0.1
VCC
3.0
V
-150
150
-150
150
µA
1.6
V
VCC GND
0.095
VCC GND
0.095
DIFFERENTIAL OUTPUT (Q, Q)
Output High Voltage
VOH
Figure 1
Output Low Voltage
VOL
Figure 1
0.9
Differential Output
Voltage
VOD
Figure 1
250
2
1.6
1.6
0.9
350
450
250
0.9
350
450
250
V
350
_______________________________________________________________________________________
450
mV
Differential LVPECL-to-LVDS Translators
(VCC = 2.375V to 2.625V for MAX9374, VCC = 3.0V to 3.6V for MAX9374A, 100Ω ±1% across outputs, VID = 0.095V to VCC or 3V,
whichever is less, VIHD = 1.2V to VCC, VILD = GND to VCC - 0.095V, unless otherwise noted. Typical values are at VIHD = 2.0V, VILD =
1.85V, VCC = 3.3V for MAX9374A, VCC = 2.5V for MAX9374.) (Notes 1, 2)
PARAMETER
SYMBOL
Change in VOD Between
Complementary Output
States
∆VOD
Output Offset Voltage
CONDITIONS
MIN
-40°C
TYP MAX
1
VOS
1.125
Change in VOS Between
Complementary Output
States
∆VOS
Output Short-Circuit
Current
IOSC
Q or Q short to
GND
Reference Voltage
VBB
IBB = ±0.6mA
(Note 4)
Supply Current
ICC
(Note 5)
MIN
+25°C
TYP MAX
25
1
1.25 1.375 1.125
1.25
MIN
25
1.375 1.125
+85°C
TYP MAX
UNITS
1
25
mV
1.25
1.375
V
3
25
3
25
3
25
mV
23
30
23
30
23
30
mA
VCC 1.26
V
30
mA
VBB AND SUPPLY
VCC 1.38
VCC - VCC 1.26 1.38
16
30
VCC - VCC 1.26 1.38
18
30
20
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.375V to 2.625V for MAX9374, VCC = 3.0V to 3.6V for MAX9374A, 100Ω ±1% across outputs, VIHD - VILD = 0.15V to VCC or
3V, whichever is less, VIHD = 1.2V to VCC, VILD = GND to VCC - 0.15V, fIN = 1GHz, input transition time = 125ps, input duty cycle =
50%, unless otherwise noted. Typical values are at VIHD = 2.0V, VILD = 1.85V, VCC = 3.3V for MAX9374A, VCC = 2.5V for MAX9374,
unless otherwise noted.) (Notes 1, 6)
PARAMETER
SYMBOL
Differential Input to
Differential Output Delay
tPLHD,
tPHLD
Single-Ended Input to
Differential Output Delay
Part-to-Part Skew
CONDITIONS
-40°C
+25°C
+85°C
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
Figure 1
116
240
420
128
250
403
145
260
440
ps
tPLHS,
tPHLS
Figure 1
126
250
430
138
250
415
155
260
450
ps
tSKPP
(Note 7)
295
ps
304
275
fIN = 1.0GHz,
clock pattern
0.9
2
1
2
1
2
fIN = 2.0GHz,
clock pattern
0.8
2
0.9
2
0.9
2
tDJ
fIN = 2.0Gbps,
223 -1 PRBS
pattern
45
75
46
75
38
75
Operating Frequency
fMAX
VOD ≥ 250mV
Output Rise/Fall Time
t R , tF
20% to 80%,
Figure 1
Added Random Jitter
(Note 8)
tRJ
Added Deterministic
Jitter (Note 8)
ps(RMS)
2.0
2.2
92
2.0
200
2.2
91
2.0
200
2.2
90
ps(P-P)
MHz
200
ps
_______________________________________________________________________________________
3
MAX9374/MAX9374A
DC ELECTRICAL CHARACTERISTICS (continued)
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.375V to 2.625V for MAX9374, VCC = 3.0V to 3.6V for MAX9374A, 100Ω ±1% across outputs, VIHD - VILD = 0.15V to VCC or
3V, whichever is less, VIHD = 1.2V to VCC, VILD = GND to VCC - 0.15V, fIN = 1GHz, input transition time = 125ps, input duty cycle =
50%, unless otherwise noted. Typical values are at VIHD = 2.0V, VILD = 1.85V, VCC = 3.3V for MAX9374A, VCC = 2.5V for MAX9374,
unless otherwise noted.) (Notes 1, 6)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Measurements are made with the device in thermal equilibrium.
DC parameters are production tested at TA = +25°C and guaranteed by design over the full operating temperature range.
Current into a pin is defined as positive. Current out of a pin is defined as negative.
Use VBB as a reference for inputs on the same device only.
100Ω across the outputs, all other pins open except VCC and GND.
Guaranteed by design and characterization. Limits are set at ±6 sigma.
Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Device jitter added to the input signal.
Typical Operating Characteristics
(MAX9374A, 100Ω ±1% across outputs, fIN = 1GHz, input transition time = 125ps, input duty cycle = 50%, VCC = 3.3V, VIHD = 2.0V,
VILD = 1.85V, TA = +25°C, unless otherwise noted.)
DIFFERENTIAL OUTPUT VOLTAGE (VOD)
vs. FREQUENCY
20
18
16
14
12
-15
10
35
60
85
300
2
250
JITTER
200
1
0.4
0.7
1.0
1.3
1.6
FALL
80
1.9
40
0
2.2
-15
-40
PROPAGATION DELAY vs. TEMPERATURE
300
MAX9374 toc04
280
PROPAGATION DELAY (ps)
260
240
220
10
280
260
240
220
200
200
180
1.2
1.5
1.8
2.1
2.4
VIHD (V)
2.7
3.0
3.3
35
TEMPERATURE (°C)
FREQUENCY (GHz)
PROPAGATION DELAY vs. HIGH VOLTAGE
OF DIFFERENTIAL INPUT (VIHD)
PROPAGATION DELAY (ps)
RISE
100
60
150
TEMPERATURE (°C)
4
MAX9374 toc03
120
MAX9374 toc05
-40
VOD
350
100
0.1
10
RISE/FALL TIME vs. TEMPERATURE
140
3
RISE/FALL TIME (ps)
DIFFERENTIAL OUTPUT VOLTAGE (mV)
100Ω LOAD
22
MAX9374 toc02
400
MAX9374 toc01
24
RANDOM JITTER (psRMS)
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT (mA)
MAX9374/MAX9374A
Differential LVPECL-to-LVDS Translators
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
60
85
Differential LVPECL-to-LVDS Translators
PIN
NAME
FUNCTION
SOT23
SO
1
4
VBB
2
5
GND
3
3
D
Inverted LVPECL Data Input. 36.5kΩ pullup to VCC and 75kΩ pulldown to GND.
4
2
D
Noninverted LVPECL Data Input. 75kΩ pullup to VCC and 75kΩ pulldown to GND.
5
8
VCC
6
7
Q
Noninverted LVDS Output. Typically terminate with 100Ω to Q.
7
6
Q
Inverted LVDS Output. Typically terminate with 100Ω to Q.
8
1
N.C.
Reference Output Voltage. Connect to the inverting or noninverting data input to provide a reference
for single-ended operation. When used, bypass with a 0.01µF ceramic capacitor to VCC; otherwise,
leave it open.
Ground. Provide a low-impedance connection to the ground plane.
Positive Supply Voltage. Bypass VCC to GND with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
No Connection. Not internally connected.
D
VIHD
VIHD - VILD
VILD
D
tPLH_
tPHL_
Q
VOH
VOD
VOS
VOL
Q
80%
80%
0 (DIFFERENTIAL)
0 (DIFFERENTIAL)
20%
20%
(Q) - (Q)
tR
tF
Figure 1. MAX9374/MAX9374A Timing Diagram
_______________________________________________________________________________________
5
MAX9374/MAX9374A
Pin Description
MAX9374/MAX9374A
Differential LVPECL-to-LVDS Translators
Detailed Description
The MAX9374/MAX9374A are 2.0GHz differential
LVPECL-to-LVDS translators. The output is differential
LVDS and conforms to the ANSI TIA/EIA-644 LVDS
standard. The inputs are biased with internal resistors
such that the output is differential low when inputs are
open. An on-chip VBB reference output is available for
single-ended input operation. The MAX9374 is
designed for low-voltage operation from 2.375V to
2.625V in systems with a nominal 2.5V supply. The
MAX9374A is designed for 3.0V to 3.6V operation in
systems with a nominal 3.3V supply.
Differential LVPECL Input
The MAX9374/MAX9374A accept differential LVPECL
inputs and can be configured to accept single-ended
inputs through the use of the VBB voltage reference output. The maximum magnitude of the differential signal
applied to the input is 3.0V or VCC, whichever is less.
This limit also applies to the difference between any reference voltage input and a single-ended input.
Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input
voltage (VIHD - VILD) apply simultaneously.
Single-Ended Inputs and VBB
The differential inputs can be configured to accept a
single-ended input through the use of the VBB reference voltage. A noninverting, single-ended input is produced by connecting VBB to the D input and applying a
single-ended input signal to the D input. Similarly, an
inverting input is produced by connecting VBB to the D
input and applying the input signal to the D input. With
a differential input configured as single ended (using
VBB), the single-ended input can be driven to VCC and
GND or with a single-ended LVPECL signal. Note that a
single-ended input must be at least VBB ±95mV or a
differential input of at least 95mV to switch the outputs
to the VOH and VOL levels specified in the DC Electrical
Characteristics table.
When using the VBB reference output, bypass it with a
0.01µF ceramic capacitor to VCC. If the VBB reference is
not used, leave it unconnected. Use VBB only for inputs
that are on the same device as the VBB reference.
Differential LVDS Output
The differential outputs conform to the ANSI TIA/EIA-644
LVDS standard. Typically, terminate the outputs with 100Ω
across Q and Q, as shown in the Typical Application
Circuit. The outputs are short-circuit protected.
Applications Information
Supply Bypassing
Bypass VCC to GND with high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors in parallel and as
close to the device as possible, with the 0.01µF capacitor closest to the device. Use multiple parallel vias to
minimize parasitic inductance. When using the VBB reference output, bypass it with a 0.01µF ceramic capacitor to VCC (if the VBB reference is not used, it can be
left open).
Controlled-Impedance Traces
Input and output trace characteristics affect the performance of the MAX9374/MAX9374A. Connect high-frequency input and output signals to 50Ω characteristic
impedance traces. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by
maintaining the 50Ω characteristic impedance through
cables and connectors. Reduce skew within a differential pair by matching the electrical length of the traces.
Output Termination
Terminate the outputs with 100Ω across Q and Q as
shown in the Typical Application Circuit. Both outputs
must be terminated.
Input Bias Resistors
Internal biasing resistors ensure a (differential) outputlow condition in the event that the inputs are not connected. The inverting input (D) is biased with a 36.5kΩ pulldown to V CC and a 75kΩ pullup to GND. The
noninverting input (D) is biased with a 75kΩ pullup to
VCC and 75kΩ pulldown to GND.
6
_______________________________________________________________________________________
Differential LVPECL-to-LVDS Translators
VBB
1
8
75kΩ
N.C.
N.C.
1
75kΩ
75kΩ
8
VCC
36.5kΩ
GND
2
7
Q
D
2
7
Q
D
3
6
Q
D
3
6
Q
5
GND
36.5kΩ
D
75kΩ
4
75kΩ
5
VCC
VBB
75kΩ
4
MAX9374/MAX9374A
MAX9374/MAX9374A
SOT23
SO
Chip Information
TRANSISTOR COUNT: 236
PROCESS: Bipolar
_______________________________________________________________________________________
7
MAX9374/MAX9374A
Pin Configurations/Functional Diagrams
Differential LVPECL-to-LVDS Translators
SOT23, 8L.EPS
MAX9374/MAX9374A
Package Information
8
_______________________________________________________________________________________
Differential LVPECL-to-LVDS Translators
9LUCSP, 3x3.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX9374/MAX9374A
Package Information (continued)
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