Cypress CY7C425-10JC 256/512/1k/2k/4k x 9 asynchronous fifo Datasheet

19/21/25/29/
CY7C419/21/25/29/33
256/512/1K/2K/4K x 9 Asynchronous FIFO
Features
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Asynchronous first-in first-out (FIFO) buffer memories
256 x 9 (CY7C419)
512 x 9 (CY7C421)
1K x 9 (CY7C425)
2K x 9 (CY7C429)
4K x 9 (CY7C433)
Dual-ported RAM cell
High-speed 50.0-MHz read/write independent of
depth/width
Low operating power: ICC = 35 mA
Empty and Full flags (Half Full flag in standalone)
TTL compatible
Retransmit in standalone
Expandable in width
PLCC, 7x7 TQFP, SOJ, 300-mil and 600-mil DIP
Pin compatible and functionally equivalent to IDT7200,
IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201,
AM7202, AM7203, and AM7204
Functional Description
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and
CY7C432/3 are first-in first-out (FIFO) memories offered in
600-mil wide and 300-mil wide packages. They are, respectively, 256, 512, 1,024, 2,048, and 4,096 words by 9-bits wide.
Cypress Semiconductor Corporation
Document #: 38-06001 Rev. *A
•
Each FIFO memory is organized such that the data is read in
the same sequential order that it was written. Full and Empty
flags are provided to prevent overrun and underrun. Three additional pins are also provided to facilitate unlimited expansion
in width, depth, or both. The depth expansion technique steers
the control signals from one device to another in parallel, thus
eliminating the serial addition of propagation delays, so that
throughput is not reduced. Data is steered in a similar manner.
The read and write operations may be asynchronous; each
can occur at a rate of 50.0 MHz. The write operation occurs
when the write (W) signal is LOW. Read occurs when read (R)
goes LOW. The nine data outputs go to the high-impedance
state when R is HIGH.
A Half Full (HF) output flag is provided that is valid in the standalone and width expansion configurations. In the depth expansion configuration, this pin provides the expansion out
(XO) information that is used to tell the next FIFO that it will be
activated.
In the standalone and width expansion configurations, a LOW
on the retransmit (RT) input causes the FIFOs to retransmit
the data. Read enable (R) and write enable (W) must both be
HIGH during retransmit, and then R is used to access the data.
The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425,
CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated
using an advanced 0.65-micron P-well CMOS technology. Input ESD protection is greater than 2000V and latch-up is prevented by careful layout and guard rings.
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 30, 2002
CY7C419/21/25/29/33
Logic Block Diagram
Pin Configurations
DATA INPUTS
(D0–D 8)
DIP
Top View
D3
D8
W
NC
Vcc
D4
D5
PLCC/LCC
Top View
RAM ARRAY
256 x 9
512 x 9
1024x 9
2048x 9
4096x 9
WRITE
POINTER
READ
POINTER
Q3
Q8
GND
NC
R
Q4
Q5
THREESTATE
BUFFERS
READ
CONTROL
XI
MR
C420–2
28
1
27
2
26
3
4
25
5
24
7C419
6 7C420/1 23
7 7C424/5 22
8 7C428/9 21
7C432/3
9
20
10
19
11
18
12
17
13
16
15
14
C420–3
32 3130 29 28 27 26 25
D1
D0
XO/HF
Vcc
D4
D5
D6
D7
FL/RT
MR
EF
XO/HF
Q7
Q6
Q5
Q4
R
FL/RT
EF
FF
EXPANSION
LOGIC
D2
RESET
LOGIC
FLAG
LOGIC
XO/HF
Q7
Q6
TQFP
Top View
DATA OUTPUTS
(Q0–Q 8)
R
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
D6
D7
NC
FL/RT
MR
EF
D5
D6
WRITE
CONTROL
4 3 2 1 323130
5
29
6
28
7
27
8
26
7C419
7C421/5/9 25
9
7C433
10
24
11
23
12
22
13
21
14 15 1617 181920
D3
D8
W
VCC
D4
W
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
C420–1
1
2
3
4
5
6
7
8
NC
NC
XI
FF
Q0
Q1
D7
FL/RT
24
23
22
21
20
19
18
17
7C419
7C421/5/9
7C433
NC
NC
MR
EF
XO/HF
Q7
9 10 11 12 13 14 15 16
Q6
Q5
Q2
Q3
Q8
GND
R
Q4
C420–4
Selection Guide
256 x 9
7C419–10
7C419–15
512 x 9 (600-mil only)
512 x 9
7C421–10
7C421–15
1K x 9 (600-mil only)
1K x 9
7C425–10
7C425–15
2K x 9 (600-mil only)
2K x 9
7C419–30
7C420–20
7C420–25
7C421–20
7C421–25
7C424–20
7C424–25
7C425–20
7C425–25
7C420–40
7C420–65
7C421–30
7C421–40
7C421–65
7C424–30
7C424–40
7C424–65
7C425–30
7C425–40
7C425–65
7C428–20
7C429–10
7C429–15
7C429–20
4K x 9 (600-mil only)
4K x 9
7C419–40
7C428–65
7C429–25
7C429–30
7C432–25
7C429–40
7C429–65
7C432–40
7C433–10
7C433–15
7C433–20
7C433–25
7C433–30
7C433–40
7C433–65
Frequency (MHz)
50
40
33.3
28.5
25
20
12.5
Maximum Access Time (ns)
10
15
20
25
30
40
65
ICC1 (mA)
35
35
35
35
35
35
35
Maximum Rating [1]
(Above which the useful life may be impaired. For user guidelines, not tested.)
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
Power Dissipation.......................................................... 1.0W
Storage Temperature .................................–65°C to +150°C
Output Current, into Outputs (LOW)............................ 20 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Static Discharge Voltage ........................................... >2000V
(per MIL–STD–883, Method 3015)
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Latch-Up Current..................................................... >200 mA
Note:
1. Single Power Supply: The voltage on any input or I/O pin can not exceed the power pin during power-up.
Document #: 38-06001 Rev. *A
Page 2 of 22
CY7C419/21/25/29/33
Operating Range
Range
Ambient Temperature[2]
VCC
0°C to + 70°C
5V ± 10%
Industrial
–40°C to +85°C
5V ± 10%
Military
–55°C to +125°C
5V ± 10%
Commercial
Electrical Characteristics Over the Operating Range[3]
7C419–10, 15, 30, 40
7C420/1–10, 15, 20, 25, 30, 40, 65
7C424/5–10, 15, 20, 25, 30, 40, 65
7C428/9–10, 15, 20, 25, 30, 40, 65
7C432/3–10, 15, 20, 25, 30, 40, 65
Parameter
Description
VOH
Output HIGH Voltage
Test Conditions
VCC = Min., IOH = –2.0 mA
VOL
VIH
Output LOW Voltage
Input HIGH Voltage
VCC = Min., IOL = 8.0 mA
Com’l
VIL
Input LOW Voltage
IIX
IOZ
Input Leakage Current
Output Leakage Current
GND < VI < VCC
R > VIH, GND < VO < VCC
IOS
Output Short Circuit Current[5]
VCC = Max., VOUT = GND
Mil/Ind
Min.
2.4
Max.
Unit
V
2.0
0.4
VCC
V
V
2.2
Note 4
VCC
0.8
V
–10
–10
+10
+10
µA
µA
–90
mA
Electrical Characteristics Over the Operating Range[3] (continued)
Parameter
ICC
Description
Operating Current
Test Conditions
VCC = Max.,
IOUT = 0 mA
f = fMAX
Com’l
7C419–10
7C419–15
7C421–10
7C421–15
7C425–10
7C425–15
7C429–10
7C429–15
7C420–20
7C421–20
7C424–20
7C425–20
7C428–20
7C429–20
7C433–10
7C433–15
7C433–20
7C420–25
7C421–25
7C424–25
7C425–25
7C429–25
7C432–25
7C433–25
Min. Max. Min. Max. Min. Max. Min. Max.
85
Mil/Ind
65
55
50
100
90
80
Unit
mA
ICC1
Operating Current
VCC = Max.,
IOUT = 0 mA
F = 20 MHz
Com’l
35
35
35
35
mA
ISB1
Standby Current
All Inputs =
VIH Min.
Com’l
10
10
10
10
mA
15
15
15
Power-Down Current All Inputs >
VCC –0.2V
Com’l
5
5
5
8
8
8
ISB2
Mil/Ind
Mil/Ind
5
mA
Notes:
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. VIL (Min.) = –2.0V for pulse durations of less than 20 ns.
5. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Document #: 38-06001 Rev. *A
Page 3 of 22
CY7C419/21/25/29/33
Electrical Characteristics Over the Operating Range[3] (continued)
7C419–30
7C421–30
7C424–30
7C425–30
7C429–30
7C433–30
Parameter
ICC
Description
Test Conditions
Operating Current
Min.
Max.
7C419–40
7C420–40
7C421–40
7C424–40
7C425–40
7C420–65
7C421–65
7C424–65
7C425–65
7C428–65
7C429–65
7C429–40
7C432–40
7C433–40
Min.
7C433–65
Max.
Units
VCC = Max.,
IOUT = 0 mA
f = fMAX
Com’l
40
Max.
35
Min.
35
mA
Mil/Ind
75
70
65
ICC1
Operating Current
VCC = Max.,
IOUT = 0 mA
F = 20 MHz
Com’l
35
35
35
mA
ISB1
Standby Current
All Inputs =
VIH Min.
Com’l
10
10
10
mA
Mil
15
15
15
ISB2
Power-Down Current
All Inputs >
VCC –0.2V
Com’l
5
5
5
Mil
8
8
8
mA
Capacitance[6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 4.5V
Max.
Unit
6
pF
6
pF
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 500 Ω
5V
R1 500 Ω
5V
OUTPUT
ALL INPUT PULSES
3.0V
OUTPUT
R2
333 Ω
30 pF
INCLUDING
JIGAND
SCOPE
C420–6
(a)
R2
333 Ω
5 pF
INCLUDING
JIGAND
SCOPE
C420–7
GND
≤ 3 ns
90%
10%
90%
10%
≤ 3 ns
C420–8
(b)
Equivalent to:
THÉVENIN EQUIVALENT
200 Ω
OUTPUT
2V
Document #: 38-06001 Rev. *A
Page 4 of 22
CY7C419/21/25/29/33
Switching Characteristics Over the Operating Range[7, 8]
Parameter
Description
7C419–10
7C419–15
7C421–10
7C421–15
7C425–10
7C425–15
7C429–10
7C429–15
7C420–20
7C421–20
7C424–20
7C425–20
7C428–20
7C429–20
7C433–10
7C433–15
7C433–20
Min.
Max.
Min.
Max.
Min.
Max.
Max.
Access Time
tRR
Read Recovery Time
10
10
10
10
ns
tPR
Read Pulse Width
10
15
20
25
ns
tLZR[6,9]
Read LOW to Low Z
3
3
3
3
ns
Data Valid After Read HIGH
5
15
5
35
Unit
tA
10
30
Min.
Read Cycle Time
tDVR
25
7C429–25
7C432–25
7C433–25
tRC
[9,10]
20
7C420–25
7C421–25
7C424–25
7C425–25
20
5
ns
25
5
ns
ns
tHZR[6,9,10]
Read HIGH to High Z
tWC
Write Cycle Time
20
25
30
35
ns
tPW
Write Pulse Width
10
15
20
25
ns
tHWZ[6,9]
Write HIGH to Low Z
5
5
5
5
ns
tWR
Write Recovery Time
10
10
10
10
ns
tSD
Data Set-Up Time
6
8
12
15
ns
tHD
Data Hold Time
0
0
0
0
ns
tMRSC
MR Cycle Time
20
25
30
35
ns
tPMR
MR Pulse Width
10
15
20
25
ns
tRMR
MR Recovery Time
10
10
10
10
ns
tRPW
Read HIGH to MR HIGH
10
15
20
25
ns
tWPW
Write HIGH to MR HIGH
10
15
20
25
ns
tRTC
Retransmit Cycle Time
20
25
30
35
ns
tPRT
Retransmit Pulse Width
10
15
20
25
ns
tRTR
Retransmit Recovery Time
10
10
10
10
ns
15
15
15
18
ns
Notes:
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30 pF load
capacitance, as in part (a) of AC Test Load and Waveforms, unless otherwise specified.
8. See the last page of this specification for Group A subgroup testing information.
9. tHZR transition is measured at +200 mV from VOL and –200 mV from VOH. tDVR transition is measured at the 1.5V level. tHWZ and tLZR transition is measured
at ±100 mV from the steady state.
10. tHZR and tDVR use capacitance loading as in part (b) of AC Test Load and Waveforms.
Document #: 38-06001 Rev. *A
Page 5 of 22
CY7C419/21/25/29/33
Switching Characteristics Over the Operating Range[7, 8] (continued)
Parameter
Description
7C419–10
7C419–15
7C421–10
7C421–15
7C425–10
7C425–15
7C429–10
7C429–15
7C420–20
7C421–20
7C424–20
7C425–20
7C428–20
7C429–20
7C433–10
7C433–15
7C433–20
Max.
Min.
Max.
Unit
MR to EF LOW
20
25
30
35
ns
tHFH
MR to HF HIGH
20
25
30
35
ns
tFFH
MR to FF HIGH
20
25
30
35
ns
tREF
Read LOW to EF LOW
10
15
20
25
ns
tRFF
Read HIGH to FF HIGH
10
15
20
25
ns
tWEF
Write HIGH to EF HIGH
10
15
20
25
ns
tWFF
Write LOW to FF LOW
10
15
20
25
ns
tWHF
Write LOW to HF LOW
10
15
20
25
ns
tRHF
Read HIGH to HF HIGH
10
15
20
25
ns
tRAE
Effective Read from Write HIGH
25
ns
tRPE
Effective Read Pulse Width After EF HIGH
tWAF
Effective Write from Read HIGH
tWPF
Effective Write Pulse Width After FF HIGH
tXOL
Expansion Out LOW Delay from Clock
10
15
20
25
ns
tXOH
Expansion Out HIGH Delay from Clock
10
15
20
25
ns
10
10
Max.
15
15
10
10
Min.
Max.
7C429–25
7C432–25
7C433–25
tEFL
Document #: 38-06001 Rev. *A
Min.
7C420–25
7C421–25
7C424–25
7C425–25
20
20
15
15
Min.
25
20
20
ns
25
25
ns
ns
Page 6 of 22
CY7C419/21/25/29/33
Switching Characteristics Over the Operating Range[7, 8] (continued)
7C419–30
7C421–30
7C424–30
7C425–30
7C429–30
7C433–30
Parameter
Description
Min.
Max.
40
7C419–40
7C420–40
7C421–40
7C424–40
7C425–40
7C429–40
7C432–40
7C433–40
Min.
Max.
7C433–65
Min.
Max.
Read Cycle Time
tA
Access Time
tRR
Read Recovery Time
10
10
15
ns
tPR
Read Pulse Width
30
40
65
ns
tLZR[6,9]
tDVR[9,10]
tHZR[6,9,10]
Read LOW to Low Z
3
3
3
ns
Data Valid After Read HIGH
5
5
5
ns
tWC
Write Cycle Time
40
50
80
ns
tPW
Write Pulse Width
30
40
65
ns
tHWZ[6,9]
Write HIGH to Low Z
5
5
5
ns
tWR
Write Recovery Time
10
10
15
ns
tSD
Data Set-Up Time
18
20
30
ns
tHD
Data Hold Time
0
0
0
ns
tMRSC
MR Cycle Time
40
50
80
ns
tPMR
MR Pulse Width
30
40
65
ns
tRMR
MR Recovery Time
10
10
15
ns
tRPW
Read HIGH to MR HIGH
30
40
65
ns
tWPW
Write HIGH to MR HIGH
30
40
65
ns
tRTC
Retransmit Cycle Time
40
50
80
ns
tPRT
Retransmit Pulse Width
30
40
65
ns
tRTR
Retransmit Recovery Time
10
tEFL
MR to EF LOW
40
50
80
ns
tHFH
MR to HF HIGH
40
50
80
ns
tFFH
MR to FF HIGH
40
50
80
ns
tREF
Read LOW to EF LOW
30
35
60
ns
tRFF
Read HIGH to FF HIGH
30
35
60
ns
tWEF
Write HIGH to EF HIGH
30
35
60
ns
tWFF
Write LOW to FF LOW
30
35
60
ns
tWHF
Write LOW to HF LOW
30
35
60
ns
tRHF
Read HIGH to HF HIGH
30
35
60
ns
tRAE
Effective Read from Write HIGH
60
ns
tRPE
Effective Read Pulse Width After EF HIGH
tWAF
Effective Write from Read HIGH
tWPF
Effective Write Pulse Width After FF HIGH
tXOL
Expansion Out LOW Delay from Clock
30
40
65
ns
tXOH
Expansion Out HIGH Delay from Clock
30
40
65
ns
30
Read HIGH to High Z
80
Unit
tRC
Document #: 38-06001 Rev. *A
50
7C420–65
7C421–65
7C424–65
7C425–65
7C428–65
7C429–65
40
20
20
10
30
30
20
15
35
40
30
30
ns
65
35
ns
ns
65
40
ns
ns
60
65
ns
ns
Page 7 of 22
CY7C419/21/25/29/33
Switching Waveforms
Asynchronous Read and Write
tRC
tA
tPR
tA
tRR
R
tLZR
tDVR
tHZR
DATA VALID
Q0–Q 8
tPW
tWC
DATA VALID
tWR
W
tSD
tHD
DATA VALID
D0–D 8
DATA VALID
C420–9
Master Reset
tMRSC
tPMR
MR
R, W
[12]
[11]
tRPW
tWPW
tEFL
tRMR
EF
tHFH
HF
tFFH
FF
C420–10
Half-Full Flag
HALF FULL
HALF FULL+1
HALF FULL
W
tRHF
R
tWHF
HF
C420–11
Notes:
11. W and R ≥ VIH around the rising edge of MR.
12. tMRSC = tPMR + tRMR.
Document #: 38-06001 Rev. *A
Page 8 of 22
CY7C419/21/25/29/33
Switching Waveforms (continued)
Last Write to First Read Full Flag
LAST WRITE
FIRST READ
ADDITIONAL
READS
FIRST WRITE
R
W
tRFF
tWFF
FF
C420–12
Last Read to First Write Empty Flag
LAST READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST READ
W
R
tREF
tWEF
EF
tA
DATA OUT
VALID
VALID
C420–13
[13]
Retransmit
tRTC[14]
tPRT
FL/RT
R,W
tRTR
C420–14
Notes:
13. EF, HF and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTC.
14. tRTC = tPRT + tRTR.
Document #: 38-06001 Rev. *A
Page 9 of 22
CY7C419/21/25/29/33
Switching Waveforms (continued)
Empty Flag and Read Data Flow-Through Mode
DATA IN
W
tRAE
R
tREF
EF
tWEF
tHWZ
tRPE
tA
DATA OUT
DATA VALID
C420–15
Full Flag and Write Data Flow-Through Mode
R
tWAF
tWPF
W
tRFF
tWFF
FF
tHD
DATA IN
DATA VALID
tA
DATA OUT
tSD
DATA VALID
C420–16
Document #: 38-06001 Rev. *A
Page 10 of 22
CY7C419/21/25/29/33
Switching Waveforms (continued)
Expansion Timing Diagrams
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
W
tWR
tXOH
tXOL
[15]
XO1(XI2)
tHD
tSD
DATA VALID
D0–D 8
tHD
tSD
DATA VALID
C420–17
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
R
tRR
tXOL
[15]
tXOH
XO1(XI2)
tHZR
tLZR
tDVR
tDVR
DATA
VALID
Q0–Q 8
DATA
VALID
tA
tA
C420–18
Note:
15. Expansion Out of device 1 (XO1) is connected to Expansion In of device 2 (XI2).
Architecture
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9,
CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048,
4096 words of 9 bits each (implemented by an array of dual-port RAM cells), a read pointer, a write pointer, control signals (W, R, XI, XO, FL, RT, MR), and Full, Half Full, and Empty
flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory
cell used in the RAM. The cell itself enables the read and write
operations to be independent of each other, which is necessary to achieve truly asynchronous operation of the inputs and
outputs. A second benefit is that the time required to increment
Document #: 38-06001 Rev. *A
the read and write pointers is much less than the time that
would be required for data propagation through the memory,
which would be the case if the memory were implemented
using the conventional register array architecture.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF) and Full flags (FF) being HIGH. Read (R) and write
(W) must be HIGH tRPW/tWPW before and tRMR after the rising
edge of MR for a valid reset cycle. If reading from the FIFO
after a reset cycle is attempted, the outputs will all be in the
high-impedance state.
Page 11 of 22
CY7C419/21/25/29/33
Writing Data to the FIFO
The availability of at least one empty location is indicated by a
HIGH FF. The falling edge of W initiates a write cycle. Data
appearing at the inputs (D0–D8) tSD before and tHD after the
rising edge of W will be stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs tWEF after the first
LOW-to-HIGH transition of W for an empty FIFO. HF goes
LOW tWHF after the falling edge of W following the FIFO actually being Half Full. Therefore, the HF is active once the FIFO
is filled to half its capacity plus one word. HF will remain LOW
while less than one half of total memory is available for writing.
The LOW-to-HIGH transition of HF occurs tRHF after the rising
edge of R when the FIFO goes from half full +1 to half full. HF
is available in standalone and width expansion modes. FF
goes LOW tWFF after the falling edge of W, during the cycle in
which the last available location is filled. Internal logic prevents
overrunning a full FIFO. Writes to a full FIFO are ignored and
the write pointer is not incremented. FF goes HIGH tRFF after
a read from a full FIFO.
Reading Data from the FIFO
The falling edge of R initiates a read cycle if the EF is not LOW.
Data outputs (Q0–Q8) are in a high-impedance condition between read operations (R HIGH), when the FIFO is empty, or
when the FIFO is not the active device in the depth expansion
mode.
When one word is in the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition of EF. The rising edge of R causes the
data outputs to go to the high-impedance state and remain
such until a write is performed. Reads to an empty FIFO are
ignored and do not increment the read pointer. From the empty
condition, the FIFO can be read tWEF after a valid write.
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last MR cycle. A LOW pulse on
RT resets the internal read pointer to the first physical location
of the FIFO. R and W must both be HIGH while and tRTR after
retransmit is LOW. With every read cycle after retransmit, previously accessed data as well as not previously accessed data
is read and the read pointer is incremented until it is equal to
the write pointer. Full, Half Full, and Empty flags are governed
by the relative locations of the read and write pointers and are
updated during a retransmit cycle. Data written to the FIFO
after activation of RT are transmitted also.
Up to the full depth of the FIFO can be repeatedly retransmitted.
Standalone/Width Expansion Modes
Standalone and width expansion modes are set by grounding
Expansion In (XI) and tying First Load (FL) to VCC. FIFOs can
Document #: 38-06001 Rev. *A
be expanded in width to provide word widths greater than nine
in increments of nine. During width expansion mode, all control
line inputs are common to all devices, and flag outputs from
any device can be monitored.
Depth Expansion Mode (see Figure 1)
Depth expansion mode is entered when, during a MR cycle,
Expansion Out (XO) of one device is connected to Expansion
In (XI) of the next device, with XO of the last device connected
to XI of the first device. In the depth expansion mode the First
Load (FL) input, when grounded, indicates that this part is the
first to be loaded. All other devices must have this pin HIGH.
To enable the correct FIFO, XO is pulsed LOW when the last
physical location of the previous FIFO is written to and pulsed
LOW again when the last physical location is read. Only one
FIFO is enabled for read and one for write at any given time.
All other devices are in standby.
FIFOs can also be expanded simultaneously in depth and
width. Consequently, any depth or width FIFO can be created
of word widths in increments of 9. When expanding in depth,
a composite FF must be created by ORing the FFs together.
Likewise, a composite EF is created by ORing the EFs together. HF and RT functions are not available in depth expansion
mode.
Use of the Empty and Full Flags
In order to achieve the maximum frequency, the flags must be
valid at the beginning of the next cycle. However, because
they can be updated by either edge of the read of write signal,
they must be valid by one-half of a cycle. Cypress FIFOs meet
this requirement; some competitors’ FIFOs do not.
The reason why the flags are required to be valid by the next
cycle is fairly complex. It has to do with the “effective pulse
width violation” phenomenon, which can occur at the full and
empty boundary conditions, if the flags are not properly used.
The empty flag must be used to prevent reading from an empty
FIFO and the full flag must be used to prevent writing into a full
FIFO.
For example, consider an empty FIFO that is receiving read
pulses. Because the FIFO is empty, the read pulses are ignored by the FIFO, and nothing happens. Next, a single word
is written into the FIFO, with a signal that is asynchronous to
the read signal. The (internal) state machine in the FIFO goes
from empty to empty+1. However, it does this asynchronously
with respect to the read signal, so that it cannot be determined
what the effective pulse width of the read signal is, because
the state machine does not look at the read signal until it goes
to the empty+1 state. In a similar manner, the minimum write
pulse width may be violated by attempting to write into a full
FIFO, and asynchronously performing a read. The empty and
full flags are used to avoid these effective pulse width violations, but in order to do this and operate at the maximum frequency, the flag must be valid at the beginning of the next
cycle.
Page 12 of 22
CY7C419/21/25/29/33
XO
R
W
FF
9
EF
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
9
D
9
Q
FL
VCC
XI
XO
FULL
FF
EF
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
9
EMPTY
FL
XI
XO
*
FF
9
MR
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
EF
FL
XI
* FIRST DEVICE
C420–19
Figure 1. Depth Expansion
Document #: 38-06001 Rev. *A
Page 13 of 22
CY7C419/21/25/29/33
Ordering Information
Speed
(ns)
10
15
Ordering Code
Package
Type
Package Type
Operating
Range
CY7C419–10AC
A32
32-Pin Thin Plastic Quad Flatpack
CY7C419–10JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C419–10PC
P21
28-Lead (300-Mil) Molded DIP
CY7C419–10VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C419–15AC
A32
32-Pin Thin Plastic Quad Flatpack
CY7C419–15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C419–15VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C419–15JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
Commercial
30
CY7C419–30JC
J65
32-Lead Plastic Leaded Chip Carrier
40
CY7C419–40AC
A32
32-Pin Thin Plastic Quad Flatpack
CY7C419–40JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
Commercial
Ordering Information (continued)
Speed
(ns)
Ordering Code
Package
Type
Package Type
25
CY7C420–25PC
P15
28-Lead (600-Mil) Molded DIP
40
CY7C420–40PC
P15
28-Lead (600-Mil) Molded DIP
65
CY7C420–65PC
P15
28-Lead (600-Mil) Molded DIP
Operating
Range
Commercial
Ordering Information (continued)
Speed
(ns)
10
15
20
25
30
Ordering Code
Package
Type
Package Type
Operating
Range
CY7C421–10AC
A32
32-Pin Thin Plastic Quad Flatpack
CY7C421–10JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C421–10PC
P21
28-Lead (300-Mil) Molded DIP
CY7C421–10VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C421–15AC
A32
32-Pin Thin Plastic Quad Flatpack
CY7C421–15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C421–15JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C421–15VI
V21
28-Lead (300-Mil) Molded SOJ
CY7C421–15DMB
D22
28-Lead (300-Mil) CerDIP
CY7C421–15LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C421–20JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C421–20PC
P21
28-Lead (300-Mil) Molded DIP
CY7C421–20VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C421–20JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C421–25JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C421–25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C421–25VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C421–25JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C421–25PI
P21
28-Lead (300-Mil) Molded DIP
CY7C421–25DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7C421–30JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C421–30PC
P21
28-Lead (300-Mil) Molded DIP
Document #: 38-06001 Rev. *A
Commercial
Commercial
Industrial
Military
Commercial
Industrial
Page 14 of 22
CY7C419/21/25/29/33
Ordering Information (continued)
Speed
(ns)
30
40
65
Ordering Code
Package
Type
Package Type
Operating
Range
CY7C421–30JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C421–30DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7C421–30LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C421–40JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C421–40PC
P21
28-Lead (300-Mil) Molded DIP
CY7C421–40VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C421–40JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C421–65JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C421–65PC
P21
28-Lead (300-Mil) Molded DIP
CY7C421–65VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C421–65JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C421–65DMB
D22
28-Lead (300-Mil) CerDIP
Military
Commercial
Ordering Information (continued)
Speed
(ns)
Ordering Code
Package
Type
Package Type
Operating
Range
40
CY7C424–40PC
P15
28-Lead (600-Mil) Molded DIP
Commercial
65
CY7C424–65PC
P15
28-Lead (600-Mil) Molded DIP
Commercial
Ordering Information (continued)
Speed
(ns)
10
15
20
25
30
Ordering Code
Package
Type
Package Type
CY7C425–10AC
A32
32-Pin Thin Plastic Quad Flatpack
CY7C425–10JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C425–10PC
P21
28-Lead (300-Mil) Molded DIP
CY7C425–10VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C425–15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C425–15PC
P21
28-Lead (300-Mil) Molded DIP
CY7C425–15DMB
D22
28-Lead (300-Mil) CerDIP
CY7C425–15LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C425–20JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C425–20PC
P21
28-Lead (300-Mil) Molded DIP
CY7C425–20VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C425–25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C425–25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C425–25JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C425–25VI
V21
28-Lead (300-Mil) Molded SOJ
CY7C425–25DMB
D22
28-Lead (300-Mil) CerDIP
CY7C425–25LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C425–30JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C425–30PC
P21
28-Lead (300-Mil) Molded DIP
CY7C425–30VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C425–30VI
V21
28-Lead (300-Mil) Molded SOJ
Document #: 38-06001 Rev. *A
Operating
Range
Commercial
Commercial
Military
Commercial
Commercial
Industrial
Military
Commercial
Industrial
Page 15 of 22
CY7C419/21/25/29/33
Ordering Information (continued)
Speed
(ns)
40
65
Ordering Code
Package
Type
Package Type
Operating
Range
CY7C425–40JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C425–40PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
CY7C425–40VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C425–40JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C425–65JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C425–65PC
P21
28-Lead (300-Mil) Molded DIP
Ordering Information (continued)
Speed
(ns)
Ordering Code
Package
Type
Package Type
Operating
Range
20
CY7C428–20PC
P15
28-Lead (600-Mil) Molded DIP
Commercial
25
CY7C428–25DMB
D16
28-Lead (600-Mil) CerDIP
Military
65
CY7C428–65PC
P15
28-Lead (600-Mil) Molded DIP
Commercial
Ordering Information (continued)
Speed
(ns)
10
15
20
25
30
40
65
Ordering Code
Package
Type
Package Type
Operating
Range
CY7C429–10AC
A32
32-Pin Thin Plastic Quad Flatpack
CY7C429–10JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C429–10PC
P21
28-Lead (300-Mil) Molded DIP
CY7C429–15JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C429–15JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C429–15DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7C429–15LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C429–20JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C429–20PC
P21
28-Lead (300-Mil) Molded DIP
CY7C429–20VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C429–20DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7C429–25JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C429–25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C429–25VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C429–25JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C429–25DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7C429–25LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C429–30JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C429–30PC
P21
28-Lead (300-Mil) Molded DIP
CY7C429–30VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C429–30DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7C429–40AC
A32
32-Pin Thin Plastic Quad Flatpack
Commercial
CY7C429–40JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C429–40PC
P21
28-Lead (300-Mil) Molded DIP
CY7C429–65JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C429–65PC
P21
28-Lead (300-Mil) Molded DIP
CY7C429–65JI
J65
32-Lead Plastic Leaded Chip Carrier
Document #: 38-06001 Rev. *A
Commercial
Commercial
Commercial
Commercial
Industrial
Page 16 of 22
CY7C419/21/25/29/33
Ordering Information (continued)
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
25
CY7C432–25PC
P15
28-Lead (600-Mil) Molded DIP
Commercial
40
CY7C432–40PC
P15
28-Lead (600-Mil) Molded DIP
Commercial
Ordering Information (continued)
Speed
(ns)
10
15
20
25
30
40
65
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C433–10AC
A32
32-Pin Thin Plastic Quad Flatpack
CY7C433–10JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C433–10PC
P21
28-Lead (300-Mil) Molded DIP
CY7C433–10VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C433–15AC
A32
32-Pin Thin Plastic Quad Flatpack
CY7C433–15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C433–15JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C433–15PI
P21
28-Lead (300-Mil) Molded DIP
CY7C433–15DMB
D22
28-Lead (300-Mil) CerDIP
CY7C433–15LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C433–20AC
A32
32-Pin Thin Plastic Quad Flatpack
CY7C433–20JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C433–20PC
P21
28-Lead (300-Mil) Molded DIP
CY7C433–25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C433–25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C433–25VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C433–25JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C433–30JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C433–30PC
P21
28-Lead (300-Mil) Molded DIP
CY7C433–30JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C433–30PI
P21
28-Lead (300-Mil) Molded DIP
CY7C433–30DMB
D22
28-Lead (300-Mil) CerDIP
CY7C433–30LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C433–40JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C433–40PC
P21
28-Lead (300-Mil) Molded DIP
CY7C433–40VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C433–40JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C433–65JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C433–65PC
P21
28-Lead (300-Mil) Molded DIP
Document #: 38-06001 Rev. *A
Commercial
Commercial
Industrial
Military
Commercial
Commercial
Industrial
Military
Commercial
Page 17 of 22
CY7C419/21/25/29/33
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Switching Characteristics
Subgroups
Parameters
Subgroups
VOH
1, 2, 3
tRC
9, 10, 11
VOL
1, 2, 3
tA
9, 10, 11
VIH
1, 2, 3
tRR
9, 10, 11
VIL Max.
1, 2, 3
tPR
9, 10, 11
IIX
1, 2, 3
tDVR
9, 10, 11
ICC
1, 2, 3
tWC
9, 10, 11
ICC1
1, 2, 3
tPW
9, 10, 11
ISB1
1, 2, 3
tWR
9, 10, 11
ISB2
1, 2, 3
tSD
9, 10, 11
IOS
1, 2, 3
tHD
9, 10, 11
tMRSC
9, 10, 11
tPMR
9, 10, 11
tRMR
9, 10, 11
tRPW
9, 10, 11
tWPW
9, 10, 11
tRTC
9, 10, 11
tPRT
9, 10, 11
tRTR
9, 10, 11
tEFL
9, 10, 11
tHFH
9, 10, 11
tFFH
9, 10, 11
tREF
9, 10, 11
tRFF
9, 10, 11
tWEF
9, 10, 11
tWFF
9, 10, 11
tWHF
9, 10, 11
tRHF
9, 10, 11
tRAE
9, 10, 11
tRPE
9, 10, 11
tWAF
9, 10, 11
tWPF
9, 10, 11
tXOL
9, 10, 11
tXOH
9, 10, 11
Document #: 38-06001 Rev. *A
Page 18 of 22
CY7C419/21/25/29/33
Package Diagrams
32-Lead Thin Plastic Quad Flat Pack A32
28-Lead (600-Mil) CerDIP D16
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835
MIL-STD-1835
D- 10Config.A
Document #: 38-06001 Rev. *A
D- 15 Config.A
Page 19 of 22
CY7C419/21/25/29/33
Package Diagrams (continued)
32-Lead Plastic Leaded Chip Carrier J65
32-Pin Rectangular Leadless Chip Carrier L55
MIL-STD-1835 C-12
28-Lead (600-Mil) Molded DIP P15
Document #: 38-06001 Rev. *A
Page 20 of 22
CY7C419/21/25/29/33
Package Diagrams (continued)
28-Lead (300-Mil) Molded DIP P21
28-Lead (300-Mil) Molded SOJ V21
Document #: 38-06001 Rev. *A
Page 21 of 22
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C419/21/25/29/33
Document Title: CY7C419, CY7C421, CY7C425, CY7C429, CY7C433 256/512/1K/2K/4Kx9 Asynchronous FIFO
Document Number: 38-06001
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
106462
07/11/01
SZV
Change from Spec Number: 38-00079 to 38-06001
*A
122332
12/30/02
RBI
Added power up requirements to maximum ratings information.
Document #: 38-06001 Rev. *A
Page 22 of 22
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