ON MC33368DG High voltage greenline power factor controller Datasheet

MC33368
High Voltage GreenLinet
Power Factor Controller
The MC33368 is an active power factor controller that functions as a
boost preconverter in off−line power supply applications. MC33368 is
optimized for low power, high density power supplies requiring a
minimum board area, reduced component count and low power
dissipation. The narrow body SOIC package provides a small
footprint. Integration of the high voltage startup saves approximately
0.7 W of power compared to resistor bootstrapped circuits.
The MC33368 features a watchdog timer to initiate output
switching, a one quadrant multiplier to force the line current to follow
the instantaneous line voltage a zero current detector to ensure critical
conduction operation, a transconductance error amplifier, a current
sensing comparator, a 5.0 V reference, an undervoltage lockout
(UVLO) circuit which monitors the VCC supply voltage and a CMOS
driver for driving MOSFETs. The MC33368 also includes a
programmable output switching frequency clamp. Protection features
include an output overvoltage comparator to minimize overshoot, a
restart delay timer and cycle−by−cycle current limiting.
Features
MARKING
DIAGRAM
16
SO−16
D SUFFIX
CASE 751K
16
MC33368D
AWLYWWG
1
1
A
WL
YY, Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
Lossless Off−Line Startup
Output Overvoltage Comparator
Leading Edge Blanking (LEB) for Noise Immunity
Watchdog Timer to Initiate Switching
Restart Delay Timer
This is a Pb−Free Device*
(TOP VIEW)
16 Line
5.0 Vref
1
Restart Delay
2
Voltage FB
3
Comp
4
Mult
5
Current Sense
6
11 Gate
Zero Current
7
10 PGND
AGND
8
9 LEB
SO−16
•
•
•
•
•
•
http://onsemi.com
13 Frequency Clamp
12 VCC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. 11
1
Publication Order Number:
MC33368/D
MC33368
Line
Restart Delay
Restart Delay
VCC
Output
Overvoltage
FB
Comp
Mult
LEB
Current Sense
ZC Det
UVLO
Multiplier/
Error
Amplifier
S
PWM
Internal Bias
Generator
Vref
AGND
S
R
Current
Sense
Gate
Q
PGND
WatchdogTimer/
Zero Current Detector
Frequency
Clamp
Frequency
Clamp
This device contains 240 active transistors.
Figure 1. Representative Block Diagram
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted)
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Rating
Symbol
Value
Unit
Power Supply Voltage (Transient)
VCC
20
V
Power Supply Voltage (Operating)
VCC
16
V
Line Voltage
VLine
500
V
Current Sense, Multiplier, Compensation, Voltage Feedback, Restart Delay and Zero
Current Input Voltage
Vin1
−1.0 to +10
V
LEB Input, Frequency Clamp Input
Vin2
−1.0 to +20
V
Zero Current Detect Input
Iin
±5.0
mA
Restart Diode Current
Iin
5.0
mA
PD
RqJA
450
178
mW
°C/W
TJ
150
°C
Operating Ambient Temperature
TA
−25 to +125
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package Case 751K
Maximum Power Dissipation @ TA = 70°C
Thermal Resistance, Junction−to−Air
Operating Junction Temperature
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: ESD data available upon request.
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2
MC33368
ELECTRICAL CHARACTERISTICS (VCC = 14.5 V, for typical values TA = 25°C, for min/max values TJ = −25 to +125°C)
Characteristic
Symbol
Min
Typ
Max
Input Bias Current (VFB = 5.0 V)
IIB
Input Offset Voltage (VComp = 3.0 V)
VIO
Transconductance (VComp = 3.0 V)
Output Source (VFB = 4.6 V, VComp = 3.0 V)
Output Sink (VFB = 5.4 V, VComp = 3.0 V)
Unit
−
0
1.0
mA
−
2.0
50
mV
gm
30
51
80
mmho
IO
IO
9.0
9.0
17.5
17.5
30
30
mA
VFB(OV)
1.07 VFB
1.084 VFB
1.1 VFB
V
TP
−
705
−
ns
IIB
−
−0.2
−1.0
mA
Input Threshold, VComp
Vth(M)
1.8
2.1
2.4
V
Dynamic Input Voltage Range
Multiplier Input
Compensation
VMult
VComp
0 to 2.5
Vth(M) to
(Vth(M) + 1.0)
0 to 3.5
Vth(M) to
(Vth(M) + 2.0)
−
−
K
0.25
0.51
0.75
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ERROR AMPLIFIER
OVERVOLTAGE COMPARATOR
Voltage Feedback Input Threshold
Propagation Time to Output
MULTIPLIER
Input Bias Current, VMult (VFB = 0 V)
V
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Multiplier Gain (VMult = 0.5 V, VComp = Vth(M) + 1.0 V)
V
K+
V
CS
Mult
V
1/V
Threshold
–V
th(M)
Comp
VOLTAGE REFERENCE
Voltage Reference (IO = 0 mA, TJ = 25°C)
Vref
4.95
5.0
5.05
V
Line Regulation (VCC = 10 V to 16 V)
Regline
−
5.0
100
mV
Load Regulation (IO = 0 − 5.0 mA)
Regload
−
5.0
100
mV
Vref
4.8
−
5.2
V
Maximum Output Current
IO
5.0
10
−
mA
Reference Undervoltage Lockout Threshold
Vth
−
4.5
−
V
Input Threshold Voltage (Vin Increasing)
Vth
1.0
1.2
1.4
V
Hysteresis (Vin Decreasing)
VH
100
200
300
mV
Delay to Output
Tpd
−
127
−
ns
Input Bias Current (VCS = 0 to 2.0 V)
IIB
−
0.2
1.0
mA
Input Offset Voltage (VMult = −0.2 V)
VIO
−
4.0
50
mV
Vth(max)
1.3
1.5
1.8
V
tPHL(in/out)
50
270
425
ns
Vth(FC)
1.9
2.0
2.1
V
Frequency Clamp Capacitor Reset Current (VFC = 0.5 V)
Ireset
0.5
1.7
4.0
mA
Frequency Clamp Disable Voltage
VDFC
−
7.3
8.0
V
Total Output Variation Over Line, Load and Temperature
ZERO CURRENT DETECTOR
CURRENT SENSE COMPARATOR
Maximum Current Sense Input Threshold (VComp = 5.0 V,
VMult = 5.0 V)
Delay to Output (VLEB = 12 V, VComp = 5.0 V, VMult = 5.0 V)
(VCS = 0 to 5.0 V Step, CL = 1.0 nF)
FREQUENCY CLAMP
Frequency Clamp Input Threshold
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3
MC33368
ELECTRICAL CHARACTERISTICS (continued) (VCC = 14.5 V, for typical values TA = 25°C, for min/max values TJ = −25 to +125°C)
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Characteristic
Symbol
Min
Typ
Max
Unit
Source Resistance (Current Sense = 0 V, VGate = VCC − 1.0 V)
Sink Resistance (Current Sense = 3.0 V, VGate = 1.0 V)
ROH
ROL
4.0
4.0
8.6
7.2
20
20
W
Output Voltage Rise Time (25% − 75%) (CL = 1.0 nF)
tr
−
55
200
ns
Output Voltage Fall Time (75% − 25%) (CL = 1.0 nF)
tf
−
70
200
ns
VO(UV)
−
0.01
0.25
V
Input Bias Current
Ibias
−
0.1
0.5
mA
Threshold (as Offset from VCC) (VLEB Increasing)
VLEB
1.0
2.25
2.75
V
VH
100
270
500
mV
Vth(on)
11.5
13
14.5
V
VShutdown
7.0
8.5
10
V
VH
−
4.5
−
V
tDLY
180
385
800
ms
Vth(restart)
1.5
2.3
3.0
V
Irestart
3.1
5.2
7.1
mA
Line Startup Current (VCC = 0 V, VLine = 50 V)
ISU
5.0
16
25
mA
Line Operating Current (VCC = Vth(on), VLine = 50 V)
IOP
3.0
12.9
20
mA
VCC Dynamic Operating Current (50 kHz, CL = 1.0 nF)
VCC Static Operating Current (IO = 0)
ICC
−
−
5.3
3.0
8.5
−
mA
Line Pin Leakage (VLine = 500 V)
ILine
−
30
80
mA
DRIVE OUTPUT
Output Voltage in Undervoltage (VCC = 7.0 V, ISink = 1.0 mA)
LEADING EDGE BLANKING
Hysteresis (VLEB Decreasing)
UNDERVOLTAGE LOCKOUT
Startup Threshold (VCC Increasing)
Minimum Operating Voltage After Turn−On (VCC Decreasing)
Hysteresis
TIMER
Watchdog Timer
Restart Timer Threshold
Restart Pin Output Current (Vrestart = 0 V, Vref = 5.0 V)
TOTAL DEVICE
ORDERING INFORMATION
Package
Shipping†
MC33368DG
SOIC−16
(Pb−Free)
48 Units / Rail
MC33368DR2G
SOIC−16
(Pb−Free)
2500 Units / Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
1.6
VCC = 14 V
TA = 25°C
1.4
VCS, CURRENT SENSE PIN 6 THRESHOLD (V)
VCS, CURRENT SENSE PIN 6 THRESHOLD (V)
MC33368
VPin 4 = 4.0 V
= 3.75 V
= 3.0 V
1.2
= 3.5 V
1.0
= 2.75 V
= 3.25 V
0.8
= 2.5 V
0.6
0.4
= 2.25 V
0.2
= 2.0 V
0.6
1.4
2.2
3.0
0.04
8.0
4.0
0
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (°C)
0.02
0
-0.12
= 2.0 V
-0.06
0
0.06
0.12
0.20
110
VCC = 14 V
109
108
107
106
-55
30
60
60
Transconductance
90
100
120
150
1.0 k
10 k
100 k
θ, EXCESS PHASE (DEGREES)
80
VCC = 14 V
VO = 2.0 to 4.0 V
RL = 10 kW
TA = 25°C
180
10 M
1.0 M
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (°C)
6.0 V
Phase
40
-25
Figure 5. Overvoltage Comparator Input
Threshold versus Temperature
0
100
g m, TRANSCONDUCTANCE (μ mho)
= 2.25 V
0.01
Figure 4. Reference Voltage versus Temperature
-20
10
= 2.5 V
0.03
Figure 3. Current Sense Input Threshold
versus Multiplier Input, Expanded View
12
0
= 2.75 V
0.05
Figure 2. Current Sense Input Threshold
versus Multiplier Input
VCC = 14 V
20
= 3.0 V
0.06
VM, MULTIPLIER PIN 5 INPUT VOLTAGE (V)
16
-4.0
-55
VPin 4 = 4.0 V
0.07
VM, MULTIPLIER PIN 5 INPUT VOLTAGE (V)
VFB(OV), OVERVOLTAGE INPUT THRESHOLD (% VFB )
ΔVFB , VOLTAGE FEEDBACK THRESHOLD
CHANGE (mV)
0
-0.2
0.08
VCC = 14 V
TA = 25°C
4.0 V
2.0 V
0V
-1.0 V
f, FREQUENCY (Hz)
5.0 ms/DIV
Figure 6. Error Amplifier Transconductance
and Phase versus Frequency
Figure 7. Error Amplifier Transient Response
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5
1.50
VCC = 14 V
Voltage
1.76
1.72
1.10
Current
1.68
1.64
-55
-25
0
25
50
75
0.90
100
0.70
125
500
VCC = 14 V
460
420
380
340
-55
-25
0
25
50
75
100
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 8. Quickstart Charge Current
versus Temperature
Figure 9. Watchdog Timer Delay
versus Temperature
125
6.0
20
OUTPUT VOLTAGE (V)
1.30
I chg, QUICKSTART CHARGE CURRENT (mA)
t DLY, WATCHDOG TIME DELAY ( μ s)
1.80
VCC = 14 V
CL = 1000 pF
TA = 25°C
15
I CC , SUPPLY CURRENT (mA)
Vchg, QUICKSTART CHARGE VOLTAGE (V)
MC33368
10
5.0
0
-5.0
Pulse tested with a 4.0 V peak, 50 kHz square
wave through a 22 k resistance into Pin 7.
4.0
2.0
2.0
5.0 ms/DIV
0
Figure 10. Drive Output Waveform
CO = 1000 pF
Pin 3, 6, 8= GND
Pin 5 = 1.0 k to GND
TA = 25°C
4.0
6.0
8.0
10
12
14
VCC, SUPPLY VOLTAGE (V)
Figure 11. Supply Current versus
Supply Voltage
1000
OUTPUT VOLTAGE (V)
Rθ JA(t), THERMAL RESISTANCE
JUNCTION-TO-AIR ( °C/W)
100
200
Output
Voltage
0
2.0
1.0
Load
Current
0
10
0.01
0.1
1.0
10
100
t, TIME (s)
200 ms/DIV
Figure 12. Transient Thermal Resistance
Figure 13. Low Load Detection
Response Waveform
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6
OUTPUT CURRENT (A)
3.0
400
MC33368
FUNCTIONAL DESCRIPTION
INTRODUCTION
input circuits operate at a frequency much higher than that
of the ac line, they are smaller, lighter in weight, and more
efficient than a passive circuit that yields similar results.
With proper control of the preconverter, almost any complex
load can be made to appear resistive to the ac line, thus
significantly reducing the harmonic current content.
With the goal of exceeding the requirements of legislation
on line current harmonic content, there is an ever increasing
demand for an economical method of obtaining a unity
power factor. This data sheet describes a monolithic control
IC that was specifically designed for power factor control
with minimal external components. It offers the designer a
simple cost effective solution to obtain the benefits of active
power factor correction.
Most electronic ballasts and switching power supplies use
a bridge rectifier and a bulk storage capacitor to derive raw
dc voltage from the utility ac line, Figure 14.
Operating Description
The MC33368 contains many of the building blocks and
protection features that are employed in modern high
performance current mode power supply controllers.
Referring to the block diagram in Figure 16, note that a
multiplier has been added to the current sense loop and that
this device does not contain an oscillator. A description of
each of the functional blocks is given below.
Converter
Rectifiers
Bulk
Storage
Capacitor
AC
Line
Error Amplifier
Load
An Error Amplifier with access to the inverting input and
output is provided. The amplifier is a transconductance type,
meaning that it has high output impedance with controlled
voltage−to−current gain (gm 50 mmhos). The noninverting
input is internally biased at 5.0 V ±2.0%. The output voltage
of the power factor converter is typically divided down and
monitored by the inverting input. The maximum input bias
current is −1.0 mA which can cause an output voltage error
that is equal to the product of the input bias current and the
value of the upper divider resistor R2. The Error Amplifier
output is internally connected to the Multiplier and is pinned
out (Pin 4) for external loop compensation. Typically, the
bandwidth is set below 20 Hz so that the amplifier’s output
voltage is relatively constant over a given ac line cycle. In
effect, the error amplifier monitors the average output voltage
of the converter over several line cycles resulting in a fixed
Drive Output on−time. The amplifier output stage can sink
and source 11.5 mA of current and is capable of swinging from
1.7 to 5.0 V, assuring that the Multiplier can be driven over its
entire dynamic range.
Note that by using a transconductance type amplifier, the
input is allowed to move independently with respect to the
output, since the compensation capacitor is connected to
ground. This allows dual usage of the Voltage Feedback pin
by the Error Amplifier and Overvoltage Comparator.
Figure 14. Uncorrected Power Factor Circuit
This simple rectifying circuit draws power from the line
when the instantaneous ac voltage exceeds the capacitor
voltage. This occurs near the line voltage peak and results in
a high charge current spike, Figure 15. Since power is only
taken near the line voltage peaks, the resulting spikes of
current are extremely nonsinusoidal with a high content of
harmonics. This results in a poor power factor condition
where the apparent input power is much higher than the real
power. Power factor ratios of 0.5 to 0.7 are common.
Vpk
Rectified
DC
0
Line Sag
AC Line
Voltage
Overvoltage Comparator
0
An Overvoltage Comparator is incorporated to eliminate
the possibility of runaway output voltage. This condition
can occur during initial startup, sudden load removal, or
during output arcing and is the result of the low bandwidth
that must be used in the Error Amplifier control loop. The
Overvoltage Comparator monitors the peak output voltage
of the converter, and when exceeded, immediately
terminates MOSFET switching. The comparator threshold
is internally set to 1.08 Vref. In order to prevent false tripping
during normal operation, the value of the output filter
capacitor C3 must be large enough to keep the peak−to−peak
ripple less than 16% of the average dc output.
AC Line
Current
Figure 15. Uncorrected Power Factor Input Waveforms
Power factor correction can be achieved with the use of
either a passive or active input circuit. Passive circuits
usually contain a combination of large capacitors, inductors,
and rectifiers that operate at the ac line frequency. Active
circuits incorporate some form of a high frequency
switching converter for the power processing with the boost
converter being the most popular topology. Since active
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7
MC33368
Multiplier
voltage sensing is lost. Under these conditions, the Current
Sense Comparator threshold will be internally clamped to
1.5 V. Therefore, the maximum peak switch current is:
A single quadrant, two input multiplier is the critical
element that enables this device to control power factor. The
ac haversines are monitored at Pin 5 with respect to ground
while the Error Amplifier output at Pin 4 is monitored with
respect to the Voltage Feedback Input threshold. A graph of
the Multiplier transfer curve is shown in Figure 2. Note that
both inputs are extremely linear over a wide dynamic range,
0 to 3.2 V for Pin 5 and 2.5 to 4.0 V for Pin 4. The Multiplier
output controls the Current Sense Comparator threshold as
the ac voltage traverses sinusoidally from zero to peak line.
This has the effect of forcing the MOSFET on−time to track
the input line voltage, thus making the preconverter load
appear to be resistive.
ǒ
Pin 6 Threshold [ 0.55 V
Pin 4
–V
I
A watchdog timer function was added to the IC to
eliminate the need for an external oscillator when used in
stand alone applications. The Timer provides a means to
automatically start or restart the preconverter if the Drive
Output has been off for more than 385 ms after the inductor
current reaches zero.
Ǔ VPin 5
Pin 3
Undervoltage Lockout and Quickstart
The MC33368 has a 5.0 V internal reference brought out
to Pin 1 and capable of sourcing 10 mA typically. It also
contains an Undervoltage Lockout (UVLO) circuit which
suppresses the Gate output at Pin 11 if the VCC supply
voltage drops below 8.5 V typical.
A Quickstart circuit has been incorporated to optimize
converter startup. During initial startup, compensation
capacitor C1 will be discharged, holding the Error Amplifier
output below the Multiplier’s threshold. This will prevent
Drive Output switching and delay bootstraping of capacitor
C4 by diode D6. If Pin 4 does not reach the multiplier
threshold before C4 discharges below the lower SMPS
UVLO threshold, the converter will hiccup and experience
a significant startup delay. The Quickstart circuit is designed
to precharge C1 to 1.7 V. This level is slightly below the
Pin 4 Multiplier threshold, allowing immediate Drive
Output switching.
Restart Delay
A restart delay pin is provided to allow hiccup mode fault
protection in case of a short circuit condition and to prevent
the SMPS from repeatedly trying to restart after the input
line voltage has been removed. When power is first applied,
there is no startup delay, but subsequent cycling of the VCC
voltage will result in delay times that are programmed by an
external resistor and capacitor. The Restart Delay, Pin 2, is
a high impedance, so that an external capacitor can provide
delay times as long as several seconds.
If the SMPS output is short circuited, the transformer
winding, which provides the VCC voltage to the control IC
and the MC33368, will be unable to sustain VCC to the
control circuits. The restart delay capacitor at Pin 2 of the
MC33368 prevents the high voltage startup transistor within
the IC from maintaining the voltage on C4. After VCC drops
below the UVLO threshold in the SMPS, the SMPS
switching transistors are held off for the time programmed
by the values of the restart capacitor (C9) and resistor (R8).
Current Sense Comparator and RS Latch
The Current Sense Comparator RS Latch configuration
used ensures that only a single pulse appears at the Drive
Output during a given cycle. The inductor current is
converted to a voltage by inserting a ground−referenced
sense resistor R7 in series with the source of output switch.
This voltage is monitored by the Current Sense Input and
compared to a level derived from the Multiplier output. The
peak inductor current under normal operating conditions is
controlled by the threshold voltage of Pin 6 where:
+
1.5 V
R7
Timer
The MC33368 operates as a critical conduction current
mode controller, whereby output switch conduction is
initiated by the Zero Current Detector and terminated when
the peak inductor current reaches the threshold level
established by the Multiplier output. The Zero Current
Detector initiates the next on−time by setting the RS Latch
at the instant the inductor current reaches zero. This critical
conduction mode of operation has two significant benefits.
First, since the MOSFET cannot turn−on until the inductor
current reaches zero, the output rectifier’s reverse recovery
time becomes less critical allowing the use of an inexpensive
rectifier. Second, since there are no deadtime gaps between
cycles, the ac line current is continuous thus limiting the
peak switch to twice the average input current
The Zero Current Detector indirectly senses the inductor
current by monitoring when the auxiliary winding voltage
falls below 1.2 V. To prevent false tripping, 200 mV of
hysteresis is provided. The Zero Current Detector input is
internally protected by two clamps. The upper 10 V clamp
prevents input overvoltage breakdown while the lower
−0.7 V clamp prevents substrate injection. An external
resistor must be used in series with the auxiliary winding to
limit the current through the clamps to 5.0 mA or less.
pk
+
With the component values shown in Figure 16, the
Current Sense Comparator threshold, at the peak of the
haversine, varies from 110 mV at 90 Vac to 100 mV at
268 Vac. The Current Sense Input to Drive Output
propagation delay is typically 200 ns.
Zero Current Detector
I
pk(max)
Pin 6 Threshold
R7
Abnormal operating conditions occur when the
preconverter is running at extremely low line or if output
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8
MC33368
Switching Frequency Clamp function can be disabled by
connecting the FC input, Pin 13, to the VCC supply Pin 12.
For best results, the minimum off−time, determined by the
values of R10 and C7, should be chosen so that ts(min) = t(on)
+ t(off)fc. Output drive is inhibited when the voltage at the
frequency clamp input is less than 2.0 V. When the output
drive is high, C7 is discharged through an internal 100 mA
current source. When the output drive switches low, C7 is
charged through R10. The drive output is inhibited until the
voltage across C7 reaches 2.0 V, establishing a minimum
off−time where:
In this manner, the SMPS switching transistors are operated
at very low duty cycles, preventing their destruction. If the
short circuit fault is removed, the power supply system will
turn on by itself in a normal startup mode after the restart
delay has timed out.
Output Switching Frequency Clamp
In normal operation, the MC33368 operates the boost
inductor in the critical mode. That is, the inductor current
ramps to a peak value, ramps down to zero, then
immediately begins ramping positive again. The peak
current is programmed by the multiplier output within the
IC. As the input voltage haversine declines to near zero, the
output switch on−time becomes constant, rather than going
to zero because of the small integrated dc voltage at Pin 5
caused by C2, R3 and R5. Because of this, the average line
current does not exactly follow the line voltage near the zero
crossings. The Output Switching Frequency Clamp
remedies this situation to improve power factor and
minimize EMI generated in this operating region. The
values of R10 and C7, as shown in Figure 16, program a
minimum off−time in the frequency clamp which overrides
the zero current detect signal, forcing a minimum off−time.
This allows discontinuous conduction operation of the boost
inductor in the zero crossing region, and the average line
current more nearly follows the voltage. The Output
t
(off)fc
+ * R10 C7 log e
ƪ ǒ Ǔƫ
1 *
V
2
CC
Output
The IC contains a CMOS output driver that was
specifically designed for direct drive of power MOSFETs.
The Gate Output is capable of up to ±1500 mA peak current
with a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the Gate
Output in a sinking mode whenever the Undervoltage
Lockout is active. This characteristic eliminates the need for
an external gate pull−down resistor. The totem−pole output
has been optimized to minimize cross−conduction current
during high speed operation.
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9
MC33368
Table 1. Design Equations
Calculation
Formula
Converter Output Power
P
+ V
O
I
L(pk)
ǒ
Inductance
t
L +
P
+
h Vac
O –Vac
(LL)
Ǹ2
Ǹ2 V
(on)
+
(off)
Minimum Switch
Off−Time
t
t
+
min
V
t + – R10 C7 ln
d
Switching Frequency
t
(on)
Peak Switch Current
Multiplier Input Voltage
NOTE:
V
DV
O(pp)
O
+ V
+I
+
ref
L(pk)
ǒ
O
V
CC
V
)t
V
R7 +
Converter Output
Voltage
–1
Ǔ
–2
CC
I
(off)
L(pk)
Set the multiplier input voltage VM to 3.0 V at high line.
Empirically adjust VM for the lowest distortion over the
ac line voltage range while guaranteeing startup at
minimum line.
ǒR5
) 1Ǔ
R3
ǒR2
) 1Ǔ – I IB R1
R1
BW +
The delay time is used to override the minimum
off−time at the ac line zero crossings by programming
the Frequency Clamp with C7 and R10.
Set the current sense threshold VCS to 1.0 V for
universal input (85 to 265 Vac) operation and to 0.5 V
for fixed input (92 to 138 Vac, or 184 to 276 Vac)
operation. Note that VCS must be less than 1.4 V.
CS
Vac Ǹ 2
Ǹǒ
The off−time is at a minimum at ac line crossings. This
equation is used to calculate t(off) as Theta approaches
zero.
The minimum switching frequency occurs at the peak of
the ac line voltage. As the ac line voltage traverses
from peak to zero, t(off) approaches zero producing an
increase in switching frequency.
1
f+
M
The off−time t(off) is greatest at the peak of the ac line
voltage and approaches zero at the ac line zero
crossings. Theta (q) represents the angle of the ac line
voltage.
L I
P L(pk)
+
Let the switching cycle t = 40 ms for universal input (85
to 265 Vac) operation and 20 ms for fixed input (92 to
138 Vac, or 184 to 276 Vac) operation.
In theory, the on−time t(on) is constant. In practice, t(on)
tends to increase at the ac line zero crossings due to
the charge on capacitor C5. Let Vac = Vac(LL) for initial
t(on) and t(off) calculations.
(on)
Delay Time
V
2
L
O P
V
O
Ǹ 2 Vac ŤSin qŤ
(off)
(LL)
h Vac 2
Switch Off−Time
t
h Vac
P
O O
2P
t
Calculated at the minimum required ac line voltage for
output regulation. Let the efficiency η = 0.92 for low line
operation.
O
(LL)
Ǔ
V
Switch On−Time
Error Amplifier
Bandwidth
I
O O
2 Ǹ2 P
Peak Indicator Current
Converter Output
Peak−to−Peak
Ripple Voltage
Notes
Calculate the maximum required output power.
Ǔ
1
2 p f ac C3
2
) ESR 2
The IIB R1 error term can be minimized with a divider
current in excess of 100 mA.
The calculated peak−to−peak ripple must be less than
16% of the average dc output voltage to prevent false
tripping of the Overvoltage Comparator. Refer to the
Overvoltage Comparator Text. ESR is the equivalent
series resistance of C3.
The bandwidth is typically set to 20 Hz. When operating
at high ac line, the value of C1 may need to be
increased.
gm
2 p C1
The following converter characteristics must be chosen:
VO = Desired output voltage.
Vac(LL) = AC RMS minimum required operating line voltage for output regulation.
IO = Desired output current.
DVO = Converter output peak−to−peak ripple voltage.
Vac = AC RMS operating line voltage.
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10
MC33368
1N4006
D4
D2
92 to
270
Vrms
EMI
Filter
D1
C5
1.0
D3
Line
16
MC33368
Vref
Vref
D6
D8 R13
VCC 1N4744 51 1N4934
15 V
R8
10 k
RD
C9
330 mF
2
AGND
UVLO
Timer
Q
8
R
12
Zero
Current
Detect
RS Latch
7 15 V
ZCD
1.2/1.0
R
R
S
S
Q
S
Set Dominant
1.5 V
T
R4
22 k
Gate
320 mH
MUR130
VO
D5
C3
220
To VCC
Pin 12
PGND
R5
1.3 M
Q1
R11
10
11
Overvoltage
Comparator
MTP8N50E
R2
470 k
10
Low
Load Detect
FC
9
LEB
6
Leading Edge
Blanking
CS
Mult
R7
0.1
0.25 W
5.0 V
Reference
5
C2
0.01
R10
10
C7
10 pF
13
Frequency
Clamp
1.08 x Vref
Quickstart
R3
20 k
C4
100
13/8.0
Multiplier
4
1
Comp
3
Vref
C1
0.68
Vref
C6
0.1
FB
T: Coilcraft N2881−A
Primary = 62 turns of #22 AWG
Secondary = 5 turns of #22 AWG
Core = Coilcraft PT2510, EE25
Gap = 0.072″ total for a primary inductance (Lp) of 320 mH
Not Used: D7, C8, R6, R9
Power Factor Controller Test Data
DC Output
AC Line Input
Vrms
Pin
PF
Ifund
Current Harmonic Distortion (% Ifund)
THD
2
3
5
7
90
79.7
0.999
0.89
0.5
0.15
0.09
0.06
100
79.3
0.998
0.79
0.5
0.14
0.09
110
78.9
0.997
0.72
0.5
0.16
0.13
120
78.5
0.996
0.66
0.5
0.15
130
78.1
0.994
0.60
0.5
0.14
138
77.8
0.991
0.57
0.5
0.15
VO(pp)
VO
IO
PO
n(%)
0.09
3.0
244.4
0.31
76.01
95.4
0.08
0.10
3.0
242.9
0.31
75.54
95.3
0.08
0.10
3.0
242.9
0.31
75.30
95.4
0.12
0.08
0.13
3.0
243.0
0.31
75.57
96.3
0.12
0.07
0.14
3.0
243.0
0.31
75.57
96.7
0.14
0.08
0.14
3.0
243.0
0.31
75.57
97.1
Heatsink = AAVID Engineering Inc., 590302B03600, or 593002B03400
Figure 16. 80 W Power Factor Controller
http://onsemi.com
11
R1
10 k
MC33368
1N5406
D2
EMI
Filter
92 to
270 Vrms
C5
1.0
D4
D1
D3
Line
16
MC33368
Vref
Vref
D8 R13
D6
VCC 1N4744 51 1N4934
15 V
R8
1.0 M
RD
C9
2.2
2
AGND
UVLO
Q
8
Timer
R
RS Latch
R
R
S
S
Q
S
Set Dominant
1.5 V
12
Zero
Current
Detect
7 15 V
ZCD
R4
22 k
6.9 V
1.2/1.0
T
MUR460
Gate
R11
10
11
Overvoltage
Comparator
PGND
R5
1.3 M
Q1
C3
330
To VCC
Pin 12
MTW20N50E
R2
820 k
13
Frequency
Clamp
1.08 x Vref
FC
9
Quickstart
LEB
6
Leading Edge
Blanking
CS
Mult
C2
0.01
R7
0.1
5.0 V
Reference
5
Multiplier
Comp
4
1
C1
2.2
Vref
FB
3
T: Coilcraft N2880−A
L = 870 mHy
Primary: 78 turns of #16 AWG
Secondary: 6 turns of #18 AWG
Core: Coilcraft PT4215, EE42−15
Gap: 0.104″ total
Vref
C6
0.1
Not Used: D7, C7, C8, R6, R9, R10
Power Factor Controller Test Data
DC Output
AC Line Input
Current Harmonic Distortion (% Ifund)
Vrms
Pin
PF
VO
D5
10
Low
Load Detect
R3
10 k
C4
100
13/8.0
Ifund
THD
2
3
5
7
VO(pp)
VO
IO
PO
n(%)
90
190.4 0.995
2.11
5.8
0.16
0.32
0.24
0.80
3.6
398.0
0.44
175.9
92.4
120
192.1 0.997
1.60
3.2
0.08
0.17
0.07
0.30
3.6
398.9
0.44
177.1
92.2
138
192.7 0.997
1.40
0.9
0.08
0.24
0.03
0.15
3.6
402.3
0.45
179.0
92.9
180
194.3 0.995
1.08
0.9
0.04
0.18
0.04
0.08
3.6
409.1
0.45
182.9
94.1
240
189.3 0.983
0.80
0.7
0.08
0.21
0.08
0.06
3.6
407.0
0.45
181.1
95.7
268
186.3 0.972
0.71
0.6
0.11
0.32
0.10
0.10
3.6
406.2
0.44
180.4
96.8
Heatsink = AAVID Engineering Inc., 590302B03600
Figure 17. 175 W Universal Input Power Factor Controller
http://onsemi.com
12
R1
10 k
MC33368
Line
2X Step-up
Isolation
Transformer
Autoformer
EMI Filter
AC Power
Analyzer
PM 1000
HI
115 Vrms
Input
W
VA
VD
Acf Ainst Freq HARM
HI
0.1
A
1
T
PF Vrms Arms
0
V
L.O.
0 to 270 Vac
1.0 Output to
Power Factor
Correction
Circuit
L.O.
Neutral
Voltech
An RFI filter is required for best performance when connecting the preconverter directly to the ac line. The filter attenuates the level of high
frequency switching that appears on the ac line current waveform. Figures 16 and 17 work well with commercially available two stage filters
such as the Delta Electronics 03DPCG6. Shown above is a single stage test filter that can easily be constructed with four ac line rated
capacitors and a common−mode transformer. Coilcraft CMT3−28−2 was used to test Figures 16 and 17. It has a minimum inductance of 28 mH
and a maximum current rating of 2.0 A. Coilcraft CMT4−17−9 was used to test Figure 20. It has a minimum inductance of 17 mH and a
maximum current rating of 9.0 A. Circuit conversion efficiency η (%) was calculated without the power loss of the RFI filter.
Figure 18. Power Factor Test Setup
D2
92 to
270 Vrms
EMI
Filter
D1
D4
C5
1.0
D3
Line
16
Vref
Vref
MC33368
R8
10 k
15 V
RD
C9
330 mF
UVLO
Timer
Q
2
AGND
8
0V
1.2/1.0
6.9 V
R5
1.3 M
10
13
Frequency
Clamp
C1
22
1
VCC
Vref
C6
0.1
Vref
3
10 k
1.0 k
2N3904
1.0 k
Figure 19. On/Off Control
http://onsemi.com
13
MTW14N50E
R2
820 k
R7
0.1
5.0 V
Reference
Comp
C3
330
CS
Mult
4
Q1
LEB
6
Leading Edge
Blanking
Multiplier
R11
10
DC
Out
D5
FC
9
Quickstart
C2
0.01
T
PGND
1.08 x Vref
R3
10 k
7 15 V
ZCD
R4
22 k
11
Low
Load Detect
5
C4
100
Gate
Overvoltage
Comparator
Off
On
13/8.0
R
R
S
S
Q
S
Set Dominant
On/Off
Input
5.0 V
12
Zero
Current
Detect
RS Latch
1.5 V
1N4148
R
R13
51 D6
VCC D8
FB
R1
10 k
MC33368
92 to
270
Vac
D2
1N5406
D4
D1
D3
EMI
Filter
C5
1.0
Line
16
Vref
Vref
MC33368
R8
1.0 M
15 V
RD
C9
330 mF
UVLO
Q
2
AGND
8
Timer
R
12
Zero
Current
Detect
13/8.0
RS Latch
1.2/1.0
R
R
S
S
Q
S
Set Dominant
1.5 V
1.5 V
1N4934
C4
100
7 15 V
ZCD
R4
22 k
T
MUR460
D5
Gate
Q1
11
C3 400 V
330
R11
10
Overvoltage
Comparator
PGND
R5
1.3 M
MTW20N50E
Vref
R2
820 k
10
Low
Load Detect
13
Frequency
Clamp
1.08 x Vref
CS
Mult
C2
0.01
5.0 V
Reference
Multiplier
4
Comp
C1
1.0
1
Vref
C6
0.1
C7
470 pF
LEB
6
Leading Edge
Blanking
5
R10
10 k
FC
9
Quickstart
R3
10.5 k
R13
51 D6
1N4744
VCC D8
3
R9
10
C8
0.001
R7
0.1
FB
Vref
R1
10 k
Figure 20. 400 W Power Factor Controller
http://onsemi.com
14
MC33368
D3
DC Output
C6
AC Input
D1
R3 C2
C5
D7
R5
R1
R2
R8
R6
C1
D2
R4
D6
IC1
C9
C7
R10
J
C8
J
D4
R7
C4
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÏÏÏÏ
ÎÎÎÎÎÎ
ÏÏÏÏ
R13
R11 J
J
R9
Transformer
D8
Q1
C3
S
D
G
D5
J = Jumper
(Top View)
4.5″
MC33368
3.0″
(Bottom View)
Figure 21. Printed Circuit Board and Component Layout
(Circuits of Figures 16 and 17)
http://onsemi.com
15
MC33368
PACKAGE DIMENSIONS
SO−16
D SUFFIX
CASE 751K−01
ISSUE O
16
S
−A−
−B−
0.25 (0.010)
M
B
9
P
1
M_
F
8
G
R X 45 _
C
−T−
K
14 X D
0.25 (0.010)
SEATING
PLANE
J
M
T A
S
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005)
TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.368
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
S
GreenLine is a trademark of Motorola, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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16
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MC33368/D