ON FS6377-01iG-XTP Programmable 3-pll clock generator ic Datasheet

FS6377
Programmable 3-PLL Clock Generator IC
1.0 Key Features
•
•
•
•
•
•
•
•
•
Three on-chip PLLs with programmable reference and feedback dividers
Four independently programmable muxes and post dividers
I2C™-bus serial interface
Programmable power-down of all PLLs and output clock drivers
One PLL and two mux/post-divider combinations can be modified by SEL_CD input
Tristate outputs for board testing
5V to 3.3V operation
Accepts 5MHz to 27MHz crystal resonators
Commercial and industrial temperature ranges offered
2.0 General Description
The FS6377 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. Three
2
I C-programmable phase locked loops (PLLs) feeding four programmable muxes and post dividers provide a high degree of flexibility.
Figure 1: Pin Configuration
©2008 SCILLC. All rights reserved.
May 2008 – Rev. 4
Publication Order Number:
FS6377/D
FS6377
Figure 2: Block Diagram
Table 1: Pin Descriptions
Pin
Type
Name
Description
U
SDA
Serial interface data input/output
SEL_CD
Selects one of two PLL C, mux D/C and post divider C/D combinations
PD
Power-down input
VSS
Ground
1
DI O
2
DI
U
3
DI
U
4
P
5
AI
XIN
Crystal oscillator input
6
AO
XOUT
Crystal oscillator output
7
DI
8
P
9
DI
10
DO
U
U
OE
Output enable input
VDD
Power supply (5V to 3.3V)
ADDR
Address select
CLK_D
D clock output
11
P
VSS
Ground
12
DO
CLK_C
C clock output
13
DO
CLK_B
B clock output
14
P
VDD
Power supply (5V to 3.3V)
15
DO
16
DI
U
CLK_A
A clock output
SCL
Serial interface clock output
Key: AI: Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-up; DID = Input with Internal Pull-down; DIO = Digital Input/Output;
DI-3 = Three-level Digital Input; DO = Digital Output; P = Power/Ground; # = Active Low Pin
Rev. 4 | Page 2 of 24 | www.onsemi.com
FS6377
3.0 Functional Block Description
3.1 Phase Locked Loops (PLLs)
Each of the three on-chip PLLs is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a
desired frequency by a ratio of integers. This frequency multiplication is exact.
As shown in Figure 3, each PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop
filter, a voltage-controlled oscillator (VCO), and a feedback divider.
During operation, the reference frequency (fREF), generated by the on-board crystal oscillator, is first reduced by the reference divider.
The divider value is called the "modulus," and is denoted as NR for the reference divider. The divided reference is then fed into the PFD.
The PFD controls the frequency of the VCO (fVCO) through the charge pump and loop filter. The VCO provides a high speed, low noise,
continuously variable frequency clock source for the PLL. The output of the VCO is fed back to the PFD through the feedback divider
(the modulus is denoted by NF) to close the loop.
The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at
the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is:
Figure 3: PLL Diagram
3.1.1. Reference Divider
The reference divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divideddown frequency to the PFD. The reference divider is an 8-bit divider, and can be programmed for any modulus from 1 to 255 by
programming the equivalent binary value. A divide-by-256 can also be achieved by programming the eight bits to 00h.
3.1.2. Feedback Divider
The feedback divider is based on a dual-modulus prescaler technique. The technique allows the same granularity as a fully
programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also
called a prescaler) is placed between the VCO and the programmable feedback divider because of the high speeds at which the VCO
can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall
power consumption of the divider.
Rev. 4 | Page 3 of 24 | www.onsemi.com
FS6377
For example, a fixed divide-by-eight could be used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective
modulus of the entire feedback divider to multiples of eight. This limitation would restrict the ability of the PLL to achieve a desired inputfrequency-to-output frequency ratio without making both the reference and feedback divider values comparatively large.
A large feedback modulus means that the divided VCO frequency is relatively low, requiring a wide loop bandwidth to permit the low
frequencies. A narrow loop bandwidth tuned to high frequencies is essential to minimizing jitter; therefore, divider moduli should always
be as small as possible.
To understand the operation, refer to Figure 4. The M-counter (with a modulus always equal to M) is cascaded with the dual-modulus
prescaler. The A-counter controls the modulus of the prescaler. If the value programmed into the A-counter is A, the prescaler will be
set to divide by N+1 for A prescaler outputs. Thereafter, the prescaler divides by N until the M-counter output resets the A-counter, and
the cycle begins again. Note that N=8 and A and M are binary numbers.
Suppose that the A-counter is programmed to zero. The modulus of the prescaler will always be fixed at N; and the entire modulus of
the feedback divider becomes MxN.
Next, suppose that the A-counter is programmed to a one. This causes the prescaler to switch to a divide-by-N+1 for its first divide
cycle and then revert to a divide-by-N. In effect, the A-counter absorbs (or "swallows") one extra clock during the entire cycle of the
feedback divider. The overall modulus is now seen to be equal to MxN+1.
This example can be extended to show that the feedback divider modulus is equal to MxN+A, where A<M.
Figure 4: Feedback Divider
3.1.3. Feedback Divider Programming
For proper operation of the feedback divider, the A-counter must be programmed only for values that are less than or equal to the Mcounter. Therefore, not all divider moduli below 56 are available for use. The selection of divider values is listed in Table 2.
Above a modulus of 56, the feedback divider can be programmed to any value up to 2047.
Table 2: Feedback Divider Modulus Under 56
M-Counter:
FBKDIV[10:3]
A-Counter: FBKDIV[2:0]
000
001
010
011
100
101
110
00000001
8
9
00000010
16
17
18
00000011
24
25
26
27
00000100
32
33
34
35
00000101
40
41
42
43
44
45
00000110
48
49
50
51
52
53
54
00000111
56
57
58
59
60
61
62
111
36
Feedback Divider Modulus
Rev. 4 | Page 4 of 24 | www.onsemi.com
63
FS6377
3.2 Post Divider Muxes
As shown in Figure 2, an input mux in front of each post divider stage can select from any one of the PLL frequencies or the reference
frequency. The frequency selection is done via the I2C-bus.
The input frequency on two of the four muxes (mux C and D in Figure 2) can be changed without reprogramming by a logic-level input
on the SEL_CD pin.
3.3 Post Dividers
The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to
the variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to
where NF, NR and NP are the feedback, reference and post divider moduli respectively, and fCLK and fREF are the output and reference
oscillator frequencies. The extra integer in the denominator permits more flexibility in the programming of the loop for many applications
where frequencies must be achieved exactly.
The modulus on two of the four post dividers muxes (post dividers C and D in Figure 2) can be altered without reprogramming by a
logic level on the SEL_CD pin.
4.0 Device Operation
The FS6377 powers up with all internal registers cleared to zero, delivering the crystal frequency to all outputs. For operation to occur,
the registers must be loaded in a most significant-bit (MSB) to least-significant-bit (LSB) order. The register mapping of the FS6377 is
shown in Table 3, and I2C-bus programming information is detailed in Section 5.0.
Control of the reference, feedback and post dividers is detailed in Table 5. Selection of these dividers directly controls how fast the VCO
will run. The maximum VCO speed is noted in
Table 13.
4.1 SEL_CD Input
The SEL_CD pin provides a way to alter the operation of PLL C, muxes C and D and post dividers C and D without having to reprogram
the device. A logic-low on the SEL_CD pin selects the control bits with a "C1" or "D1" notation, per Table 3. A logic-high on the
SEL_CD pin selects the control bits with "C2" or "D2" notation, per Table 3.
Note that changing between two running frequencies using the SEL_CD pin may produce glitches in the output, especially if the postdivider(s) is/are altered.
4.2 Power-Down and Output Enable
A logic-high on the PD pin powers down only those portions of the FS6377 which have their respective power-down control bits
enabled. Note that the PD pin has an internal pull-up.
When a post divider is powered down, the associated output driver is forced low. When all PLLs and post dividers are powered down
the crystal oscillator is also powered down. The XIN pin is forced low, and the XOUT pin is pulled high.
A logic-low on the OE pin tristates all output clocks. Note that this pin has an internal pull-up.
Rev. 4 | Page 5 of 24 | www.onsemi.com
FS6377
4.3 Oscillator Overdrive
For applications where an external reference clock is provided (and the crystal oscillator is not required), the reference clock should be
connected to XOUT and XIN should be left unconnected (float).
For best results, make sure the reference clock signal is as jitter-free as possible, can drive a 40pF load with fast rise and fall times and
can swing rail-to-rail.
If the reference clock is not a rail-to-rail signal, the reference must be AC coupled to XOUT through a 0.01µF or 0.1µF capacitor. A
minimum 1V peak-to-peak signal is required to drive the internal differential oscillator buffer.
5.0 I2C-bus Control Interface
This device is a read/write slave device meeting all Philips I2C-bus specifications except a "general call." The bus has to be controlled
by a master device that generates the serial clock SCL, controls bus access and generates the START and STOP conditions while the
device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode
is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver.
2
I C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-one corresponds to a nominal voltage of
VDD, while a logic-zero corresponds to ground (VSS).
5.1 Bus Conditions
Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable
whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START
2
or STOP condition. The following bus conditions are defined by the I C-bus protocol.
5.1.1. Not Busy
Both the data (SDA) and clock (SLC) lines remain high to indicate the bus is not busy.
5.1.2. START Data Transfer
A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be
preceded by a START condition.
5.1.3. STOP Data Transfer
A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be
followed by a STOP condition.
5.1.4. Data Valid
The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START
condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per
data bit.
Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred
between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is
overwritten to the device after the first sixteen bytes will overflow into the first register, then the second, and so on, in a first-in, firstoverwritten fashion.
Rev. 4 | Page 6 of 24 | www.onsemi.com
FS6377
5.1.5. Acknowledge
When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must
generate an extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the
high period of the master acknowledge clock pulse. Setup and hold times must be taken into account.
The master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been read (clocked)
out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition.
5.2 I2C-bus Operation
All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The device
accepts the following I2C-bus commands.
5.2.1. Slave Address
After generating a START condition, the bus master broadcasts a seven-bit slave address followed by a R/W bit. The address of the
device is:
A6
A5
A4
A3
A2
A1
A0
1
0
1
1
X
0
0
where X is controlled by the logic level at the ADDR pin.
2
The variable ADDR bit allows two different devices to exist on the same bus. Note that every device on an I C-bus must have a unique
address to avoid bus conflicts. The default address sets A2 to one via the pull-up on the ADDR pin.
5.2.2. Random Register Write Procedure
Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted
after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the
slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an
acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned
by the device, and the master generates a STOP condition.
If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored.
5.2.3. Random Register Read Procedure
Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is
transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device
that a register address will follow after the slave device acknowledges its device address. The register address is then written into the
slave's address pointer.
Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write
procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a
logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit
word. The master does not acknowledge the transfer but does generate a STOP condition.
5.2.4. Sequential Register Write Procedure
Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after
each write. This procedure is more efficient than the random register write if several registers must be written.
To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the
addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address
Rev. 4 | Page 7 of 24 | www.onsemi.com
FS6377
is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write up to sixteen bytes of
data into the addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the
device between each byte of data must occur before the next data byte is sent.
Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP
condition to occur. Registers are therefore updated at different times during a sequential register write.
5.2.5. Sequential Register Read Procedure
Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by
one after each read. This procedure is more efficient than the random register read if several registers must be read.
To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure.
This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address.
The register address is then written into the slave's address pointer.
Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write
procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a
logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits all 16 bytes
of data starting with the initial addressed register. The register address pointer will overflow if the initial register address is larger than
zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition.
Rev. 4 | Page 8 of 24 | www.onsemi.com
FS6377
Figure 5: Random Register Write Procedure
Figure 6: Random Register Read Procedure
Figure 7: Sequential Register Write Procedure
Figure 8: Sequential Register Read Procedure
Rev. 4 | Page 9 of 24 | www.onsemi.com
FS6377
6.0 Programming Information
Table 3: Register Map
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Address
BIT 7
BIT 6
BIT 5
MUX_D2[1:0]
MUX_C2[1:0]
Byte 15
PDPOST_D
PDPOST_C PDPOST_B
PDPOST_A
(selected via SEL_CD = 1
(selected via SEL_CD = 1)
POST_D2[3:0]
POST_C2[3:0]
Byte 14
(selected via SEL_CD = 1)
(selected via SEL_CD = 1)
POST_D1[3:0]
POST_C1[3:0]
Byte 13
(selected via SEL_CD = 0)
(selected via SEL_CD = 0)
Byte 12
POST_B[3:0]
POST_A[3:0]
MUX_D1[1:0]
LFTC_C2
CP_C2
FBKDIV_D2[10:8] M-Counter
Byte 11
Reserved (0)
(selected via SEL_CD = 0)
(SEL_CD = 1)
(SEL_CD = 1)
(selected via SEL_CD pin = 1)
FBKDIV_C2[7:3] M-Counter
FBKDIV_C2[2:0] A-Counter
Byte 10
(selected via SEL_CD pin = 1)
(selected via SEL_CD pin = 1)
REFDIV_C2[7:0]
Byte 9
(selected via SEL_CD pin = 1)
MUX_C1[1:0]
LFTC_C1
CP_C1
FBKDIV_c1[10:8] M-Counter
Byte 8
PDPLL_C
(selected via SEL_CD = 0)
(SEL_CD = 0)
(SEL_CD = 0)
(selected via SEL_CD = 0)
FBKDIV_C1[7:3] M-Counter
FBKDIV_C1[2:0] A-Counter
Byte 7
(selected via SEL_CD = 0)
(selected via SEL_CD = 1)
REFDIV_C1[7:0]
Byte 6
(selected via SEL_CD = 0)
Byte 5
MUX_B[1:0]
PDPLL_B
LFTC_B
CP_B
FBKDIV_B[10:8] M-Counter
FBKDIV_B[7:3] M-Counter
Byte 4
REFDIV_B[7:0]
Byte 3
Byte 2
FBKDIV_B[2:0] A-Counter
MUX_A[1:0]
Byte 1
PDPLL_A
LFTC_A
CP_A
FBKDIV_A[7:3] M-Counter
Byte 0
FBKDIV_A[10:8] M-Counter
FBKDIV_A[2:0] A-Counter
REFDIV_A[7:0]
Note: All register bits are cleared to zero on power-up.
6.1 Control Bit Assignment
If any PLL control bit is altered during device operation, including those bits controlling the reference and feedback dividers, the output
frequency will slew smoothly (in a glitch-free manner) to the new frequency. The slew rate is related to the programmed loop filter time
constant.
However, any programming changes to any mux or post divider control bits will cause a glitch on an operating clock output.
Rev. 4 | Page 10 of 24 | www.onsemi.com
FS6377
6.2 Power-Down
All power-down functions are controlled by enable bits. The bits select which portions of the device to power-down when the PD input is
asserted.
Table 4: Power-Down Bits
Name
Description
PDPLL_A
(Bit 21)
PDLL_B
(Bit 45)
Power-Down PLL A
Bit = 0
Power on
Bit = 1
Power off
Power-Down PLL B
Bit = 0
Power on
Bit = 1
Power off
Power-Down PLL C
Bit = 0
Power on
Bit = 1
Power off
PDLL_C
(Bit 69)
Reserved (0)
Set these reserved bits to zero (0)
(Bit 69)
Power-Down POST Divider A
PDPOSTA
Bit = 0
Power on
(Bit 120)
Bit = 1
Power off
Power-Down POST Divider B
PDPOSTB
Bit = 0
Power on
(Bit 121)
Bit = 1
Power off
Power-Down POST Divider C
PDPOSTC
Bit = 0
Power on
(Bit 122)
Bit = 1
Power off
Power-Down POST Divider D
PDPOSTD
Bit = 0
Power on
(Bit 123)
Bit = 1
Power off
Table 5: Divider Control Bits
Name
Description
REFDIV_A[7:0]
Reference Divider A (NR)
(Bits 7-0)
REFDIV_B[7:0]
Reference Divider B (NR)
(Bits 31-24)
REFDIV_C1[7:0] Reference Divider C1 (NR)
(Bits 55-48)
selected when the SEL_CD pin = 0
REFDIV_C2[7:0] Reference Divider C2 (NR)
(Bits 79-72)
selected when the SEL_CD pin = 1
Feedback Divider A (NF)
FBKDIV_A[10:0] FBKDIV_A[2:0]
A-Counter value
(Bits 18-8)
FBKDIV_A[10:3]
M-Counter value
Feedback Divider B (NF)
FBKDIV_B[10:0] FBKDIV_B[2:0]
A-Counter value
(Bits 42-32)
FBKDIV_B[10:3]
M-Counter value
Feedback Divider C1 (NF)
selected when the SEL_CD pin = 0
FBKDIV_C1[10:0] FBKDIV_C1[2:0]
A-Counter value
(Bits 66-56)
FBKDIV_C1[10:3]
M-Counter value
Feedback Divider C2 (NF)
selected when the SEL_CD pin = 1
FBKDIV_C2[10:0] FBKDIV_C2[2:0] A-Counter value
(Bits 90-80)
FBKDIV_C2[10:3] M-Counter value
Rev. 4 | Page 11 of 24 | www.onsemi.com
FS6377
Table 6: Divider Control Bits
Name
Description
POST_A[3:0]
POST divider A (see Table 7)
(Bits 99-96)
POST_B[3:0]
POST divider B (see Table 7)
(Bits 103-100)
POST_C1[3:0]
POST divider C1 (see Table 7)
(Bits 107-104)
selected when the SEL_CD pin = 0
POST_C2[3:0]
POST divider C2 (see Table 7)
(Bits 115-112)
selected when the SEL_CD pin = 1
POST_D1[3:0]
POST divider D1 (see Table 7)
(Bits 111-108)
selected when the SEL_CD pin = 0
POST_D2[3:0]
POST divider D2 (see Table 7)
(Bits 119-116)
selected when the SEL_CD pin = 1
Table 7: Post Divider Modulus
BIT [3] BIT [2] BIT [1] BIT [0]
Divide By
0
0
0
0
1
0
0
0
1
2
3
0
0
1
0
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
8
0
1
1
0
0
1
1
1
9
1
0
0
0
10
1
0
0
1
12
1
0
1
0
15
1
0
1
1
16
1
1
0
0
18
1
1
0
1
20
1
1
1
0
25
1
1
1
1
50
Rev. 4 | Page 12 of 24 | www.onsemi.com
FS6377
Table 8: PLL Tuning Bits
Name
Description
LFTC_A
(Bit 20)
LFTC_B
(Bit 44)
LFTC_C1
(Bit 68)
LFTC_C2
(Bit 92)
CP_A
(Bit 19)
CP_B
(Bit 43)
CP_C1
(Bit 67)
CP_C2
(Bit 91)
Loop Filter Time Constant A
Bit = 0
Short time constant: 7µs
Bit = 1
Long time constant: 20µs
Loop Filter Time Constant B
selected when the SEL_CD pin = 0
Bit = 0
Short time constant: 7µs
Bit = 1
Long time constant: 20µs
Loop Filter Time Constant C1
selected when the SEL_CD pin = 1
Bit = 0
Short time constant: 7µs
Bit = 1
Long time constant: 20µs
Loop Filter Time Constant C2
Bit = 0
Short time constant: 7µs
Bit = 1
Long time constant: 20µs
Charge Pump A
Bit = 0
Current = 2µA
Bit = 1
Current = 10µA
Charge Pump B
Bit = 0
Current = 2µA
Bit = 1
Current = 10µA
Charge Pump C1
selected when the SEL_CD pin = 0
Bit = 0
Current = 2µA
Bit = 1
Current = 10µA
Charge Pump C2
selected when the SEL_CD pin = 1
Bit = 0
Current = 2µA
Bit = 1
Current = 10µA
Rev. 4 | Page 13 of 24 | www.onsemi.com
FS6377
Table 9: Mux Select Bits
Name
Description
Mux A Frequency Select
MUX_A[1:0]
(Bits 23-22)
Bit 23
Bit 22
0
0
Reference frequency
0
1
PLL A frequency
1
0
PLL B frequency
1
1
PLL C frequency
Mux B Frequency Select
MUX_B[1:0]
(Bits 47-46)
Bit 47
Bit 46
0
0
0
1
PLL A frequency
1
0
PLL B frequency
1
1
Mux C1 Frequency Select
selected when the SEL_CD pin = 0
Bit 71
Bit 70
0
MUX_C1[1:0]
0
(Bits 71-70)
1
0
Reference frequency
PLL A frequency
0
PLL B frequency
0
PLL C frequency
Reference frequency
1
PLL A frequency
0
PLL B frequency
1
1
Mux D1 Frequency Select
selected when the SEL_CD pin = 0
Bit 95
Bit 94
0
MUX_D1[1:0]
0
(Bits 95-94)
1
PLL C frequency
1
1
1
Mux C2 Frequency Select
selected when the SEL_CD pin = 1
Bit 125
Bit 124
MUX_C2[1:0] 0
(Bits 1250
124)
1
Reference frequency
0
PLL C frequency
Reference frequency
1
PLL A frequency
0
PLL B frequency
1
1
Mux D2 Frequency Select
selected when the SEL_CD pin = 1
Bit 127
Bit 126
MUX_D2[1:0] 0
(Bits 1270
126)
1
0
1
PLL C frequency
Reference frequency
1
PLL A frequency
0
PLL B frequency
1
PLL C frequency
Rev. 4 | Page 14 of 24 | www.onsemi.com
FS6377
7.0 Electrical Specifications
Table 10: Absolute Maximum Ratings
Parameter
Supply voltage, dc (VSS = ground)
Input voltage, dc
Output voltage, dc
Input clamp current, dc (VI < 0 or VI > VDD)
Output clamp current, dc (VI < 0 or VI > VDD)
Storage temperature range (non-condensing)
Ambient temperature range, under bias
Junction temperature
Re-flow solder profile
Input static discharge voltage protection (MIL-STD 883E, Method 3015.7)
Symbol
VDD
V1
VO
IIK
IOK
TS
TA
TJ
Min.
VSS – 0.5
VSS – 0.5
VSS – 0.5
-50
-50
-65
-55
Max.
7
VDD + 0.5
VDD + 0.5
50
50
150
125
150
2
Units
V
V
V
mA
mA
°C
°C
°C
Per IPC/JEDEC J-STD-020B
kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional
operation of the device of these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for
extended conditions may affect device performance, functionality and reliability.
CAUTION: ELETROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic
discharge.
Table 11: Operating Conditions
Parameter
Supply voltage
Symbol
VDD
Ambient operating temperature range
TA
Crystal resonator frequency
Crystal resonator load capacitance
Serial data transfer rate
Output driver load capacitance
fXIN
CXL
Table 12: DC Electrical Specifications
Parameter
Overall
Supply current, dynamic, with load outputs
Conditions/Descriptions
5V ± 10%
3.3V ± 10%
Commercial
Industrial
Parallel resonant, AT cut
Standard mode
Min.
4.5
3
0
-40
5
Typ.
5
3.3
Max.
5.5
3.6
70
85
27
18
10
100
15
CL
Symbol
IDD
Supply current, static
IDDL
Power-Down, Output Enable Pins (PD, OE)
High-level input voltage
VIH
Low-level input voltage
VIL
Hysteresis voltage
Vhys
High-level input current
Low-level input current (pull-up)
Serial Interface I/O (SCL, SDA)
IIH
IIL
High-level input voltage
VIH
Low-level input voltage
VIL
Hysteresis voltage
Vhys
High-level input current
Low-level input current (pull-up)
Low-level output sink current (SDA)
IIH
IIL
IOL
Conditions/Descriptions
Min.
VDD = 5.5V, fCLK = 50MHz, CL = 15pF
See Figure 10 for more information
VDD = 5.5V, device powered down
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 3.6V
VIL = 0V
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 3.6V
VIL = 0V
VOL = 0.4V, VDD = 5.5V
Rev. 4 | Page 15 of 24 | www.onsemi.com
Units
V
°C
MHz
pF
kb/s
pF
Typ.
Max.
43
mA
0.3
3.85
2.52
VSS - 0.3
VSS - 0.3
-1
-20
3.85
2.52
VSS - 0.3
VSS - 0.3
-1
-20
mA
VDD +0.3
VDD +0.3
1.65
1.08
2.20
1.44
-36
V
V
V
1
-80
VDD +0.3
VDD +0.3
1.65
1.08
2.20
1.44
-36
26
Units
µA
µA
V
V
V
1
-80
µA
µA
mA
FS6377
Table 12: DC Electrical Specifications (continued)
Mode and Frequency Select Inputs (ADDR, SEL_CD)
High-level input voltage
VIH
Low-level input voltage
VIL
High-level input current
Low-level input current (pull-up)
Crystal Oscillator Feedback (XIN)
IIH
IIL
Threshold bias voltage
VTH
IIH
High-level input current
Low-level input current
IIL
Crystal loading capacitance*
CL(xtal)
Input loading capacitance*
CL(XIN)
Crystal Oscillator Driver (XOUT)
High-level output source current
IOH
Low-level output sink current
IOL
Clock Outputs (CLK_A, CLK_B, CLK_C, CLK_D)
High-level output source current
IOH
Low-level output sink current
IOL
ZOH
Output impedance
ZOL
Tristate output current
IZ
Short circuit source current*
ISCH
Short circuit sink current*
ISCL
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 3.6V
2.4
2.0
VSS - 0.3
VSS - 0.3
-1
-20
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 5.5V, oscillator powered down
VDD = 5.5V
As seen by an external crystal
connected to XIN and XOUT
As seen by an external clock driver on
XOUT; XIN unconnected
VDD = V(XIN) = 5.5V, VO = 0V
VDD = 5.5V, V(XIN) = 0V, VO = 5.5V
-36
2.9
1.7
54
5
-25
10
-10
VO = 2.4V
VO = 0.4V
VO = 0.5VDD; output driving high
VO = 0.5VDD; output driving low
-54
V
V
µA
µA
V
15
-75
µA
mA
µA
18
pF
36
pF
21
-21
30
-30
-125
23
29
27
-10
VDD = 5.5V, VO = 0V; shorted for 30s,
max.
VDD = VO = 5.5V; shorted for 30s, max.
VDD +0.3
VDD +0.3
0.8
0.8
1
-80
mA
mA
mA
mA
Ω
10
µA
-150
mA
123
mA
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent
nominal characterization data and are not currently production tested on any specific limits. Min. and max. characterization data are ± 3σ from typical. Negative currents
indicate current flows out of the device.
Low Drive Current (mA)
Voltage
Min.
Typ.
(V)
0
0
0
0.2
9
11
0.5
22
25
0.7
29
34
1
39
46
1.2
44
52
1.5
51
61
1.7
55
66
2
60
73
2.2
62
77
2.5
65
81
2.7
65
83
3
66
85
3.5
67
87
4
68
88
4.5
69
89
5
91
5.5
Max.
0
12
29
40
55
64
76
83
92
97
104
108
112
117
119
120
121
123
High Drive Current (mA)
Voltage
Min.
Typ.
Max.
(V)
0
-87
-112
-150
0.5
-85
-110
-147
1
-83
-108
-144
1.5
-80
-104
-139
2
-74
-97
-131
2.5
-65
-88
-121
2.7
-61
-84
-116
3
-53
-77
-108
3.2
-48
-71
-102
3.5
-39
-62
-92
3.7
-32
-55
-85
4
-21
-44
-74
4.2
-13
-36
-65
4.5
0
-24
-52
4.7
-15
-43
5
0
-28
5.2
-11
5.5
0
The data in this table represents nominal characterization data only.
Figure 9: CLK_A, CLK_B, CLK_C, CLK_D Clock Outputs
Rev. 4 | Page 16 of 24 | www.onsemi.com
FS6377
Figure 10: Dynamic Current vs. Output Frequency
Rev. 4 | Page 17 of 24 | www.onsemi.com
FS6377
Table 13: AC Timing Specifications
Parameter
Symbol
Conditions/Descriptions
Clock
(MHz)
Min.
Typ.
Max.
Units
Overall
Output frequency*
fO
VCO frequency*
fVCO
VCO gain*
Loop filter time constant*
AVCO
Rise time*
tr
Fall time*
tr
Tristate enable delay*
Tristate disable delay*
Clock stabilization time*
tPZL, tPZH
tPZL, tPZH
tSTB
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 3.6V
0.8
0.8
40
40
Jitter, period (peak-peak)*
tj(ΔP)
tj(ΔP)
1
1
Output active from power-up, via PD pin
After last register is written
On rising edges 500µs apart at 2.5V relative to an
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, all other PLLs active (B = 60MHz,
C = 40MHz, D = 14.318MHz)
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, no other PLLs active
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, all other PLLs active (B = 60MHz,
C = 40MHz, D = 14.318MHz)
Clock Outputs (PLL B clock via CLK_B pin) Approximate
Duty cycle*
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
tj(LT)
On rising edges 500µs apart at 2.5V relative to an
Jitter, long term (σy(τ))*
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, no other PLLs active
Jitter, period (peak-peak)*
400
7
20
1.9
1.6
1.8
1.5
LFTC bit = 0
LFTC bit = 1
VO = 0.5V to 4.5V; CL = 15pF
VO = 0.3V to 3.0V; CL = 15pF
VO = 4.5V to 0.5V; CL = 15pF
VO = 3.0V to 0.3V; CL = 15pF
Divider Modulus
Feedback divider
NF
See Table 2
Reference divider
NR
Post divider
NP
See Table 8
Clock Outputs (PLL A clock via CLK_A pin) Approximate
Duty cycle*
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
tj(LT)
On rising edges 500µs apart at 2.5V relative to an
Jitter, long term (σy(τ))*
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, no other PLLs active
On rising edges 500µs apart at 2.5V relative to an
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, all other PLLs active (A = 50MHz,
C = 40MHz, D = 14.318MHz)
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, no other PLLs active
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, all other PLLs active (A = 50MHz,
C = 40MHz, D = 14.318MHz)
Rev. 4 | Page 18 of 24 | www.onsemi.com
150
100
230
170
µs
ns
ns
8
8
1
8
1
1
2047
255
50
45
55
100
45
50
165
100
110
50
390
MHz
MHz/V
100
100
MHz
ns
ns
µs
ms
%
ps
ps
100
45
55
100
45
60
75
100
120
60
400
%
ps
ps
FS6377
Table 13: AC Timing Specifications continued
Clock Outputs (PLL_C clock via CLK_C pin) Approximate
Duty cycle*
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
tj(LT)
On rising edges 500µs apart at 2.5V relative to an
Jitter, long term (σy(τ))*
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, no other PLLs active
Jitter, period (peak-peak)*
tj(ΔP)
On rising edges 500µs apart at 2.5V relative to an
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, all other PLLs active (A = 50MHz,
B = 60MHz, D = 14.318MHz)
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, no other PLLs active
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, all other PLLs active (A = 50MHz,
B = 60MHz, D = 14.318MHz)
Clock Outputs (Crystal Oscillator via CLK_D pin) Approximate
Duty cycle*
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
tj(LT)
On rising edges 500µs apart at 2.5V relative to an
Jitter, long term (σy(τ))*
ideal clock, CL = 15pF, fXIN = 14.318MHz, no other
PLLs active
100
45
55
100
45
40
105
100
120
40
440
%
ps
ps
14.318
45
55
14.318
20
14.318
40
14.318
90
14.318
450
%
ps
Jitter, period (peak-peak)*
tj(ΔP)
From rising edges to the next at 2.5V, CL = 15pF,
fXIN = 14.318MHz, all other PLLs active (A = 50MHz,
B = 60MHz, C = 40MHz)
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, no other PLLs active
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, all other PLLs active
(A = 50MHz, B = 60MHz, C = 40MHz)
ps
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent
nominal characterization data and are not currently production tested to any specific limits. Min. and max. characterization data are ±3σ from typical.
Table 14: Serial Interface Timing Specifications
Parameter
Symbol
Clock frequency
Bus free time between STOP and
START
Set-up time, START (repeated)
Hold time, START
Set-up time, data input
Hold time, data input
fSCL
tsu:STA
tnd:STA
tsu:DAT
thd:DAT
Output data valid from clock
tAA
Rise time, data and clock
Fall time, data and clock
High time, clock
Low time, clock
Set-up time, STOP
tR
tF
tHI
tLO
Tsu:STO
Conditions/Description
SCL
tBUF
SDA
SDA
Minimum delay to bridge undefined region of
the falling edge of SCL to avoid unintended
START or STOP
SDA, SCL
SDA, SCL
SCL
SCL
Standard Mode
Min.
Max.
0
100
4.7
4.7
4.0
250
0
4.0
4.7
4.0
Units
kHz
µs
µs
µs
ns
µs
3.5
µs
1000
300
ns
ns
µs
µs
µs
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*)
represent nominal characterization data and are not currently production tested to any specific limits. Min. and max. characterization data are ±3σ from typical.
Rev. 4 | Page 19 of 24 | www.onsemi.com
FS6377
Figure 11: Bus Timing Data
Figure 12: Data Transfer Sequence
8.0 Package Information – For Both ‘Green’ and ‘No-Green’
Table 15: 16-pin SOIC (0.150") Package Dimensions
Dimensions
Inches
Millimeters
Min.
Max.
Min.
Max.
A
0.061
0.068
1.55
1.73
A1 0.004
0.0098
0.102 0.249
A2 0.055
0.061
1.40
1.55
B
0.013
0.019
0.33
0.49
C
0.0075 0.0098
0.191 0.249
D
0.386
0.393
9.80
9.98
E
0.150
0.157
3.81
3.99
e
0.050 BSC
1.27 BSC
H
0.230
0.244
5.84
6.20
h
0.010
0.016
0.25
0.41
L
0.016
0.035
0.41
0.89
0°
8°
0°
8°
Θ
Rev. 4 | Page 20 of 24 | www.onsemi.com
FS6377
Table 16: 16-pin SOIC (0.150") Package Characteristics
Parameter
Symbol
Conditions/Description
Thermal impedance, junction to freeAir flow = 0m/s
ΘJA
air16-pin 0.150” SOIC
Corner lead
Lead inductance, self
L11
Center lead
Lead inductance, mutual
L12
Any lead to any adjacent lead
Lead capacitance, bulk
C11
Any lead to VSS
Typ.
Units
110
°C/W
4.0
3.0
0.4
0.5
nH
pF
nH
9.0 Ordering Information
Part Number
FS6377-01G-XTD
FS6377-01G-XTP
FS6377-01iG-XTD
FS6377-01iG-XTP
Package
16-pin (0.150”) SOIC
(small outline package)
‘Green’ or lead-free packaging
16-pin (0.150”) SOIC
(small outline package)
‘Green’ or lead-free packaging
16-pin (0.150”) SOIC
(small outline package)
‘Green’ or lead-free packaging
16-pin (0.150”) SOIC
(small outline package)
‘Green’ or lead-free packaging
Shipping Configuration
Temperature Range
Tube/Tray
0°C to 70°C (commercial)
Tape & Reel
0°C to 70°C (commercial)
Tube/Tray
-40°C to 85°C (industrial)
Tape & Reel
-40°C to 85°C (industrial)
10.0 Demonstration Software
Windows XP- (and earlier) based software is available from ON Semiconductor that illustrates the capabilities of the FS6377 and aids in
application development.
Contact your local sales representative for more information.
10.1 Software Requirements
• PC running MS Windows 95/98, 98 SE, ME, NT4, 2000, XP Home Edition, or XP Professional Edition
• 1.8MB available space on hard drive C
• Internet access to operate program found at www.amis.com/products/clocks/FS6377.html
10.2 Demo Program Operation
Launch the demo program from the website. Note that the parallel port cannot be accessed if your machine is not connected to the
demo board. A warning message will appear as shown in Figure 13.
Clicking “Ignore” starts the program for calculation only.
The FS6377 demo hardware is available on a limited basis for demonstration by an ON SEMICONDUCTOR field applications engineer,
but is no longer available for purchase.
The opening screen is shown in Figure 14.
Rev. 4 | Page 21 of 24 | www.onsemi.com
FS6377
Figure 13: Warning Message- Click”Ignore”
Figure 14: Opening Screen
10.2.1. Example Programming
Type a value for the crystal resonator frequency in MHz in the reference crystal box. This frequency provides the basis for all of the PLL
calculations that follow.
Next, click on the PLL A box. A pop-up screen similar to Figure 15 should appear. Type in a desired output clock frequency in MHz, set
the operating voltage (3.3V or 5V) and the desired maximum output frequency error. Pressing Calculate Solutions generates several
possible divider and VCO-speed combinations.
Rev. 4 | Page 22 of 24 | www.onsemi.com
FS6377
Figure 15: PLL Screen
For a 100MHz output, the VCO should ideally operate at a higher frequency, and the reference and feedback dividers should be as
small as possible. In this example, highlight Solution #7. Notice the VCO operates at 200MHz with a post divider of two to obtain an
optimal 50 percent duty cycle.
Now choose which mux and post divider to use (that is, choose an output pin for the 100MHz output). Selecting A places the PostDiv
value in Solution #7 into post divider A and switches mux A to take the output of PLL A.
The PLL screen should disappear, and now the value in the PLL A box is the new VCO frequency chosen in Solution #7. Also note that
mux A has been switched to PLL A and the post divider A has the chosen 100MHz output displayed.
Repeat the steps for PLL B.
PLL C supports two different output frequencies depending on the setting of the SEL_CD pin. Both mux C and mux D are also affected
by the logic level on the SEL_CD pin, as are the post dividers C and D.
Figure 16: Post Divider Menu
Rev. 4 | Page 23 of 24 | www.onsemi.com
FS6377
Click on PLL C1 to open the PLL screen. Set a desired frequency, however, now choose the post divider B as the output divider. Notice
the post divider box has split in two (as shown in Figure 16). The post divider B box now shows that the divider is dependent on the
setting of the SEL_CD pin for as long as mux B is the PLL C output.
Clicking on post divider A reveals a pull-down menu provided to permit adjustment of the post divider value independently of the PLL
screen. A typical menu is shown in Figure 16. The range of possible post divider values is also given in Table 7.
The register settings are shown to the left in the screen shown in Figure 14. Clicking on a register location displays a screen shown in
Figure 17. Individual bits can be poked, or the entire register value can be changed.
Figure 17: Register Screen
11.0 Revision History
Revision
1
2
3
4
Date
2004
2004
October 2007
May 2008
Modification
Initial doc
Update content to new AMIS template
Update to ON Semiconductor template
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any
products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical”
parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the
rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or
use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action
Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800-282-9855
Toll Free USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81-3-5773-3850
Rev. 4 | Page 24 of 24 | www.onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative