FAN5026 Dual DDR/Dual-Output PWM Controller Features General Description ■ Highly flexible dual synchronous switching PWM The FAN5026 PWM controller provides high efficiency and regulation for two output voltages adjustable in the range from 0.9V to 5.5V that are required to power I/O, chip-sets, and memory banks in high-performance computers, set top boxes, and VGA cards. Synchronous rectification contributes to high efficiency over a wide range of loads. Efficiency is even further enhanced by using MOSFET’s RDS(ON) as a current sense component. ■ ■ ■ ■ ■ ■ ■ ■ controller includes modes for: – DDR mode with in-phase operation for reduced channel interference – 90° phase shifted two-stage DDR Mode for reduced input ripple – Dual Independent regulators 180° phase shifted Complete DDR Memory power solution – VTT Tracks VDDQ/2 – VDDQ/2 Buffered Reference Output Lossless current sensing on low-side MOSFET or Precision current sensing using sense resistor VCC Under-voltage Lockout Wide power input range: 3 to 16V Excellent dynamic response with Voltage Feed-Forward and Average Current Mode control Power-Good Signal Supports DDR-II and HSTL TSSOP28 package Feed-forward ramp modulation, average current mode control scheme, and internal feedback compensation provide fast response to load transients. Out-of-phase operation with 180° phase shift reduces input current ripple. The controller can be transformed into a complete DDR memory power supply solution by activating a designated pin. In DDR mode of operation one of the channels tracks the output voltage of another channel and provides output current sink and source capability — features essential for proper powering of DDR chips. The buffered reference voltage required by this type of memory is also provided. The FAN5026 monitors these outputs and generates separate PGx (power good) signals when the soft-start is completed and the output is within ±10% of its set point. A built-in over-voltage protection prevents the output voltage from going above 120% of the set point. Normal operation is automatically restored when the over-voltage conditions go away. Under-voltage protection latches the chip off when either output drops below 75% of its set value after the soft-start sequence for this output is completed. An adjustable over-current function monitors the output current by sensing the voltage drop across the lower MOSFET. If precision current-sensing is required, an external current-sense resistor may optionally be used. Applications ■ DDR VDDQ and VTT voltage generation ■ Desktop computer ■ Graphics cards Ordering Information Part Number Temperature Range Package Packing FAN5026MTC -40°C to 85°C TSSOP-28 Rails FAN5026MTCX -40°C to 85°C TSSOP-28 Tape and Reel ©2005 Fairchild Semiconductor Corporation FAN5026 Rev. 1.0.5 1 www.fairchildsemi.com FAN5026 Dual DDR/Dual-Output PWM Controller October 2005 FAN5026 Dual DDR/Dual-Output PWM Controller Block Diagrams +5 VCC VIN (BATTERY) = 3 to 16V FAN5026 Q1 ILIM1 L OUT1 VOUT1 = 2.5V PWM 1 COUT1 Q2 DDR VIN (BATTERY) Q3 ILIM2/ REF2 L OUT2 VOUT2 = 1.8V PWM 2 COUT2 Q4 Figure 1. Dual Output Regulator +5 VCC VIN (BATTERY) = 3 to 16V FAN5026 Q1 ILIM1 L OUT1 PWM 1 Q2 VDDQ = 2.5V COUT1 R +5 DDR R Q3 L OUT2 PG2/REF VTT = VDDQ/2 1.25V Q4 PWM 2 COUT2 ILIM2/REF2 Figure 2. Typical Application 2 FAN5026 Rev. 1.0.5 www.fairchildsemi.com AGND LDRV1 PGND1 SW1 HDRV1 BOOT1 ISNS1 EN1 GND VSEN1 ILIM1 SS1 DDR VIN 1 2 28 27 3 4 26 25 5 6 24 23 7 8 FAN5026 22 21 9 10 20 19 11 12 18 17 13 14 16 15 VCC LDRV2 PGND2 SW2 HDRV2 BOOT2 ISNS2 EN2 GND VSEN2 ILIM2/REF2 SS2 PG2/REF2OUT PG1 TSSOP-28 θJA = 50°C/W; θJC = 16°C/W. See note below. Note: θJA and θJC values are determined using a 4 layer, 1" square PCB with 1 ounce copper. Pin Definitions Pin Number Pin Name 1 AGND Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. 2 27 LDRV1 LDRV2 Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET. 3 26 PGND1 PGND2 Power Ground. The return for the low-side MOSFET driver. Connect to source of low-side MOSFET. 4 25 SW1 SW2 5 24 HDRV1 High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET. 6 23 BOOT1 BOOT2 BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 3. 7 22 ISNS1 ISNS2 Current Sense Input. Monitors the voltage drop across the lower MOSFET or external sense resistor for current feedback. 8 21 EN1 EN2 Enable. Enables operation when pulled to logic high. Toggling EN will also reset the regulator after a latched fault condition. These are CMOS inputs whose state is indeterminate if left open. 9 20 GND Ground. These pins should be tied to AGND for proper operation. 10 19 VSEN1 VSEN2 11 ILIM1 12 17 SS1 SS2 Pin Function Description Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and low-side MOSFET drain. Output Voltage Sense. The feedback from the outputs. Used for regulation as well as PG, under-voltage and over-voltage protection and monitoring. Current Limit 1. A resistor from this pin to GND sets the current limit. Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization. During initialization, this pin is charged with a 5µA current source. 3 FAN5026 Rev. 1.0.5 www.fairchildsemi.com FAN5026 Dual DDR/Dual-Output PWM Controller Pin Configurations Pin Number Pin Name 13 DDR DDR Mode Control. High = DDR mode. Low = 2 separate regulators operating 180° out of phase. 14 VIN Input Voltage. Normally connected to battery, provides voltage feed-forward to set the amplitude of the internal oscillator ramp. When using the IC for 2-step conversion from 5V input, connect through 100K to ground, which will set the appropriate ramp gain and synchronize the channels 90° out of phase. 15 PG1 Power Good Flag. An open-drain output that will pull LOW when VSEN is outside of a ±10% range of the 0.9V reference. 16 PG2 / REF2OUT Power Good 2. When not in DDR Mode: Open-drain output that pulls LOW when the VOUT is out of regulation or in a fault condition Reference Out 2. When in DDR Mode, provides a buffered output of REF2. Typically used as the VDDQ/2 reference. 18 ILIM2 / REF2 28 VCC Pin Function Description Current Limit 2. When not in DDR Mode, A resistor from this pin to GND sets the current limit. Reference for reg #2 when in DDR Mode. Typically set to VOUT1/2. VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V (UVLO falling). Absolute Maximum Ratings Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Parameter Max. Units VCC Supply Voltage Min. Typ. 6.5 V VIN 18 V BOOT, SW, ISNS, HDRV 24 V BOOT to SW 6.5 V All Other Pins –0.3 VCC+0.3 V Junction Temperature (TJ) –40 150 °C Storage Temperature –65 150 °C 300 °C Lead Soldering Temperature, 10 seconds Recommended Operating Conditions Parameter Conditions Supply Voltage VCC Min. Typ. Max. Units 4.75 5 5.25 V 16 V 85 °C Supply Voltage VIN Ambient Temperature (TA) note 1 –40 4 FAN5026 Rev. 1.0.5 www.fairchildsemi.com FAN5026 Dual DDR/Dual-Output PWM Controller Pin Definitions (Continued) Recommended operating conditions, unless otherwise noted. Parameter Conditions Min. Typ. Max. Units 2.2 3.0 mA 30 µA 30 µA –30 µA 1 µA Power Supplies VCC Current LDRV, HDRV Open, VSEN forced above regulation point Shut-down (EN=0) VIN Current – Sinking VIN = 15V VIN Current – Sourcing VIN = 0V 10 –15 VIN Current – Shut-down UVLO Threshold Rising VCC 4.3 4.55 4.75 V Falling 4.1 4.25 4.45 V UVLO Hysteresis 300 mV Oscillator Frequency 255 300 345 KHz Ramp Amplitude, pk–pk VIN = 16V 2 V Ramp Amplitude, pk–pk VIN = 5V 1.25 V 0.5 V Ramp / VIN Gain VIN ≥ 3V 125 mV/V Ramp / VIN Gain 1V < VIN < 3V 250 mV/V Ramp Offset Reference and Soft Start Internal Reference Voltage Soft Start Current (ISS) 0.891 at start-up Soft Start Complete Threshold 0.9 0.909 V –5 µA 1.5 V PWM Converters Load Regulation IOUTX from 0 to 5A, VIN from 5 to 15V -2 VSEN Bias Current 50 80 +2 % 120 nA Under-Voltage Shutdown as % of set point. 2µS noise filter 70 75 80 % Over-Voltage Threshold as % of set point. 2µS noise filter 115 120 125 % ISNS Over-Current Threshold RILIM= 68.5KΩ see Figure 10. 112 140 168 µA Minimum Duty Cycle 10 % Output Drivers HDRV Output Resistance LDRV Output Resistance Sourcing 12 15 Ω Sinking 2.4 4 Ω Sourcing 12 15 Ω Sinking 1.2 2 Ω PG (Power Good Output) and Control pins as % of set point, 2µS noise filter –86 –94 % Upper Threshold as % of set point, 2µS noise filter 108 116 % PG Output Low IPG = 4mA 0.5 V Leakage Current VPULLUP = 5V PG2/REF2OUT Voltage DDR = 1, 0 mA < IREF2OUT < 10mA Lower Threshold 99 1 µA 1.01 % VREF2 DDR, EN Inputs Input High 2 Input Low 5 FAN5026 Rev. 1.0.5 V 0.8 V www.fairchildsemi.com FAN5026 Dual DDR/Dual-Output PWM Controller Electrical Specifications VDD CBOOT BOOT EN VIN POR/UVLO Q1 DDR HDRV ADAPTIVE GATE CONTROL LOGIC DDR VIN Q2 VDD RAMP OSC VOUT SW OVP CLK L OUT COUT LDRV PGND Q PWM S/H S R PWM RAMP ILIM det. VSEN ISNS RSENSE CURRENT PROCESSING EA IOUT ? ILIM R ILIM SS PGOOD VREF Reference and Soft Start DDR REF2 Figure 3. IC Block Diagram 6 FAN5026 Rev. 1.0.5 www.fairchildsemi.com FAN5026 Dual DDR/Dual-Output PWM Controller 5V FAN5026 Dual DDR/Dual-Output PWM Controller Typical Applications VIN = 3 to 16V VCC +5 VIN 14 28 6 C4 ILIM1 EN1 SS1 +5 C2 11 8 4 PWM 1 +5 3 PG1 7 15 10 DDR EN2 SS2 C3 23 21 17 C6 R7 R5 PGND2 ISNS1 VSEN1 BOOT2 R6 D2 24 +5 C7 HDRV2 SW2 L2 VTT = VDDQ/2 Q2B 16 VDDQ = 2.5V LDRV1 Q2A 1.25V@10mA PWM 2 27 AGND L1 SW1 R1 13 25 PG2/REF C5 HDRV1 Q1B 2 12 R4 +5 D1 Q1A 5 R3 C9 C1 BOOT1 9 26 20 22 1 19 18 R2 C8 LDRV2 PGND2 R8 ISNS2 VSEN2 ILIM2/REF2 Figure 4. DDR Regulator Application Table 1. DDR Regulator BOM Description Qty Ref. Vendor Part Number Capacitor 68µF, Tantalum, 25V, ESR 150mΩ 1 C1 AVX Capacitor 10nF, Ceramic 2 C2, C3 Any Capacitor 68µF, Tantalum, 6V, ESR 1.8Ω 1 C4 AVX Capacitor 150nF, Ceramic 2 C5, C7 Any Capacitor 180µF, Specialty Polymer 4V, ESR 15mΩ 2 C6A, C6B Panasonic EEFUE0G181R Capacitor 1000µF, Specialty Polymer 4V, ESR 10mΩ 1 C8 Kemet T510E108(1)004AS4115 Capacitor 0.1µF, Ceramic 1 C9 Any 1.82KΩ, 1% Resistor 3 R1, R2, R6 Any 56.2KΩ, 1% Resistor 1 R3 Any TPSV686*025#0150 TAJB686*006 10KΩ, 5% Resistor 1 R4 Any 3.24KΩ, 1% Resistor 1 R5 Any 1.5KΩ, 1% Resistor 2 R7, R8 Any Schottky Diode 30V 2 D1, D2 Fairchild BAT54 Inductor 6.4µH, 6A, 8.64mΩ 1 L1 Panasonic ETQ-P6F6R4HFA Inductor 0.8µH, 6A, 2.24mΩ 1 L2 Panasonic ETQ-P6F0R8LFA Dual MOSFET with Schottky 2 Q1, Q2 Fairchild FDS6986S (note 1) DDR Controller 1 U1 Fairchild FAN5026 Notes: 1. Suitable for applications of 4A continuous, 6A peak for VDDQ. If continuous operation above 6A is required use single SO-8 packages for Q1A (FDS6612A) and Q1B (FDS6690S) respectively. Using FDS6690S, change R7 to 1200 Ω. Refer to Power MOSFET Selection, page 14 for more information. 2. C6 = 2 X 180µF in parallel. 7 FAN5026 Rev. 1.0.5 www.fairchildsemi.com FAN5026 Dual DDR/Dual-Output PWM Controller Typical Applications (Continued) VIN = 3 to 16V VCC +5 VIN 14 28 C9 C1 6 D1 BOOT1 C4 +5 Q1A 5 R2 ILIM1 EN1 SS1 C2 11 4 HDRV1 L1 SW1 2.5V@4A C6 8 Q1B PWM 1 12 2 +5 3 R3 7 PG1 C5 15 10 21 23 LDRV1 R4 R6 PGND2 ISNS1 R5 VSEN1 VIN EN2 BOOT2 D2 Q2A PG2 SS2 16 24 17 25 C3 AGND DDR GND GND HDRV2 +5 C7 SW2 L2 1.8V@2A Q2B 1 PWM 2 13 27 20 26 9 22 19 18 C8 LDRV2 R7 R8 PGND2 ISNS2 R9 VSEN2 R1 ILIM2 Figure 5. Dual Regulator Application Table 2. Dual Regulator BOM Description Qty Ref. Vendor Capacitor 68µF, Tantalum, 25V, ESR 95mΩ 1 C1 AVX Capacitor 10nF, Ceramic 2 C2, C3 Any Capacitor 68µF, Tantalum, 6V, ESR 1.8Ω 1 C4 AVX Part Number TPSV686*025#095 TAJB686*006 Capacitor 150nF, Ceramic 2 C5, C7 Any Capacitor 330µF, Poscap, 4V, ESR 40mΩ 2 C6, C8 Sanyo Capacitor 0.1µF, Ceramic 2 C9 Any 56.2KΩ, 1% Resistor 1 R1, R2 Any 10KΩ, 5% Resistor 1 R3 Any 3.24KΩ, 1% Resistor 1 R4 Any 1.82KΩ, 1% Resistor 3 R5, R8, R9 Any 1.5KΩ, 1% Resistor 2 R6, R7 Any Schottky Diode 30V 2 D1, D2 Fairchild BAT54 Inductor 6.4µH, 6A, 8.64mΩ 2 L1, L2 Panasonic ETQ-P6F6R4HFA 4TPB330ML Dual MOSFET with Schottky 1 Q1 Fairchild FDS6986S (note 1) DDR Controller 1 U1 Fairchild FAN5026 Note: 1. If currents above 4A continuous required, use single SO-8 packages for Q1A/Q2A (FDS6612A) and Q1B/Q2B (FDS6690S) respectively. Using FDS6690S, change R6/R7 as required. Refer to Power MOSFET Selection, page 14 for more information. 8 FAN5026 Rev. 1.0.5 www.fairchildsemi.com CLK Overview VDDQ The FAN5026 is a multi-mode, dual channel PWM controller intended for graphic chipset, SDRAM, DDR DRAM or other low output voltage power applications in PC’s, VGA Cards and set top boxes. The IC integrates a control circuitry for two synchronous buck converters. The output voltage of each controller can be set in the range of 0.9V to 5.5V by an external resistor divider. VTT Figure 6. Noise-Susceptible 180° Phasing for DDR1 In-phase operation is optimal to reduce inter-converter interference when VIN is higher than 5V, (when VIN is from a battery), as can be seen in Figure 7. Since the duty cycle of PWM1 (generating VDDQ) is short, its switching point occurs far away from the decision point for the VTT regulator, whose duty cycle is nominally 50%. The two synchronous buck converters can operate from either an unregulated DC source (such as a notebook battery) with voltage ranging from 5.0V to 16V, or from a regulated system rail of 3.3V to 5V. In either mode of operation the IC is biased from a +5V source. The PWM modulators use an average current mode control with input voltage feed-forward for simplified feedback loop compensation and improved line regulation. Both PWM controllers have integrated feedback loop compensation that dramatically reduces the number of external components. CLK VDDQ The FAN5026 can be configured to operate as a complete DDR solution. When the DDR pin is set high, the second channel can provide the capability to track the output voltage of the first channel. The PWM2 converter is prevented from going into hysteretic mode if the DDR pin is set high. In DDR mode, a buffered reference voltage (buffered voltage of the REF2 pin), required by DDR memory chips, is provided by the PG2 pin. VTT Figure 7. Optimal In-Phase Operation for DDR1 When VIN ≈ 5V, 180° phase shifted operation can be rejected for the same reasons demonstrated Figure 6. In-phase operation with VIN ≈ 5V is even worse, since the switch point of either converter occurs near the switch point of the other converter as seen in Figure 8. In this case, as VIN is a little higher than 5V it will tend to cause early termination of the VTT pulse width. Conversely, VTT’s switch point can cause early termination of the VDDQ pulse width when VIN is slightly lower than 5V. Converter Modes and Synchronization Table 3. Converter Modes and Synchronization Mode VIN VIN Pin DDR Pin PWM 2 w.r.t. PWM1 DDR1 Battery VIN HIGH IN PHASE DDR2 +5V R to GND HIGH + 90° DUAL ANY VIN LOW + 180° CLK VDDQ When used as a dual converter (as in Figure 5), out-ofphase operation with 180 degree phase shift reduces input current ripple. VTT For the “2-step” conversion (where the VTT is converted from VDDQ as in Figure 4) used in DDR mode, the duty cycle of the second converter is nominally 50% and the optimal phasing depends on VIN. The objective is to keep noise generated from the switching transition in one converter from influencing the “decision” to switch in the other converter. Figure 8. Noise-Susceptible In-Phase Operation for DDR2 These problems are nicely solved by delaying the 2nd converter's clock by 90° as shown in Figure 9. In this way, all switching transitions in one converter take place far away from the decision points of the other converter. When VIN is from the battery, it’s typically higher than 7.5V. As shown in Figure 6, 180° operation is undesirable since the turn-on of the VDDQ converter occurs very near the decision point of the VTT converter. 9 FAN5026 Rev. 1.0.5 www.fairchildsemi.com FAN5026 Dual DDR/Dual-Output PWM Controller Circuit Description The following discussion refers to Figure 10. The current through RSENSE resistor (ISNS) is sampled shortly after Q2 is turned on. That current is held, and summed with the output of the error amplifier. This effectively creates a current mode control loop. The resistor connected to ISNSx pin (RSENSE) sets the gain in the current feedback loop. For stable operation, the voltage induced by the current feedback at the PWM comparator input should be set to 30% of the ramp amplitude at maximum load current and line voltage. The following expression estimates the recommended value of RSENSE as a function of the maximum load current (ILOAD(MAX)) and the value of the MOSFET’s RDS(ON): VDDQ VTT Figure 9. Optimal 90° Phasing for DDR2 Initialization and Soft Start Assuming EN is high, FAN5026 is initialized when VCC exceeds the rising UVLO threshold. Should VCC drop below the UVLO threshold, an internal Power-On Reset function disables the chip. I LOAD ( MAX ) • R DS ( ON ) • 4.1K R SENSE = ---------------------------------------------------------------------------- – 100 30% • 0.125 • V IN ( MAX ) The voltage at the positive input of the error amplifier is limited by the voltage at the SS pin which is charged with a 5µA current source. Once CSS has charged to VREF (0.9V) the output voltage will be in regulation. The time it takes SS to reach 0.9V is: RSENSE must, however, be kept higher than: 0.9 × C SS T 0.9 = ------------------------5 I LOAD ( MAX ) • R DS ( ON ) - – 100 R SENSE ( MIN ) = ---------------------------------------------------------150µA (1) (2a) (2b) where T0.9 is in seconds if CSS is in µF. When SS reaches 1.5V, the Power Good outputs are enabled and hysteretic mode is allowed. The converter is forced into PWM mode during soft start. 0.17pF 1.5M S/H 17pF 300K 4.14K VSEN V to I in + I1A = ISNS TO PWM COMP ISNS RSENSE I1B = ISNS 9 LDRV in – PGND CSS SS Reference and Soft Start ILIM det. 0.9V 2.5V I2 = ILIM RILIM 4 * ILIM 3 ILIM mirror Figure 10. Current Limit / Summing Circuits 10 FAN5026 Rev. 1.0.5 www.fairchildsemi.com FAN5026 Dual DDR/Dual-Output PWM Controller Current Processing Section CLK Gate Driver Section A ratio of ISNS is also compared to the current established when a 0.9 V internal reference drives the ILIM pin. The threshold is determined at the point when the ISNS ILIM × 4 . Since --------------- > ---------------------9 3 The adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals providing necessary amplification, level shifting and shoot-through protection. Also, it has functions that help optimize the IC performance over a wide range of operating conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1 volt. Similarly, the upper MOSFET is not turned on until the gateto-source voltage of the lower MOSFET has decreased to less than approximately 1 volt. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through. I LOAD × R DS ( ON ) ISNS = -------------------------------------------100 + R SENSE therefore, 0.9V 4 9 × ( 100 + R SENSE ) I LIMIT = -------------- × --- × ---------------------------------------------------R DS ( ON ) R ILIM 3 or 10.8 ( 100 + R SENSE ) R ILIM = --------------- × ------------------------------------------R DS ( ON ) I LIMIT (3a) (3b) Since the tolerance on the current limit is largely dependent on the ratio of the external resistors, it is fairly accurate if the voltage drop on the Switching Node side of RSENSE is an accurate representation of the load current. When using the MOSFET as the sensing element, the variation of RDS(ON) causes proportional variation in the ISNS. This value not only varies from device to device, but also has a typical junction temperature coefficient of about 0.4%/°C (consult the MOSFET datasheet for actual values), so the actual current limit set point will decrease proportional to increasing MOSFET die temperature. A factor of 1.6 in the current limit setpoint should compensate for all MOSFET RDS(ON) variations, assuming the MOSFET’s heat sinking will keep its operating die temperature below 125°C. There must be a low-resistance, low-inductance path between the driver pin and the MOSFET gate for the adaptive dead-time circuit to work properly. Any delay along that path will subtract from the delay generated by the adaptive dead-time circuit and shoot-through may occur. Frequency Loop Compensation Due to the implemented current mode control, the modulator has a single pole response with -1 slope at frequency determined by load 1 F PO = -----------------------2πR O C O where RO is load resistance and CO is load capacitance. For this type of modulator, Type 2 compensation circuit is usually sufficient. To reduce the number of external components and simplify the design task, the PWM controller has an internally compensated error amplifier. Figure 12 shows a Type 2 amplifier and its response along with the responses of a current mode modulator and of the converter. The Type 2 amplifier, in addition to the pole at the origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole. Q2 LDRV ISNS (5) RSENSE R1 PGND Figure 11. Improving Current Sensing Accuracy 1 F Z = ---------------------- = 6kHz 2πR 2 C 1 (6a) More accurate sensing can be achieved by using a resistor (R1) instead of the RDS(ON) of the FET as shown in Figure 11. This approach causes higher losses, but yields greater accuracy in both VDROOP and ILIMIT. R1 is a low value (e.g. 10mΩ) resistor. 1 F P = ---------------------- = 600kHz 2πR 2 C 2 (6b) This region is also associated with phase ‘bump’ or reduced phase shift. The amount of phase shift reduction depends the width of the region of flat gain and has a maximum value of 90 degrees. To further simplify the converter compensation, the modulator gain is kept independent of the input voltage variation by providing feedforward of VIN to the oscillator ramp. Current limit (ILIMIT) should be set sufficiently high as to allow inductor current to rise in response to an output load transient. Typically, a factor of 1.3 is sufficient. In addition, since ILIMIT is a peak current cut-off value, we will need to multiply ILOAD(MAX) by the inductor ripple current (we'll use 25%). For example, in Figure 5 the target for ILIMIT would be: ILIMIT > 1.2 × 1.25 × 1.6 × 6A ≈ 14A (4) 11 FAN5026 Rev. 1.0.5 www.fairchildsemi.com FAN5026 Dual DDR/Dual-Output PWM Controller Setting the Current Limit L ( OUT ) × C ( OUT ) C ( Z ) = ------------------------------------------------------R5 R2 C1 R1 (7) VIN Protection EA Out REF The converter output is monitored and protected against extreme overload, short circuit, over-voltage and undervoltage conditions. C ve rte r 18 A sustained overload on an output sets the PGx pin low and latches-off the whole chip. Operation can be restored by cycling the VCC voltage or by toggling the EN pin. on err or a mp modulator If VOUT drops below the under-voltage threshold, the chip shuts down immediately. 14 0 F P0 FZ FP Over-Current Sensing If the circuit’s current limit signal (“ILIM det” as shown in Figure 10) is high at the beginning of a clock cycle, a pulse-skipping circuit is activated and HDRV is inhibited. The circuit continues to pulse skip in this manner for the next 8 clock cycles. If at any time from the 9th to the 16th clock cycle, the “ILIM det” is again reached, the overcurrent protection latch is set, disabling the chip. If “ILIM det” does not occur between cycle 9 and 16, normal operation is restored and the over-current circuit resets itself. Figure 12. Compensation The zero frequency, the amplifier high frequency gain and the modulator gain are chosen to satisfy most typical applications. The crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. The only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. With this type of compensation plenty of phase margin is easily achieved due to zero-pole pair phase ‘boost’. PGOOD 1 Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within the 10kHz...50kHz range gives some additional phase ‘boost’. Fortunately, there is an opposite trend in mobile applications to keep the output capacitor as small as possible. SHUTDOWN 2 VOUT 3 If a larger inductor value or low ESR values are called for by the application, additional phase margin can be achieved by putting a zero at the LC crossover frequency. This can be achieved with a capacitor across the feedback resistor (e.g. R5 from Figure 5) as shown below. L(OUT) CH1 5.0V CH3 2.0AΩ C(Z) M 10.0µs Over-Voltage / Under-Voltage Protection Should the VSNS voltage exceed 120% of VREF (0.9V) due to an upper MOSFET failure, or for other reasons, the overvoltage protection comparator will force LDRV high. This action actively pulls down the output voltage and, in the event of the upper MOSFET failure, will eventually blow the battery fuse. As soon as the output voltage drops below the threshold, the OVP comparator is disengaged. C(OUT) VSEN R6 This OVP scheme provides a ‘soft’ crowbar function which helps to tackle severe load transients and does not invert the output voltage when activated — a common problem for latched OVP schemes. Figure 13. Improving Phase Margin 12 FAN5026 Rev. 1.0.5 CH2 100mV Figure 14. Over-Current Protection Waveforms VOUT R5 8 CLK IL www.fairchildsemi.com FAN5026 Dual DDR/Dual-Output PWM Controller The optimal value of C(Z) is: C2 V IN – V OUT V OUT L = ------------------------------ × -------------F SW × ∆I V IN Over-Temperature Protection The chip incorporates an over temperature protection circuit that shuts the chip down when a die temperature of about 150°C is reached. Normal operation is restored at die temperature below 125°C with internal Power On Reset asserted, resulting in a full soft-start cycle. for this example we’ll use: VIN = 12V, VOUT = 2.5V ∆I = 25% × 6A = 1.5A FSW = 300KHz. therefore L ≈ 4.4µH Design and Component Selection Guidelines Output Capacitor Selection As an initial step, define operating input voltage range, output voltage, minimum and maximum load currents for the controller. The output capacitor serves two major functions in a switching power supply. Along with the inductor it filters the sequence of pulses produced by the switcher, and it supplies the load transient currents. The output capacitor requirements are usually dictated by ESR, Inductor ripple current (∆I) and the allowable ripple voltage (∆V). Setting the Output Voltage The internal reference is 0.9V. The output is divided down by a voltage divider to the VSEN pin (for example, R5 and R6 in Figure 4). The output voltage therefore is: V OUT – 0.9V 0.9V ------------ = -------------------------------R6 R5 (10) ∆V ESR < -------∆I (8a) (11) To minimize noise pickup on this node, keep the resistor to GND (R6) below 2K. We selected R6 at 1.82K. Then choose R5: In addition, the capacitor’s ESR must be low enough to allow the converter to stay in regulation during a load step. The ripple voltage due to ESR for the converter in Figure 5 is 120mV P-P. Some additional ripple will appear due to the capacitance value itself: ( 1.82K ) × ( V OUT – 0.9 ) - = 3.24K R5 = -----------------------------------------------------------0.9 ∆I ∆V = -----------------------------------------C OUT × 8 × F SW (8b) (12) For DDR applications converting from 3.3V to 2.5V, or other applications requiring high duty cycles, the duty cycle clamp must be disabled by tying the converter’s FPWM to GND. When converter’s FPWM is GND, the converter's maximum duty cycle will be greater than 90%. When using as a DDR converter with 3.3V input, set up the converter for In-Phase synchronization by tying the VIN pin to +5V. which is only about 1.5mV for the converter in Figure 5 and can be ignored. Output Inductor Selection Input Capacitor Selection The minimum practical output inductor value is the one that keeps inductor current just on the boundary of continuous conduction at some minimum load. The industry standard practice is to choose the minimum current somewhere from 15% to 35% of the nominal current. At light load, the controller can automatically switch to hysteretic mode of operation to sustain high efficiency. The following equations help to choose the proper value of the output filter inductor. The input capacitor should be selected by its ripple current rating. ∆V OUT ∆I = 2 × I MIN = -----------------ESR I VTT I REG1 = I VDDQ + ---------2 The capacitor must also be rated to withstand the RMS current which is approximately 0.3 X (∆I), or about 400mA for the converter in Figure 5. High frequency decoupling capacitors should be placed as close to the loads as physically possible. Two-Stage Converter Case In DDR mode (Figure 4), the VTT power input is powered by the VDDQ output, therefore all of the input capacitor ripple current is produced by the VDDQ converter. A conservative estimate of the output current required for the 2.5V regulator is: (9) 13 FAN5026 Rev. 1.0.5 www.fairchildsemi.com FAN5026 Dual DDR/Dual-Output PWM Controller where ∆I is the inductor ripple current and ∆VOUT is the maximum ripple allowed. Similarly, if an output short-circuit or severe load transient causes the output to droop to less than 75% of its regulation set point. Should this condition occur, the regulator will shut down. I RMS = I OUT ( MAX ) D – D 2 (13) Assuming switching losses are about the same for both the rising edge and falling edge, Q1’s switching losses, occur during the shaded time when the MOSFET has voltage across it and current through it. where D is the duty cycle of the PWM1 converter: V OUT 2.5 D < -------------- = -------V IN 12 (14) These losses are given by: therefore: PUPPER = PSW + PCOND 2.5 2.5 2 I RMS = 3.5 -------- – -------- = 1.42A 12 12 (15) V DS × I L P SW = --------------------- × 2 × t S F SW 2 (17a) V OUT 2 P COND = -------------- × I OUT × R DS ( ON ) V IN (17b) Dual Converter 180° Phased In Dual mode (Figure 5), both converters contribute to the capacitor input ripple current. With each converter operating 180° out of phase, the RMS currents add in the following fashion: 2 2 I RMS ( 1 ) + I RMS ( 2 ) or I RMS = ( I1 ) ( D1 – D1 ) + ( I2 ) ( D2 – D2 ) 2 PUPPER is the upper MOSFET’s total losses, and PSW and PCOND are the switching and conduction losses for a given MOSFET. RDS(ON) is at the maximum junction temperature (TJ). tS is the switching period (rise or fall time) and is t2+t3 Figure . (16a) I RMS = 2 where: 2 2 (16b) The driver’s impedance and CISS determine t2 while t3’s period is controlled by the driver's impedance and QGD. Since most of tS occurs when VGS = VSP we can use a constant current assumption for the driver to simplify the calculation of tS: which for the dual 3A converters of Figure 5, calculates to: I RMS = 1.51A CISS Power MOSFET Selection C ISS VDS Losses in a MOSFET are the sum of its switching (PSW) and conduction (PCOND) losses. In typical applications, the FAN5026 converter’s output voltage is low with respect to its input voltage, therefore the Lower MOSFET (Q2) is conducting the full load current for most of the cycle. Q2 should therefore be selected to minimize conduction losses, thereby selecting a MOSFET with low RDS(ON). ID In contrast, the high-side MOSFET (Q1) has a much shorter duty cycle, and it's conduction loss will therefore have less of an impact. Q1, however, sees most of the switching losses, so Q1’s primary selection criteria should be gate charge. QGS Q GD 4.5V VSP VTH QG(SW) V GS High-Side Losses t1 Figure shows a MOSFET’s switching interval, with the upper graph being the voltage and current on the Drain to Source and the lower graph detailing VGS vs. time with a constant current charging the gate. The x-axis there- t2 t3 t4 t5 Figure 15. Switching Losses and QG 14 FAN5026 Rev. 1.0.5 C GD www.fairchildsemi.com FAN5026 Dual DDR/Dual-Output PWM Controller fore is also representative of gate charge (QG). CISS = CGD + CGS, and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as VDS is falling). The gate charge (QG) parameters on the lower graph are either specified or can be derived from MOSFET datasheets. As an example, if average IVDDQ is 3A, and average IVTT is 1A, IVDDQ current will be about 3.5A. If average input voltage is 12V, RMS input ripple current will be: 5V C GD RD HDRV Layout Considerations RGATE Switching converters, even during normal operation, produce short pulses of current which could cause substantial ringing and be a source of EMI if layout constrains are not observed. G CGS SW There are two sets of critical components in a DC-DC converter. The switching power components process large amounts of energy at high rate and are noise generators. The low power components responsible for bias and feedback functions are sensitive to noise. Figure 16. Drive Equivalent Circuit Q G ( SW ) Q G ( SW ) t S = --------------------- ≈ -----------------------------------------------------I DRIVER VCC – V SP ------------------------------------------------ R DRIVER + R GATE (18) A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as: QG(SW) = QGD + QGS – QTH where QTH is the gate charge required to get the MOSFET to it’s threshold (VTH). For the high-side MOSFET, VDS = VIN, which can be as high as 20V in a typical portable application. Care should also be taken to include the delivery of the MOSFET’s gate power (PGATE) in calculating the power dissipation required for the FAN5026: PGATE = QG × VCC × FSW Notice all the nodes that are subjected to high dV/dt voltage swing such as SW, HDRV and LDRV, for example. All surrounding circuitry will tend to couple the signals from these nodes through stray capacitance. Do not oversize copper traces connected to these nodes. Do not place traces connected to the feedback components adjacent to these traces. It is not recommended to use High Density Interconnect Systems, or micro-vias on these signals. The use of High Density Interconnect Systems or micro-vias on these signals is not recommended. The use of normal thermal vias is left to the discretion of the designer. (19) where QG is the total gate charge to reach VCC. Low-Side Losses Q2, however, switches on or off with its parallel shottky diode conducting, therefore VDS ≈ 0.5V. Since PSW is proportional to VDS, Q2’s switching losses are negligible and we can select Q2 based on RDS(ON) only. Keep the wiring traces from the IC to the MOSFET gate and source as short as possible and capable of handling peak currents of 2A. Minimize the area within the gatesource path to reduce stray inductance and eliminate parasitic ringing at the gate. Conduction losses for Q2 are given by: 2 P COND = ( 1 – D ) × I OUT × R DS ( ON ) Locate small critical components like the soft-start capacitor and current sense resistors as close as possible to the respective pins of the IC. (20) The FAN5026 utilizes advanced packaging technologies with lead pitches of 0.6mm. High performance analog semiconductors utilizing narrow lead spacing may require special considerations in PWB design and manufacturing. It is critical to maintain proper cleanliness of the area surrounding these devices. It is not recommended to use any type of rosin or acid core solder, or the use of flux in either the manufacturing or touch up process as these may contribute to corrosion or enable electromigration and/or eddy currents near the sensitive low current signals. When chemicals such as these are used on or near the PWB, it is suggested that the entire PWB be cleaned and dried completely before applying power. where RDS(ON) is the RDS(ON) of the MOSFET at the highest operating junction temperature and V OUT D = -------------V IN is the minimum duty cycle for the converter. Since DMIN < 20% for portable computers, (1–D) ≈ 1 produces a conservative result, further simplifying the calculation. The maximum power dissipation (PD(MAX)) is a function of the maximum allowable die temperature of the low-side MOSFET, the θJ-A, and the maximum allowable ambient temperature rise: T J ( MAX ) – T A ( MAX ) P D ( MAX ) = -----------------------------------------------θJ – A (21) 15 FAN5026 Rev. 1.0.5 www.fairchildsemi.com FAN5026 Dual DDR/Dual-Output PWM Controller θJ-A, depends primarily on the amount of PCB area that can be devoted to heat sinking (see FSC app note AN-1029 for SO-8 MOSFET thermal information). VIN 28-Pin TSSOP –A– 9.7 ± 0.1 0.51 TYP 15 28 14 7.72 1.78 3.2 6.4 4.4 ± 0.1 4.16 –B– 0.2 B A ALL Lead Tips 0.65 0.42 PIN # 1 IDENT LAND PATTERN RECOMMENDATION 1.2 MAX 0.1 C ALL LEAD TIPS +0.15 0.90 –0.10 See Detail A 0.09–0.20 –C– 0.10 ± 0.05 0.65 0.19–0.30 0.13 A B C 12.00° Top & Botom R0.16 GAGE PLANE R0.31 DIMENSIONS ARE IN MILLIMETERS .025 0°–8° 0.61 ± 0.1 NOTES: A. Conforms to JEDEC registration MO-153, variation AB, Ref. Note 6, dated 7/93. B. Dimensions are in millimeters. C. Dimensions are exclusive of burrs, mold flash, and tie bar extensions. D Dimensions and Tolerances per ANsI Y14.5M, 1982 16 FAN5026 Rev. 1.0.5 SEATING PLANE 1.00 DETAIL A www.fairchildsemi.com FAN5026 Dual DDR/Dual-Output PWM Controller Mechanical Dimensions The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FAST ActiveArray™ FASTr™ Bottomless™ FPS™ Build it Now™ FRFET™ CoolFET™ GlobalOptoisolator™ CROSSVOLT™ GTO™ DOME™ HiSeC™ EcoSPARK™ I2C™ E2CMOS™ i-Lo™ EnSigna™ ImpliedDisconnect™ FACT™ IntelliMAX™ FACT Quiet Series™ Across the board. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I16 17 FAN5026 Rev. 1.0.5 www.fairchildsemi.com FAN5026 Dual DDR/Dual-Output PWM Controller TRADEMARKS