ON MC74LVXC3245 Configurable dual supply octal transceiver Datasheet

MC74LVXC3245
Configurable Dual Supply
Octal Transceiver
with 3−State Outputs for 3 V Systems
The 74LVXC3245 is a 24−pin dual−supply, octal configurable
voltage interface transceiver especially well suited for PCMCIA and
other real time configurable I/O applications. The VCCA pin accepts a
3.0 V supply level; the A port is a dedicated 3.0 V port. The VCCB pin
accepts a 3.0 V−to−5.0 V supply level. The B port is configured to
track the VCCB supply level. A 5.0 V level on the VCCB pin will
configure the I/O pins at a 5.0 V level and a 3.0 V VCCB will configure
the I/O pins at a 3.0 V level. The A port interfaces with a 3.0 V host
system and the B port to the card slots. This device will allow the
VCCB voltage source pin and I/O pins on the B port to float when OE is
High. This feature is necessary to buffer data to and from a PCMCIA
socket that permits PCMCIA cards to be inserted and removed during
normal operation. The Transmit/Receive (T/R) input determines the
direction of data flow. Transmit (active−High) enables data from the A
port to B port. Receive (active−Low) enables data from the B port to
the A port.
•
•
•
•
•
Bidirectional Interface Between 3.0 V and 3.0 V/5.0 V Buses
Control Inputs Compatible with TTL Level
Outputs Source/Sink Up to 24 mA
Guaranteed Simultaneous Switching Noise Level and Dynamic
Threshold Performance
Available in SOIC and TSSOP Packages
Flexible VCCB Operating Range
Allows B Port and VCCB to Float Simultaneously When OE is High
Functionally Compatible With the 74 Series 245
These Devices are Pb−Free and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 6
MARKING
DIAGRAMS
24
24
SOIC−24
DW SUFFIX
CASE 751E
1
1
LVXC3245
AWLYYWWG
1
24
24
1
Features
•
•
•
•
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LVXC
3245G
ALYW
TSSOP−24
DT SUFFIX
CASE 948H
1
LVXC3245
A
WL, L
Y
WW, W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
MC74LVXC3245/D
MC74LVXC3245
OE 22
T/R 2
VCCB NC
24
23
OE
B0
B1
B2
B3
B4
B5
B6
B7
GND
22
21
20
19
18
17
16
15
14
13
A0
3
21
A1
20
1
2
VCCA T/R
3
4
5
6
7
8
9
10
A0
A1
A2
A3
A4
A5
A6
A7
11
12
A2
19
A3
OE
T/R
A0−A7
B0−B7
17
Function
A5
Output Enable Input
Transmit/Receive Input
Side A 3−State Inputs or 3−State Outputs
Side B 3−State Inputs or 3−State Outputs
Figure 2. Logic Diagram
OE
T/R
OPERATING MODE
Non−Inverting
L
L
B Data to A Bus
L
H
A Data to B Bus
H
X
Z
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level
and Transitions are Acceptable; for ICC reasons, Do Not Float Inputs
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2
B6
10
14
INPUTS
B5
9
15
A7
B4
8
16
A6
B3
7
PIN NAMES
Pins
B2
6
18
A4
B1
5
GND GND
Figure 1. 24−Lead Pinout (Top View)
B0
4
B7
MC74LVXC3245
MAXIMUM RATINGS
Symbol
VCCA,
VCCB
VI
VI/O
Parameter
Value
DC Supply Voltage
DC Input Voltage
DC Input Diode Current
IOK
DC Output Diode Current
OE, T/R
−0.5 to VCCA +0.5
V
An
−0.5 to VCCA +0.5
V
Bn
−0.5 to VCCB +0.5
V
OE, T/R
IO
DC Output Source/Sink Current
ICC,
IGND
DC Supply Current
TSTG
Storage Temperature Range
Unit
V
DC Input/Output Voltage
IIK
Condition
−0.5 to +7.0
Per Output Pin
Maximum Current
DC Latchup Source/Sink Current
±20
VI < GND
mA
±50
VO < GND; VO > VCC
mA
±50
mA
±50
±200
mA
−65 to +150
°C
±300
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCCA,
VCCB
VI
VI/O
TA
Dt/DV
Parameter
Min
Max
Unit
2.3
3.0
3.6
5.5
V
OE, T/R
0
VCCA
V
An
Bn
0
0
VCCA
VCCB
V
−40
+85
°C
0
8
ns/V
Supply Voltage (VCCA ≤ VCCB)
VCCA
VCCB
Input Voltage
Input/Output Voltage
Operating Free−Air Temperature
Minimum Input Edge Rate
VIN from 30% to 70% of VCC; VCC at 3.0 V, 4.5 V, 5.5 V
DC ELECTRICAL CHARACTERISTICS
TA = 25°C
Symbol
VIHA
Parameter
Minimum HIGH Level
Input Voltage
VIHB
VILA
VOHB
An
OE
T/R
Bn
Maximum LOW Level
Input Voltage
VILB
VOHA
Condition
An
OE
T/R
Bn
Minimum HIGH Level
Output Voltage
VCCA
VCCB
2.3
3.0
3.6
3.0
3.6
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
2.3
3.0
3.6
3.0
3.6
5.5
2.00
2.00
3.85
2.00
2.00
3.85
V
2.3
3.0
3.6
3.0
3.6
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
2.3
3.0
3.6
3.0
3.6
5.5
0.80
0.80
1.65
0.80
0.80
1.65
V
IOUT = −100 mA
IOH = −12 mA
IOH = −24 mA
IOH = −12 mA
IOH = −24 mA
3.0
3.0
3.0
2.3
2.3
3.0
3.0
3.0
3.0
4.5
2.99
2.85
2.65
2.50
2.30
2.90
2.56
2.35
2.30
2.10
2.90
2.46
2.25
2.20
2.00
V
IOUT = −100 mA
IOH = −12 mA
IOH = −24 mA
IOH = −24 mA
3.0
3.0
3.0
3.0
3.0
3.0
3.0
4.5
2.99
2.85
2.65
4.25
2.90
2.56
2.35
3.86
2.90
2.46
2.25
3.76
V
VOUT ≤ 0.1 V
or
≥ VCC − 0.1 V
VOUT ≤ 0.1 V
or
≥ VCC − 0.1 V
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3
Typ
TA = −40 to +85°C
Guaranteed Limits
Unit
MC74LVXC3245
DC ELECTRICAL CHARACTERISTICS
TA = 25°C
Symbol
VOLA
Parameter
Maximum LOW Level
Output Voltage
VOLB
TA = −40 to +85°C
Condition
VCCA
VCCB
Typ
Guaranteed Limits
IOUT = 100 mA
IOL = 24 mA
IOL = 12 mA
IOL = 24 mA
3.0
3.0
2.7
2.7
3.0
3.0
3.0
4.5
0.002
0.21
0.11
0.22
0.10
0.36
0.36
0.42
0.10
0.44
0.44
0.50
V
IOUT = 100 mA
IOL = 24 mA
IOL = 24 mA
3.0
3.0
3.0
3.0
3.0
4.5
0.002
0.21
0.18
0.10
0.36
0.36
0.10
0.44
0.44
V
mA
IIN
Max Input Leakage
Current
OE,
T/R
VI = VCCA, GND
3.6
3.6
3.6
5.5
±0.1
±0.1
±1.0
±1.0
IOZA
Max 3−State Output
Leakage
An
VI = VIH, VIL
OE = VCCA
VO = VCCA, GND
3.6
3.6
3.6
5.5
±0.5
±0.5
±5.0
±5.0
IOZB
Max 3−State Output
Leakage
Bn
VI = VIH, VIL
OE = VCCA
VO = VCCB, GND
3.6
3.6
3.6
5.5
±0.5
±0.5
±5.0
±5.0
DICC
Maximum ICC/Input
Bn
VI = VCCB−2.1 V
3.6
5.5
1.35
1.5
All Inputs
VI = VCC−0.6 V
3.6
3.6
0.35
0.5
ICCA1
1.0
Unit
mA
mA
mA
mA
Quiescent VCCA Supply Current as B Port
Floats
An = VCCA or GND
Bn = Open,
OE = VCCA,
T/R = VCCA,
VCCB = Open
3.6
Open
5
50
ICCA2
Quiescent VCCA Supply Current
An = VCCA or GND
Bn = VCCB or
GND, OE = GND,
T/R = GND
3.6
3.6
3.6
5.5
5
5
50
50
ICCB
Quiescent VCCB Supply Current
An = VCCA or GND
Bn = VCCB or
GND, OE = GND,
T/R = VCCA
3.6
3.6
3.6
5.5
5
8
50
80
VOLPA
Quiet Output Max Dynamic VOL
Notes 1, 2
3.3
3.3
3.3
5.0
0.8
0.8
V
Notes 1, 2
3.3
3.3
3.3
5.0
0.8
1.5
V
Notes 1, 2
3.3
3.3
3.3
5.0
−0.8
−0.8
V
Notes 1, 2
3.3
3.3
3.3
5.0
−0.8
−1.2
V
Notes 1, 3
3.3
3.3
3.3
5.0
2.0
2.0
V
Notes 1, 3
3.3
3.3
3.3
5.0
2.0
3.5
V
Notes 1, 3
3.3
3.3
3.3
5.0
0.8
0.8
V
Notes 1, 3
3.3
3.3
3.3
5.0
0.8
1.5
V
VOLPB
VOLVA
Quiet Output Min Dynamic VOL
VOLVB
VIHDA
Min HIGH Level Dynamic Input Voltage
VIHDB
VILDA
VILDB
Max LOW Level Dynamic Input Voltage
mA
mA
mA
1. Worst case package.
2. Max number of outputs defined as (n). Data inputs are driven 0 V to VCC level; one output at GND.
3. Max number of data inputs (n) switching. (n−1) inputs switching 0 V to VCC level. Input under test switching: VCC level to threshold (VIHD),
0 V to threshold (VILD), f = 1 MHz.
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4
MC74LVXC3245
AC ELECTRICAL CHARACTERISTICS
TA = −40 to +85°C; CL = 50 pF
VCCA = 2.7−3.6 V
VCCB = 4.5−5.5 V
Symbol
Parameter
VCCA = 2.7−3.6 V
VCCB = 3.0−3.6 V
Min
Typ
(Note 4)
Max
Min
Typ
(Note 5)
Max
Unit
tPHL
tPLH
Propagation Delay A to B
1.0
1.0
4.8
3.9
8.5
7.0
1.0
1.0
5.5
5.2
9.0
8.5
ns
tPHL
tPLH
Propagation Delay B to A
1.0
1.0
3.8
4.3
7.0
8.0
1.0
1.0
4.4
5.1
7.5
8.0
ns
tPZL
tPZH
Output Enable Time OE to B
1.0
1.0
4.7
4.8
8.5
9.0
1.0
1.0
6.0
6.1
9.5
10.0
ns
tPZL
tPZH
Output Enable Time OE to A
1.0
1.0
5.9
5.4
10.0
9.5
1.0
1.0
6.4
5.8
10.5
9.5
ns
tPHZ
tPLZ
Output Disable Time OE to B
1.0
1.0
4.0
3.8
8.5
8.0
1.0
1.0
6.3
4.5
10.0
8.5
ns
tPHZ
tPLZ
Output Disable Time OE to A
1.0
1.0
4.6
3.1
10.0
7.0
1.0
1.0
5.2
3.4
10.0
7.0
ns
tOSHL
tOSLH
Output to Output Skew, Data to Output
(Note 6)
1.0
1.5
1.0
1.5
ns
4. Typical values at VCCA = 3.3 V, VCCB = 5.0 V at 25°C.
5. Typical values at VCCA = 3.3 V, VCCB = 3.3 V at 25°C.
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Condition
Typical
Unit
CIN
Input Capacitance
VCCA = 3.3 V; VCCB = 5.0 V
4.5
pF
CI/O
Input/Output Capacitance
VCCA = 3.3 V; VCCB = 5.0 V
10
pF
CPD
Power Dissipation Capacitance
(Measured at 10 MHz)
VCCB = 5.0 V
VCCA = 3.3 V
50
40
pF
A→B
B→A
ORDERING INFORMATION
Package
Shipping†
SOIC−24
(Pb−Free)
1000 Tape & Reel
MC74LVXC3245DTG
TSSOP−24*
(Pb−Free)
62 Units / Rail
MC74LVXC3245DTR2G
TSSOP−24*
(Pb−Free)
2500 Tape & Reel
Device
MC74LVXC3245DWR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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5
MC74LVXC3245
VCCA
VCCB
LVXC3245
SD(0:15)
SLOT 0
ISA BUS (IEEE P996)
LVXC3245
POWER
SWITCHES
PCMCIA 2.0
JEIDA 4.1
COMPATIBLE
CONTROLLER
SLOT 0
SLOT 1
5V
VCC
3V
VCC
LVXC3245
SLOT 1
SD(0:15)
LVXC3245
OPTIONAL
Figure 3. Block Diagram
Configurable I/O Application for PCMCIA Cards
rail−to−rail output swings, maximizing the reliability of the
interface.
The VCCA pin must always be tied to a 3.3 V power supply.
This voltage connection provides internal references needed
to account for variations in VCCB. When connected as in the
figure above, the LVXC3245 meets all the voltage and current
requirements of the ISA bus standard (IEEE P996).
The 74LVXC3245 is a dual−supply device well suited for
PCMCIA configurable I/O applications. The LVXC3245
consumes less than 1mW of quiescent power in all modes of
operation, making it ideal for low power notebook designs.
The LVXC3245 meets all PCMCIA I/O voltage requirements
at 5.0 V and 3.3 V operation. By tying the VCCB pin to the
card voltage supply, the PCMCIA card will always have
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6
MC74LVXC3245
VCC
An, Bn
50% VCC
50% VCC
0V
tPLH
tPHL
VOH
50% VCC
Bn, An
50% VCC
VOL
WAVEFORM 1 - PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
VCC
50% VCC
50% VCC
OE, T/R
0V
tPHZ
tPZH
VCC
VOH - 0.3 V
50% VCC
An, Bn
≈0V
tPZL
tPLZ
≈ VCC
50% VCC
An, Bn
VOL + 0.3 V
GND
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 4. AC Waveforms
VCC
R1
PULSE
GENERATOR
DUT
RT
CL
TEST
RL
SWITCH
tPLH, tPHL, tPZH, tPHZ
Open
tPZL, tPLZ
2xVCC
CL = 50 pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 500 W or equivalent
RT = ZOUT of pulse generator (typically 50 W)
Figure 5. Test Circuit
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2xVCC
OPEN
MC74LVXC3245
PACKAGE DIMENSIONS
SOIC−24
DW SUFFIX
CASE 751E−04
ISSUE E
−A−
24
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
13
−B−
12X
P
0.010 (0.25)
1
M
B
M
12
24X
D
J
0.010 (0.25)
M
T A
S
B
S
F
R
C
−T−
SEATING
PLANE
22X
G
K
M
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8
X 45 _
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
15.25
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0_
8_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0_
8_
0.395
0.415
0.010
0.029
MC74LVXC3245
PACKAGE DIMENSIONS
TSSOP−24
DT SUFFIX
CASE 948H−01
ISSUE A
24X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
V
S
S
S
2X
24
L/2
13
B
−U−
L
PIN 1
IDENT.
12
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
S
A
−V−
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
C
0.10 (0.004)
−T− SEATING
PLANE
G
D
H
−W−
MILLIMETERS
MIN
MAX
7.70
7.90
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.303
0.311
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
DETAIL E
N
K
ÇÇÇ
ÉÉ
ÇÇÇ
ÉÉ
0.25 (0.010)
K1
J1
M
N
F
SECTION N−N
DETAIL E
J
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74LVXC3245/D
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