LINER LTC4227 Dual ideal diode and hot swap controller Datasheet

LTC4228-1/LTC4228-2
Dual Ideal Diode and
Hot Swap Controller
Features
Description
Power Path and Inrush Current Control for
Redundant Supplies
Low Loss Replacement for Power Schottky Diodes
Protects Output Voltage from Input Brownouts
Allows Safe Hot Swapping from a Live Backplane
2.9V to 18V Operating Range
Controls N-Channel MOSFETs
Limits Peak Fault Current in ≤1µs
Adjustable Current Limit with Circuit Breaker
Adjustable Current Limit Fault Delay
Smooth Switchover without Oscillation
0.5µs Ideal Diode Turn-On and Turn-Off Time
Status, Fault and Power Good Outputs
LTC4228-1: Latch Off After Fault
LTC4228-2: Automatic Retry After Fault
28-Lead 4mm × 5mm QFN and SSOP Packages
n
n
n
n
n
n
n
n
n
n
n
n
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Applications
n
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The LTC4228 regulates the forward voltage drop across
the external MOSFETs and sense resistor to ensure smooth
current transfer from one supply to the other without
oscillation. The ideal diodes turn on quickly to reduce
the load voltage droop during supply switch-over. If the
input supply fails or is shorted, a fast turn-off minimizes
reverse-current transients.
The LTC4228 allows independent on/off control, and reports
fault and power good status for the supply. The LTC4228
improves on the LTC4225 by recovering more quickly from
input brownouts to preserve the output voltage.
Redundant Power Supplies
MicroTCA Systems and Servers
Telecom Networks
Power Prioritizer
n
The LTC®4228 offers ideal diode and Hot Swap™ functions
for two power rails by controlling two external N-channel
MOSFETs in each rail. MOSFETs acting as ideal diodes replace two high power Schottky diodes and the associated
heat sinks, saving power and board area. Hot Swap control
MOSFETs allow boards to be safely inserted and removed
from a live backplane by limiting inrush current. The supply
output is also protected against short-circuit faults with a
fast acting current limit and internal timed circuit breaker.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
Typical Application
µTCA Application
Si7336ADP
12V
0.004Ω
PLUG-IN
CARD 1
Si7336ADP
0.1µF
CPO1
IN1
SENSE1+ SENSE1– HGATE1 OUT1
DGATE1
ON1
20k
INTVCC
TMR1
LTC4228
TMR2
GND
IN2
1V/DIV
47nF
47nF
IIN1
2A/DIV
PLUG-IN
CARD 2
EN2
PWRGD2
FAULT2
STATUS2
20k
ON2
137k
IN1
1V/DIV
STATUS1
FAULT1
PWRGD1
EN1
137k
0.1µF
Smooth Supply Switchover
12V
7.6A
CPO2
IN2
DGATE2
IIN2
2A/DIV
SENSE2+ SENSE2– HGATE2 OUT2
200ms/DIV
422512 TA01b
0.1µF
12V
Si7336ADP
0.004Ω
12V
7.6A
Si7336ADP
BACKPLANE
422812 TA01a
422812f
1
LTC4228-1/LTC4228-2
Absolute Maximum Ratings (Notes 1, 2)
Supply Voltages
IN1, IN2................................................... –0.3V to 24V
INTVCC...................................................... –0.3V to 7V
Input Voltages
ON1, ON2, EN1, EN2............................... –0.3V to 24V
TMR1, TMR2..........................–0.3V to INTVCC + 0.3V
SENSE1+, SENSE2+................................. –0.3V to 24V
SENSE1–, SENSE2–................................ –0.3V to 24V
Output Voltages
FAULT1, FAULT2, PWRGD1, PWRGD2...... –0.3V to 24V
STATUS1, STATUS2................................. –0.3V to 24V
CPO1, CPO2 (Note 3).............................. –0.3V to 35V
DGATE1, DGATE2 (Note 3)...................... –0.3V to 35V
HGATE1, HGATE2 (Note 4)...................... –0.3V to 35V
OUT1, OUT2............................................ –0.3V to 24V
Average Currents
FAULT1, FAULT2, PWRGD1, PWRGD2....................5mA
STATUS1, STATUS2...............................................5mA
INTVCC..................................................................1mA
Operating Temperature Range
LTC4228C................................................. 0°C to 70°C
LTC4228I..............................................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
GN Package....................................................... 300°C
Pin Configuration
TOP VIEW
27 OUT1
28 27 26 25 24 23
DGATE1
3
26 PWRGD1
OUT1
28 HGATE1
2
HGATE1
1
CPO1
CPO1
STATUS1
DGATE1
PWRGD1
STATUS1
TOP VIEW
SENSE1– 1
22 FAULT1
SENSE1–
4
25 FAULT1
SENSE1+ 2
21 ON1
SENSE1+
5
24 ON1
IN1 3
20 EN1
IN1
6
23 EN1
19 TMR1
INTVCC
7
22 TMR1
18 TMR2
GND
8
21 TMR2
IN2
9
20 EN2
SENSE2+ 10
19 ON2
SENSE2– 11
18 FAULT2
INTVCC 4
29
GND 5
IN2 6
17 EN2
SENSE2+ 7
16 ON2
SENSE2– 8
15 FAULT2
PWRGD2
OUT2
HGATE2
STATUS2
CPO2
DGATE2
9 10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 43°C/W (NOTE 5)
EXPOSED PAD (PIN 29) PCB GND CONNECTION OPTIONAL
DGATE2 12
CPO2 13
STATUS2 14
17 PWRGD2
16 OUT2
15 HGATE2
GN PACKAGE
28-LEAD PLASTIC SSOP NARROW
TJMAX = 125°C, θJA = 80°C/W
422812f
2
LTC4228-1/LTC4228-2
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4228CUFD-1#PBF
LTC4228CUFD-1#TRPBF
42281
28-Lead (4mm × 5mm) Plastic QFN
0°C to 70°C
LTC4228CUFD-2#PBF
LTC4228CUFD-2#TRPBF
42282
28-Lead (4mm × 5mm) Plastic QFN
0°C to 70°C
LTC4228IUFD-1#PBF
LTC4228IUFD-1#TRPBF
42281
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 85°C
LTC4228IUFD-2#PBF
LTC4228IUFD-2#TRPBF
42282
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 85°C
LTC4228CGN-1#PBF
LTC4228CGN-1#TRPBF
LTC4228GN-1
28-Lead Plastic SSOP
0°C to 70°C
LTC4228CGN-2#PBF
LTC4228CGN-2#TRPBF
LTC4228GN-2
28-Lead Plastic SSOP
0°C to 70°C
LTC4228IGN-1#PBF
LTC4228IGN-1#TRPBF
LTC4228GN-1
28-Lead Plastic SSOP
–40°C to 85°C
LTC4228IGN-2#PBF
LTC4228IGN-2#TRPBF
LTC4228GN-2
28-Lead Plastic SSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supplies
VIN
Input Supply Range
l
IIN
Input Supply Current
l
VINTVCC
Internal Regulator Voltage
I = 0, –500µA
l
4.5
5
5.6
V
VINTVCC(UVL)
Internal VCC Undervoltage Lockout
INTVCC Rising
l
2.1
2.2
2.3
V
l
30
60
90
mV
l
10
25
40
mV
∆VINTVCC(HYST) Internal VCC Undervoltage Lockout Hysteresis
2.9
2.5
18
V
5
mA
Ideal Diode Control
∆VFWD(REG)
Forward Regulation Voltage (VINn – VOUTn)
∆VDGATE
External N-Channel Gate Drive
(VDGATEn – VINn)
IN < 7V, ∆VFWD = 0.1V, I = 0, –1µA
IN = 7V to 18V, ∆VFWD = 0.1V, I = 0, –1µA
l
l
5
10
7
12
14
14
V
V
∆VDGATE(ST)
Diode MOSFET On Detect Threshold
STATUS Pulls Low, ∆VFWD = 50mV
l
0.3
0.7
1.1
V
ICPO(UP)
CPOn Pull-Up Current
CPO = IN = 2.9V
CPO = IN = 18V
l
l
–60
–50
–95
–85
–120
–110
µA
µA
IDGATE(FPU)
DGATEn Fast Pull-Up Current
∆VFWD = 0.2V, ∆VDGATE = 0V, CPO = 17V
–1.5
A
IDGATE(FPD)
DGATEn Fast Pull-Down Current
∆VFWD = –0.2V, ∆VDGATE = 5V
1.5
A
tON(DGATE)
DGATEn Turn-On Delay
∆VFWD = 0.2V, CDGATE = 10nF
l
0.25
0.5
µs
tOFF(DGATE)
DGATEn Turn-Off Delay
∆VFWD = –0.2V, CDGATE = 10nF
l
0.2
0.5
µs
Hot Swap Control
∆VSENSE(CB)
Circuit Breaker Trip Sense Voltage
(VSENSEn+ – VSENSEn–)
l
47.5
50
52.5
mV
∆VSENSE(ACL)
Active Current Limit Sense Voltage
(VSENSEn+ – VSENSEn–)
l
55
65
75
mV
l
1.75
1.9
2.05
l
10
50
90
VSENSE+(UVL)
SENSEn+ Undervoltage Lockout
∆VSENSE+(HYST) SENSEn+ Undervoltage Lockout Hysteresis
SENSE+ Rising
V
mV
SENSEn+ Input Current
SENSE+ = 12V
l
150
350
500
µA
ISENSE–
SENSEn– Input Current
SENSE– = 12V
l
10
50
100
µA
∆VHGATE
External N-Channel Gate Drive
(VHGATEn – VOUTn)
IN < 7V, I = 0, –1µA
IN = 7V to 18V, I = 0, –1µA
l
l
4.8
10
7
12
14
14
V
V
ISENSE+
422812f
3
LTC4228-1/LTC4228-2
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted.
SYMBOL
PARAMETER
∆VHGATE(PG)
Gate-Source Voltage for Power Good
CONDITIONS
l
MIN
TYP
MAX
3.6
4.2
4.8
UNITS
V
IHGATE(UP)
External N-Channel Gate Pull-Up Current
Gate Drive On, HGATE = 0V
l
–7
–10
–13
µA
IHGATE(DN)
External N-Channel Gate Pull-Down Current
Gate Drive Off, OUT = 12V,
HGATE = OUT + 5V
l
150
300
500
µA
IHGATE(FPD)
External N-Channel Gate Fast
Pull-Down Current
Fast Turn-Off, OUT = 12V,
HGATE = OUT + 5V
l
100
200
300
mA
tPHL(SENSE)
Sense Voltage (SENSEn+ – SENSEn–)
High to HGATEn Low
∆VSENSE = 300mV, CHGATE = 10nF
l
0.5
1
µs
tOFF(HGATE)
ENn High to HGATEn Low
ONn Low to HGATEn Low
SENSEn+ Low to HGATEn Low
l
l
l
20
10
10
40
20
20
µs
µs
µs
tD(HGATE)
ONn High, ENn Low to HGATEn
Turn-On Delay
l
100
150
ms
tP(HGATE)
ONn to HGATEn Propagation Delay
ON = Step 0.8V to 2V
l
10
20
µs
VON(TH)
ONn Threshold Voltage
ON Rising
l
1.21
1.235
1.26
V
∆VON(HYST)
ONn Hysteresis
l
40
80
140
mV
VON(RESET)
ONn Fault Reset Threshold Voltage
ON Falling
l
0.55
0.6
0.63
V
ION(LEAK)
ONn Input Leakage Current
ON = 5V
l
0
±1
µA
VEN(TH)
ENn Threshold Voltage
EN Rising
l
1.185
1.235
1.284
∆VEN(HYST)
ENn Hysteresis
l
40
130
200
mV
IEN(UP)
ENn Pull-Up Current
EN = 1V
l
–7
–10
–13
µA
VTMR(TH)
TMRn Threshold Voltage
TMR Rising
TMR Falling
l
l
1.198
0.15
1.235
0.2
1.272
0.25
V
V
ITMR(UP)
TMRn Pull-Up Current
TMR = 1V, In Fault Mode
l
–75
–100
–125
µA
ITMR(DN)
TMRn Pull-Down Current
TMR = 2V, No Faults
l
1.4
2
2.6
µA
ITMR(RATIO)
TMRn Current Ratio ITMR(DN)/ITMR(UP)
l
1.4
2
2.7
%
IOUT
OUTn Current
OUT = 11V, IN = 12V, ON = 2V
OUT = 13V, IN = 12V, ON = 2V
l
l
50
2.5
120
5
µA
mA
VOL
Output Low Voltage
(FAULTn, PWRGDn, STATUSn)
I = 1mA
l
0.15
0.4
V
VOH
Output High Voltage
(FAULTn, PWRGDn, STATUSn)
I = –1µA
l INTVCC – 1 INTVCC – 0.5
IOH
Input Leakage Current
(FAULTn, PWRGDn, STATUSn)
V = 18V
l
IPU
Output Pull-Up Current
(FAULTn, PWRGDn, STATUSn)
V = 1.5V
l
tRST(ON)
ONn Low to FAULTn High
50
Input/Output Pin
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
l
–7
V
V
0
±1
µA
–10
–13
µA
20
40
µs
Note 3: An internal clamp limits the DGATE and CPO pins to a minimum of
10V above and a diode below IN. Driving these pins to voltages beyond the
clamp may damage the device.
Note 4: An internal clamp limits the HGATE pin to a minimum of 10V
above and a diode below OUT. Driving this pin to voltages beyond the
clamp may damage the device.
Note 5: Thermal resistance is specified when the exposed pad is soldered
to a 3" × 4.5", four layer, FR4 board.
422812f
4
LTC4228-1/LTC4228-2
Typical Performance Characteristics TA = 25°C, VIN = 12V, unless otherwise noted.
IN Supply Current vs Voltage
4
6
INTVCC Load Regulation
CPO Voltage vs Current
12
VIN = 12V
5
10
VCPO – VIN (∆VCPO) (V)
3
INTVCC (V)
IIN (mA)
4
2
VIN = 3.3V
3
2
1
1
0
0
3
6
9
VIN (V)
15
12
0
18
0
–2
–4
–6
ILOAD (mA)
GATE DRIVE (∆VHGATE) (V)
VDGATE – VIN (∆VDGATE) (V)
VIN = 18V
VIN = 2.9V
0
0
–20
–40
–80
–60
IDGATE (µA)
–100
VIN = 12V
VIN = 2.9V
6
1.5
1.0
4
0.5
2
0
0
–2
–4
–6
–8
–10
–0.5
–12
0
3
6
75
100
422812 G07
9
12
VOUT (V)
422812 G05
100
66
65
64
–25
0
25
50
TEMPERATURE (°C)
18
Active Current Limit Delay
vs Sense Voltage
67
63
–50
15
422812 G06
ACTIVE CURRENT LIMIT DELAY (µs)
ACTIVE CURRENT LIMIT SENSE VOLTAGE (mV)
CIRCUIT BREAKER TRIP VOLTAGE (mV)
49
–120
2.0
Active Current Limit Sense
Voltage vs Temperature
50
–100
VIN = 12V
IHGATE (µA)
51
–80
–60
ICPO (µA)
2.5
8
0
–120
52
0
25
50
TEMPERATURE (°C)
–40
OUT Current vs Voltage
10
Circuit Breaker Trip Voltage
vs Temperature
–25
–20
422812 G03
VOUT = VIN
422812 G04
48
–50
0
3.0
12
4
–2
–2
–10
–8
IOUT (mA)
VOUT = VIN – 0.1V
8
VIN = 2.9V
2
Hot Swap Gate Voltage vs Current
14
10
2
4
422812 G02
Diode Gate Voltage vs Current
6
VIN = 18V
6
0
422812 G01
12
8
75
100
422812 G08
CHGATE = 10nF
10
1
0.1
50
100
150
200
250
SENSE VOLTAGE (VIN – VSENSE) (mV)
300
422812 G09
422812f
5
LTC4228-1/LTC4228-2
Typical Performance Characteristics TA = 25°C, VIN = 12V, unless otherwise noted.
HGATE Pull-Up Current
vs Temperature
TMR Pull-Up Current
vs Temperature
–103
–11.0
0.8
–10.5
OUTPUT LOW VOLTAGE (V)
–102
TMR PULL-UP CURRENT (µA)
HGATE PULL-UP CURRENT (µA)
PWRGD, FAULT, STATUS Output
Low Voltage vs Current
–101
–10.0
–100
–9.5
–9.0
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
–99
0.6
0.4
0.2
–98
–97
–50
–25
0
25
50
TEMPERATURE (°C)
422812 G10
75
100
422812 G11
0
0
1
3
2
CURRENT (mA)
4
5
422812 G12
Pin Functions
CPO1, CPO2: Charge Pump Output. Connect a capacitor
from CPO1 or CPO2 to the corresponding IN1 or IN2 pin.
The value of this capacitor is approximately 10× the gate
capacitance (CISS) of the external MOSFET for ideal diode
control. The charge stored on this capacitor is used to pull
up the gate during a fast turn-on. Leave this pin open if
fast turn-on is not needed.
DGATE1, DGATE2: Ideal Diode MOSFET Gate Drive Output. Connect this pin to the gate of an external N-channel
MOSFET for ideal diode control. An internal clamp limits
the gate voltage to 12V above and a diode voltage below
IN. During fast turn-on, a 1.5A pull-up charges DGATE from
CPO. During fast turn-off, a 1.5A pull-down discharges
DGATE to IN.
EN1, EN2: Enable Input. Ground this pin to enable Hot
Swap control. If this pin is pulled high, the MOSFET is not
allowed to turn on. A 10µA current source pulls this pin
up to a diode below INTVCC. Upon EN going low when ON
is high, an internal timer provides a 100ms start-up delay
for debounce, after which the fault is cleared.
Exposed Pad (UFD Package): The exposed pad may be
left open or connected to device ground.
FAULT1, FAULT2: Fault Status Output. Open-drain output
that is normally pulled high by a 10µA current source to a
diode below INTVCC. It may be pulled above INTVCC using
an external pull-up. It pulls low when the circuit breaker
is tripped after an overcurrent fault timeout. Leave open
if unused.
GND: Device Ground.
HGATE1, HGATE2: Hot Swap MOSFET Gate Drive Output.
Connect this pin to the gate of the external N-channel
MOSFET for Hot Swap control. An internal 10µA current
source charges the MOSFET gate. An internal clamp limits
the gate voltage to 12V above and a diode below OUT.
During turn-off, a 300µA pull-down discharges HGATE to
ground. During an output short or INTVCC undervoltage
lockout, a fast 200mA pull-down discharges HGATE to OUT.
IN1, IN2: Positive Supply Input and Ideal Diode’s MOSFET
Gate Drive Return. The 5V INTVCC supply is generated
from IN1, IN2, OUT1 and OUT2 via an internal diode-OR.
The voltage sensed at this pin is used to control DGATE
for forward voltage regulation and reverse turn-off. The
gate fast pull-down current returns through this pin when
DGATE is discharged.
422812f
6
LTC4228-1/LTC4228-2
Pin Functions
INTVCC: Internal 5V Supply Decoupling Output. This pin
must have a 0.1µF or larger capacitor. An external load of
less than 500µA can be connected at this pin.
at this pin is used for monitoring the current limit. This
pin has an undervoltage lockout threshold of 1.9V that
will turn off the Hot Swap MOSFET.
ON1, ON2: On Control Input. A rising edge above 1.235V
turns on the external Hot Swap MOSFET and a falling edge
below 1.155V turns it off. Connect this pin to an external
resistive divider from IN or SENSE+ to monitor the supply
undervoltage condition. Pulling the ON pin below 0.6V
resets the electronic circuit breaker.
SENSE1–, SENSE2–: Negative Current Sense Input. Connect this pin to the output of the current sense resistor.
The current limit circuit controls HGATE to limit the voltage
between SENSE+ and SENSE– to 65mV. A circuit breaker
trips when the sense voltage exceeds 50mV for more than
a fault filter delay configured at the TMR pin.
OUT1, OUT2: Output Voltage Sense and Hot Swap’s MOSFET Gate Drive Return. Connect this pin to the output side
of the external MOSFET. The voltage sensed at this pin is
used to control DGATE. The gate fast pull-down current
returns through this pin when HGATE is discharged.
STATUS1, STATUS2: Diode MOSFET Status Output.
Open-drain output that is normally pulled high by a 10µA
current source to a diode below INTVCC. It may be pulled
above INTVCC using an external pull-up. It pulls low when
the MOSFET gate drive between DGATE and IN exceeds
the gate-to-source voltage of 0.7V. Leave open if unused.
PWRGD1, PWRGD2: Power Status Output. Open-drain
output that is normally pulled high by a 10µA current
source to a diode below INTVCC. It may be pulled above
INTVCC using an external pull-up. It pulls low when the
MOSFET gate drive between HGATE and OUT exceeds
the gate-to-source voltage of 4.2V. Leave open if unused.
TMR1, TMR2: Timer Capacitor Terminal. Connect a capacitor between this pin and ground to set a 12ms/µF duration
for current limit before the external Hot Swap MOSFET
is turned off. The duration of the off time is 617ms/µF,
resulting in a 2% duty cycle.
SENSE1+, SENSE2+: Positive Current Sense Input. Connect
this pin to the output of the external ideal diode MOSFET
and input of the current sense resistor. The voltage sensed
422812f
7
LTC4228-1/LTC4228-2
Block Diagram
SENSE1+
65mV
HGATE1
SENSE1–
50mV
+ –+
A1
–
12V
SENSE2–
50mV
+– +
ECB1
–
SENSE2+
65mV
+ –+
ECB2
–
HGATE2
+– +
A2
–
12V
IN2
IN1
10µA
10µA
–+
25mV
25mV
1.235V
ON1
INTVCC
0.6V
10µA
+
–
EN1
1.235V
CP5
1.9V
– CP1
+
–
+
CP2
HGATE2 ON
HGATE1 ON
FAULT2 RESET
FAULT1 RESET
CARD1 PRESENCE DETECT
SENSE2+
1.9V
STAT2
CP3
CP4
+
–
IN1
STAT1
UV2
+
–
+
–
+–
+ UV1
–
–
+
0.7V
INTVCC
UV3
PG2
4.2V
SENSE1+
DGATE1
+ –
+–
HGATE1
PG1
OUT2
INTVCC
ON2
INTVCC
0.6V
INTVCC
TMR1
0.2V
–
+
CP7
–
+
CP8
10µA
10µA
PWRGD1
GND
*UFD PACKAGE ONLY
INTVCC
LOGIC
CP10
TMR2
0.2V
2µA
INTVCC
FAULT1
1.235V
1.235V
2µA
STATUS1
EN2
100µA
CP9
+
–
1.235V
+
–
100µA
DGATE2
IN2
1.235V
CP6
CARD2 PRESENCE DETECT
HGATE2
4.2V
0.7V
–
+
2.2V
–
+
DGATE2
12V
–
+
OUT1
CPO2
GATE
DRIVER 2
+
GA2
–
5V LDO
+–
100µA
+–
12V
+
GA1
–
INTVCC
+
–
GATE
DRIVER 1
DGATE1
INTVCC
CHARGE
PUMP 2
f = 2MHz
+–
CHARGE
PUMP 1
f = 2MHz
100µA
CPO1
INTVCC
10µA
INTVCC
10µA
INTVCC
10µA
INTVCC
10µA
INTVCC
10µA
STATUS2
FAULT2
PWRGD2
EXPOSED PAD*
422812 BD
422812f
8
LTC4228-1/LTC4228-2
Operation
The LTC4228 functions as an ideal diode with inrush current limiting and overcurrent protection by controlling two
external N-channel MOSFETs (MD and MH) on a supply
path. This allows boards to be safely inserted and removed
in systems with a backplane powered by redundant supplies, such as µTCA applications. The LTC4228 has two
separate ideal diode and Hot Swap controllers, each
providing independent control for the two input supplies.
When the LTC4228 is first powered up, the gates of the
external MOSFETs are held low, keeping them off. The gate
drive amplifier (GA1, GA2) monitors the voltage between the
IN and OUT pins and drives the DGATE pin. The amplifier
quickly pulls up the DGATE pin, turning on the MOSFET
for ideal diode control, when it senses a large forward
voltage drop. The stored charge in an external capacitor
connected between the CPO and IN pins provides the
charge needed to quickly turn on the ideal diode MOSFET.
An internal charge pump charges up this capacitor at device
power-up. The DGATE pin sources current from the CPO
pin and sinks current into the IN and GND pins. When the
DGATE to IN voltage exceeds 0.7V, the STATUS pin pulls
low to indicate that the ideal diode MOSFET is turned on.
Pulling the ON pin high and the EN pin low initiates a
100ms debounce timing cycle. After this timing cycle,
a 10µA current source from the charge pump ramps up
the HGATE pin. When the Hot Swap MOSFET turns on,
the inrush current is limited at a level set by an external
sense resistor (RS) connected between the SENSE+ and
SENSE– pins. An active current limit amplifier (A1, A2)
servos the gate of the MOSFET to 65mV across the current
sense resistor. Inrush current can be further reduced, if
desired, by adding a capacitor from HGATE to GND. When
the MOSFET ’s gate overdrive (HGATE to OUT voltage)
exceeds 4.2V, the PWRGD pin pulls low.
When both of the MOSFETs are turned on, the gate drive
amplifier controls DGATE to servo the forward voltage
drop (VIN – VOUT) across the sense resistor and the two
MOSFETs to 25mV. If the load current causes more than
25mV of voltage drop, the DGATE voltage rises to enhance
the MOSFET used for ideal diode control. For large output
currents, the ideal diode MOSFET is driven fully on and
the voltage drop across the MOSFETs is equal to the sum
of the ILOAD • RDS(ON) of the two MOSFETs in series.
In the case of an input supply short circuit when the
MOSFETs are conducting, a large reverse current starts
flowing from the load towards the input. The gate drive
amplifier detects this failure condition as soon as it appears and turns off the ideal diode MOSFET by pulling
down the DGATE pin.
In the case where an overcurrent fault occurs on the supply output, the current is limited to 65mV/RS. After a fault
filter delay set by 100µA charging the TMR pin capacitor,
the circuit breaker trips and pulls the HGATE pin low, turning off the Hot Swap MOSFET. Only the supply at fault is
affected, with the corresponding FAULT pin latched low.
At this point, the DGATE pin continues to pull high and
keeps the ideal diode MOSFET on.
Internal clamps limit both the DGATE to IN and CPO to IN
voltages to 12V. The same clamp also limits the CPO and
DGATE pins to a diode voltage below the IN pin. Another
internal clamp limits the HGATE to OUT voltage to 12V
and also clamps the HGATE pin to a diode voltage below
the OUT pin.
Power to the LTC4228 is supplied from either the IN or
OUT pins, through an internal diode-OR circuit to a low
dropout regulator (LDO). That LDO generates a 5V supply
at the INTVCC pin and powers the LTC4228’s internal low
voltage circuitry.
422812f
9
LTC4228-1/LTC4228-2
Applications Information
High availability systems often employ parallel-connected
power supplies or battery feeds to achieve redundancy
and enhance system reliability. Power ORing diodes are
commonly used to connect these supplies at the point of
load, but at the expense of power loss due to significant
diode forward voltage drop. The LTC4228 minimizes this
power loss by using external N-channel MOSFETs for the
pass elements, allowing for a low voltage drop from the
supply to the load when the MOSFETs are turned on. When
an input source voltage drops below the output common
supply voltage, the appropriate MOSFET is turned off,
thereby matching the function and performance of an ideal
diode. By adding a current sense resistor in between the
two external MOSFETs that are separately controlled, the
LTC4228 enhances the ideal diode performance with inrush
current limiting and overcurrent protection (see Figure 1).
This allows the boards to be safely inserted and removed
from a live backplane without damaging the connector.
Internal VCC Supply
The LTC4228 can operate with input supplies from 2.9V
to 18V at the IN pins. The power supply to the device is
MD1
Si7336ADP
BULK
SUPPLY
BYPASS
CAPACITOR
Turn-On Sequence
The board power supply at the OUT pin is controlled with
two external N-channel MOSFETs (MD, MH). The MOSFET
MD on the supply side functions as an ideal diode, while
MH on the load side acts as a Hot Swap controlling the
power supplied to the output load. The sense resistor, RS,
IN1
DGATE1
R1
20k
R3
20k
R4
137k
CF2
10nF
INTVCC
LTC4228
GND
OUT1
VSENSE1+
R5
100k
R6
100k
CT1
47nF
CT2
47nF
+
CL1
1600µF
R7
100k
PLUG-IN
CARD 2
EN2
PWRGD2
FAULT2
STATUS2
ON2
CPO2
IN2
DGATE2
SENSE2+ SENSE2– HGATE2
RH2
10Ω
CCP2
0.1µF
VIN2
12V
RHG1
47Ω
CHG1
15nF
STATUS1
FAULT1
PWRGD1
EN1
TMR1
TMR2
ON1
C1
0.1µF
12V
7.6A
SENSE1+ SENSE1– HGATE1
R2
137k
CF1
10nF
PLUG-IN
CARD 1
MH1
Si7336ADP
RH1
10Ω
CCP1
0.1µF
CPO1
An undervoltage lockout circuit prevents all of the MOSFETs
from turning on until the INTVCC voltage exceeds 2.2V. A
0.1µF capacitor is recommended between the INTVCC and
GND pins, close to the device for bypassing. No external
supply should be connected at the INTVCC pin so as not
to affect the LDO’s operation. A small external load of less
than 500µA can be connected at the INTVCC pin.
BULK
SUPPLY
BYPASS
CAPACITOR
MD2
Si7336ADP
RS2
0.004Ω
OUT2
RHG2
47Ω
CHG2
15nF
R8
100k
R9
100k
R10
100k
+
VIN1
12V
RS1
0.004Ω
internally regulated at 5V by a low dropout regulator (LDO)
with an output at the INTVCC pin. An internal diode-OR
circuit selects the highest of the supplies at the IN and OUT
pins to power the device through the LDO. The diode-OR
scheme permits the device’s power to be temporarily kept
alive by the OUT load capacitance when the IN supplies
have collapsed or shut off.
VSENSE2+
MH2
Si7336ADP
CL2
1600µF
12V
7.6A
BACKPLANE
422812 F01
Figure 1. µTCA Application Supplying 12V Power to Two µTCA Slots
422812f
10
LTC4228-1/LTC4228-2
Applications Information
monitors the load current for overcurrent detection. The
HGATE capacitor, CHG, controls the gate slew rate to limit
the inrush current. Resistor RHG with CHG compensates
the current control loop, while RH prevents high frequency
oscillations in the Hot Swap MOSFET.
During a normal power-up, the ideal diode MOSFET turns
on first. As soon as the internally generated supply, INTVCC,
rises above its 2.2V undervoltage lockout threshold, the
internal charge pump is allowed to charge up the CPO
pins. Because the Hot Swap MOSFET is turned off at
power-up, OUT remains low. As a result, the ideal diode
gate drive amplifier senses a large forward drop between
the IN and OUT pins, causing it to pull up DGATE to the
CPO pin voltage.
Before the Hot Swap MOSFET can be turned on, EN must
remain low and ON must remain high for a 100ms debounce
cycle to ensure that any contact bounces during the insertion have ceased. At the end of the debounce cycle, the
internal fault latches are cleared. The Hot Swap MOSFET
is then allowed to turn on by charging up HGATE with a
10µA current source from the charge pump. The voltage
at the HGATE pin rises with a slope equal to 10µA/CHG and
the supply inrush current flowing into the load capacitor,
CL, is limited to:
C
IINRUSH = L • 10µA
CHG
The OUT voltage follows the HGATE voltage when the
Hot Swap MOSFET turns on. If the voltage across the
current sense resistor, RS, becomes too high, the inrush
current will be limited by the internal current limiting
circuitry. Once the MOSFET gate overdrive exceeds 4.2V,
the corresponding PWRGD pin pulls low to indicate that
the power is good. Once OUT reaches the input supply
voltage, HGATE continues to ramp up. An internal 12V
clamp limits the HGATE voltage above OUT.
When both of the MOSFETs are turned on, the gate drive
amplifier controls the gate of the ideal diode MOSFET, to
servo its forward voltage drop across RS, MD and MH to
25mV. If the load current causes more than 25mV of drop,
the MOSFET gate is driven fully on and the voltage drop
across the MOSFET is equal to ILOAD • RDS(ON).
Turn-Off Sequence
The external MOSFETs can be turned off by a variety of
conditions. A normal turn-off for the Hot Swap MOSFET is
initiated by pulling the ON pin below its 1.155V threshold
(80mV ON pin hysteresis), or pulling the EN pin above
its 1.235V threshold. Additionally, an overcurrent fault
of sufficient duration to trip the circuit breaker also turns
off the Hot Swap MOSFET. Normally, the LTC4228 turns
off the MOSFET by pulling the HGATE pin to ground with
a 300µA current sink.
All of the MOSFETs turn off when INTVCC falls below its
undervoltage lockout threshold (2.2V). The DGATE pin is
pulled down with a 100µA current to one diode voltage
below the IN pin, while the HGATE pin is pulled down to
the OUT pin by a 200mA current.
The gate drive amplifier controls the ideal diode MOSFET
to prevent reverse current when the input supply falls
below OUT. If the input supply collapses quickly, the gate
drive amplifier turns off the ideal diode MOSFET with a
fast pull-down circuit as soon as it detects that IN is 20mV
IN
10V/DIV
CPO
10V/DIV
DGATE
10V/DIV
OUT
10V/DIV
20ms/DIV
422812 F02
Figure 2. Ideal Diode Controller Start-Up Waveforms
ON
5V/DIV
HGATE
10V/DIV
OUT
10V/DIV
PWRGD
10V/DIV
50ms/DIV
422812 F03
Figure 3. Hot Swap Controller Power-Up Sequence
422812f
11
LTC4228-1/LTC4228-2
Applications Information
below OUT. If the input supply falls at a more modest rate,
the gate drive amplifier controls the MOSFET to maintain
OUT at 25mV below IN.
Board Presence Detect with EN
If ON is high when the EN pin goes low, indicating a board
presence, the LTC4228 initiates a 100ms timing cycle for
contact debounce. Upon board insertion, any bounces
on the EN pin restart the timing cycle. When the 100ms
timing cycle is done, the internal fault latches are cleared.
If the EN pin remains low at the end of the timing cycle,
HGATE is charged up with a 10µA current source to turn
on the Hot Swap MOSFET.
If the EN pin goes high, indicating a board removal, the
HGATE pin is pulled low with a 300µA current sink after
a 20µs delay, turning off the Hot Swap MOSFET without
clearing any latched faults.
period of 14 timing cycles at the TMR pin. For the latch-off
part (LTC4228-1), the HGATE pin voltage does not restart
at the end of the cool-off period, unless the latched fault
is cleared by pulling the ON pin low or toggling the EN
pin from high to low. For the auto-retry part (LTC4228-2),
the latched fault is cleared automatically at the end of the
cool-off period, and the HGATE pin restarts charging up
to turn on the MOSFET. Figure 4 shows an overcurrent
fault on the 12V output.
OUT
10V/DIV
HGATE
10V/DIV
ILOAD
40A/DIV
100µs/DIV
Overcurrent Fault
The LTC4228 features an adjustable current limit with circuit
breaker function that protects the external MOSFETs against
short circuits or excessive load current. The voltage across
the external sense resistor (RS1, RS2) is monitored by an
electronic circuit breaker (ECB) and active current limit
(ACL) amplifier. The electronic circuit breaker will turn off
the Hot Swap MOSFET with a 300µA current from HGATE
to GND if the voltage across the sense resistor exceeds
∆VSENSE(CB) (50mV) for longer than the fault filter delay
configured at the TMR pin.
Active current limiting begins when the sense voltage
exceeds the ACL threshold ∆VSENSE(ACL) (65mV), which
is 1.3× the ECB threshold ∆VSENSE(CB). The gate of the
Hot Swap MOSFET is brought under control by the ACL
amplifier and the output current is regulated to maintain
the ACL threshold across the sense resistor. At this point,
the fault filter starts the timeout with a 100µA current
charging the TMR pin capacitor. If the TMR pin voltage
exceeds its threshold (1.235V), the external MOSFET
turns off with HGATE pulled to ground by 300µA, and its
associated FAULT pulls low.
After the Hot Swap MOSFET turns off, the TMR pin capacitor is discharged with a 2µA pull-down current until
its threshold reaches 0.2V. This is followed by a cool-off
422812 F04
Figure 4. Overcurrent Fault on 12V Output
In the event of a severe short-circuit fault on the 12V output
as shown in Figure 5, the output current can surge to tens
of amperes. The LTC4228 responds within 1µs to bring
the current under control by pulling the HGATE to OUT
voltage down to zero volts. Almost immediately, the gate
of the Hot Swap MOSFET recovers rapidly due to the RHG
and CHG network, and current is actively limited until the
electronic circuit breaker times out. Due to parasitic supply lead inductance, an input supply without any bypass
capacitor may collapse during the high current surge
and then spike upwards when the current is interrupted.
Figure 11 shows the input supply transient suppressors
consisting of Z1, RSNUB1, CSNUB1 and Z2, RSNUB2, CSNUB2
for the two supplies if there is no input capacitance.
OUT
10V/DIV
HGATE
10V/DIV
ILOAD
40A/DIV
2µs/DIV
422812 F05
Figure 5. Severe Short-Circuit on 12V Output
422812f
12
LTC4228-1/LTC4228-2
Applications Information
Active Current Loop Stability
The active current loop on the HGATE pin is compensated
by the parasitic gate capacitance of the external N-channel
MOSFET. No further compensation components are normally required. In the case when a MOSFET with CISS ≤
2nF is chosen, an RHG and CHG compensation network
connected at the HGATE pin may be required. The value
of CHG is selected based on the inrush current allowed for
the output load capacitance. The resistor, RHG, connected
in series with CHG accelerates the MOSFET gate recovery
for active current limiting after a fast gate pull-down due
to an output short. The value of CHG should be ≤100nF
and RHG should be between 10Ω and 100Ω for optimum
performance.
TMR Pin Functions
An external capacitor, CT , connected from the TMR pin to
GND serves as fault filtering when the supply output is in
active current limit. When the voltage across the sense
resistor exceeds the circuit breaker trip threshold (50mV),
TMR pulls up with 100µA. Otherwise, it pulls down with 2µA.
The fault filter times out when the 1.235V TMR threshold
is exceeded, causing the corresponding FAULT pin to pull
low. The fault filter delay or circuit breaker time delay is:
tCB = CT • 12[ms/µF]
After the circuit breaker timeout, the TMR pin capacitor
pulls down with 2µA from the 1.235V TMR threshold
until it reaches 0.2V. Then, it completes 14 cooling cycles
consisting of the TMR pin capacitor charging to 1.235V
with a 100µA current and discharging to 0.2V with a 2µA
current. At that point, the HGATE pin voltage is allowed to
start up if the fault has been cleared as described in the
Resetting Faults section. When the latched fault is cleared
during the cool-off period, the corresponding FAULT pin
pulls high. The total cool-off time for the MOSFET after
an overcurrent fault is:
(LTC4228‑1). For the auto-retry part (LTC4228-2), the
latched fault is cleared automatically following the cool-off
period and the HGATE pin voltage is allowed to restart.
Resetting Faults (LTC4228-1)
For the latch-off part (LTC4228-1), an overcurrent fault
is latched after tripping the circuit breaker, and the corresponding FAULT pin is asserted low. If the LTC4228
controls the MOSFETs on two supplies, only the Hot Swap
MOSFET on the supply at fault is turned off and the other
is not affected.
To reset a latched fault and restart the output, pull the
corresponding ON pin below 0.6V for more than 100µs
and then high above 1.235V. The fault latches reset and
the FAULT pin deasserts on the falling edge of the ON pin.
When ON goes high again, a 100ms debounce cycle is
initiated before the HGATE pin voltage restarts. Toggling
the EN pin high and then low again also resets a fault,
but the FAULT pin pulls high at the end of the 100ms
debounce cycle before the HGATE pin voltage starts up.
Bringing all the supplies below the INTVCC undervoltage
lockout threshold (2.2V) shuts off all the MOSFETs and
resets all the fault latches. A 100ms debounce cycle is
initiated before a normal start-up when any of the supplies
is restored above the INTVCC UVLO threshold.
Auto-Retry After a Fault (LTC4228-2)
If the latched fault is not cleared after the cool-off period,
the cooling cycles continue until the fault is cleared.
For the auto-retry part (LTC4228-2), the latched fault is reset
automatically after a cool-off timing cycle as described in
the TMR Pin Functions section. At the end of the cool-off
period, the fault latch is cleared and FAULT pulls high. The
HGATE pin voltage is allowed to start up and turn on the
Hot Swap MOSFET. If the output short persists, the supply
powers up into a short with active current limiting until
the circuit breaker times out and FAULT again pulls low. A
new cool-off cycle begins with TMR ramping down with
a 2µA current. The whole process repeats itself until the
output short is removed. Since tCB and tCOOL are a function of TMR capacitance, CT, the auto-retry duty cycle is
equal to 0.1%, irrespective of CT.
After the cool-off period, the HGATE pin is only allowed to
pull up if the fault has been cleared for the latch-off part
Figure 6 shows an auto-retry sequence after an overcurrent fault.
tCOOL = CT • 11[s/µF]
422812f
13
LTC4228-1/LTC4228-2
Applications Information
input supplies are restored and INTVCC exceeds its UVLO
threshold.
TMR
1V/DIV
There is a 10µs glitch filter on the ON pin to reject supply
glitches. By placing a filter capacitor, CF , with the resistive divider at the ON pin, the glitch filter delay is further
extended by the RC time constant to prevent any false fault.
ILOAD
20A/DIV
HGATE
5V/DIV
FAULT
10V/DIV
Power Good Monitor
50ms/DIV
422812 F06
Figure 6. Auto-Retry Sequence After a Fault
Supply Undervoltage Monitor
The ON pin functions as a turn-on control and an input supply monitor. A resistive divider connected between the input
supply (IN1 or SENSE1+, IN2 or SENSE2+) and GND at the respective ON pin monitors the supply undervoltage condition.
The undervoltage threshold is set by proper selection of the
resistors and is given by:

R TOP 
VIN(UVTH) =  1+
• VON(TH)
 RBOTTOM 
Internal circuitry monitors the MOSFET gate overdrive
between the HGATE and OUT pins. The power good status
for each supply is reported via its respective open-drain
output, PWRGD1 or PWRGD2. They are normally pulled
high by an external pull-up resistor or the internal 10µA
pull-up. The power good output asserts low when the gate
overdrive exceeds 4.2V during the HGATE start-up. Once
asserted low, the power good status is latched and can only
be cleared by pulling the ON pin low, toggling the EN pin
from low to high, or INTVCC entering undervoltage lockout.
The power good output continues to pull low while HGATE
is regulating in active current limit, but pulls high when
the circuit breaker times out and pulls the HGATE pin low.
where VON(TH) is the ON rising threshold (1.235V).
CPO and DGATE Start-Up
An undervoltage fault occurs if the input supply falls below
its undervoltage threshold for longer than 20µs. The FAULT
pin will not be pulled low. If the ON pin voltage falls below
1.155V but remains above 0.6V, the Hot Swap MOSFET is
turned off by a 300µA pull-down from HGATE to ground.
The Hot Swap MOSFET turns back on instantly without
the 100ms debounce cycle when the input supply rises
above its undervoltage threshold.
The CPO and DGATE pin voltages are initially pulled up
to a diode below the IN pin when first powered up. CPO
starts ramping up 7µs after INTVCC clears its undervoltage lockout level. Another 40µs later, DGATE also starts
ramping up with CPO. The CPO ramp rate is determined
by the CPO pull-up current into the combined CPO and
DGATE pin capacitances. An internal clamp limits the CPO
pin voltage to 12V above the IN pin, while the final DGATE
pin voltage is determined by the gate drive amplifier. An
internal 12V clamp limits the DGATE pin voltage above IN.
However, if the ON pin voltage drops below 0.6V, it turns
off the Hot Swap MOSFET and clears the associated fault
latches. The Hot Swap MOSFET turns back on only after a
100ms debounce cycle when the input supply is restored
above its undervoltage threshold. An undervoltage fault on
one supply does not affect the operation of the other supply. The ideal diode function controlled by the ideal diode
MOSFET is unaffected by undervoltage fault conditions.
If both IN supplies fall until the internally generated supply, INTVCC, drops below its 2.2V UVLO threshold, all the
MOSFETs are turned off and the fault latches are cleared.
Operation resumes from a fresh start-up cycle when the
MOSFET Selection
The LTC4228 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFETs are
on-resistance, RDS(ON), the maximum drain-source voltage, BVDSS, and the threshold voltage.
The gate drive for the ideal diode MOSFET and Hot Swap
MOSFET is guaranteed to be greater than 5V and 4.8V
respectively when the supply voltages at IN1 and IN2 are
between 2.9V and 7V. When the supply voltages at IN1 and
422812f
14
LTC4228-1/LTC4228-2
Applications Information
IN2 are greater than 7V, the gate drive is guaranteed to be
greater than 10V. The gate drive is limited to not more than
14V. This allows the use of logic-level threshold N-channel
MOSFETs and standard N-channel MOSFETs above 7V. An
external Zener diode can be used to clamp the potential
from the MOSFET’s gate to source if the rated breakdown
voltage is less than 14V.
The maximum allowable drain-source voltage, BVDSS,
must be higher than the supply voltages as the full supply voltage can appear across the MOSFET. If an input or
output is connected to ground, the full supply voltage will
appear across the MOSFET. The RDS(ON) should be small
enough to conduct the maximum load current, and also
stay within the MOSFET ’s power rating.
CPO Capacitor Selection
The recommended value of the capacitor, CCP , between the
CPO and IN pins is approximately 10× the input capacitance, CISS, of the ideal diode MOSFET. A larger capacitor
takes a correspondingly longer time to charge up by the
internal charge pump. A smaller capacitor suffers more
voltage drop during a fast gate turn-on event as it shares
charge with the MOSFET gate capacitance.
Supply Transient Protection
When the capacitances at the input and output are very
small, rapid changes in current during input or output shortcircuit events can cause transients that exceed the 24V
absolute maximum ratings of the IN and OUT pins. To minimize such spikes, use wider traces or heavier trace plating
to reduce the power trace inductance. Also, bypass locally
with a 10µF electrolytic and 0.1µF ceramic, or alternatively
clamp the input with a transient voltage suppressor (Z1, Z2).
A 10Ω, 0.1µF snubber damps the response and eliminates
ringing (See Figure 11).
Design Example
As a design example for selecting components, consider
a 12V system with a 7.6A maximum load current for the
two supplies (see Figure 1).
First, select the appropriate value of the current sense
resistors (RS1 and RS2) for the 12V supply. Calculate
the sense resistor value based on the maximum load
current ILOAD(MAX), the minimum circuit breaker trip current ITRIP(MIN) and the lower limit for the circuit breaker
threshold ΔVSENSE(CB)(MIN). A load current margin given
as a ratio of ITRIP(MIN)/ILOAD(MAX) is provided for allowing
backfeeding current to flow through the sense resistor
momentarily, without false tripping the circuit breaker on
the higher supply before the reverse turn-off is activated on
the lower supply. Assuming a load current margin of 1.5×,
ITRIP(MIN) = 1.5 • ILOAD(MAX) = 1.5 • 7.6A = 11.4A
RS =
∆VSENSE(CB)(MIN)
ITRIP(MIN)
=
47.5mV
= 4.16mΩ
11.4A
Choose a 4mΩ sense resistor with a 1% tolerance.
Next, calculate the RDS(ON) of the MOSFET to achieve
the desired forward drop at maximum load. Assuming
a forward drop, ∆VFWD of 60mV across the two external
MOSFETs:
RDS(ON,TOTAL) ≤
∆VFWD
ILOAD(MAX)
=
60mV
= 7.9mΩ
7.6A
The Si7336ADP offers a good choice with a maximum
RDS(ON) of 3mΩ at VGS = 10V, thereby giving a total of
6mΩ for two MOSFETs in the supply path. The input capacitance, CISS, of the Si7336ADP is about 5600pF. Slightly
exceeding the 10× recommendation, a 0.1µF capacitor is
selected for CCP1 and CCP2 at the CPO pins.
Next, verify that the thermal ratings of the selected MOSFET, Si7336ADP, are not exceeded during power-up or an
output short.
Assuming the MOSFET dissipates power due to inrush
current charging the load capacitor, CL, at power-up, the
energy dissipated in the MOSFET is the same as the energy
stored in the load capacitor, and is given by:
1
ECL = • CL • VIN2
2
For CL = 1600µF, the time it takes to charge up CL is
calculated as:
tCHARGE =
CL • VIN 1600µF • 12V
=
= 19ms
IINRUSH
1A
422812f
15
LTC4228-1/LTC4228-2
Applications Information
The inrush current is set to 1A by adding capacitance,
CHG, at the gate of the Hot Swap MOSFET.
CHG =
CL •IHGATE(UP)
IINRUSH
=
1600µF • 10µA
= 16nF
1A
Choose a practical value of 15nF for CHG.
The average power dissipated in the MOSFET is calculated
as:
PAVG =
ECL
1 1600µF • (12V )
= •
= 6W
2
19ms
2
tCHARGE
The MOSFET selected must be able to tolerate 6W for
19ms during power-up. The SOA curves of the Si7336ADP
provide for 1.5A at 30V (45W) for 100ms. This is sufficient to satisfy the requirement. The increase in junction
temperature due to the power dissipated in the MOSFET
is ∆T = PAVG • ZthJC where ZthJC is the junction-to-case
thermal impedance. Under this condition, the Si7336ADP
data sheet indicates that the junction temperature will
increase by 4.8°C using ZthJC = 0.8°C/W (single pulse).
The duration and magnitude of the power pulse during an
output short is a function of the TMR capacitance, CT , and
the LTC4228’s active current limit. The short-circuit duration is given as CT • 12[ms/µF] = 0.56ms for CT = 0.047µF.
The maximum short-circuit current is calculated using the
maximum active current limit threshold ∆VSENSE(ACL)(MAX)
and minimum RS value.
ISHORT(MAX) =
∆VSENSE(ACL)(MAX)
RS(MIN)
=
75mV
= 18.9A
3.96mΩ
So, the maximum power dissipated in the MOSFET is
18.9A • 12V = 227W for 0.56ms. The Si7336ADP data
sheet indicates that the worst-case increase in junction
temperature during this short-circuit condition is 22.7°C
using ZthJC = 0.1°C/W (single pulse). Choosing CT =
0.047µF will not cause the maximum junction temperature
of the MOSFET to be exceeded. The SOA curves of the
Si7336ADP provide for 15A at 30V (450W) for 1ms. This
also satisfies the requirement.
Next, select the resistive divider at the ON1 and ON2 pins
to provide an undervoltage threshold of 9.6V for the 12V
supply. First, choose the bottom resistors, R1 and R3, to be
20k. Then, calculate the top resistor value for R2 and R4:
 VIN(UVTH) 
R TOP = 
– 1 •RBOTTOM
 VON(TH)

 9.6V

R TOP = 
– 1 • 20k = 135k
 1.235V 
Choose the nearest 1% resistor value of 137k for R2 and
R4. In addition, there is a 0.1µF bypass (C1) at the INTVCC
pin and a 10nF filter capacitor (CF) at the ON pin to prevent
the supply glitches from turning off the Hot Swap MOSFET.
PCB Layout Considerations
For proper operation of the LTC4228’s circuit breaker, Kelvin
connection to the sense resistor is strongly recommended.
The PCB layout should be balanced and symmetrical to
minimize wiring errors. In addition, the PCB layout for the
sense resistor and the power MOSFET should include good
thermal management techniques for optimal device power
dissipation. A recommended PCB layout is illustrated in
Figure 7.
Connect the IN and OUT pin traces as close as possible to
the MOSFETs’ terminals. Keep the traces to the MOSFETs
wide and short to minimize resistive losses. The PCB traces
associated with the power path through the MOSFETs
should have low resistance. The suggested trace width for
1oz copper foil is 0.03" for each ampere of DC current to
keep PCB trace resistance, voltage drop and temperature
rise to a minimum. Note that the sheet resistance of 1oz
copper foil is approximately 0.5mΩ/square, and voltage
drops due to trace resistance add up quickly in high current applications.
It is also important to place the bypass capacitor, C1, for
the INTVCC pin, as close as possible between INTVCC and
GND. Also place CCP1 near the CPO1 and IN1 pins, and
CCP2 near the CPO2 and IN2 pins. The transient voltage
suppressors, Z1 and Z2, when used, should be mounted
close to the LTC4228 using short lead lengths.
422812f
16
LTC4228-1/LTC4228-2
Applications Information
µTCA Application
In the µTCA application shown in Figure 1, the output
load capacitor is required to hold up the supply to the
downstream load for a short duration when all of the input supplies are not available. This happens when the IN
supply collapses to ground momentarily while the other
redundant supply to the diode-ORed output is not turned
on. As soon as the reverse voltage between IN and OUT
pins is detected, DGATE is pulled down quickly to turn off
the ideal diode MOSFET. By placing the sense resistor in
between the ideal diode and Hot Swap MOSFET, it allows
the SENSE+ pin voltage to be held up by the output load
capacitance temporarily when the input supply collapses.
This prevents the SENSE+ voltage from entering into undervoltage lockout and turning off the Hot Swap MOSFET.
As the IN supply recovers, it charges up the depleted load
CURRENT FLOW
TO LOAD
IN1
W
capacitance and provides power to the downstream load
instantly if the Hot Swap MOSFET is not turned off.
Power Prioritizer
Figure 8 shows an application where either of two supplies
is passed to the output on the basis of priority, rather than
simply allowing the highest voltage to prevail. The 5V primary supply (INPUT 1) is passed to the output whenever
it is available; power is drawn from the 12V backup supply
(INPUT 2) only when the primary supply is unavailable. As
long as INPUT 1 is above the 4.3V UV threshold set by the
R1-R2 divider at the ON1 pin, MH1 is turned on connecting
INPUT 1 to the output. When MH1 is on, PWRGD1 goes
low, which in turn pulls ON2 low and disables the IN2
path by turning MH2 off. If the primary supply fails and
INPUT 1 drops below 4.3V, ON1 turns off MH1 and PWRGD1
S
D
S
D
S
G
CURRENT FLOW
TO LOAD
MH1
PowerPAK SO-8
MD1
PowerPAK SO-8
D
G
D
S
D
D
S
D
D
S
RS1
W
TRACK WIDTH W:
0.03" PER AMPERE
ON 1oz Cu FOIL
RH1
•
•
•
•
CCP1
28 27 26 25 24 23
Z1
•••
C1
VIAS TO GND PLANE
•
1
22
2
21
3
20
4
Z2
17
7
16
8
15
W
CURRENT FLOW
TO LOAD
10 11 12 13 14
•
•
18
6
9
•
19
LTC4228UFD
5
•••
IN2
OUT1
CCP2
RH2
•
S
D
D
G
S
D
D
S
S
D
D
S
G
D
D
S
MD2
PowerPAK SO-8
RS2
MH2
PowerPAK SO-8
W
OUT2
CURRENT FLOW
TO LOAD 422812 F07
Figure 7. Recommended PCB Layout for Power MOSFETs and Sense Resistors
422812f
17
LTC4228-1/LTC4228-2
Applications Information
goes high, allowing ON2 to turn on MH2 and connect the
INPUT 2 to the output. Diode D1 ensures that ON2 remains
above 0.6V while in the off state so that when ON2 goes
high, MH2 is turned on immediately without invoking the
100ms turn-on delay. When INPUT 1 returns to a viable
voltage, MH1 turns on and MH2 turns off. The ideal diode
MOSFETs MD1 and MD2 prevent backfeeding of one input
to the other under any condition.
Additional Applications
In most applications, the two external MOSFETs are configured with the MOSFET on the supply side as the ideal
diode and the MOSFET on the load side as the Hot Swap
control. But for some applications, the arrangement of the
MOSFETs for the ideal diode and the Hot Swap control may
be reversed as shown in Figure 9. The Hot Swap MOSFET
5V
PRIMARY
SUPPLY
MD1
SiR466DP
INPUT 1
CF1
0.1µF
R4
41.2k
C1
0.1µF
MH1
SiR466DP
RH1
10Ω
CCP1
0.1µF
CPO1
R1
20k
RS1
0.006Ω
+
Z1
SMAJ13A
R2
49.9k
is placed on the supply side and the ideal diode MOSFET
on the load side with the source terminals connected together. If this configuration is operated with 12V supplies,
the gate-to-source breakdown voltage of the MOSFETs
can be exceeded when the input or output is connected
to ground as the LTC4228’s internal 12V clamps only limit
the DGATE-to-IN and HGATE-to-OUT pin voltages. Choose
a MOSFET whose gate-to-source breakdown voltage is
rated for 25V or more as 24V voltage can appear across
the GATE and SOURCE pins of the MOSFET during an
input or output short. As shown in Figure 9, if a MOSFET
with a lower rated gate-to-source breakdown voltage is
chosen, an external Zener diode clamp is required between
the GATE and SOURCE pins of the MOSFET to prevent it
from breaking down.
IN1
DGATE1 SENSE1+ SENSE1– HGATE1
STATUS1
FAULT1
ON1
PWRGD1
INTVCC
TMR1
TMR2
LTC4228
GND
CT2
0.1µF
CT1
0.1µF
PWRGD2
FAULT2
STATUS2
EN2
CPO2
IN2
DGATE2 SENSE2+ SENSE2– HGATE2
OUT2
CCP2
0.1µF
INPUT 2
+
CL
470µF
OUT1
EN1
ON2
12V
BACKUP
SUPPLY
RHG1
47Ω
CHG1
33nF
VOUT
5A
Z2
SMAJ13A
R3
3.92k
D1
LS4148
MD2
SiR466DP
RS2
0.006Ω
MH2
SiR466DP
422812 F08
Figure 8. 2-Channel Power Prioritizer
422812f
18
LTC4228-1/LTC4228-2
Applications Information
RS1
0.006Ω
RH1
10Ω
CCP1
0.1µF
CPO1
RHG1
47Ω
CHG1
15nF
IN1 SENSE1+ SENSE1– HGATE1
+
DGATE1
PWREN2
INTVCC
LTC4228
GND
PLUG-IN
CARD 2
CT1
47nF
CT2
47nF
EN2
PWRGD2
FAULT2
STATUS2
ON2
CPO2
CL1
1000µF
OUT1
STATUS1
FAULT1
PWRGD1
EN1
TMR1
TMR2
ON1
C1
0.1µF
12V
5A
ZH1 ZD1
BULK
SUPPLY
BYPASS
CAPACITOR
PWREN1
PLUG-IN
CARD 1
MD1
SiR466DP
IN2 SENSE2+ SENSE2– HGATE2
CCP2
0.1µF
RH2
10Ω
DGATE2
OUT2
RHG2
47Ω
CHG2
15nF
+
VIN1
12V
MH1
SiR466DP
CL2
1000µF
ZH2 ZD2
VIN2
12V
RS2
0.006Ω
BULK
SUPPLY
BYPASS
CAPACITOR
MD2
SiR466DP
MH2
SiR466DP
422812 F09
12V
5A
BACKPLANE
ZH1, ZD1, ZH2, ZD2: CMHZ4706
Figure 9. An Application with the Hot Swap MOSFET on the Supply Side and the Ideal Diode MOSFET on the Load Side
MD1
SiR158DP
VIN1
12V
RS1
0.003Ω
+
Z1
SMAJ13A
RH1
10Ω
CCP1
0.1µF
CPO1
R2
137k
R1
20k
CF1
0.1µF
R4
28k
CF2
0.1µF
IN1
RHG1
47Ω
CHG1
15nF
DGATE1 SENSE1+ SENSE1– HGATE1
OUT1
EN1
ON1
C1
0.1µF
R3
20k
MH1
SiR158DP
12V
10A
CL1
1000µF
VSENSE1+
R5
2.7k
R6
2.7k
R7
2.7k
D1
D2
D3
STATUS1
FAULT1
PWRGD1
INTVCC
TMR1
TMR2
LTC4228
GND
VSENSE2+
CT1
22nF
CT2
0.1µF
R8
2.7k
R9
2.7k
R10
2.7k
D1
D2
D3
PWRGD2
FAULT2
STATUS2
ON2
EN2
IN2 DGATE2
CPO2
SENSE2+ SENSE2– HGATE2
D1, D3: GREEN LED LN1351C
D2: RED LED LN1261CAL
OUT2
CCP2
0.1µF
VIN2
3.3V
BACKPLANE
CONNECTOR
CARD
CONNECTOR
Z2
SMAJ13A
MD2
SiR468DP
RS2
0.015Ω
MH2
SiR468DP
+
CL2
100µF
3.3V
2A
422812 F10
Figure 10. Plug-In Card Supply Holdup Using Ideal Diode at 12V and 3.3V Input Supplies
422812f
19
LTC4228-1/LTC4228-2
Applications Information
RS1
0.006Ω
MD1
SiR466DP
VIN1
12V
+
RSNUB1
10Ω
Z1
SMAJ13A
CCP1
0.1µF
CSNUB1
0.1µF
CPO1
R2
137k
C1
0.1µF
R3
20k
RH1
10Ω
IN1
DGATE1
CF2
0.1µF
SENSE1+ SENSE1– HGATE1
CARD
CONNECTOR
INTVCC
TMR1
TMR2
LTC4228
GND
R6
100k
R7
100k
VSENSE2+
CT1
47nF
CT2
47nF
PWRGD2
FAULT2
STATUS2
CPO2
Z2
SMAJ13A
R5
100k
STATUS1
FAULT1
PWRGD1
DGATE2 SENSE2+ SENSE2– HGATE2
IN2
MD2
SiR466DP
RSNUB2
10Ω
RS2
0.006Ω
R8
100k
R9
100k
R10
100k
OUT2
RH2
10Ω
CCP2
0.1µF
BACKPLANE
CONNECTOR
12V
5A
CL
1000µF
VSENSE1+
OUT1
ON2
EN2
R4
137k
VIN2
12V
RHG1
47Ω
CHG1
15nF
EN1
ON1
CF1
0.1µF
R1
20k
MH1
SiR466DP
RHG2
47Ω
CHG2
15nF
422812 F11
MH2
SiR466DP
CSNUB2
0.1µF
Figure 11. Card Resident Application with the Output Diode-ORed
MD1
SiR466DP
+
9V
BATTERY
SUPPLY
IN1
DGATE1
CL
1000µF
OUT1
CF2
10nF
STATUS1
FAULT1
PWRGD1
INTVCC
TMR1
TMR2
LTC4228
GND
EN2
IN2
DGATE2
SENSE2+ SENSE2– HGATE2
RH2
10Ω
CCP2
0.1µF
Z2
SMAJ17A
CT2
47nF
CT1
47nF
PWRGD2
FAULT2
STATUS2
ON2
CPO2
15V
POWER
ADAPTER
SUPPLY
RHG1
47Ω
CHG1
15nF
SENSE1+ SENSE1– HGATE1
ON1
CF1
10nF
C1
0.1µF
R4
187k
RH1
10Ω
VOUT
5A
EN1
R2
88.7k
R3
20k
MH1
SiR466DP
+
CCP1
0.1µF
Z1
SMAJ17A
CPO1
R1
20k
RS1
0.006Ω
MD2
SiR466DP
RS2
0.006Ω
OUT2
RHG2
47Ω
CHG2
15nF
MH2
SiR466DP
422812 F12
Figure 12. Battery Application with the Output Diode-ORed
422812f
20
LTC4228-1/LTC4228-2
Applications Information
POWER MODULE #1
BACKPLANE
12V
IN1
DGATE1 SENSE1+ SENSE1– HGATE1 OUT1
IN2
DGATE2 SENSE2+ SENSE2– HGATE2
AMC #1
LTC4228*
OUT2
12V
AMC #2
•
• 8x
•
•
(12 AMCs, 2 CUs, 2 MCHs) • 16x
•
12V
MCH #1
IN1
DGATE1 SENSE1+ SENSE1– HGATE1 OUT1
IN2
DGATE2 SENSE2+ SENSE2– HGATE2
LTC4228*
OUT2
12V
MCH #2
POWER MODULE #2
12V
IN1
DGATE1 SENSE1+ SENSE1– HGATE1 OUT1
IN2
DGATE2 SENSE2+ SENSE2– HGATE2 OUT2
LTC4228*
12V
•
• 8x
•
12V
IN1
DGATE1 SENSE1+ SENSE1– HGATE1 OUT1
IN2
DGATE2 SENSE2+ SENSE2– HGATE2 OUT2
LTC4228*
12V
422812 F13
*ADDITIONAL DETAILS OMITTED FOR CLARITY
Figure 13. 12V Distribution in µTCA Redundant Power Subsystem
422812f
21
LTC4228-1/LTC4228-2
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.50 REF
2.65 ± 0.05
3.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ± 0.10
(2 SIDES)
0.75 ± 0.05
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
27
28
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ± 0.10
(2 SIDES)
3.50 REF
3.65 ± 0.10
2.65 ± 0.10
(UFD28) QFN 0506 REV B
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
422812f
22
LTC4228-1/LTC4228-2
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.386 – .393*
(9.804 – 9.982)
.045 ±.005
28 27 26 25 24 23 22 21 20 19 18 17 1615
.254 MIN
.033
(0.838)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ±.0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
1
RECOMMENDED SOLDER PAD LAYOUT
.015 ±.004
× 45°
(0.38 ±0.10)
.0075 – .0098
(0.19 – 0.25)
2 3
4
5 6
7
8
9 10 11 12 13 14
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN28 REV B 0212
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
422812f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC4228-1/LTC4228-2
Typical Application
Plug-In Card Diode-OR Application with Hot Swap First Followed by Ideal Diode Control
RS1
0.006Ω
VIN1
5V
Z1
SMAJ7A
+
CCP1
0.1µF
CPO1
PWREN
MD1
MH1
Si7790DP Si7790DP
IN1
SENSE1+ SENSE1– HGATE1
DGATE1
EN1
ON1
R1
10k
C1
0.1µF
CL
100µF
5V
5A
OUT1
STATUS1
FAULT1
PWRGD1
INTVCC
TMR1
TMR2
LTC4228
GND
CT2
0.1µF
CT1
0.1µF
PWRGD2
FAULT2
STATUS2
ON2
EN2
CPO2
IN2
SENSE2+ SENSE2– HGATE2
DGATE2
OUT2
CCP2
0.1µF
VIN2
5V
BACKPLANE
CONNECTOR
Z2
SMAJ7A
CARD
CONNECTOR
RS2
0.006Ω
MD2
MH2
Si7790DP Si7790DP
422812 TA02
Related Parts
PART NUMBER
LTC1421
LTC1645
LTC1647-1/LTC1647-2/
LTC1647-3
LTC4210
LTC4211
LTC4215
LTC4216
LTC4218
LTC4221
LTC4222
LTC4223
LTC4224
LTC4225
LTC4227
LTC4352
LTC4354
LTC4355
LTC4357
LTC4358
DESCRIPTION
Dual Channel, Hot Swap Controller
Dual Channel, Hot Swap Controller
Dual Channel, Hot Swap Controller
COMMENTS
Operates from 3V to 12V, Supports –12V, SSOP-24
Operates from 3V to 12V, Power Sequencing, SO-8 or SO-14
Operates from 2.7V to 16.5V, SO-8 or SSOP-16
Single Channel, Hot Swap Controller
Single Channel, Hot Swap Controller
Single Channel, Hot Swap Controller
Single Channel, Hot Swap Controller
Single Channel, Hot Swap Controller
Dual Channel, Hot Swap Controller
Dual Channel, Hot Swap Controller
Dual Supply Hot Swap Controller
Dual Channel, Hot Swap Controller
Dual Ideal Diode and Hot Swap Controller
Dual Ideal Diode and Single Hot Swap
Controller
Low Voltage Ideal Diode Controller
Negative Voltage Diode-OR Controller and
Monitor
Positive High Voltage Ideal Diode-OR and
Monitor
Positive High Voltage Ideal Diode
Controller
5A Ideal Diode
Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6
Operates from 2.7V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10
Operates from 2.9V to 15V, I2C Compatible Monitoring, SSOP-16 or QFN-24
Operates from 0V to 6V, Active Current Limiting, MSOP-10 or DFN-12
Operates from 2.9V to 26.5V, Active Current Limiting, SSOP-16 or DFN-16
Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16
Operates from 2.9V to 29V, I2C Compatible Monitoring, SSOP-36 or QFN-32
Controls 12V and 3.3V, Active Current Limiting, SSOP-16 or DFN-16
Operates from 2.7V to 6V, Active Current Limiting, MSOP-10 or DFN-10
Operates from 2.9V to 18V, Controls Four N-Channels, GN-24 or QFN-24
Operates from 2.9V to 18V, Controls Three N-Channels, GN-16 or QFN-20
Operates from 0V to 18V, Controls N-Channel, MSOP-12 or DFN-12
80V Operation, Controls Two N-Channels, SO-8 or DFN-8
Operates from 9V to 80V, Controls Two N-Channels, S0-16 or DFN-14
Operates from 9V to 80V, Controls N-Channel, MSOP-8 or DFN-6
Operates from 9V to 26.5V, On-Chip N-Channel, TSSOP-16 or DFN-14
422812f
24 Linear Technology Corporation
LT 0812 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
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 LINEAR TECHNOLOGY CORPORATION 2012