Product Folder Sample & Buy Support & Community Tools & Software Technical Documents NE5534, NE5534A, SA5534, SA5534A SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 NE5534x, SA5534x Low-Noise Operational Amplifiers 1 Features 3 Description • The NE5534, NE5534A, SA5534, and SA5534A devices are high-performance operational amplifiers combining excellent dc and ac characteristics. Some of the features include very low noise, high outputdrive capability, high unity-gain and maximum-outputswing bandwidths, low distortion, and high slew rate. 1 • • • • • • • • • Equivalent Input Noise Voltage 3.5 nV/√Hz Typ Unity-Gain Bandwidth 10 MHz Typ Common-Mode Rejection Ratio 100 dB Typ High DC Voltage Gain 100 V/mV Typ Peak-to-Peak Output Voltage Swing 32 V Typ With VCC± = ±18 V and RL = 600 Ω High Slew Rate 13 V/μs Typ Wide Supply-Voltage Range ±3 V to ±20 V Low Harmonic Distortion Offset Nulling Capability External Compensation Capability These operational amplifiers are compensated internally for a gain equal to or greater than three. Optimization of the frequency response for various applications can be obtained by use of an external compensation capacitor between COMP and COMP/BAL. The devices feature input-protection diodes, output short-circuit protection, and offsetvoltage nulling capability with use of the BALANCE and COMP/BAL pins (see Figure 10). For the NE5534A and SA5534A devices, a maximum limit is specified for the equivalent input noise voltage. 2 Applications • • • • Audio Preamplifiers Servo Error Amplifiers Medical Equipment Telephone Channel Amplifiers Device Information PART NUMBER NE5534x SA5534x PACKAGE (PIN) BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.91 mm SOIC (8) 4.90 mm × 3.91 mm SO (8) 6.20 mm × 5.30 mm 4 Simplified Schematic COMP COMP/BAL IN− − OUT IN+ + BALANCE 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. NE5534, NE5534A, SA5534, SA5534A SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 4 4 4 4 5 6 7 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Operating Characteristics.......................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 8.1 Overview ................................................................... 9 8.2 Functional Block Diagram ......................................... 9 8.3 Feature Description................................................. 10 8.4 Device Functional Modes........................................ 10 9 Application and Implementation ........................ 11 9.1 General Application................................................. 11 9.2 Typical Application ................................................. 12 10 Power Supply Recommendations ..................... 14 11 Layout................................................................... 15 11.1 Layout Guidelines ................................................. 15 11.2 Layout Example .................................................... 15 12 Device and Documentation Support ................. 16 12.1 12.2 12.3 12.4 Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 16 16 16 16 13 Mechanical, Packaging, and Orderable Information ........................................................... 16 5 Revision History Changes from Revision C (September 2004) to Revision D Page • Added Applications,Device Information table, Handling Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1 • Deleted Ordering Information table. ....................................................................................................................................... 1 2 Submit Documentation Feedback Copyright © 1979–2014, Texas Instruments Incorporated Product Folder Links: NE5534 NE5534A SA5534 SA5534A NE5534, NE5534A, SA5534, SA5534A www.ti.com SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 6 Pin Configuration and Functions NE5534, SA5534 . . . D (SOIC), P (PDIP), OR PS (SOP) PACKAGE NE5534A, SA5534A . . . D (SOIC) OR P (PDIP) PACKAGE (TOP VIEW) BALANCE IN− IN+ VCC− 1 8 2 7 3 6 4 5 COMP/BAL VCC+ OUT COMP Pin Functions PIN NAME NO. BALANCE 1 COMP/BAL COMP TYPE DESCRIPTION I External frequency compensation 8 I External offset voltage adjustment/External frequency compensation 5 O External offset voltage adjustment IN+ 3 I Noninverting input IN- 2 I Inverting Input OUT 6 O Output VCC+ 7 — Positive Supply VCC- 4 — Negative Supply Copyright © 1979–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: NE5534 NE5534A SA5534 SA5534A 3 NE5534, NE5534A, SA5534, SA5534A SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN VCC+ Supply voltage (2) VCC TYP 0 VCC– (1) (2) (3) (4) (5) UNIT 22 V V –22 0 Input voltage, either input (2) (3) VCC– VCC+ V Input current (4) –10 10 mA 150 °C Duration of output short circuit (5) TJ MAX Unlimited Operating virtual-junction temperature Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–. The magnitude of the input voltage must never exceed the magnitude of the supply voltage. Excessive current will flow if a differential input voltage in excess of approximately 0.6 V is applied between the inputs, unless some limiting resistance is used. The output may be shorted to ground or either power supply. Temperature and/or supply voltages must be limited to ensure the maximum dissipation rating is not exceeded. 7.2 Handling Ratings Tstg MIN MAX UNIT –65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins 0 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins 0 200 Storage temperature range V(ESD) Electrostatic discharge V 7.3 Recommended Operating Conditions MIN VCC Supply voltage TA Operating free-air temperature MAX UNIT VCC+ 5 15 V VCC– –5 –15 V NE5534, NE5534A 0 70 SA5534, SA5534A –40 85 °C 7.4 Thermal Information THERMAL METRIC NE5534, NE5534A SA5534, and SA5534A (1) D P PS UNIT 8 PINS RθJA (1) (2) (3) 4 Package thermal impedance (2) (3) 97 85 95 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953). The package thermal impedance is calculated in accordance with JESD 51-7. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA) / θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. Submit Documentation Feedback Copyright © 1979–2014, Texas Instruments Incorporated Product Folder Links: NE5534 NE5534A SA5534 SA5534A NE5534, NE5534A, SA5534, SA5534A www.ti.com SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 7.5 Electrical Characteristics VCC± = ±15 V, TA = 25°C (unless otherwise noted) TEST CONDITIONS (1) PARAMETER VIO Input offset voltage VO = 0 RS = 50 Ω IIO Input offset current VO = 0 IIB Input bias current VO = 0 VICR Common-mode input-voltage range VO(PP) Maximum peak-to-peak output-voltage swing RL ≥ 600 Ω VO = ±10 V RL ≥ 600 Ω, AVD Large-signal differential-voltage amplification RL ≥ 2 kΩ, VO±10 V Avd Small-signal differential-voltage amplification f = 10 kHz VO = ±10 V BOM Unity-gain bandwidth ri Input resistance zo Output impedance kSVR Supply-voltage rejection ratio (ΔVCC or ΔVIO) IOS Output short-circuit current ICC Total supply current MAX 0.5 4 TA = Full range 5 TA = 25°C 20 TA = Full range 300 400 TA = 25°C 500 TA = Full range 1500 2000 ±12 ±13 VCC± = ±15 V 24 26 VCC± = ±18 V 30 32 TA = 25°C 25 100 TA = Full range 15 TA = 25°C 25 TA = Full range 15 CC = 0 2.2 CC = 0 200 95 VCC± 18 V, RL = 600 Ω VO = ±14 V CC = 22 pF 70 CC = 22 pF CL = 100 pF mV nA nA V V/mV 100 CC = 22 pF UNIT V 6 30 CMRR Common-mode rejection ratio (1) TA = 25°C TYP CC = 22 pF Maximum output-swing bandwidth B1 MIN V/mV kHz 10 MHz 100 kΩ 0.3 Ω AVD = 30 dB, CC = 22 pF RL = 600 Ω, f = 10 kHz VO = 0, RS = 50 Ω VIC = VICRmin 70 100 dB VCC± = ±9 V to ±15 V, VO = 0 RS = 50 Ω 80 100 dB 38 mA VO = 0, No load TA = 25°C 4 8 mA All characteristics are measured under open-loop conditions with zero common-mode input voltage, unless otherwise specified. For NE5534 and NE5534A, full range is 0°C to 70°C. For SA5534 and SA5534A, full range is –40°C to 85°C. Copyright © 1979–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: NE5534 NE5534A SA5534 SA5534A 5 NE5534, NE5534A, SA5534, SA5534A SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 www.ti.com 7.6 Operating Characteristics VCC± = ±15 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS NE5534, SA5534 TYP SR Slew rate Rise time Overshoot factor tr Rise time Overshoot factor Vn Equivalent input noise voltage In Equivalent input noise current F Average noise figure 6 NE5534A, SA5534A MIN TYP UNIT MAX CC = 0 13 13 CC = 22 pF 6 6 20 20 20 20 % 50 50 ns 35% — VI = 50 mV, RL = 600 Ω, CL = 100 pF VI = 50 mV, RL = 600 Ω, CL = 500 pF AVD = 1, CC = 22 pF AVD = 1, CC = 47 pF 35% V/μs ns f = 30 Hz 7 5.5 7 f = 1 kHz 4 3.5 4.5 f = 30 Hz 2.5 1.5 f = 1 kHz 0.6 0.4 RS = 5 kΩ Submit Documentation Feedback f = 10Hz to 20 kHz 0.9 nV/√Hz pA/√Hz dB Copyright © 1979–2014, Texas Instruments Incorporated Product Folder Links: NE5534 NE5534A SA5534 SA5534A NE5534, NE5534A, SA5534, SA5534A www.ti.com SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 VO(PP) VOPP − Maximum Peak-to-Peak Output Voltage − V Normalized Input Bias Current and Input Offset Current 7.7 Typical Characteristics 1.6 VCC± = ±15 V 1.4 Offset 1.2 Bias 1 0.8 0.6 0.4 −75 −50 75 100 −25 0 25 50 TA − Free-Air Temperature − °C 125 20 15 10 CC = 22 pF 5 CC = 47 pF VCC± = ±15 V TA = 25°C 0 100 1k 10 k 100 k 1M Figure 2. Maximum Peak-to-Peak Output Voltage vs Frequency 105 104 103 CC = 0 pF 102 CC = 22 pF 10 100 1k 10 k 100 k 1 M f − Frequency − Hz 10 M 100 M Normalized Slew Rate and Unity-Gain Bandwidth AVD − Differential Voltage Amplification − V/mV 25 1.2 VCC± = ±15 V TA = 25°C 1 10 CC = 0 f − Frequency − Hz Figure 1. Normalized Input Bias Current and Input Offset Current vs Free-Air Temperature 106 30 TA = 25°C 1.1 Unity-Gain Bandwidth 1 0.9 0.8 0.7 Slew Rate 0.6 0.5 0.4 0 5 10 15 | VCC± | − Supply Voltage − V 20 Figure 3. Large-Signal Differential Voltage Amplification vs Frequency Figure 4. Normalized Slew Rate and Unity-Gain Bandwidth vs Supply Voltage Figure 5. Normalized Slew Rate and Unity-Gain Bandwidth vs Free-Air Temperature Figure 6. Total Harmonic Distortion vs Frequency Copyright © 1979–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: NE5534 NE5534A SA5534 SA5534A 7 NE5534, NE5534A, SA5534, SA5534A SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 www.ti.com Typical Characteristics (continued) Figure 7. Equivalent Input Noise Voltage vs Frequency Figure 8. Equivalent Input Noise Current vs Frequency Figure 9. Total Equivalent Input Noise Voltage vs Source Resistance 8 Submit Documentation Feedback Copyright © 1979–2014, Texas Instruments Incorporated Product Folder Links: NE5534 NE5534A SA5534 SA5534A NE5534, NE5534A, SA5534, SA5534A www.ti.com SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 8 Detailed Description 8.1 Overview The NE5534, NE5534A, SA5534, and SA5534A devices are high-performance operational amplifiers combining excellent dc and ac characteristics. Some of the features include very low noise, high output-drive capability, high unity-gain and maximum-output-swing bandwidths, low distortion, and high slew rate. These operational amplifiers are compensated internally for a gain equal to or greater than three. Optimization of the frequency response for various applications can be obtained by use of an external compensation capacitor between COMP and COMP/BAL. The devices feature input-protection diodes, output short-circuit protection, and offset-voltage nulling capability with use of the BALANCE and COMP/BAL pins (see the Application Circuit Diagram). For the NE5534A and SA5534A devices, a maximum limit is specified for the equivalent input noise voltage. 8.2 Functional Block Diagram BALANCE COMP/BAL 8 1 100 pF IN+ 12 kΩ COMP 5 7 12 kΩ 3 40 pF 15 Ω 6 IN− VCC+ 2 12 pF 7 pF 15 Ω 4 Copyright © 1979–2014, Texas Instruments Incorporated OUT Submit Documentation Feedback Product Folder Links: NE5534 NE5534A SA5534 SA5534A VCC− 9 NE5534, NE5534A, SA5534, SA5534A SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 www.ti.com 8.3 Feature Description 8.3.1 Offset-Voltage Null Capability The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, currentgain betas (β), collector or emitter resistors, and so on. The input offset pins allow the designer to adjust for these mismatches by external circuitry. See the Application and Implementation section for more details on design techniques. 8.3.2 Slew Rate The slew rate is the rate at which an operational amplifier can change its output when there is a change on the input. The NE5534 and SA5534 devices have a 13-V/μs slew rate. 8.3.3 Common-Mode Rejection Ratio The common-mode rejection ratio (CMRR) of an amplifier is a measure of how well the device rejects unwanted input signals common to both input leads. It is found by taking the ratio of the change in input offset voltage to the change in the input voltage and converting to decibels. Ideally the CMRR is infinite, but in practice, amplifiers are designed to have it as high as possible. The CMRR of the NE5534 and SA5534 devices is 100 dB. 8.3.4 Unity-Gain Bandwidth The unity-gain bandwidth is the frequency up to which an amplifier with a unity gain may be operated without greatly distorting the signal. The NE5534 and SA5534 devices have a 10-MHz unity-gain bandwidth. 8.3.5 External Compensation Capability Frequency compensation with a capacitor may be used to increase the gain-bandwidth product (GBW) of the amplifier. See the Application and Implementation section for more details on design techniques. 8.4 Device Functional Modes The NE5534 and SA5534 devices are powered on when the supply is connected. Each of these devices can be operated as a single supply operational amplifier or dual supply amplifier depending on the application. 10 Submit Documentation Feedback Copyright © 1979–2014, Texas Instruments Incorporated Product Folder Links: NE5534 NE5534A SA5534 SA5534A NE5534, NE5534A, SA5534, SA5534A www.ti.com SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 General Application The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, currentgain betas (β), collector or emitter resistors, and so on. The input offset pins allow the designer to adjust for these mismatches by external circuitry. These input mismatches can be adjusted by putting resistors or a potentiometer between the inputs as shown in Figure 10. A potentiometer can be used to fine tune the circuit during testing or for applications which require precision offset control. More information about designing using the input-offset pins, see Offset Voltage of Operational Amplifiers (SLOA045). VCC+ 22 kΩ 100 kΩ CC − 5534 + VCC− Frequency Compensation and Offset-Voltage Nulling Circuit Figure 10. Application Circuit Copyright © 1979–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: NE5534 NE5534A SA5534 SA5534A 11 NE5534, NE5534A, SA5534, SA5534A SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 www.ti.com 9.2 Typical Application The voltage follower configuration of the operational amplifier is used for applications where a weak signal is used to drive a relatively high current load. This circuit is also called a buffer amplifier or unity gain amplifier. The inputs of an operational amplifier have a very high resistance which puts a negligible current load on the voltage source. The output resistance of the operational amplifier is almost negligible, so it can provide as much current as necessary to the output load. 10 k 12 V VOUT + VIN Figure 11. Voltage Follower Schematic 9.2.1 Design Requirements • Output range of 2 V to 11 V • Input range of 2 V to 11 V 9.2.2 Detailed Design Procedure 9.2.2.1 Output Voltage Swing The output voltage of an operational amplifier is limited by its internal circuitry to some level below the supply rails. For this amplifier, the output voltage swing is within ±12 V, which accommodates the input and output voltage requirements. 9.2.2.2 Supply and Input Voltage For correct operation of the amplifier, neither input must be higher than the recommended positive supply rail voltage or lower than the recommended negative supply rail voltage. The chosen amplifier must be able to operate at the supply voltage that accommodates the inputs. Because the input for this application goes up to 11 V, the supply voltage must be 12 V. Using a negative voltage on the lower rail rather than ground, allows the amplifier to maintain linearity for inputs below 2 V. 12 Submit Documentation Feedback Copyright © 1979–2014, Texas Instruments Incorporated Product Folder Links: NE5534 NE5534A SA5534 SA5534A NE5534, NE5534A, SA5534, SA5534A www.ti.com SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 Typical Application (continued) 9.2.3 Application Curves for Output Characteristics 12 4 2 10 0 IIN (mA) VOUT (V) 8 6 ±2 ±4 ±6 4 ±8 2 ±10 0 ±12 0 2 4 6 8 10 VIN (V) 12 0 2 4 6 8 10 VIN (V) C001 Figure 12. Output Voltage vs Input Voltage 12 C002 Figure 13. Current Drawn by the Input of the Voltage Follower (IIN) vs the Input Voltage 20 18 16 ICC (mA) 14 12 10 8 6 4 2 0 0 2 4 6 VIN (V) 8 10 12 C003 Figure 14. Current Drawn from Supply (ICC) vs the Input Voltage Copyright © 1979–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: NE5534 NE5534A SA5534 SA5534A 13 NE5534, NE5534A, SA5534, SA5534A SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 www.ti.com 10 Power Supply Recommendations The NE5534 and SA5534 devices are specified for operation from ±5 to ±15 V; many specifications apply from 0°C to 70°C for the NE5534 device and –40°C to 85°C for the SA5534 device. CAUTION Supply voltages larger than ±22 V can permanently damage the device (see the Absolute Maximum Ratings). Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout Guidelines. 14 Submit Documentation Feedback Copyright © 1979–2014, Texas Instruments Incorporated Product Folder Links: NE5534 NE5534A SA5534 SA5534A NE5534, NE5534A, SA5534, SA5534A www.ti.com SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 11 Layout 11.1 Layout Guidelines • • • • • • For best operational performance of the device, use good PCB layout practices, including: Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications. Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. On multilayer PCBs, one or more layers are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to Circuit Board Layout Techniques (SLOA089). To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicularly, as opposed to in parallel, with the noisy trace. Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in . Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. 11.2 Layout Example RIN VIN RG + VOUT RF Figure 15. Operational Amplifier Schematic for Noninverting Configuration Place components close to device and to each other to reduce parasitic errors Run the input traces as far away from the supply lines as possible RF BALANCE COMP/BAL IN1í VCC+ IN1+ OUT VCCí COMP VS+ Use low-ESR, ceramic bypass capacitor RG GND VIN RIN GND Only needed for dual-supply operation GND VS(or GND for single supply) VOUT Ground (GND) plane on another layer Figure 16. Operational Amplifier Board Layout for Noninverting Configuration Copyright © 1979–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: NE5534 NE5534A SA5534 SA5534A 15 NE5534, NE5534A, SA5534, SA5534A SLOS070D – JULY 1979 – REVISED NOVEMBER 2014 www.ti.com 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY NE5534 Click here Click here Click here Click here Click here NE5534A Click here Click here Click here Click here Click here SA5534 Click here Click here Click here Click here Click here SA5534A Click here Click here Click here Click here Click here 12.2 Trademarks All trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 16 Submit Documentation Feedback Copyright © 1979–2014, Texas Instruments Incorporated Product Folder Links: NE5534 NE5534A SA5534 SA5534A PACKAGE OPTION ADDENDUM www.ti.com 24-Apr-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) NE5534AD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 5534A NE5534ADR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 5534A NE5534ADRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 5534A NE5534ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 5534A NE5534AJG OBSOLETE CDIP JG 8 TBD Call TI Call TI -55 to 125 NE5534AP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE5534AP NE5534APE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE5534AP NE5534D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 NE5534 NE5534DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 NE5534 NE5534DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 NE5534 NE5534DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 NE5534 NE5534IP OBSOLETE PDIP P 8 TBD Call TI Call TI 0 to 70 NE5534P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE5534P NE5534PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE5534P SA5534AD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 SA5534A SA5534ADG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 SA5534A SA5534ADR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 SA5534A SA5534AP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA5534AP Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Apr-2015 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SA5534APE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA5534AP SA5534D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 SA5534 SA5534DE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 SA5534 SA5534DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 SA5534 SA5534P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA5534P SA5534PSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5534 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Apr-2015 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 1-Oct-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant NE5534ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE5534DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SA5534ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SA5534DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SA5534PSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Oct-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) NE5534ADR SOIC D 8 2500 340.5 338.1 20.6 NE5534DR SOIC D 8 2500 340.5 338.1 20.6 SA5534ADR SOIC D 8 2500 340.5 338.1 20.6 SA5534DR SOIC D 8 2500 340.5 338.1 20.6 SA5534PSR SO PS 8 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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