AD ADF4106 Pll frequency synthesizer Datasheet

a
PLL Frequency Synthesizer
ADF4106
GENERAL DESCRIPTION
FEATURES
6.0 GHz Bandwidth
2.7 V to 3.3 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended
Tuning Voltage in 3 V Systems
Programmable Dual Modulus Prescaler
8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
Programmable Anti-Backlash Pulsewidth
3-Wire Serial Interface
Analog and Digital Lock Detect
Hardware and Software Power-Down Mode
The ADF4106 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low-noise digital PFD (Phase Frequency Detector), a precision
charge pump, a programmable reference divider, programmable
A and B counters and a dual-modulus prescaler (P/P + 1). The
A (6-bit) and B (13-bit) counters, in conjunction with the dual
modulus prescaler (P/P + 1), implement an N divider (N = BP + A).
In addition, the 14-bit reference counter (R Counter), allows
selectable REFIN frequencies at the PFD input. A complete
PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage
Controlled Oscillator). Its very high bandwidth means that
frequency doublers can be eliminated in many high-frequency
systems, simplifying system architecture and lowering cost.
APPLICATIONS
Broadband Wireless Access
Instrumentation
Wireless LANS
Base Stations For Wireless Radio
FUNCTIONAL BLOCK DIAGRAM
AVDD
VP
DVDD
CPGND
RSET
REFERENCE
14-BIT
R COUNTER
REFIN
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
14
R COUNTER
LATCH
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1
CPI6 CPI5 CPI4
LOCK
DETECT
CLK
DATA
24-BIT INPUT
REGISTER
LE
FUNCTION
LATCH
22
FROM
FUNCTION
LATCH
AB COUNTER
LATCH
HIGH Z
19
AVDD
MUXOUT
MUX
13
SDOUT
N = BP + A
13-BIT
B COUNTER
LOAD
RFINA
RFINB
M3 M2 M1
PRESCALER
P/P + 1
LOAD
6-BIT
A COUNTER
ADF4106
6
REV. 0
CE
AGND
DGND
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
10%; AV ≤ V ≤ 5.5 V; AGND = DGND = CPGND = 0 V;
ADF4106–SPECIFICATIONS1 R(AV ==5.1DVk;= 3dBmV referred
to 50 ; T = T to T unless otherwise noted.)
DD
DD
DD
SET
A
B Version
BChips2
(typ)
Unit
0.5/6.0
–10/0
0.5/6.0
–10/0
GHz min/max
dBm min/max
300
300
MHz max
20/250
20/250
MHz min/max
REFIN Input Sensitivity5
0.8/AVDD
0.8/AVDD
V p-p min/max
REFIN Input Capacitance
REFIN Input Current
10
± 100
10
± 100
pF max
µA max
PHASE DETECTOR
Phase Detector Frequency6
56
56
MHz max
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
5
625
2.5
2.7/10
1
2
1.5
2
5
625
2.5
2.7/10
1
2
1.5
2
mA typ
µA typ
% typ
kΩ typ
nA typ
% typ
% typ
% typ
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
1.4
0.6
±1
10
1.4
0.6
±1
10
V min
V max
µA max
pF max
LOGIC OUTPUTS
VOH, Output High Voltage
1.4
1.4
V min
VOH, Output High Voltage
IOH
VOL, Output Low Voltage
1.4
100
0.4
1.4
100
0.4
V min
µA max
V max
2.7/3.3
AVDD
AVDD/5.5
15
0.4
10
2.7/3.3
AVDD
AVDD/5.5
13
0.4
10
V min/V max
Parameter
RF CHARACTERISTICS
RF Input Frequency (RFIN)3
RF Input Sensitivity
Maximum Allowable
Prescaler Output Frequency4
REFIN CHARACTERISTICS
REFIN Input Frequency
POWER SUPPLIES
AVDD
DVDD
VP
IDD7 (AIDD + DIDD)
IP
Power-Down Mode8 (AIDD + DIDD)
1
P
MIN
MAX
Test Conditions/Comments
See Figure 3 for Input Circuit
–2–
V min/V max
mA max
mA max
µA typ
For f < 20 MHz, Use DC-Coupled
Square Wave, (0 to VDD)
AC-Coupled; When DC-Coupled,
0 to VDD max (CMOS Compatible)
Programmable, See Table V
With RSET = 5.1 kΩ
With RSET = 5.1 kΩ
See Table V
0.5 V ⱕ VCP ⱕ VP – 0.5 V
0.5 V ⱕ VCP ⱕ VP – 0.5 V
VCP = VP/2
Open Drain Output Chosen 1 kΩ
Pull-up to 1.8 V
CMOS Output Chosen
IOL = 500 µA
AVDD ⱕ VP ⱕ 5.5 V
13 mA typ
TA = 25°C
REV. 0
ADF4106
B Version
BChips2
(typ)
Unit
Test Conditions/Comments
–174
–166
–159
–174
–166
–159
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
–93
–74
–84
–93
–74
–84
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ 25 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ 1 MHz PFD Frequency
@ VCO Output
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 1 kHz Offset and 1 MHz PFD Frequency
–90/–92
–65/–70
–70/–75
–90/–92
–65/–70
–70/–75
dBc typ
dBc typ
dBc typ
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 1 MHz/2 MHz and 1 MHz PFD Frequency
1
Parameter
NOISE CHARACTERISTICS
ADF4106 Phase Noise Floor9
Phase Noise Performance10
900 MHz Output11
5800 MHz Output12
5800 MHz Output13
Spurious Signals
900 MHz Output11
5800 MHz Output12
5800 MHz Output13
NOTES
1
Operating temperature range (B Version) is –40°C to +85°C.
2
The BChip specifications are given as typical values.
3
Use a square wave for lower frequencies, below the mimimum stated.
4
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency
that is less than this value.
5
AVDD = DVDD = 3 V
6
Guaranteed by design. Sample tested to ensure compliance.
7
TA = 25°C; AVDD = DVDD = 3 V; P = 16; RF IN = 6.0 GHz
8
TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RF IN = 6.0 GHz
9
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
10
The phase noise is measured with the EVAL-ADF4106EB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (fREFOUT = 10 MHz @ 0 dBm).
11
fREFIN = 10 MHz; f PFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 900 MHz; N = 4500; Loop B/W = 20 kHz
12
fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 5800 MHz; N = 29000; Loop B/W = 20 kHz
13
fREFIN = 10 MHz; fPFD = 1 MHz; Offset Frequency = 1 kHz; f RF = 5800 MHz; N = 5800; Loop B/W = 100 kHz
Specifications subject to change without notice.
TIMING CHARACTERISTICS
(AVDD = DVDD = 3 V 10%; AVDD ≤ VP ≤ 5.5 V; AGND = DGND = CPGND = 0 V; RSET = 5.1 k;
TA = TMIN to TMAX unless otherwise noted.)
Parameter
Limit at
TMIN to TMAX
(B Version)
Unit
Test Conditions/Comments
t1
t2
t3
t4
t5
t6
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
Guaranteed by design but not production tested.
t3
t4
CLOCK
t1
DATA
DB23 (MSB)
t2
DB22
DB2
DB1 (CONTROL
BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t6
LE
t5
LE
Figure 1. Timing Diagram
REV. 0
–3–
ADF4106
ABSOLUTE MAXIMUM RATINGS 1, 2
ORDERING GUIDE
(TA = 25°C unless otherwise noted.)
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
VP to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.3 V
VP to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP ␪JA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
CSP ␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . 122°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Model
Temperature Range
Package Option*
ADF4106BRU
ADF4106BCP
–40°C to +85°C
–40°C to +85°C
RU-16
CP-20
*RU = Thin Shrink Small Outline Package (TSSOP)
CP = Chip Scale Package
Contact the factory for chip availability.
Note that aluminum bond wire should not be used with the ADF4106 die.
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
This device is a high-performance RF integrated circuit with an ESD rating of
<2 kV and it is ESD sensitive. Proper precautions should be taken for handling and
assembly.
3
GND = AGND = DGND = 0 V
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADF4106 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
ADF4106
PIN CONFIGURATIONS
Chip Scale Package
20 CP
19 RSET
18 VP
17 DVDD
16 DVDD
TSSOP
16
VP
CP 2
15
DVDD
14
MUXOUT
CPGND 3
4
ADF4106
CPGND 1
AGND 2
AGND 3
RFINB 4
RFINA 5
LE
TOP VIEW
RFINB 5 (Not to Scale) 12 DATA
AGND
13
RFINA 6
11
CLK
AVDD 7
10
CE
REFIN 8
9
DGND
NOTE: TRANSISTOR COUNT 6425 (CMOS), 303 (BIPOLAR)
PIN 1
INDICATOR
ADF4106
TOP VIEW
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
AVDD 6
AVDD 7
REFIN 8
DGND 9
DGND 10
RSET 1
PIN FUNCTION DESCRIPTIONS
Mnemonic
Function
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal
voltage potential at the RSET pin is 0.6 V. The relationship between ICP and RSET is
CP
CPGND
AGND
RFINB
RFINA
AVDD
REFIN
DGND
CE
CLK
DATA
LE
MUXOUT
DVDD
VP
REV. 0
I CP MAX = 25.5
RSET
So, with RSET = 5.1 kΩ, ICPMAX = 5 mA.
Charge Pump Output. When enabled this provides ± ICP to the external loop filter, which in turn drives the
external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF. See Figure 3.
Input to the RF Prescaler. This small signal input is ac coupled to the external VCO.
Analog Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of
100 kΩ. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac coupled.
Digital Ground
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state
mode. Taking the pin high will power up the device depending on the status of the power-down bit F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches, the latch being selected using the control bits.
This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency to be
accessed externally.
Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be
set to 5 V and used to drive a VCO with a tuning range of up to 5 V.
–5–
ADF4106–Typical Performance Characteristics
FREQ
0.500
0.600
0.700
0.800
0.900
1.000
1.100
1.200
1.300
1.400
1.500
1.600
1.700
1.800
1.900
2.000
2.100
2.200
2.300
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
–40
KEYWORD – R
IMPEDANCE – 50
MAGS11
0.89148
0.88133
0.87152
0.85855
0.84911
0.83512
0.82374
0.80871
0.79176
0.77205
0.75696
0.74234
0.72239
0.69419
0.67288
0.66227
0.64758
0.62454
0.59466
0.55932
0.52256
0.48754
0.46411
0.45776
0.44859
0.44588
0.43810
0.43269
FREQ
3.300
3.400
3.500
3.600
3.700
3.800
3.900
4.000
4.100
4.200
4.300
4.400
4.500
4.600
4.700
4.800
4.900
5.000
5.100
5.200
5.300
5.400
5.500
5.600
5.700
5.800
5.900
6.000
ANGS11
– 17.2820
– 20.6919
– 24.5386
– 27.3228
– 31.0698
– 34.8623
– 38.5574
– 41.9093
– 45.6990
– 49.4185
– 52.8898
– 56.2923
– 60.2584
– 63.1446
– 65.6464
– 68.0742
– 71.3530
– 75.5658
– 79.6404
– 82.8246
– 85.2795
– 85.6298
– 86.1854
– 86.4997
– 88.8080
– 91.9737
– 95.4087
– 99.1282
MAGS11
0.42777
0.42859
0.43365
0.43849
0.44475
0.44800
0.45223
0.45555
0.45313
0.45622
0.45555
0.46108
0.45325
0.45054
0.45200
0.45043
0.45282
0.44287
0.44909
0.44294
0.44558
0.45417
0.46038
0.47128
0.47439
0.48604
0.50637
0.52172
10dB/DIV
RL = –40dBc/Hz
RMS NOISE = 0.36
–50
ANGS11
– 102.748
– 107.167
– 111.883
– 117.548
– 123.856
– 130.399
– 136.744
– 142.766
– 149.269
– 154.884
– 159.680
– 164.916
– 168.452
– 173.462
– 176.697
178.824
174.947
170.237
166.617
162.786
158.766
153.195
147.721
139.760
132.657
125.782
121.110
115.400
–60
PHASE NOISE – dBc/Hz
FREQ UNIT – GHz
PARAM TYPE – S
DATA FORMAT – MA
–70
–80
–90
–100
–110
–120
–130
–140
100Hz
1MHz
FREQUENCY OFFSET FROM 900MHz CARRIER
TPC 1. S-Parameter Data for the RF Input
TPC 4. Integrated Phase Noise (900 MHz,
200 kHz, and 20 kHz)
0
0
VDD = 3V
VP = 3V
REF LEVEL = –14.0dBm
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
AVERAGES = 30
–10
–5
OUTPUT POWER – dB
OUTPUT POWER – dB
–20
–10
–15
–20
TA = +85C
–40
–50
–60
–70
–91.0dBc/Hz
–80
–25
TA = +25C
–90
TA = –40C
–30
–30
0
1
2
3
4
5
–100
6
–400kHz
–200kHz
RF INPUT FREQUENCY – GHz
200kHz
400kHz
TPC 5. Reference Spurs (900 MHz, 200 kHz, and 20 kHz)
TPC 2. Input Sensitivity
0
0
REF LEVEL = –10dBm
REF LEVEL = –14.3dBm
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10
–20
–30
–40
–20
–50
–60
–93.0dBc/Hz
–70
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10
–10
OUTPUT POWER – dB
–10
OUTPUT POWER – dB
900MHz
FREQUENCY
–30
–40
–50
–60
–70
–80
–80
–90
–90
–100
–84.0dBc/Hz
–100
–2kHz
–1kHz
900MHz
FREQUENCY
1kHz
2kHz
–2kHz
–1kHz
5800MHz
FREQUENCY
1kHz
2kHz
TPC 6. Phase Noise (5.8 GHz, 1 MHz, and 100 kHz)
TPC 3. Phase Noise (900 MHz, 200 kHz, and 20 kHz)
–6–
REV. 0
ADF4106
–40
–5
10dB/DIV
RL = –40dBc/Hz
RMS NOISE = 1.8
–60
PHASE NOISE – dBc/Hz
VDD = 3V
VP = 5V
–15
FIRST REFERENCE SPUR – dBc
–50
–70
–80
–90
–100
–110
–120
–25
–35
–45
–55
–65
–75
–85
–130
–95
–140
100Hz
–105
1MHz
0
FREQUENCY OFFSET FROM 5800MHz CARRIER
TPC 7. Integrated Phase Noise (5.8 GHz, 1 MHz, and
100 kHz)
4
5
–120
–10
–20
–30
–40
VDD = 3V
VP = 5V
VDD = 3V, VP = 5V
ICP = 5mA
PDF FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 13 SECONDS
AVERAGES = 1
–66.0dBc
–130
OUTPUT POWER – dBc/Hz
REF LEVEL = –10.0dBm
OUTPUT POWER – dB
2
3
TUNING VOLTAGE – V
TPC 10. Reference Spurs vs. VTUNE (5.8 GHz, 1 MHz, and
100 kHz)
0
–50
1
–65.0dBc
–60
–70
–80
–140
–150
–160
–170
–90
–180
10
–100
–2MHz
–1MHz
5800MHz
1MHz
2MHz
FREQUENCY
1k
10k
100
PHASE DETECTOR FREQUENCY – Hz
100k
TPC 11. Phase Noise (referred to CP output) vs.
PFD Frequency
TPC 8. Reference Spurs (5.8 GHz, 1 MHz, and 100 kHz)
10
–60
VDD = 3V
VP = 5V
9
–70
7
AIDD – mA
PHASE NOISE – dBc/Hz
8
–80
6
5
4
3
–90
2
1
–100
–40
–20
0
20
40
TEMPERATURE – C
60
80
0
8/9
100
TPC 12. AIDD vs. Prescaler Value
TPC 9. Phase Noise (5.8 GHz, 1 MHz, and 100 kHz) vs.
Temperature
REV. 0
16/17
32/33
PRESCALER VALUE
–7–
64/65
ADF4106
6
3.5
3.0
VDD = 3V
VP = 3V
4
VP = 5V
ICP = 5mA
2.5
ICP – mA
DIDD – mA
2
2.0
1.5
0
–2
1.0
–4
0.5
0
50
150
200
250
100
PRESCALER OUTPUT FREQUENCY
–6
300
0
TPC 13. DIDD vs. Prescaler Output Frequency
2.0
2.5
3.0
VCP – V
3.5
4.0
4.5
5.0
The dual modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A and B
counters. The prescaler is programmable. It can be set in software to 8/9, 16/17, 32/33 or 64/65. It is based on a synchronous
4/5 core. There is a minimum divide ratio possible for fully
contiguous output frequencies. This minimum is determined by
P, the prescaler value and is given by: (P2 – P).
POWER-DOWN
CONTROL
100k
A AND B COUNTERS
SW2
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with an RF input
frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.
TO R COUNTER
NC
SW1
BUFFER
NO
1.5
PRESCALER (P/P + 1)
The Reference Input stage is shown in Figure 2. SW1 and SW2
are normally-closed switches. SW3 is normally-open. When
Powerdown is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
REFIN
1.0
TPC 14. Charge Pump Output Characteristics
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
NC
0.5
SW3
NC = NO CONNECT
Pulse Swallow Function
Figure 2. Reference Input Stage
The A and B counters, in conjunction with the dual modulus
prescaler make it possible to generate output frequencies which
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
RF INPUT STAGE
The RF input stage is shown in Figure 3. It is followed by a 2-stage
limiting amplifier to generate the CML clock levels needed for the
prescaler.
BIAS
GENERATOR
500
f REFIN
R
Output Frequency of external voltage controlled
oscillator (VCO).
Preset modulus of dual modulus prescaler
(8/9, 16/17, etc.,).
Preset Divide Ratio of binary 13-bit counter
(3 to 8191).
Preset Divide Ratio of binary 6-bit swallow
counter (0 to 63).
External reference frequency oscillator.
fVCO = [( P × B ) + A] ×
1.6V
fVCO
AVDD
P
500
B
RF A
IN
A
RF B
IN
fREFIN
AGND
Figure 3. RF Input Stage
–8–
REV. 0
ADF4106
MUXOUT AND LOCK DETECT
N = BP + A
TO PFD
13-BIT B
COUNTER
LOAD
PRESCALER
P/P + 1
FROM RF
INPUT STAGE
LOAD
6-BIT A
COUNTER
MODULUS
CONTROL
The output multiplexer on the ADF4110 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the Function
Latch. Table V shows the full truth table. Figure 6 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
N DIVIDER
Figure 4. A and B Counters
R COUNTER
The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383
are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N =
BP + A) and produces an output proportional to the phase and
frequency difference between them. Figure 5 is a simplified
schematic. The PFD includes a programmable delay element
which controls the width of the anti-backlash pulse. This pulse
ensures that there is no deadzone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
Reference Counter Latch, ABP2 and ABP1 control the width of
the pulse. See Table III.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive Phase Detector cycles is less than
15 ns. With LDP set to “1,” five consecutive cycles of less than
15 ns are required to set the lock detect. It will stay set high
until a phase error of greater than 25 ns is detected on any subsequent PD cycle.
The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 k⍀ nominal. When
lock has been detected this output will be high with narrow lowgoing pulses.
DVDD
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
MUX
CONTROL
MUXOUT
N COUNTER OUTPUT
SDOUT
VP
HI
D1
Q1
CHARGE
PUMP
UP
DGND
U1
R DIVIDER
Figure 6. MUXOUT Circuit
CLR1
PROGRAMMABLE
DELAY
ABP2
HI
INPUT SHIFT REGISTER
U3
CP
ABP1
CLR2 DOWN
D2 Q2
U2
N DIVIDER
CPGND
The ADF4110 family digital section includes a 24-bit input shift
register, a 14-bit R counter and a 19-bit N counter, comprising a
6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits
(C2, C1) in the shift register. These are the two LSBs, DB1 and
DB0, as shown in the timing diagram of Figure 1. The truth table
for these bits is shown in Table VI. Table I shows a summary
of how the latches are programmed.
R DIVIDER
Table I. C2, C1 Truth Table
N DIVIDER
CP OUTPUT
Figure 5. PFD Simplified Schematic and Timing (In Lock)
REV. 0
Control Bits
C2
C1
Data Latch
0
0
1
1
R Counter
N Counter (A and B)
Function Latch (Including Prescaler)
Initialization Latch
–9–
0
1
0
1
ADF4106
Table II. Latch Summary
LOCK
DETECT
PRECISION
REFERENCE COUNTER LATCH
RESERVED
TEST
MODE BITS
ANTIBACKLASH
WIDTH
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
X
0
0
LDP
T2
T1
CONTROL
BITS
14-BIT REFERENCE COUNTER
ABP2 ABP1
R14
R13
R12
R11
R10
R9
R8
DB8
DB7
DB6
DB5
DB4
DB3
DB2
R7
R6
R5
R4
R3
R2
R1
DB1
DB0
C2 (0) C1 (0)
13-BIT B COUNTER
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
B2
B1
A6
A5
A4
A3
A2
A1
C2 (0) C1 (1)
COUNTER
RESET
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
G1
CONTROL
BITS
6-BIT A COUNTER
POWERDOWN 1
RESERVED
CP GAIN
N COUNTER LATCH
CONTROL
BITS
DB1
DB0
PD
POLARITY
DB5
DB4
F4
F3
F2
M3
M2
M1
FASTLOCK
ENABLE
CP THREESTATE
PD
POLARITY
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
TIMER COUNTER
CONTROL
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P2
P1
PD2
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
TC4
TC3
TC2
TC1
F5
MUXOUT
CONTROL
DB3 DB2
PD1
F1
COUNTER
RESET
CP THREESTATE
DB6
CURRENT
SETTING
1
POWERDOWN 1
FASTLOCK
ENABLE
DB7
CURRENT
SETTING
2
FASTLOCK
MODE
DB8
PRESCALER
VALUE
POWERDOWN 2
DB9
FASTLOCK
MODE
FUNCTION LATCH
DB1
DB0
C2 (1) C1 (0)
PRESCALER
VALUE
P2
P1
POWERDOWN 2
INITIALIZATION LATCH
PD2
CURRENT
SETTING
2
CPI6
CPI5
CPI4
CURRENT
SETTING
1
CPI3
CPI2
CPI1
TIMER COUNTER
CONTROL
TC4
TC3
TC2
TC1
–10–
F5
F4
F3
F2
MUXOUT
CONTROL
DB6
M3
DB5
M2
DB4
M1
DB3 DB2
PD1
F1
CONTROL
BITS
DB1
DB0
C2 (1) C1 (1)
REV. 0
ADF4106
LOCK
DETECT
PRECISION
Table III. Reference Counter Latch Map
RESERVED
TEST
MODE BITS
ANTIBACKLASH
WIDTH
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
X
0
0
LDP
T2
T1
ABP2 ABP1
CONTROL
BITS
14-BIT REFERENCE COUNTER
R14
R13
R12
R11
R10
R9
R8
DB8
DB7
DB6
DB5
DB4
DB3
DB2
R7
R6
R5
R4
R3
R2
R1
DB1
DB0
C2 (0) C1 (0)
X = DON’T CARE
ABP2
0
0
1
1
ABP1
0
1
0
1
R14
0
0
0
0
.
.
.
1
R13
0
0
0
0
.
.
.
1
R12
0
0
0
0
.
.
.
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
R3
0
0
0
1
.
.
.
1
R2
0
1
1
0
.
.
.
0
R1
1
0
1
0
.
.
.
0
DIVIDE RATIO
1
2
3
4
.
.
.
16380
1
1
1
..........
1
0
1
16381
1
1
1
..........
1
1
0
16382
1
1
1
..........
1
1
1
16383
ANTIBACKLASH PULSEWIDTH
2.9ns
1.3ns
6.0ns
2.9ns
TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL
OPERATION
LDP
0
1
OPERATION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPERATION
REV. 0
–11–
ADF4106
CP GAIN
Table IV. AB Counter Latch Map
RESERVED
DB23
X
13-BIT B COUNTER
DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12
X
G1
B13
B12
B11
B10
B9
B8
B7
B6
CONTROL
BITS
6-BIT A COUNTER
B5
DB11 DB10
B4
B3
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
B2
B1
A6
A5
A4
A3
A2
A1
DB1
DB0
C2 (0) C1 (1)
X = DON’T CARE
A6
0
0
0
0
.
.
.
1
1
1
1
B13
0
0
0
0
.
.
.
1
1
1
1
B12
0
0
0
0
.
.
.
1
1
1
1
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
0
0
1
1
B11
0
0
0
0
.
.
.
1
1
1
1
CP GAIN
0
1
1
2
0
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
B3
0
0
0
1
.
.
.
1
1
1
1
B2
0
0
1
1
.
.
.
0
0
1
1
B1
0
1
0
1
.
.
.
0
1
0
1
A5
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
A2
0
0
1
1
.
.
.
0
0
1
1
A1
0
1
0
1
.
.
.
0
1
0
1
A COUNTER
DIVIDE RATIO
0
1
2
3
.
.
.
60
61
62
63
B COUNTER DIVIDE RATIO
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
3
.
.
.
8188
8189
8190
8191
OPERATION
CHARGE PUMP CURRENT SETTING
IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING
IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING
IS USED
CHARGE PUMP CURRENT IS
SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK
MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION
N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH.
B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY
ADJACENT VALUES OF (N FREF), AT THE OUTPUT, NMIN IS (P2 - P)
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS.
–12–
REV. 0
ADF4106
P1
PD2
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
TC4
TC3
TC2
TC1
F5
COUNTER
RESET
P2
POWERDOWN 1
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
PD
POLARITY
TIMER COUNTER
CONTROL
CP
THREESTATE
CURRENT
SETTING
1
FASTLOCK
ENABLE
CURRENT
SETTING
2
FASTLOCK
MODE
PRESCALER
VALUE
POWERDOWN 2
Table V. Function Latch Map
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
F4
F3
F2
M3
M2
M1
PD1
F1
F2
0
1
F3
0
1
F4
0
1
1
TC4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CE PIN
0
1
1
1
P2
0
0
1
1
REV. 0
P1
0
1
0
1
TC3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CPI6
CPI5
CP14
CPI3
0
0
0
0
1
1
1
1
CPI2
0
0
1
1
0
0
1
1
CPI1
0
1
0
1
0
1
0
1
PD2
X
X
0
1
PD1
X
0
1
1
TC2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TC1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ICP (mA)
3k
1.06
2.12
3.18
4.24
5.30
6.36
7.42
8.50
5.1k
0.625
1.25
1.875
2.5
3.125
3.75
4.375
5.0
11k
0.289
0.580
0.870
1.160
1.450
1.730
2.020
2.320
MODE
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
PRESCALER VALUE
8/9
16/17
32/33
64/65
–13–
F5
X
0
1
MUXOUT
CONTROL
PHASE DETECTOR
POLARITY
NEGATIVE
POSITIVE
F1
0
1
CONTROL
BITS
DB1
DB0
C2 (1) C1 (0)
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
FASTLOCK MODE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
TIMEOUT
(PFD CYCLES)
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
M3
0
0
M2
0
0
M1
0
1
0
0
1
1
0
1
1
1
0
0
0
1
1
1
1
1
0
1
OUTPUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DVDD
DVDD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND
ADF4106
P1
PD2
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
TC4
TC3
TC2
TC1
F5
COUNTER
RESET
P2
POWERDOWN 1
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
PD
POLARITY
TIMER COUNTER
CONTROL
CP
THREESTATE
CURRENT
SETTING
1
FASTLOCK
ENABLE
CURRENT
SETTING
2
FASTLOCK
MODE
PRESCALER
VALUE
POWERDOWN 2
Table VI. Initialization Latch Map
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
F4
F3
F2
M3
M2
M1
PD1
F1
F2
0
1
F3
0
1
F4
0
1
1
TC4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CE PIN
0
1
1
1
P2
0
0
1
1
P1
0
1
0
1
TC3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CPI6
CPI5
CP14
CPI3
0
0
0
0
1
1
1
1
CPI2
0
0
1
1
0
0
1
1
CPI1
0
1
0
1
0
1
0
1
PD2
X
X
0
1
PD1
X
0
1
1
TC2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TC1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F5
X
0
1
MUXOUT
CONTROL
PHASE DETECTOR
POLARITY
NEGATIVE
POSITIVE
F1
0
1
CONTROL
BITS
DB1
DB0
C2 (1) C1 (1)
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
FASTLOCK MODE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
TIMEOUT
(PFD CYCLES)
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
M3
0
0
M2
0
0
M1
0
1
0
0
1
1
0
1
1
1
0
0
0
1
1
1
1
1
0
1
OUTPUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DVDD
DVDD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND
ICP (mA)
3k
1.06
2.12
3.18
4.24
5.30
6.36
7.42
8.50
5.1k
0.625
1.25
1.875
2.5
3.125
3.75
4.375
5.0
11k
0.289
0.580
0.870
1.160
1.450
1.730
2.020
2.320
MODE
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
PRESCALER VALUE
8/9
16/17
32/33
64/65
–14–
REV. 0
ADF4106
THE FUNCTION LATCH
Fastlock Mode 2
With C2, C1 set to 1,0, the on-chip function latch will be
programmed. Table V shows the input data format for programming the Function Latch.
The charge pump current is switched to the contents of Current
Setting 2. The device enters Fastlock by having a “1” written to
the CP Gain bit in the AB counter latch. The device exits
Fastlock under the control of the Timer Counter. After the
timeout period determined by the value in TC4–TC1, the CP
Gain bit in the AB counter latch is automatically reset to “0”
and the device reverts to normal mode instead of Fastlock. See
Table V for the timeout periods.
Counter Reset
DB2 (F1) is the counter reset bit. When this is “1,” the R counter
and the A,B counters are reset. For normal operation this bit
should be “0.” Upon powering up, the F1 bit needs to be disabled
(set to “0”). The N counter then resumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle).
Power-Down
DB3 (PD1) and DB21 (PD2) on the ADF4110 Family, provide
programmable power-down modes. They are enabled by the CE
pin. When the CE pin is low, the device is immediately disabled
regardless of the states of PD2, PD1. In the programmed asynchronous power-down, the device powers down immediately
after latching a “1” into bit PD1, with the condition that PD2
has been loaded with a “0.” In the programmed synchronous
power-down, the device power down is gated by the charge
pump to prevent unwanted frequency jumps. Once the powerdown is enabled by writing a “1” into bit PD1 (on condition
that a “1” has also been loaded to PD2), then the device will go
into power-down on the occurrence of the next charge pump
event. When a power down is activated (either synchronous or
asynchronous mode including CE-pin-activated power down),
the following events occur:
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load state
conditions.
The charge pump is forced into three-state mode.
The digital clock detect circuitry is reset.
The RFIN input is debiased.
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading and
latching data.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, M1 on the
ADF4110 Family. Table V shows the truth table.
Fastlock Enable Bit
DB9 of the Function Latch is the Fastlock Enable Bit. Only
when this is “1” is Fastlock enabled.
Fastlock Mode Bit
DB10 of the Function Latch is the Fastlock Mode bit. When
Fastlock is enabled, this bit determines which Fastlock Mode is
used. If the Fastlock Mode bit is “0,” Fastlock Mode 1 is
selected and if the Fastlock Mode bit is “1,” Fastlock Mode 2 is
selected.
Timer Counter Control
The user has the option of programming two charge pump currents. The intent is that the Current Setting 1 is used when the
RF output is stable and the system is in a static state. Current
Setting 2 is meant to be used when the system is dynamic and in a
state of change (i.e., when a new output frequency is programmed).
The normal sequence of events is as follows:
Users initially decide what the preferred charge pump currents
are will be. For example, they may choose 2.5 mA as Current
Setting 1 and 5 mA as the Current Setting 2. At the same time
they must also decide how long they want the secondary current to stay active before reverting to the primary current. This
is controlled by the Timer Counter Control Bits DB14 to
DB11 (TC4–TC1) in the Function Latch. The truth table is
given in Table V.
Now, when users wish to program a new output frequency, they
can simply program the AB counter latch with new values for A
and B. At the same time they can set the CP Gain bit to a “1,”
which sets the charge pump with the value in CPI6–CPI4 for a
period of time determined by TC4–TC1. When this time is up,
the charge pump current reverts to the value set by CPI3–CPI1.
At the same time the CP Gain bit in the A, B Counter latch is
reset to 0 and is now ready for the next time that the user wishes
to change the frequency again.
Note that there is an enable feature on the Timer Counter. It is
enabled when Fastlock Mode 2 is chosen by setting the Fastlock
Mode bit (DB10) in the Function Latch to “1.”
Charge Pump Currents
CPI3, CPI2, CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Table V.
Prescaler Value
P2 and P1 in the Function Latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 300 MHz. Thus, with
an RF frequency of 4 GHz, a prescaler value of 16/17 is valid
but a value of 8/9 is not valid.
PD Polarity
Fastlock Mode 1
This bit sets the Phase Detector Polarity Bit. See Table V.
The charge pump current is switched to the contents of Current
Setting 2. The device enters Fastlock by having a “1” written to
the CP Gain bit in the AB counter latch. The device exits
Fastlock by having a “0” written to the CP Gain bit in the AB
counter latch.
CP Three-State
REV. 0
This bit controls the CP output pin. With the bit set high, the
CP output is put into three-state. With the bit set low, the CP
output is enabled.
–15–
ADF4106
THE INITIALIZATION LATCH
Counter Reset Method
When C2, C1 = 1, 1, the Initialization Latch is programmed. This is
essentially the same as the Function Latch (programmed when
C2, C1 = 1, 0).
• Apply VDD.
• Do a Function Latch Load (“10” in two LSBs). As part of
this, load “1” to the F1 bit. This enables the counter reset.
• Do an R Counter Load (“00” in two LSBs).
• Do an AB Counter Load (“01” in two LSBs).
• Do a Function Latch Load (“10” in two LSBs). As part of
this, load “0” to the F1 bit. This disables the counter reset.
However, when the Initialization Latch is programmed there is
an additional internal reset pulse applied to the R and AB
counters. This pulse ensures that the AB counter is at load point
when the AB counter data is latched and the device will begin
counting in close phase alignment.
If the Latch is programmed for synchronous power-down (CE
pin is High; PD1 bit is High; PD2 bit is Low), the internal pulse
also triggers this powerdown. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse
and so close phase alignment is maintained when counting resumes.
When the first AB counter data is latched after initialization, the
internal reset pulse is again activated. However, successive AB
counter loads after this will not trigger the internal reset pulse.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
After initially powering up the device, there are three ways to
program the device.
Initialization Latch Method
• Apply VDD.
• Program the Initialization Latch (“11” in two LSBs of input
word). Make sure that F1 bit is programmed to “0.”
• Do a Function Latch load (“10” in two LSBs of the control
word), making sure that the F1 bit is programmed to a “0.”
• Do an R load (“00” in two LSBs).
• Do an AB load (“01” in two LSBs).
When the Initialization Latch is loaded, the following occurs:
1. The function latch contents are loaded.
2. An internal pulse resets the R, A, B and timeout counters to
load state conditions and also three-states the charge pump.
Note that the prescaler bandgap reference and the oscillator
input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes.
3. Latching the first AB counter data after the initialization
word will activate the same internal reset pulse. Successive
AB loads will not trigger the internal reset pulse unless there
is another initialization.
CE Pin Method
• Apply VDD.
• Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
• Program the Function Latch (10).
• Program the R Counter Latch (00).
• Program the AB Counter Latch (01).
• Bring CE high to take the device out of power-down.
The R and AB counters will now resume counting in close
alignment. Note that after CE goes high, a duration of 1 µs may
be required for the prescaler bandgap voltage and oscillator
input buffer bias to reach steady state.
CE can be used to power the device up and down in order to
check for channel activity. The input register does not need to
be reprogrammed each time the device is disabled and enabled
as long as it has been programmed at least once after VDD was
initially applied.
This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and
three-states the charge pump, but does not trigger synchronous
power-down.
APPLICATION SECTION
Local Oscillator for LMDS Base Station Transmitter
Figure 7 shows the ADF4106 being used with a VCO to produce the LO for an LMDS base station operation in the
5.4 GHz to 5.8 GHz band.
The reference input signal is applied to the circuit at FREFIN
and, in this case, is terminated in 50 Ω. A typical base station
system would have either a TCXO or an OCXO driving the
Reference Input without any 50 Ω termination.
In order to have a channel spacing of 1 MHz at the output, the
10 MHz reference input must be divided by 10, using the on-chip
reference divider of the ADF4106.
The charge pump output of the ADF4106 (Pin 2) drives the
loop filter. In calculating the loop filter component values, a
number of items need to be considered. In this example, the
loop filter was designed so that the overall phase margin for the
system would be 45 degrees. Other PLL system specifications
are given below:
KD = 2.5 mA
KV = 80 MHz/V
Loop Bandwidth = 50 kHz
FREF = 1 MHz
N = 5800
Extra Reference Spur Attenuation = 10 dB
All of these specifications are needed and used to come up with
the loop filter component values shown in Figure 7.
Figure 7 gives a typical phase noise performance of –83 dBc/Hz
at 1 kHz offset from the carrier. Spurs are better than –62 dBc.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives the
RF Output terminal. A T-circuit configuration provides 50 Ω
matching between the VCO output, the RF output and the
RFIN terminal of the synthesizer. Note that the ADF4106 RF
input looks like 50 Ω at 5.8 GHz and so no terminating resistor
is needed. When operating at lower frequencies however, this is
not the case.
In a PLL system, it is important to know when the system is in
lock. In Figure 7, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be programmed to monitor various internal signals in the synthesizer.
One of these is the LD or lock-detect signal.
–16–
REV. 0
ADF4106
VP
VDD
RFOUT
100pF
1000pF
1000pF
FREFIN
AVDD DVDD VP
CP
REFIN
100pF
6.2k
100pF
4.3k
51
18
18
VCC
20pF
V940ME03
18
ADF4106
CE
MUXOUT
CLK
DATA
LE
1, 3, 4, 5, 7, 8,
9, 11, 12, 13
LOCK
DETECT
100pF
RFINA
RFINB
DGND
5.1k
AGND
RSET
CPGND
SPI COMPATIBLE SERIAL BUS
1.5nF
100pF
NOTE
DECOUPLING CAPACITORS (0.1F/10pF) ON AVDD, DVDD,
VP OF THE ADF4106 AND ON VCC OF THE V940ME03 HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 7. Local Oscillator for LMDS Base Station
INTERFACING
ADuC812 Interface
The ADF4106 has a simple SPI-compatible serial interface for
writing to the device. SCLK, SDATA and LE control the data
transfer. When LE (Latch Enable) goes high, the 24 bits which
have been clocked into the input register on each rising edge of
SCLK will get transferred to the appropriate latch. See Figure 1
for the Timing Diagram and Table I for the Latch Truth Table.
Figure 8 shows the interface between the ADF4106 and the
ADuC812 microconverter. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI Master
Mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4106 needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the microconverter to the device. When the third byte has
been written the LE input should be brought high to complete
the transfer.
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz
or one update every 1.2 µs. This is certainly more than adequate
for systems which will have typical lock times in hundreds of
microseconds.
REV. 0
–17–
ADF4106
On first applying power to the ADF4106, it needs at three writes
(one each to the R counter latch, the N counter latch and the
function latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control
power-down (CE input) and to detect lock (MUXOUT configured as lock detect and polled by the port input).
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed will be 166 kHz.
SCLOCK
MOSI
SCLK
ADSP-2181 Interface
Figure 9 shows the interface between the ADF4106 and the
ADSP-21xx Digital Signal Processor. The ADF4106 needs a
24-bit serial word for each latch write. The easiest way to
accomplish this using the ADSP-21xx family is to use the
Autobuffered Transmit Mode of operation with Alternate Framing.
This provides a means for transmitting an entire block of serial
data before an interrupt is generated. Set up the word length for
8 bits and use three memory locations for each 24-bit word. To
program each 24-bit latch, store the three 8-bit bytes, enable the
Autobuffered mode and then write to the transmit register of the
DSP. This last operation initiates the autobuffer transfer.
SDATA
SCLOCK
ADuC812
I/O PORTS
LE
ADF4106
MOSI
SCLK
SDATA
CE
ADSP-21xx
MUXOUT
(LOCK DETECT)
TFS
LE
ADF4106
CE
I/O FLAGS
MUXOUT
(LOCK DETECT)
Figure 8. ADuC812 to ADF4106 Interface
Figure 9. ADSP-21xx to ADF4106 Interface
–18–
REV. 0
ADF4106
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Thin Shrink SO Package (TSSOP)
(RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
8
PIN 1
0.0433 (1.10)
MAX
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
8
0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) 0
BSC
0.0075 (0.19) 0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
20-Leadless Frame Chip Scale Package (LFCSP)
(CP-20)
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
0.024 (0.60)
0.017 (0.42)
16
0.009 (0.24)
15
0.157 (4.0)
BSC SQ
PIN 1
INDICATOR
TOP
VIEW
0.148 (3.75)
BSC SQ
0.031 (0.80) MAX
0.026 (0.65) NOM
12 MAX
0.035 (0.90) MAX
0.033 (0.85) NOM
SEATING
PLANE
0.020 (0.50)
BSC
0.008 (0.20)
REF
0.012 (0.30)
0.009 (0.23)
0.007 (0.18)
0.030 (0.75)
0.022 (0.60)
0.014 (0.50)
11
10
1
0.080 (2.25)
0.083 (2.10) SQ
0.077 (1.95)
6
0.080 (2.00)
REF
0.002 (0.05)
0.0004 (0.01)
0.0 (0.0)
–19–
20
BOTTOM
VIEW
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
REV. 0
0.010 (0.25)
MIN
5
–20–
PRINTED IN U.S.A.
C02720–.8–10/01(0)

Open as PDF

Similar pages