Intersil ISL8016IR33Z 6a low quiescent current high efficiency synchronous buck regulator Datasheet

6A Low Quiescent Current High Efficiency Synchronous
Buck Regulator
ISL8016
Features
The ISL8016 is a high efficiency, monolithic, synchronous
step-down DC/DC converter that can deliver up to 6A continuous
output current from a 2.7V to 5.5V input supply. The output
voltage is adjustable from 0.6V to VIN. With an adjustable current
limit, reverse current protection, pre-bias start and over
temperature protection the ISL8016 offers a highly robust power
solution. It uses current control architecture to deliver fast
transient response and excellent loop stability.
• High Efficiency Synchronous Buck Regulator with up to 97%
Efficiency
The ISL8016 integrates a pair of low ON-resistance P-Channel
and N-Channel internal MOSFETs to maximize efficiency and
minimize external component count. 100% duty-cycle operation
allows less than 200mV dropout at 6A output current. Adjustable
frequency and synchronization allow the ISL8016 to be used in
applications requiring low noise. Paralleling capability with
phase interleaving allows the IC to support >6A output current
while offering reduced input and output noise.
The ISL8016 can be configured for discontinuous or forced
continuous operation at light load. Forced continuous operation
reduces noise and RF interference while discontinuous mode
provides high efficiency by reducing switching losses at light loads.
The ISL8016 is offered in a space saving 20 Ld 3x4 QFN lead free
package with exposed pad lead frames for excellent thermal
performance. The complete converter occupies less than 0.15in2
area.
Various fixed output voltages are available upon request. See
Ordering Information on page 2 for more detail.
• 1% Reference Accuracy Over-Temperature/Load/Line
• Fixed Output Voltage Option
• ±10% Output Voltage Margining
• Adjustable Current Limit
• Current Sharing Capable
• Start-up with Pre-Biased Output
• Internal Soft-Start - 1ms or Adjustable, Internal/External
Compensation
• Soft-Stop Output Discharge During Disabled
• Adjustable Frequency from 500kHz to 4MHz - Default at 1MHz
• External Synchronization up to 4MHz - Master to Slave Phase
Shifting Capability
• Peak current limiting, Hiccup Mode Short Circuit Protection
and Over-Temperature Protection‘
Applications
• DC/DC POL Modules
• µC/µP, FPGA and DSP Power
• Plug-in DC/DC Modules for Routers and Switchers
• Portable Instruments
• Test and Measurement Systems
• Li-ion Battery Powered Devices
100
EFFICIENCY (%)
95
90
3.3VOUT PFM
85
3.3VOUT PWM
80
75
70
0.0
1.0
2.0
3.0
IOUT (A)
4.0
5.0
6.0
FIGURE 1. EFFICIENCY T = +25°C VIN = 5V
May 5, 2011
FN7616.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL8016
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
OUTPUT VOLTAGE (V)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL8016IRAJZ
016A
Adjustable
-40 to +85
20 Ld 3x4 QFN
L20.3x4
ISL8016IR12Z
016W
1.2V
-40 to +85
20 Ld 3x4 QFN
L20.3x4
ISL8016IR15Z
016B
1.5V
-40 to +85
20 Ld 3x4 QFN
L20.3x4
ISL8016IR18Z
016C
1.8V
-40 to +85
20 Ld 3x4 QFN
L20.3x4
ISL8016IR25Z
016F
2.5V
-40 to +85
20 Ld 3x4 QFN
L20.3x4
ISL8016IR33Z
016N
3.3V
-40 to +85
20 Ld 3x4 QFN
L20.3x4
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8016. For more information on MSL please see techbrief TB363.
Pin Configuration
PGND
PGND
SGND
VFB
ISL8016
(20 LD QFN)
TOP VIEW
20
19
18
17
PGND
1
16
COMP
PHASE
2
15
SS
PHASE
3
14
ISET
PAD
2
VIN
5
12
FS
VIN
6
11
EN
7
8
9
10
SYNCIN
VSET
SYNCOUT
13
PG
4
VIN
PHASE
FN7616.1
May 5, 2011
ISL8016
Pin Descriptions
PIN
SYMBOL
1, 19, 20
PGND
Power ground.
2, 3, 4
PHASE
Switching node connection. Connect to one terminal of the inductor.
5, 6, 7
VIN
Input supply voltage. Connect two 22µF ceramic capacitors to power ground.
8
PG
Power-good is an open-drain output. Use 10kΩ to 100kΩ pull-up resistor connected between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms from the output reaching regulation.
9
SYNCOUT
This pin outputs a 250µA current source that is turned on at the rising edge of the internal clock or
SYNCIN. When SYNCOUT voltage reaches 1V, a reset circuit will activate and discharge SYNCOUT to 0V.
SYNCOUT is held at 0V in PFM light load to reduce quiescent current.
10
SYNCIN
Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state if SYNCIN
is floating.
11
EN
Regulator enable pin. Enables the output when driven to high. Shuts down the chip and discharges the
output capacitor when driven to low. There is an internal 1MΩ pull-down resistor to prevent an
undefined logic state in case of EN pin float.
12
FS
This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz
and configured for internal compensation if FS is connected to VIN.
13
VSET
VSET is the output margining setting of the regulators. Connect to SGND for -10%, keep it floating for
no margining, and connect to VIN for +10%.
14
ISET
ISET is the peak output current limit and SKIP current limit setting of the regulators. Connect to SGND
for 2A, to VIN for 4A, and keep it floating for 6A.
15
SS
16, 17
COMP, VFB
18
SGND
Signal ground.
EPAD
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many
vias as possible under the pad connecting to the system GND plane for optimal thermal performance.
3
DESCRIPTION
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor
from SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
The feedback network of the regulator, VFB, is the negative input to the transconductance error
amplifier. COMP is the output of the amplifier if the FS resistor is used. If internal compensation is used
(FS = VIN), the comp pin should be tied to SGND. The output voltage is set by an external resistor divider
connected to VFB. With a properly selected divider, the output voltage can be set to any voltage
between VIN and the 0.6V reference. While internal compensation offers a solution for many typical
applications, an external compensation network may offer improved performance for some designs.
In addition to regulation, VFB is also used to determine the state of PG.
Short VFB to OUTPUT when using one of the available fixed VOUT options.
FN7616.1
May 5, 2011
ISL8016
Typical Application Diagrams
INPUT
2.7V TO 5.5V
VIN
EN
C1
2x22µF
PHASE
C2
2x47µF
ISL8016
R1
100k
OUTPUT
1.8V/6A
L
1.0µH
R2
200k
PGND
C3*
10pF
PG
SYNCIN
SYNCOUT
VIN
FS
ISET
VSET
SGND
R3
100k
VFB
COMP
SS
* C3 is optional. Recommend
putting a placeholder for it. Check
loop analysis first before use.
FIGURE 2. TYPICAL APPLICATION DIAGRAM - SINGLE CHIP 6A
TABLE 1. COMPONENT VALUE SELECTION
VOUT
0.8V
1.2V
1.5V
1.8V
2.5V
3.3V
3.6V
C1
44µF
44µF
44µF
44µF
44µF
44µF
44µF
C2 (or C8)
2x47µF
2x47µF
2x47µF
2x47µF
2x47µF
2x47µF
2x47µF
C3 (or C5)
10pF
10pF
10pF
10pF
10pF
10pF
10pF
L1 (or L2)
0.47~1µH
0.47~1µH
0.47~1µH
0.68~1.5µH
0.68~1.5µH
1~2.2µH
1~2.2µH
R2 (or R5)
33k
100k
150k
200k
316k
450k
500k
R3 (or R6)
100k
100k
100k
100k
100k
100k
100k
4
FN7616.1
May 5, 2011
ISL8016
INPUT
2.7V TO 5.5V
VIN
PHASE
C2
2 x 47µF
EN
C1
47µF
R1
100k
PG
SYNCOUT
R4
196k
R3
100k
SGND
ISET
VSET
COMP
SS
VIN
EN
PG
C4
470pF
R3
150k
C6
22nF
C7
47µF
C3*
10pF
VFB
FS
INPUT 2.7V TO 5.5V
R2
200k
ISL8016
(MASTER) PGND
SYNCIN
VIN
OUTPUT
1.8V/12A
L1
1.0µH
PHASE
ISL8016
(SLAVE)
C5
10pF
L2
1.0µH
C8
2 x 47µF
PGND
SYNCOUT
SYNCIN
FS
C13
100pF
R5
249k
ISET
VSET
SS
SGND
VFB
COMP
* C3 is optional. Recommend
putting a placeholder for it. Check
loop analysis first before use.
FIGURE 3. TYPICAL APPLICATION DIAGRAM - MULTI CHIP CONFIGURATION 12A
5
FN7616.1
May 5, 2011
ISL8016
Block Diagram
COMP
SS
SHUTDOWN
FS
SYNCIN
SYNCOUT
55pF
Soft
SOFT
START
SHUTDOWN
168k
250µA
VDD
+
BANDGAP
VREF
+
EN
+
EAMP
VIN
OSCILLATOR
COMP
-
-
P
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
HS DRIVER
VSET
3pF
+
PHASE
LS
DRIVER
N
PGND
VFB
SLOPE
Slope
COMP
6k
0.8V
+
-
CSA
-
+
OV
+
OCP
-
0.85*VREF
+
UV
ISET
ISET
THRESHOLD
+
SKIP
-
PG
1ms
DELAY
NEG CURRENT
SENSING
SGND
ZERO-CROSS
SENSING
0.1V
SCP
+
100
SHUTDOWN
FIGURE 4. FUNCTIONAL BLOCK DIAGRAM
6
FN7616.1
May 5, 2011
ISL8016
Absolute Maximum Ratings (Reference to GND)
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.8V (DC) or 7V (20ms)
EN, FS, ISET, PG, SYNCOUT, SYNCIN VFB, VSET . . . . . . . -0.3V to VIN+0.3V
PHASE . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
COMP, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Rating
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1500V
Latch Up (Tested per JESD-78A; Class 2, Level A) . . . . . .100mA @ +85°C
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
3x4 QFN Package (Notes 4, 5) . . . . . . . . . .
42
5
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 6A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside.
Analog Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions
and the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical
values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
2.5
2.7
V
INPUT SUPPLY
VIN Undervoltage Lockout Threshold
VUVLO
Rising, no load
Falling, no load
Quiescent Supply Current
IVIN
Shut Down Supply Current
ISD
2.2
2.4
V
SYNCIN = GND, no load at the output
70
µA
SYNCIN = GND, no load at the output and no
switches switching
70
90
µA
SYNCIN = VIN, FS = 1MHz, no load at the output
8
15
mA
SYNCIN = GND, VIN = 5.5V, EN = low
5
7
µA
OUTPUT REGULATION
Reference Voltage - ISL8016IRAJZ
VREF
VSET = VIN
0.651
0.660
0.669
V
VSET = FLOAT
0.594
0.600
0.606
V
VSET = SGND
0.531
0.540
0.549
V
Output Voltage - ISL8016IR12Z
VVFB
VSET = FLOAT
1.188
1.200
1.212
V
Output Voltage - ISL8016IR15Z
VVFB
VSET = FLOAT
1.485
1.500
1.515
V
Output Voltage - ISL8016IR18Z
VVFB
VSET = FLOAT
1.782
1.800
1.818
V
Output Voltage - ISL8016IR25Z
VVFB
VSET = FLOAT
2.475
2.500
2.525
V
Output Voltage - ISL8016IR33Z
VVFB
VSET = FLOAT
3.266
3.300
3.333
V
Output Voltage Margining
VVFB
VSET = VIN, Percent of OUTPUT changed
9.5
10
10.5
%
-10.5
-10
-9.5
%
VSET = SGND, Percent of OUTPUT changed
VFB Bias Current - ISL8016IRAJZ
IVFB
VFB = 0.75V
Fixed Output VFB Bias Current - ISL8016IRXXZ
IVFB
VSET = FLOAT, VFB = 10% above OUTPUT
Line Regulation
VIN = VO + 0.5V to 5.5V (minimal 2.7V)
Soft-Start Ramp Time Cycle
SS = SGND
Soft-Start Charging Current
ISS
7
VSS = 0.1V
1.4
0.1
µA
6
µA
0.2
%/V
1
ms
1.8
2.2
µA
FN7616.1
May 5, 2011
ISL8016
Analog Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions
and the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical
values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
OVERCURRENT PROTECTION
Current Limit Blanking Time
tOCON
17
Clock
pulses
Overcurrent and Auto Restart Period
tOCOFF
8
SS cycle
Positive Peak Current Limit
IPLIMIT
Peak Skip Limit
ISKIP
ISET = FLOAT
7.7
9.5
11.5
A
ISET = VIN
5.5
6.5
8.0
A
ISET = SGND
3
4.0
5
A
ISET = FLOAT
1.6
2
2.4
A
ISET = VIN
1.0
1.35
1.6
A
ISET = SGND
Zero Cross Threshold
0.85
-300
Negative Current Limit
INLIMIT
-4.25
-3
A
300
mA
-1.75
A
COMPENSATION
Error Amplifier Trans-Conductance
Trans-Resistance
FS = VIN
100
µA/V
FS with Resistor
200
µA/V
0.138
0.16
Ω
VIN = 5V, IO = 200mA
31
45
mΩ
VIN = 2.7V, IO = 200mA
44
55
mΩ
VIN = 5V, IO = 200mA
19
35
mΩ
VIN = 2.7V, IO = 200mA
25
50
mΩ
RT
0.117
PHASE
P-Channel MOSFET ON-Resistance
N-Channel MOSFET ON-Resistance
PHASE Maximum Duty Cycle
%
100
PHASE Minimum On-Time
SYNCIN = High
140
ns
OSCILLATOR
Nominal Switching Frequency
Fsw
FS = VIN
800
1000
1200
kHz
FS with RS = 402kΩ
450
525
600
kHz
FS with RS = 42.4kΩ
3300
3900
4500
kHz
0.70
0.75
0.80
V
SYNCIN Logic Low to High Transition Range
SYNCIN Hysteresis
0.15
SYNCIN Logic Input Leakage Current
SYNCOUT Charging Current
VIN = 3.6V
ISO
PWM
210
PFM
V
3.6
5
µA
250
290
µA
0
SYNCOUT Voltage Low
µA
0.3
V
0.3
V
1
2
ms
PG Pin Leakage Current
0.01
0.1
µA
OVP PG Rising Threshold
0.80
PG
Output Low Voltage
Delay Time (Rising Edge)
0.5
UVP PG Rising Threshold
80
8
85
V
90
%
FN7616.1
May 5, 2011
ISL8016
Analog Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions
and the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical
values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
UVP PG Hysteresis
5
%
PGOOD Delay Time (Falling Edge)
7
µs
ISET, VSET
Logic Input Low
Logic Input Float
0.5
Logic Input High
0.9
Logic Input Leakage Current
0.4
V
0.8
V
V
0.1
1
µA
0.4
V
EN
Logic Input Low
Logic Input High
0.9
V
EN Logic Input Leakage Current
0.1
1
µA
Thermal Shutdown
150
°C
Thermal Shutdown Hysteresis
25
°C
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
9
FN7616.1
May 5, 2011
ISL8016
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V,
100
100
95
95
2.5VOUT
90
2.5VOUT
85
1.8VOUT
EFFICIENCY (%)
EFFICIENCY (%)
EN = 3.3V, SYNCIN = VIN, L = 1.0µH, C1 = 2x22µF, C2 = 4x22µF, VOUT = 1.8V, IOUT = 0A to 6A.
1.5VOUT
80
1.2VOUT
75
90
85
1.2VOUT
80
75
70
0.0
1.0
2.0
3.0
IOUT (A)
4.0
5.0
70
0.0
6.0
FIGURE 5. EFFICIENCY vs LOAD (1MHz 3.3VIN PWM)
0.3
0.6
0.9
IOUT (A)
1.2
1.5
1.8
FIGURE 6. EFFICIENCY vs LOAD (1MHz 3.3VIN PFM)
100
100
3.3VOUT
95
3.3VOUT
95
90
EFFICIENCY (%)
EFFICIENCY (%)
1.5VOUT
1.8VOUT
2.5VOUT
1.8VOUT
85
1.5VOUT
1.2VOUT
80
75
90
85
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
80
75
70
0.0
1.0
2.0
3.0
IOUT (A)
4.0
5.0
70
0.0
6.0
FIGURE 7. EFFICIENCY vs LOAD (1MHz 5VIN PWM)
0.3
0.6
0.9
IOUT (A)
1.2
1.5
1.8
FIGURE 8. EFFICIENCY vs LOAD (1MHz 5VIN PFM)
1.8
1.84
1.5
1.83
5VIN PWM MODE
1.82
3.3VIN PWM MODE
0.9
VOUT (V)
PD (W)
1.2
0.6
1.80
0.3
1.79
0
0A LOAD
3A LOAD
1.81
6A LOAD
0.0
1.0
2.0
3.0
IOUT (A)
4.0
5.0
FIGURE 9. POWER DISSIPATION vs LOAD (1MHz, VOUT = 1.8V)
10
6.0
1.78
2.5
3.0
3.5
4.0
VIN (V)
4.5
5.0
5.5
FIGURE 10. VOUT REGULATION vs VIN (PWM VOUT = 1.8V)
FN7616.1
May 5, 2011
ISL8016
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V,
1.84
1.24
1.83
1.23
1.82
1.22
1.81
3A LOAD
VOUT (V)
VOUT (V)
EN = 3.3V, SYNCIN = VIN, L = 1.0µH, C1 = 2x22µF, C2 = 4x22µF, VOUT = 1.8V, IOUT = 0A to 6A. (Continued)
0A LOAD
3.3VIN PWM MODE
3.3VIN PFM MODE
1.21
1.80
1.20
1.79
1.19 5VIN PWM MODE
5VIN PFM MODE
6A LOAD
1.78
2.5
3.0
3.5
4.0
VIN (V)
4.5
5.0
1.18
0.0
5.5
FIGURE 11. VOUT REGULATION vs VIN (PFM VOUT = 1.8V)
1.82
5VIN PWM MODE
1.51
VOUT (V)
VOUT (V)
1.52
3.3VIN PFM MODE
1.50
5.0
6.0
3.3VIN PWM MODE
5VIN PWM MODE
3.3VIN PFM MODE
1.81
1.80
5VIN PFM MODE
1.49
1.0
2.0
3.0
IOUT (A)
5VIN PFM MODE
1.79
4.0
5.0
1.78
0.0
6.0
FIGURE 13. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V)
1.0
2.0
3.0
IOUT (A)
4.0
5.0
6.0
FIGURE 14. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V)
3.37
2.54
3.36
2.53
3.3VIN PWM MODE
5VIN PWM MODE
3.35
5VIN PWM MODE
VOUT (V)
2.52
VOUT (V)
4.0
1.83
3.3VIN PWM MODE
3.3VIN PFM MODE
3.34
3.33
2.50
5VIN PFM MODE
2.49
2.48
0.0
3.0
IOUT (A)
1.84
1.53
2.51
2.0
FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V)
1.54
1.48
0.0
1.0
1.0
2.0
3.0
IOUT (A)
3.32
4.0
5.0
FIGURE 15. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V)
11
5VIN PFM MODE
6.0
3.31
0.0
1.0
2.0
3.0
IOUT (A)
4.0
5.0
6.0
FIGURE 16. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V)
FN7616.1
May 5, 2011
ISL8016
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V,
EN = 3.3V, SYNCIN = VIN, L = 1.0µH, C1 = 2x22µF, C2 = 4x22µF, VOUT = 1.8V, IOUT = 0A to 6A. (Continued)
PHASE 2V/DIV
PHASE 2V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL 1A/DIV
FIGURE 17. STEADY STATE OPERATION AT NO LOAD (PWM)
IL 1A/DIV
FIGURE 18. STEADY STATE OPERATION AT NO LOAD (PFM)
PHASE 2V/DIV
VOUT RIPPLE 50mV/DIV
IL 2A/DIV
IL 2A/DIV
VOUT RIPPLE 20mV/DIV
FIGURE 19. STEADY STATE OPERATION WITH FULL LOAD
FIGURE 20. LOAD TRANSIENT (PWM)
VOUT RIPPLE 50mV/DIV
EN 2V/DIV
IL 52A/DIV
VOUT 1V/DIV
IL 1A/DIV
PG 5V/DIV
FIGURE 21. LOAD TRANSIENT (PFM)
12
FIGURE 22. SOFT-START WITH NO LOAD (PWM)
FN7616.1
May 5, 2011
ISL8016
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V,
EN = 3.3V, SYNCIN = VIN, L = 1.0µH, C1 = 2x22µF, C2 = 4x22µF, VOUT = 1.8V, IOUT = 0A to 6A. (Continued)
EN 2V/DIV
EN 2V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 1A/DIV
IL 1A/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 23. SOFT-START AT NO LOAD (PFM)
FIGURE 24. SOFT-START WITH PRE-BIASED 1V
EN 2V/DIV
EN 2V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 1A/DIV
IL 2A/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 25. SOFT-START AT FULL LOAD
FIGURE 26. SOFT-DISCHARGE SHUTDOWN
PHASE 5V/DIV
PHASE 5V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL 2A/DIV
IL 0.5A/DIV
SYNC 5V/DIV
FIGURE 27. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 2MHz
13
SYNC 5V/DIV
FIGURE 28. STEADY STATE OPERATION AT FULL LOAD WITH
FREQUENCY = 2MHz
FN7616.1
May 5, 2011
ISL8016
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V,
EN = 3.3V, SYNCIN = VIN, L = 1.0µH, C1 = 2x22µF, C2 = 4x22µF, VOUT = 1.8V, IOUT = 0A to 6A. (Continued)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL 2A/DIV
IL 0.2A/DIV
SYNC 5V/DIV
SYNC 5V/DIV
FIGURE 29. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 4MHz
FIGURE 30. STEADY STATE OPERATION AT FULL LOAD (PWM) WITH
FREQUENCY = 4MHz
PHASE 5V/DIV
PHASE 5V/DIV
IL 2A/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 5A/DIV
PG 5V/DIV
FIGURE 31. OUTPUT SHORT CIRCUIT
14
PG 5V/DIV
FIGURE 32. OUTPUT SHORT CIRCUIT RECOVERY
FN7616.1
May 5, 2011
ISL8016
Theory of Operation
VEAMP
The ISL8016 is a step-down switching regulator optimized for
battery-powered handheld applications. The regulator operates at
1MHz fixed default switching frequency when FS is connected to VIN.
By connecting a resistor from FS to SGND, the operating frequency
may be adjusted from 500kHz to 4MHz. Unless forced, PWM is
chosen (SYNCIN pulled HI), the regulator will allow PFM operation
and reduce switching frequency at light loading to maximize
efficiency. In this condition, no load quiescent is typically 70µA.
VCSA
DUTY
CYCLE
IL
PWM Control Scheme
VOUT
Pulling the SYNCIN high (>0.8V) forces the converter into PWM
mode, regardless of output current. The ISL8016 employs the
current-mode pulse-width modulation (PWM) control scheme for fast
transient response and pulse-by-pulse current limiting. Figure 4
shows the block diagram. The current loop consists of the oscillator,
the PWM comparator, current sensing circuit and the slope
compensation for the current loop stability. The slope compensation
is 360mV/Ts. Current sense resistance, Rt, is typically 0.138V/A. The
control reference for the current loop comes from the error
amplifier's (EAMP) output.
FIGURE 33. PWM OPERATION WAVEFORMS
SKIP Mode
Pulling the SYNCIN pin LO (<0.4V) forces the converter into PFM
mode. The ISL8016 enters a pulse-skipping mode at light load to
minimize the switching loss by reducing the switching frequency.
Figure 34 illustrates the skip-mode operation. A zero-cross
sensing circuit shown in Figure 4 monitors the N-FET current for
zero crossing. When 8 consecutive cycles of the inductor current
crossing zero are detected, the regulator enters the skip mode.
During the eight detecting cycles, the current in the inductor is
allowed to become negative. The counter is reset to zero when
the current in any cycle does not cross zero.
The PWM operation is initialized by the clock from the oscillator.
The P-Channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA and the slope compensation
reaches the control reference of the current loop, the PWM
comparator EAMP output sends a signal to the PWM logic to turn
off the P-FET and turn on the N-Channel MOSFET. The N-FET stays
on until the end of the PWM cycle. Figure 33 shows the typical
operating waveforms during the PWM operation. The dotted lines
illustrate the sum of the slope compensation ramp and the
current-sense amplifier’s CSA output.
Once the skip mode is entered, the pulse modulation starts being
controlled by the SKIP comparator shown in Figure 34. Each pulse
cycle is still synchronized by the PWM clock. The P-FET is turned on
at the clock's rising edge and turned off when the output is higher
than 1.5% of the nominal regulation or when its current reaches the
peak Skip current limit value. Then the inductor current is
discharging to 0A and stays at zero. The internal clock is disabled.
The output voltage reduces gradually due to the load current
discharging the output capacitor. When the output voltage drops to
the nominal voltage, the P-FET will be turned on again at the rising
edge of the internal clock as it repeats the previous operations.
The output voltage is regulated by controlling the VEAMP voltage
to the current loop. The bandgap circuit outputs a 0.6V reference
voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during the
start-up and will be discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage error signal
to a current output. The voltage loop is internally compensated
with the 55pF and 168kΩ RC network. The maximum EAMP
voltage output is precisely clamped to 2.4V.
PWM
0.8V
The regulator resumes normal PWM mode operation when the
output voltage drops 1.5% below the nominal voltage.
PFM
PWM
SYNCOUT
CLOCK
8 CYCLES
IL
PFM CURRENT LIMIT
LOAD CURRENT
0
NOMINAL +1.5%
VOUT
NOMINAL
NOMINAL -1.5%
FIGURE 34. SKIP MODE OPERATION WAVEFORMS
15
FN7616.1
May 5, 2011
ISL8016
Frequency Adjust
The frequency of operation is fixed at 1MHz and internal
compensation when FS is tied to VIN. Adjustable frequency
ranges from 500kHz to 4MHz via a simple resistor connecting FS
to SGND according to Equation 1:
220 ⋅ 10 3
R T [ kΩ ] = ------------------------------ – 14
f OSC [ kHz ]
PHASE1
CLOCK1
(EQ. 1)
SYNCIN_S
Figure 35 is a graph of the measured Frequency vs RT for a VIN of
2.7V and 5.5V.
SYNCOUT_M
w/Cap
0.8V
20nsDELAY
PHASE2
4200
FS (kHz)
0.75V
3500
FIGURE 36. SYNCHRONIZATION WAVEFORMS
2800
Figure 37 is a graph of the Master to Slave phase shift vs SYNCOUT
capacitance for 1MHz switching operation.
2100
300
VIN = 5.5V
1400
250
700
0
0
70
140
210
280
350
420
RTs (kΩ)
FIGURE 35. FREQUENCY vs RTs
Synchronization Control
SYNCOUT is a 250µA current pulse signal output trigger on by
rising edge of the clock or SYNCIN signal (whichever is greater in
frequency) to dive other ISL8016 and avoid system’s beat
frequencies effect. See Figure 36 for more detail. The current
pulse is terminated and SYNCOUT is discharged to 0V after 0.8V
threshold is reached. SYNCOUT is 0V if the regulator operates at
light PFM load.
To implement time shifting between the master circuit to the
slave, it is recommended to add a capacitor, C13 as shown in
Figure 3. The time delay from SYNCOUT_Master to SYNCIN_Slave
as shown in Figure 3 is calculated in pF using Equation 2:
(EQ. 2)
Where t is the desired time shift between the master and the
slave circuits in ns. Care must be taken to include PCB parasitic
capacitance of ~3pF to 10pF.
The maximum should be limited to 1/Fs-100ns to insure that
SYNCOUT has enough time to discharge before the next cycle
starts.
16
200
150
PHASE SHIFT
MEASUREMENT
100
50
The ISL8016 can be synchronized from 500kHz to 4MHz by an
external signal applied to the SYNCIN pin. SYNCIN frequency should
be greater than 50% of internal clock frequency. The rising edge on
the SYNCIN triggers the rising edge of the PHASE pulse. Make sure
that the minimum on time of the PHASE node is greater than
140ns.
C 13 ( pF ) = 0.333 ⋅ ( t – 20 ) ( ns )
PHASE SHIFT (°)
VIN = 2.7V
0
PHASE SHIFT
CALCULATION
0
40
80
120
160
200
240
C13 (pF)
FIGURE 37. PHASE SHIFT vs CAPACITANCE
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA
output with the OCP comparator, as shown in Figure 4. The current
sensing circuit has a gain of 138mV/A, from the P-FET current to
the CSA output. When the CSA output reaches a threshold set by
ISET, the OCP comparator is tripped to turn off the P-FET
immediately. See “Analog Specifications” on page 7 of the OCP
threshold for various ISET configurations. The overcurrent function
protects the switching converter from a shorted output by
monitoring the current flowing through the upper MOSFET.
Upon detection of overcurrent condition, the upper MOSFET will
be immediately turned off and will not be turned on again until
the next switching cycle. Upon detection of the initial overcurrent
condition, the overcurrent fault counter is set to 1. If, on the
subsequent cycle, another overcurrent condition is detected, the
OC fault counter will be incremented. If there are 17 sequential
OC fault detections, the regulator will be shut down under an
overcurrent fault condition. An overcurrent fault condition will
result in the regulator attempting to restart in a hiccup mode
within the delay of eight soft-start periods. At the end of the eight
soft-start wait period, the fault counters are reset and soft-start is
attempted again. If the overcurrent condition goes away during
the delay of eight soft-start periods, the output will resume back
into regulation point after hiccup mode expires.
FN7616.1
May 5, 2011
ISL8016
Similar to the overcurrent, the negative current protection is
realized by monitoring the current across the low-side N-FET, as
shown in Figure 4. When the valley point of the inductor current
reaches -3A for 4 consecutive cycles, both P-FET and N-FET are off.
The 100Ω in parallel to the N-FET will activate discharging the
output into regulation. The control will begin to switch when output
is within regulation. The regulator will be in PFM for 20µs before
switching to PWM if necessary.
PG
PG is an open-drain output of a window comparator that
continuously monitors the buck regulator output voltage. PG is
actively held low when EN is low and during the buck regulator
soft-start period. After 1ms delay of the soft-start period, PG
becomes high impedance as long as the output voltage is within
nominal regulation voltage set by VFB. When VFB drops 15%
below or raises 0.8V above the nominal regulation voltage, the
ISL8016 pulls PG low. Any fault condition forces PG low until the
fault condition is cleared by attempts to soft-start. For logic level
output voltages, connect an external pull-up resistor, R1, between
PG and VIN. A 100kΩ resistor works well in most applications.
Figure 38 is a comparison between measured and calculated
output soft-start time versus Css capacitance.
18
15
12
VSS (ms)
Negative Current Protection
SS (ms)
MEASUREMENT
9
6
SS (ms)
CALCULATION
3
0
0
8
16
24
32
40
48
CSS (nF)
FIGURE 38. SOFT-START TIME vs CSS
Enable
When the input voltage is below the undervoltage lock-out (UVLO)
threshold, the regulator is disabled.
The enable (EN) input allows the user to control the turning on or
off of the regulator for purposes such as power-up sequencing.
When the regulator is enabled, there is typically a 600µs delay
for waking up the bandgap reference and then the soft start-up
begins.
Soft Start-Up
Discharge Mode (Soft-Stop)
The soft start-up reduces the in-rush current during the start-up.
The soft-start block outputs a ramp reference to the input of the
error amplifier. This voltage ramp limits the inductor current as
well as the output voltage speed so that the output voltage rises
in a controlled fashion. When VFB is less than 0.1V at the
beginning of the soft-start, the switching frequency is reduced to
200kHz so that the output can start-up smoothly at light load
condition. During soft-start, the IC operates in the SKIP mode to
support pre-biased output condition.
When a transition to shutdown mode occurs or the VIN UVLO is
set, the outputs discharge to GND through an internal 100Ω
switch. The discharge mode is disabled if SS is tied to an external
capacitor.
UVLO
Tie SS to SGND for an internal soft-start of approximately 1ms.
Connect a capacitor from SS to SGND to adjust the soft-start
time. This capacitor, along with an internal 1.6µA current source
sets the soft-start interval of the converter, tSS.
C SS [ μF ] = 3.33 ⋅ t SS [ s ]
(EQ. 3)
CSS must be less than 33nF to insure proper soft-start reset after
fault condition.
Power MOSFETs
The power MOSFETs are optimized for best efficiency. The
ON-resistance for the P-FET is typically 30mΩ and the
ON-resistance for the N-FET is typically 20mΩ.
100% Duty Cycle
The ISL8016 features 100% duty cycle operation to maximize
the battery life. When the battery voltage drops to a level that the
ISL8016 can no longer maintain the regulation at the output, the
regulator completely turns on the P-FET. The maximum dropout
voltage under the 100% duty-cycle operation is the product of the
load current and the ON-resistance of the P-FET.
Thermal Shutdown
The ISL8016 has built-in thermal protection. When the internal
temperature reaches +150°C, the regulator is completely shut
down. As the temperature drops to +125°C, the ISL8016 resumes
operation by stepping through the soft-start.
17
FN7616.1
May 5, 2011
ISL8016
Applications Information
3.0
Output Inductor and Capacitor Selection
2.5
VO ⎞
⎛
V O • ⎜ 1 – --------⎟
V IN⎠
⎝
ΔI = -----------------------------------L • fS
VIN = 5V
2.0
VOUT (V)
To consider steady state and transient operations, ISL8016
typically uses a 1.0µH output inductor. The higher or lower
inductor value can be used to optimize the total converter system
performance. For example, for higher output voltage 3.3V
application, in order to decrease the inductor current ripple and
output voltage ripple, the output inductor value can be increased.
It is recommended to set the ripple inductor current
approximately 30% of the maximum output current for optimized
performance. The inductor ripple current can be expressed as
shown in Equation 4:
1.5
1.0
VIN = 3.3V
0.5
0.0
0.5
The ISL8016 uses an internal compensation network and the
output capacitor value is dependent on the output voltage. The
ceramic capacitor is recommended to be X5R or X7R.
In Table 1, the minimum output capacitor value is given for the
different output voltages to make sure that the whole converter
system is stable. Additional output capacitance may be added
for improved transient response.
Output Voltage Selection
The output voltage of the regulator can be programmed via an
external resistor divider that is used to scale the output voltage
relative to the internal reference voltage and feed it back to the
inverting input of the error amplifier (refer to Figure 2).
The output voltage programming resistor, R2, will depend on the
value chosen for the feedback resistor and the desired output
voltage of the regulator. The value for the feedback resistor is
typically between 10kΩ and 100kΩ, as shown in Equation 5.
VSET marginally adjusts VFB according to the “Analog
Specifications” on page 7.
Figure 39 is the recommended minimum output voltage setting
vs operational frequency in order to avoid the minimum On-Time
specification.
3.0
3.5
4.0
Input Capacitor Selection
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current flowing back to the
battery rail. At least two 22µF X5R or X7R ceramic capacitors are
a good starting point for the input capacitor selection.
Loop Compensation Design
When there is an external resistor connected from FS to SGND,
the COMP pin is active for external loop compensation. The
ISL8016 uses constant frequency peak current mode control
architecture to achieve fast loop transient response. An accurate
current sensing pilot device in parallel with the upper MOSFET is
used for peak current control signal and overcurrent protection.
The inductor is not considered as a state variable since its peak
current is constant, and the system becomes single order
system. It is much easier to design a type II compensator to
stabilize the loop than to implement voltage mode control. Peak
current mode control has inherent input voltage feed-forward
function to achieve good line regulation. Figure 40 shows the
small signal model of the synchronous buck regulator.
^
IIN
(EQ. 5)
If the output voltage desired is 0.6V, then R3 is left unpopulated
and R2 is shorted. There is a leakage current from VIN to
PHASE. It is recommended to preload the output with 10µA
minimum. Capacitance, C3, maybe added to improve transient
performance. A good starting point for C3 can be determined by
choosing a value that provides an 80kHz corner frequency
with R2.
2.0
2.5
FREQUENCY (MHz)
^
VIN
+
VO
R 2 = R 3 ⎛ ---------- – 1⎞
⎝ VFB
⎠
1.5
FIGURE 39. MINIMUM VOUT vs FREQUENCY
(EQ. 4)
The inductor’s saturation current rating needs to be at least
larger than the peak current. The ISL8016 protects the typical
peak current of 9A. The saturation current needs be over 12A for
maximum output current application.
1.0
^
ILd
1:D
^
IL
LP
^
vo
RLP
^
VINd
+
RT
Rc
Ro
Co
Ti(S)
d^
K
Fm
+
He(S)
TV(S)
^
VCOMP
-Av(S)
FIGURE 40. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
18
FN7616.1
May 5, 2011
ISL8016
PWM COMPARATOR GAIN Fm:
The PWM comparator gain Fm for peak current mode control is
given by Equation 6:
1
d̂
F m = ---------------- = -----------------------------( S e + S n )T s
v̂ comp
(EQ. 6)
Where, Se is the slew rate of the slope compensation and Sn is
given by Equation 7:
V in – V o
S n = R t -------------------L
S
1 + -----------V FB R o + R LP
ω esr A v ( S )
1
L v ( S ) = --------- ----------------------- ---------------------- --------------- , ω p ≈ ------------Rt
Vo
Ro Co
S H (S)
1 + ------- e
ωp
From Equation 14, it is shown that the system is a single order
system, which has a single pole located at ω p before the half
switching frequency. Therefore, a simple type II compensator can
be easily used to stabilize the system.
(EQ. 7)
Vo
P
Where Rt is trans-resistance, which is the gain of the current
amplifier.
C3
R2
V FB
CURRENT SAMPLING TRANSFER FUNCTION He(S):
In current loop, the current signal is sampled every switching
cycle. It has the following transfer function:
R3
VREF
-
VCOMP
GM
+
2
S
S
H e ( S ) = ------- + -------------- + 1
2 ω Q
n n
ωn
(EQ. 14)
R6
(EQ. 8)
C7
C6
2
π
where Qn and ωn are given by Q n = – ---, ω n = πf s
Power Stage Transfer Functions
Transfer function F1(S) from control to output voltage is:
S1 + ----------ω esr
v̂ o
F 1 ( S ) = ------ = V in -------------------------------------2
d̂
S
S
------- + -------------- + 1
2 ω Q
o p
ωo
FIGURE 41. TYPE II COMPENSATOR
(EQ. 9)
C
1
1
- ,Q ≈ R o -----o- ,ω o = ----------------Where ω esr = -----------Rc Co p
LP
LP Co
Transfer function F2(S) from control to inductor current is given
by Equation 10:
S
1 + -----V in
ωz
Î o
F 2 ( S ) = ---- = ----------------------- -------------------------------------R o + R LP 2
d̂
S - ------------S -----+
+1
2 ω Q
o p
ωo
(EQ. 10)
1
(EQ. 15)
C +C
1
1
6
7
Where ω cz1 = ------------- , ω cz2 = --------------, ω cp = -------------------R6 C6
R2 C3
R6 C6 C7
Compensator design goal:
High DC gain
Phase margin: 40°
Current loop gain Ti(S) is expressed as Equation 11:
(EQ. 11)
The compensator design procedure is as follows:
1
Put compensator zero ω cz1 = ( 1to3 ) ------------R C
o o
The voltage loop gain with open current loop is:
T v ( S ) = KF m F 1 ( S )A v ( S )
S ⎞⎛
S
⎛ 1 + -----------1 + ------------⎞
⎝
ω cz1⎠ ⎝
ω cz2⎠
v̂ comp
GM
A v ( S ) = ---------------- = ------------------- --------------------------------------------------------C6 + C7
S
v̂ FB
S ⎛ 1 + ----------⎞
⎝
ω cp⎠
1 1⎞
- f
Loop bandwidth fc: ⎛⎝ --4- to -----10⎠ s
Gain margin: >10dB
where ω z = ------------.
Ro Co
T i ( S ) = R t F m F 2 ( S )H e ( S )
Figure 41 shows the type II compensator and its transfer function
is expressed as follows:
(EQ. 12)
The Voltage loop gain with current loop closed is given by
Equation 13:
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower. An
optional zero can boost the phase margin. ωCZ2 is a zero due to
R2 and C3.
1
Tv ( S )
L v ( S ) = ----------------------1 + Ti ( S )
(EQ. 13)
V FB
K = --------- , V FB
Vo
Where
is the feedback voltage of the voltage
error amplifier. If Ti(S)>>1, then Equation 13 can be simplified by
Equation 14:
19
Put compensator zero ω cz2 = ( 5to8 ) ------------R C
o o
The loop gain Tv (S) at cross over frequency of fc has unity gain.
Therefore, the compensator resistance R6 is determined by:
2πf c V o C o R t
R 6 = -------------------------------GM ⋅ V FB
(EQ. 16)
FN7616.1
May 5, 2011
ISL8016
where GM is the sum of the trans-conductance, gm, of the
voltage error amplifier in each phase. Compensator capacitor C6
is then given by:
1
1
C 6 = ----------------- ,C 7 = ------------------------R 6 ω cz
2πR 6 f esr
(EQ. 17)
Example: VIN = 5V, Vo = 2.5V, Io = 6A, fs = 1MHz, Co = 44µF/3mΩ,
L = 1µH, GM = 100µs, Rt = 0.25V/A, VFB = 0.6V, Se = 0.15V/µs,
Sn = 2.55×105V/s, fc = 100kHz, then compensator resistance
R6 = 120kΩ.
Put the compensator zero at 1.5kHz (~1.5x CoRo), and put the
compensator pole at ESR zero which is 390kHz. The
compensator capacitors are:
C6 = 220pF, C7 = 3pF (there is approximately 3pF parasitic
capacitance from VCOMP to GND; therefore, C7 optional).
Figure 42 shows the simulated loop gain response. It is shown
that it has 95kHz loop bandwidth with 79° phase margin and at
least 10dB gain margin.
PCB Layout Recommendation
The PCB layout is a very important converter design step to make
sure the designed converter works well. For ISL8016, the power
loop is composed of the output inductor L’s, the output capacitor
COUT, the PHASE’s pins, and the PGND pin. It is necessary to
make the power loop as small as possible and the connecting
traces among them should be direct, short and wide. The
switching node of the converter, the PHASE pins, and the traces
connected to the node are very noisy, so keep the voltage
feedback trace away from these noisy traces. The input capacitor
should be placed as close as possible to the VIN pin , and the
ground of the input and output capacitors should be connected
as close as possible. The heat of the IC is mainly dissipated
through the thermal pad. Maximizing the copper area connected
to the thermal pad is preferable. In addition, a solid ground plane
is helpful for better EMI performance. It is recommended to add
at least 5 vias ground connection within the pad for the best
thermal relief.
60
45
30
GAIN LOOP (dB)
15
0
-15
-30
100
1k
10k
100k
1M
180
150
120
PHASE LOOP (°)
90
60
30
0
100
1k
10k
100k
1M
FIGURE 42. SIMULATED LOOP GAIN
20
FN7616.1
May 5, 2011
ISL8016
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
CHANGE
4/21/11
FN7616.1
Figures 6 and 8 - smoothed curves.
3/31/11
FN7616.0
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL8016
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/sear
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
21
FN7616.1
May 5, 2011
ISL8016
Package Outline Drawing
L20.3x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
3.00
0.10 M C A B
0.05 M C
A
B
4
20X 0.25
16X 0.50
+0.05
-0.07
17
A
16
6
PIN 1
INDEX AREA
6
PIN 1 INDEX AREA
(C 0.40)
20
1
4.00
2.65
11
+0.10
-0.15
6
0.15 (4X)
A
10
7
VIEW "A-A"
1.65
TOP VIEW
+0.10
-0.15
20x 0.40±0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
C
0.9± 0.10
SEATING PLANE
0.08 C
SIDE VIEW
(16 x 0.50)
(2.65)
(3.80)
(20 x 0.25)
C
(20 x 0.60)
0.2 REF
5
0.00 MIN.
0.05 MAX.
(1.65)
(2.80)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
22
FN7616.1
May 5, 2011