IXYS CPC75282 Line card access switch Datasheet

CPC75282
Line Card Access Switch
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
Features
Description
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The CPC75282 Dual Line Card Access Switch
(LCAS), a member of IXYS Integrated Circuits
Division’s next generation Line Card Access Switch
family, is a monolithic solid state device that provides
the switching functionality of four 2-Form-C relays in a
single, small, economical package.
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Improved Switch dV/dt Immunity of 1500V/s
Smart logic for power-up/hot-plug state control
Small 44-pin TQFP Package
Monolithic IC reliability
Low, matched RON
Eliminates the need for zero-cross switching
Flexible switch timing to transition from ringing mode
to talk mode.
Clean, bounce-free switching
Tertiary protection consisting of integrated current
limiting, voltage clamping, and thermal shutdown for
SLIC protection
5V operation with very low power consumption
Intelligent battery monitor
Latched logic-level inputs, no external drive circuitry
required
The CPC75282 Dual LCAS device is designed to
provide ringing and test access to the telephone loop
in Central Office, Digitally Added Main Line, Private
Branch Exchange, Digital Loop Carrier, and Hybrid
Fiber Coax/Fiber-In-The-Loop analog line card
applications. Test access switches provide access to
the telephone loop for line (drop) test or message
waiting in the PBX application.
Ordering Information
Applications
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VoIP Gateways
Central Office (CO)
Digital Loop Carrier (DLC)
PBX Systems
Digitally Added Main Line (DAML)
Hybrid Fiber Coax (HFC)
Fiber In The Loop (FITL)
Pair Gain System
Channel Banks
Part #
Description
CPC75282KA
44-Pin TQFP, (37/Tube)
CPC75282KATR
44-Pin TQFP, Tape & Reel (1000/Reel)
e3
Pb
Figure 1. CPC75282 Block Diagram
VDD
9,25
TTEST1
37
1/2 - CPC75282
TRINGING1
38
(Channel 1)
SW3
TLINE1
X
X SW5
X
36
SW1
21
TBAT1
22
RBAT1
14
P1
15
P2
Battery
Monitor
SW2
RLINE1
34
RRINGING1
30
X
SW4
RTEST1
X
X SW6
CH1
33
CH2
27
FGND1
DS-CPC75282-R00E
8,26
VBAT
PRELIMINARY
Switch
Control
Logic
L
A
T
C
H
24
11,23
CFG
DGND
16
P3
17
LATCH1
18
LATCH2
28
TSD1
6
TSD2
19
OFF1
20
OFF2
1
INTEGRATED CIRCUITS DIVISION
CPC75282
PRELIMINARY
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pinout by Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Pinout by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.7 Switch Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.7.1 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.7.2 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.7.3 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.7.4 Test Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.8 Digital I/O Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.9 Voltage and Power Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.10 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.11 Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.11.1 Operating States: CFG=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.11.2 Operating States: CFG=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Under Voltage Switch Lock-Out Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Switch Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3 Make-Before-Break Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.4 Make-Before-Break Operation Logic Table (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.5 Break-Before-Make Ringing to Talk Transition Logic Sequence CPC7592xA/B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.6 Break -Before- Make Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 TSD Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Ringing Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.1 Diode Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 Thermal Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
12
13
13
13
13
13
14
14
14
14
15
15
15
15
15
15
16
16
3. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Figure 1: Protection Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Figure 2: Switches 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Figure 3: Switch 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Figure 4: Switches 5-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
17
17
4. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.1 CPC75282KA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.2 CPC75282KATR Tape & Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
18
18
18
19
19
19
2
PRELIMINARY
R00E
CPC75282
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
1. Specifications
1.3 Pinout by Pin Number
Pin
1
1.1 Package Pinout
RLINE2
NC
TLINE2
TTEST2
TRINGING2
NC
TRINGING1
TTEST1
TLINE1
NC
RLINE1
Pin 1
4
RTEST2
NC
NC
6
RTEST1
NC
NC
RRINGING1
NC
TSD1
FGND1
VBAT
VDD
CFG
DGND
RBAT2
TBAT2
P1
P2
P3
LATCH1
LATCH2
OFF1
OFF2
TBAT1
RBAT1
RRINGING2
NC
TSD2
FGND2
VBAT
VDD
NC
DGND
1.2 Pinout by Channel
CH1
CH2
Name
Description
27
21
36
38
37
7
13
42
40
41
FGNDx
TBATx
TLINEx
1
9, 25
33
30
34
22
1
4
44
12
8, 26
17
28
19
18
6
20
11, 23
14
15
16
24
2, 3, 5, 10, 29,
31, 32, 35, 39,
43
1
Fault Ground
Tip Lead to the SLIC
Tip Lead of the Line Side
TRINGINGx Ringing Generator Return
TTESTx Tip Lead of the Test Bus
VDD
+5V Supply
RTESTx Ring Lead of the Test Bus
RRINGINGx Ringing Generator Source
RLINEx Ring Lead of the Line Side
RBATx
Ring Lead to the SLIC
VBAT
Battery Supply
LATCHx Data Latch Enable Control Input
TSDx
Temperature Shutdown Pin
OFFx
All Off Logic Level Input Switch Control 2
DGND
Digital Ground
P1
Logic Control Input
P2
Logic Control Input
P3
Logic Control Input
CFG
Operating States Configuration
NC
Not Connected
“x” denotes channel number
Name
Description
RTEST2 Ring Lead of the Test Bus
RRINGING2 Ringing Generator Source
TSD2
Temperature Shutdown Pin
7
FGND2
Fault Ground
9
VDD
+5V Supply
12
RBAT2
Ring Lead to the SLIC
13
14
15
16
17
TBAT2
P1
P2
P3
LATCH1
Tip Lead to the SLIC
Logic Control Input
Logic Control Input
Logic Control Input
Data Latch Enable Control Input
18
LATCH2
Data Latch Enable Control Input
19
OFF1
All Off Logic Level Input Switch Control
20
OFF2
All Off Logic Level Input Switch Control
21
TBAT1
Tip Lead to the SLIC
22
24
25
RBAT1
Ring Lead to the SLIC
Operating States Configuration
+5V Supply
27
FGND1
28
TSD1
30
32
33
34
35
36
37
38
39
40
41
CFG
VDD
Fault Ground
Temperature Shutdown Pin
RRINGING1 Ringing Generator Source
NC
Not Connected
RTEST1 Ring Lead of the Test Bus
RLINE1 Ring Lead of the Line Side
NC
TLINE1
Not Connected
Tip Lead of the Line Side
TTEST1 Tip Lead of the Test Bus
TRINGING1 Ringing Generator Return
NC
Not Connected
TRINGING2 Ringing Generator Return
TTEST2 Tip Lead of the Test Bus
TLINE2
Tip Lead of the Line Side
Not Connected
Ring Lead of the Line Side
42
43
44
RLINE2
9, 25
VDD
+5V Supply
11, 23
DGND
Digital Ground
8, 26
2, 3, 5,
10, 29,
31, 32,
35, 39, 43
VBAT
Battery Supply
NC
Not Connected
NC
2
An internal pull-down device is included on this node to set
Off as the power-up default state. These pins can also be
used as a device reset. If these pins are not used, tie to VDD
R00E
PRELIMINARY
3
CPC75282
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
1.4 Absolute Maximum Ratings
Parameter
+5V power supply (VDD)
Battery Supply
DGND to FGND Separation
Logic input voltage
Logic input to switch output
isolation
Switch open-contact
isolation (SW1, SW2, SW3,
SW5, SW6)
Switch open-contact
Isolation (SW4)
Operating relative humidity
Operating temperature
Storage temperature
1.5 ESD Rating
Minimum Maximum
Unit
ESD Rating (Human Body Model)
1000V
-0.3
-5
-0.3
7
-85
+5
VDD + 0.3
V
V
V
V
-
320
V
-
320
V
-
465
V
5
-40
-40
95
+110
+150
%
C
C
1.6 General Conditions
Unless otherwise specified, minimum and maximum
values are production testing requirements. Typical
values are characteristic of the device and are the
result of engineering evaluations. They are provided
for information purposes only and are not part of the
testing requirements.
Specifications cover the operating temperature range
TA = -40C to +85C. Also, unless otherwise specified,
all testing is performed with VDD = 5VDC, logic low
input voltage is 0VDC and logic high voltage is 5VDC.
Absolute maximum electrical ratings are at 25C.
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at conditions
beyond those indicated in the operational sections of this
data sheet is not implied.
4
PRELIMINARY
R00E
INTEGRATED CIRCUITS DIVISION
CPC75282
PRELIMINARY
1.7 Switch Specifications
1.7.1 Break Switches, SW1 and SW2
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
ISW
-
-
1
A
14.5
-
-
31
10.5
-
-
0.02
1.0
-
-
320
60
-
-
V1 + 0.5
-
-
-
300
VSW1 (differential) = TLINE to TBAT
VSW2 (differential) = RLINE to RBAT
All-Off state.
Off-State
Leakage Current
+25C,
VSW (differential) = -320V to gnd
VSW (differential) = +260V to -60V
+85 C,
VSW (differential) = -330V to gnd
VSW (differential) = +270V to -60V
-40C,
VSW (differential) = -310V to gnd
VSW (differential) = +250V to -60V
ISW(on) = ±10mA, ±40mA,
RBAT and TBAT = -2V
On Resistance
+25C
RON
+85C
-
-40C
On Resistance
Matching
Per SW1 & SW2 On Resistance test
conditions.
Maximum Differential Voltage (Vmax)
ON-State Voltage 1
Foldback Voltage Breakpoint 1 (V1)
RON
VON
Foldback Voltage Breakpoint 2 (V2)
VSW (on) = ±10V, +25C
DC current limit 1 (ILIM1) VSW (on) = ±10V, +85C
ISW
VSW (on) = ±10V, -40C
-
DC current limit 2 (ILIM2)
Dynamic current limit
(t = <0.5 s)
Break switches on, all other switches
off. Apply ±1 kV 10x1000 s pulse with
appropriate protection in place.
+85 C, OFFx = 0,
VSW (TLINE, RLINE) = ±330V
V
mA
1
-
-
ISW
-
2.5
-
A
-
-
-
-
1
A
-
-
1500
2100
-
V/s
ISW
-40 C, OFFx = 0,
VSW (TLINE, RLINE) = ±310V
Transient Immunity 2
425

ISW
+25 C, OFFx = 0,
VSW (TLINE, RLINE) = ±320V
Logic Input to Switch
Output Isolation
80

dV/dt
1 Choice of secondary protector should ensure this rating is not exceeded.
2
Applied voltage is 100VP-P square wave at 100Hz.
R00E
PRELIMINARY
5
CPC75282
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
1.7.2 Ringing Return Switch, SW3
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
VSW3 (differential) = TLINE to TRINGING
All-Off state.
+25 C,
VSW (differential) = -320V to gnd
VSW (differential) = +260V to -60V
Off-State
Leakage Current
-
+85 C,
VSW (differential) = -330V to gnd
VSW (differential) = +270V to -60V
ISW
-
ISW(on) = ±0mA, ±10mA, +25C
60
-
85
100
45
-
-
-
320
200
-
-
V1 + 0.5
-
-
-
135
70
85
-
210
1
-
-
-
2.5
-
A
1
A
-
V/s
RON
-
ISW(on) = ±0mA, ±10mA, -40C
Maximum Differential Voltage (Vmax)
ON-State Voltage
1
VON
Foldback Voltage Breakpoint 1 (V1)
Foldback Voltage Breakpoint 2 (V2)
VSW (on) = ±10V, +25C
DC current limit 1 (ILIM1) VSW (on) = ±10V, +85C
ISW
VSW (on) = ±10V, -40C
DC current limit 2 (ILIM2)
Dynamic current limit
(t = <0.5 s)
Ringing switches on, all other switches
off. Apply ±1kV 10x1000 s pulse with
appropriate protection in place.
ISW
+25C, OFFx = 0,
VSW (TRINGING, TLINE) = ±320V
Logic Input to Switch
Output Isolation
+85C, OFFx = 0,
VSW (TRINGING, TLINE) = ±330V
-
-

V
mA
ISW
-
-40C, OFFx = 0,
VSW (TRINGING, TLINE) = ±310V
Transient Immunity 2
-
-40 C,
VSW (differential) = -310V to gnd
VSW (differential) = +250V to -60V
ISW(on) = ±0mA, ±10mA, +85C
On Resistance
-
-
dV/dt
1500
2100
1 This parameter is not tested in production. Choice of secondary protector should ensure this rating is not exceeded.
2
6
Applied voltage is 100VP-P square wave at 100Hz.
PRELIMINARY
R00E
CPC75282
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
1.7.3 Ringing Switch, SW4
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
VSW4 (differential) = RLINE to RRINGING
All-Off state.
Off-State
Leakage Current
+25C
VSW (differential) = -255V to +210V
VSW (differential) = +255V to -210V
-
+85 C
VSW (differential) = -270V to +210V
VSW (differential) = +270V to -210V
ISW
-
-40 C
VSW (differential) = -245V to +210V
VSW (differential) = +245V to -210V
-
-
On Resistance
ISW (on) = ±70mA, ±80mA
RON
-
10
15

On Voltage
ISW (on) = ±1mA
VON
-
-
3
V
On-State
Leakage Current
Inputs set for ringing -Measure ringing
generator current to ground.
IRINGING
-
2
-
mA
ISW
-
-
150
mA
ISW
-
-
2
A
IRINGING
-
300
1000
A
1
A
-
V/s
Steady-State Current 1 Inputs set for ringing mode.
Surge Current
1
Release Current
Ringing switches on, all other switches
off. Apply ±1kV 10x1000 s pulse with
appropriate protection in place.
SW4 transition from on to off.
+25C, OFFx = 0,
VSW (RRINGING, RLINE) = ±320V
Logic input to switch
output isolation
+85C, OFFx = 0,
VSW (RRINGING, RLINE) = ±330V
ISW
-
-40C, OFFx = 0,
VSW (RRINGING, RLINE) = ±310V
Transient Immunity 2
-
-
dV/dt
1500
2100
1 This parameter is not tested in production. Choice of secondary protector should ensure this rating is not exceeded.
2
Applied voltage is 100VP-P square wave at 100Hz.
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PRELIMINARY
7
CPC75282
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
1.7.4 Test Switches, SW5 and SW6
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
VSW1 (differential) = TLINE to TBAT
VSW2 (differential) = RLINE to RBAT
All-Off state.
Off-State
Leakage Current
+25C,
VSW (differential) = -320V to gnd
VSW (differential) = +260V to -60V
-
+85 C,
VSW (differential) = -330V to gnd
VSW (differential) = +270V to -60V
ISW
-
-40 C,
VSW (differential) = -310V to gnd
VSW (differential) = +250V to -60V
-
-
ISW(on) = ±10mA, ±40mA,
RBAT and TBAT = -2V
On Resistance
+25C
RON
+85C
-
-40C
VSW (on) = ±10V, +25C
DC current limit
VSW (on) = ±10V, +85C
ISW
VSW (on) = ±10V, -40C
Dynamic current limit
(t = <0.5 s)
Break switches on, all other switches
off. Apply ±1kV 10x1000 s pulse with
appropriate protection in place.
ISW
+25C, OFFx = 0,
VSW (TLINE, RLINE) = ±320V
Logic Input to Switch
Output Isolation
+85C, OFFx = 0,
VSW (TLINE, RLINE) = ±330V
ISW
-40C, OFFx = 0,
VSW (TLINE, RLINE) = ±310V
Transient Immunity 1
1
8
-
dV/dt
38
-
46
70
28
-

-
175
80
110
-
210
250
-
2.5
-
A
-
-
-
-
1
A
-
-
1500
2100
-
V/s
-
mA
Applied voltage is 100VP-P square wave at 100Hz.
PRELIMINARY
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INTEGRATED CIRCUITS DIVISION
CPC75282
PRELIMINARY
1.8 Digital I/O Electrical Specifications
Parameter
Test Conditions
Symbol
Input voltage falling
VIL
Minimum
Typical
Maximum
0.8
-
-
0.6
-
-
-
-
2.0
-
-
3.0
-
-
1.1
Unit
Input Characteristics
Input Voltage, Logic Low
(P1-P3, OFFx, CFG)
Input Voltage, Logic Low
(LATCHx)
Input voltage, Logic
High (P1-P3, OFFx)
Input Voltage, Logic
High (CFG)
VIH
Input voltage rising
Input Voltage, Logic
High (LATCHx)
V
Input Leakage Current,
Logic High (OFFx)
VDD = 5.25V, VBAT = -72V, VIH = 5V
IIH
15
32
60
A
Input Leakage Current,
Logic High (P1-P3,
LATCHx, CFG)
VDD = 5.25V, VBAT = -72V, VIH = 5V
IIH
-
-
20
A
Input leakage current,
Logic Low (P1-P3,
LATCHx, OFFx, CFG)
VDD = 5.25V, VBAT = -72V, VIL = 0V
IIL
-
-
20
A
Input leakage current,
TSDx Logic High
VDD = 5.25V, VBAT = -72V, VIH = 2.4V
IIH
10
16
30
A
Input leakage current,
TSDx Logic low
VDD = 5.25V, VBAT = -72V, VIL = 0.4V
IIL
10
16
30
A
Output Characteristics
Output voltage,
TSDx Logic High
VDD = 5.25V, VBAT = -72V, ITSD = 10A
VTSD_off
2.4
VDD
-
V
Output voltage,
TSDx Logic Low
VDD = 5.25V, VBAT = -72V, ITSD = 1mA
VTSD_on
-
0
0.4
V
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PRELIMINARY
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CPC75282
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
1.9 Voltage and Power Specifications
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
Voltage Requirements
VDD
-
VDD
4.75
5.0
5.25
V
VBAT1
-
VBAT
-19
-48
-72
V
1
VBAT is used only for internal protection circuitry. If VBAT rises above-10 V, the device will enter the all-off state and will remain in the all-off
state until the battery drops below approximately -15V.
Power Specifications
VDD = 5V, VBAT = -48V, VIH = 2.4V,
VIL = 0.4V, Measure IDD and IBAT
Power consumption
Idle/Talk State
All-Off State
-
15 3
-
-
7.5
3
-
-
20 3
-
1.6 3
3.0
-
0.75
3
1.5
-
1.8/1.5 3
4.0
-
4
10
A
Unit
-
2
P
Ringing or Test Access State
mW
VDD = 5V, VBAT = -48V, VIH = 2.4V,
VIL = 0.4V
VDD Current
Idle/Talk State
IDD
All-Off State
Ringing or Test Access State
VBAT Current
VDD = 5V, VBAT = -48V, VIH = 2.4V, VIL =
0.4V, All States
IBAT
mA
2 Controlled via OFF pins.
x
3 Combined power or current of both channels, both channels in the same state. Typical values from simulation.
1.10 Protection Circuitry Electrical Specifications
Parameter
Conditions
Protection Diode Bridge
Forward Voltage drop,
Apply ± DC current limit of break
continuous current
switches
(50/60 Hz)
Forward Voltage drop, Apply ± dynamic current limit of break
surge current
switches
Temperature Shutdown Specifications 1
Shutdown activation
Not production tested - limits are
temperature
guaranteed by design and Quality
Shutdown circuit
Control sampling audits.
hysteresis
Loss of Battery Detector Threshold
Loss of Battery
Resumption of Battery
Symbol
Minimum
Typical
Maximum
VF
-
2.1
3.0
V
VF
-
5
-
TTSD_on
110
125
150
C
TTSD_off
10
-
25
C
-19
=19
-10
-15
-5
-5
V
1 Temperature shutdown flag (T
SDx) will be high during normal operation and low during temperature shutdown state.
10
PRELIMINARY
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INTEGRATED CIRCUITS DIVISION
CPC75282
PRELIMINARY
1.11 Truth Tables
1.11.1 Operating States: CFG=0
State
Idle/Talk
Test
Ringing
Test/Monitor
Idle/Talk
Test/Monitor
Ringing
Test Ringing
All-Off
P3
P2
P1
OFFx1
Break
Switches
Ringing
Switches
Test
Switches
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
x
1
ON
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
1
1
1
1
1
1
1
02
1 P1, P2, and P3 data input values are directed to a given channel when the respective LATCH logic signal is set to “0.”
x
OFFx is a per-channel control.
2
A “0” on OFFx resets the CPC75282, the device will remain in the All-Off state until OFFx is returned to “1” and the next LATCHx signal is
applied.
3 CFG is fixed at D
GND; if CFG switches states when VDD is applied, the change will be recognized by a given channel after a LATCH low
transition is applied to that channel.
1.11.2 Operating States: CFG=1
State
Idle/Talk
Test
Ringing
All-Off
Idle/Talk
Test/Monitor
Ringing
Test Ringing
All-Off
P3
P2
P1
OFFx1
Break
Switches
Ringing
Switches
Test
Switches
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
x
1
1
1
1
1
1
1
1
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
OFF
OFF
ON
OFF
ON
OFF
02
1 P1, P2, and P3 data input values are directed to a given channel when the respective LATCH logic signal is set to “0.”
x
OFFx is a per-channel control.
2
A “0” on OFFx resets the CPC75282, the device will remain in the All-Off state until OFFx is returned to “1” and the next LATCHx signal is
applied.
3 CFG is fixed at v ; if CFG switches states when V is applied, the change will be recognized by a given channel after a LATCH low
DD
DD
transition is applied to that channel.
R00E
PRELIMINARY
11
INTEGRATED CIRCUITS DIVISION
CPC75282
PRELIMINARY
2. Functional Description
away from the SLIC via the protection diode bridge.
Power-cross potentials are also reduced by the current
limiting and thermal shutdown circuits.
2.1 Introduction
The CPC75282 Dual LCAS device has six operating
states:
• Idle/Talk: Break switches SW1 and SW2 closed,
ringing switches SW3 and SW4 open, and test
switches SW5 and SW6 open.
• Ringing: Break switches SW1 and SW2 open,
ringing switches SW3 and SW4 closed, and test
switches SW5 and SW6 open.
• Test: Break switches SW1 and SW2 open, ringing
switches SW3 and SW4 open, and loop test
switches SW5 and SW6 closed.
• Test/Monitor: Break switches SW1 and SW2
closed, ringing switches SW3 and SW4 open, and
test switches SW5 and SW6 closed.
• Test Ringing: Break switches SW1 and SW2 open,
ringing switches SW3 and SW4 closed, and test
switches SW5 and SW6 closed.
• All-off: Break switches SW1 and SW2 open, ringing
switches SW3 and SW4 open, and test switches
SW5 and SW6 open.
To protect the CPC75282 from an over-voltage fault
condition, use of a secondary protector is required.
The secondary protector must limit the voltage seen at
the tip and ring terminals to a level below the
maximum breakdown voltage of the switches. To
minimize the stress on the solid-state contacts, use of
a foldback or crowbar type secondary protector is
highly recommended. With proper selection of the
secondary protector, a line card using the CPC75282
will meet all relevant ITU, LSSGR, TIA/EIA and IEC
protection requirements.
The CPC75282 operates from a single +5V supply.
This gives the device extremely low idle and active
power consumption with virtually any range of battery
voltage. The battery voltage used by the CPC75282
has a two-fold function. For protection purpose it is
used as a fault condition current source during a
negative lightning event. Second, it is used as a
reference so that in the event of battery voltage loss,
the CPC75282 will enter the All-Off state.
See “Truth Tables” on page 11 for more information.
2.2 Under Voltage Switch Lock-Out Circuitry
The CPC75282 offers break-before-make and
make-before-break switching from the ringing state to
the idle/talk state with simple logic input control.
Solid-state switch construction means no impulse
noise is generated when switching during ring
cadence or ring trip, eliminating the need for external
zero-cross switching circuitry. State control is via
simple logic input so no additional driver circuitry is
required. The linear break switches, SW1 and SW2,
have exceptionally low RON and excellent matching
characteristics. The ringing switch, SW4, has a
minimum open contact breakdown voltage of 465V at
+25°C sufficiently high with proper protection to
prevent breakdown in the presence of a transient fault
condition (i.e., passing the transient on to the ringing
generator).
Smart logic in the CPC75282 now provides for switch
state control during both power up and power loss
transitions. An internal detector is used to evaluate the
VDD supply to determine when to de-assert the
under-voltage switch lock-out circuitry with a rising
VDD and when to assert the under-voltage switch
lock-out circuitry with a falling VDD. Any time
unsatisfactory low VDD conditions exist, the lock-out
circuit overrides user switch control by blocking the
information at the external input pins, and conditioning
internal switch commands to the All-Off state. Upon
restoration of VDD, the switches will remain in the
All-Off state until the LATCHx input is pulled low.
Integrated into the CPC75282 is an over-voltage
clamping circuit, active current limiting, and a thermal
shutdown mechanism to provide protection for the
SLIC during a fault condition. Positive and negative
lightning surge currents are reduced by the current
limiting circuitry and hazardous potentials are diverted
12
The rising VDD lock-out release threshold is internally
set to ensure all internal logic is properly biased and
functional before accepting external switch commands
from the input to control the switch states. For a falling
VDD event, the lock-out threshold is set to assure
proper logic and switch behavior up to the moment the
switches are forced off and external inputs are
suppressed.
PRELIMINARY
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CPC75282
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
2.3 Switch Logic
With the CPC75282, make-before-break and
break-before-make operations can easily be
accomplished by applying the proper sequence of
logic-level inputs to the device.
2.3.1 Start-up
The CPC75282 uses smart logic to monitor the VDD
supply. Any time the VDD is below an internally set
threshold, the smart logic places the control logic to
the all-off state until the LATCHx input is pulled low.
Prior to the assertion of a logic low at the LATCHx pin,
the switch control inputs must be properly conditioned.
2.3.2 Switch Timing
When switching from the ringing state to the idle/talk
state, the CPC75282 provides the ability to control the
release timing of the ringing switches, SW3 and SW4,
relative to the state of the switches, SW1 and SW2,
using simple logic inputs. The two available
techniques are referred to as make-before-break and
break-before-make operation. When the break switch
contacts of SW1 and SW2 are closed (made) before
the ringing switch contacts of SW3 and SW4 are
opened (broken), this is referred to as
make-before-break operation. Break-before-make
operation occurs when the ringing contacts of SW3
and SW4 are opened (broken) before the switch
contacts of SW1 and SW2 are closed (made).
The logic sequences for either mode of operation are
given in “Make-Before-Break Operation Logic
Table (Ringing to Talk Transition)” on page 13 and
“Break-Before-Make Ringing to Talk Transition
Logic Sequence CPC7592xA/B” on page 14. Logic
states and explanations are shown in “Truth Tables”
on page 11.
2.3.3 Make-Before-Break Operation
To use make-before-break operation, change the logic
inputs from the ringing state directly to the idle/talk
state. Application of the idle/talk state opens the
ringing return switch, SW3, as the break switches,
SW1 and SW2, close. The ringing switch, SW4,
remains closed until the next zero-crossing of the
ringing current. While in the make-before-break state,
ringing potentials in excess of the CPC75282
protection circuitry thresholds will be diverted away
from the SLIC.
2.3.4: Make-Before-Break Operation Logic Table (Ringing to Talk Transition)
State
(CFG=0, P3=0)
P2
P1
Ringing
1
0
Makebeforebreak
0
0
Idle/Talk
0
0
R00E
LATCHx
0
OFFx
Timing
1
SW4 waiting for next zero-current
crossing to turn off. Maximum time is
one-half of the ringing cycle. In this
transition state current limited by the DC
break switch current limit value will be
sourced from the ring node of the SLIC.
Zero-cross current has occurred
PRELIMINARY
Ringing
Break
Ringing
Test
Return
Switches
Switch Switches
Switch
1x & 2 x
4x
5 x & 6x
3x
Off
On
On
Off
On
Off
On
Off
On
Off
Off
Off
13
CPC75282
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
Break-before-make operation occurs when the ringing
switches open before the break switches, SW1 and
SW2, close.
2.3.5: Break-Before-Make Ringing to Talk Transition Logic Sequence CPC7592xA/B
State
CFG=0, P3=0
P2
P1
LATCHx
OFFx
Timing
Hold this state for at least one-half of the
ringing cycle. SW4 waiting for zero
current to turn off.
Zero current has occurred.
SW4 has opened
Break switches close.
Ringing
1
0
1
All-Off
1
1
0
0
All-Off
1
1
0
Talk
0
0
1
2.3.6 Break -Before- Make Operation
Break-before-make operation can be achieved using
OFFx to disable all of the switches when pulled to a
logic low. Although logically disabled, an active
(closed) ringing switch, SW4, will remain closed until
the next zero crossing current event.
1. Pull OFFx to a logic low to end the ringing state.
This opens the ringing return switch, SW3, and
prevents any other switches from closing.
2. Keep OFFx low for at least one-half the duration
of the ringing cycle period to allow sufficient time
for a zero crossing current event to occur and for
the circuit to enter the break-before-make state.
3. During the OFFx low period, set the P1, P2, and
P3 inputs to the idle/talk state.
4. Release OFFx , allowing the internal pull-up to
activate the break switches.
2.4 Data Latch
The CPC75282 has integrated transparent data
latches. The latch enable operation is controlled by
logic input levels at the LATCHx pin. Data input to the
latch is via the input pins P1, P2, and P3 while the
outputs of the data latch are internal nodes used for
state control. When the latch enable control pin is at a
logic 0 the data latch is transparent and the input
control signals flow directly through the data latch to
the state control circuitry. A change in input will be
reflected by a change in the switch states.
14
Ringing
Break
Ringing
Test
Return
Switches
Switch Switches
Switch
1x & 2 x
4x
5 x & 6x
3x
Off
On
On
Off
Off
Off
On
Off
Off
Off
Off
Off
On
Off
Off
Off
Whenever the latch enable control pin is at logic 1, the
data latch is active and data is locked. Subsequent
changes to the input controls P1, P2, and P3 will not
result in a change to the control logic or affect the
existing switch states.
The switches will remain in the state they were in
when the LATCHx changes from logic 0 to logic 1, and
will not respond to changes in input as long as the
LATCHx is at logic 1. However, neither the TSDx nor
the OFFx are affected by the latch function. Since
internal thermal shutdown control and external OFFx
control is not affected by the state of the latch enable
input, TSDx and OFFx will override state control.
2.5 TSD Pin Description
The TSDx pins are bidirectional I/O structures with
internal pull-up resistors sourced from VDD. As
outputs, these pins indicate the status of the thermal
shutdown circuitry for the associated channels.
Typically, during normal operation, these pins will be
pulled up to VDD , but, under fault conditions that
create excess thermal loading, the channels will enter
thermal shutdown and a logic low will be output.
As inputs, the TSDx pins are utilized to place the
channel into the All-Off state by simply pulling the
input low. For applications using low-voltage logic
devices (lower than VDD), IXYS Integrated Circuits
Division recommends the use of an open-collector or
an open-drain type output to control TSDx. This avoids
PRELIMINARY
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INTEGRATED CIRCUITS DIVISION
CPC75282
PRELIMINARY
sinking the TSDx pull up bias current to ground during
normal operation when the All-Off state is not
required. If TSDx is set to a logic 1 or tied to VCC, the
channel just ignores this input, and still enters the
thermal shutdown state at high temperature.
battery monitor feature draws a small current from the
battery (less than 1A typical) and will add slightly to
the device’s overall power dissipation.
2.9 Protection
2.9.1 Diode Bridge
2.6 Ringing Switch Zero-Cross Current Turn Off
After the application of a logic input to turn SW4 off,
the ringing switch is designed to delay the change in
state until the next zero-crossing. Once on, the switch
requires a zero-current cross to turn off, and therefore
should not be used to switch a pure DC signal. The
switch will remain in the on state no matter the logic
input until the next zero crossing. These switching
characteristics will reduce and possibly eliminate
overall system impulse noise normally associated with
ringing switches. See IXYS Integrated Circuits
Division’s application note, AN-144, Impulse Noise
Benefits of Line Card Access Switches, for more
information. The attributes of ringing switch, SW4,
may make it possible to eliminate the need for a
zero-cross switching scheme. A minimum impedance
of 300 in series with the ringing generator is
recommended.
2.7 Power Supplies
Both a +5V supply and battery voltage are connected
to the CPC75282. Switch state control is powered
exclusively by the +5V supply. As a result, the
CPC75282 exhibits extremely low power consumption
during active and idle states. Although battery power
is not used for switch control, it is required to supply
current during negative overvoltage fault conditions at
tip and ring.
2.8 Battery Voltage Monitor
The CPC75282 also uses the VBAT voltage to monitor
battery voltage. If system battery voltage is lost, both
channels of the CPC75282 immediately enter the
All-Off state. It remains in this state until the battery
voltage is restored. The device also enters the All-Off
state if the battery voltage rises more positive than
about –10V with respect to ground and remains in the
All-Off state until the battery voltage drops below
approximately –15V with respect to ground. This
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Both channels of the CPC75282 use a combination of
current limited break switches, a diode bridge, and a
thermal shutdown mechanism to protect the SLIC
device or other associated circuitry from damage
during line transient events, such as lightning. During
a positive transient condition, the fault current is
conducted through the diode bridge to ground via
FGND. Voltage is clamped to a diode drop above
ground. Negative lightning is directed to battery via
steering diodes in the diode bridge. For power
induction or power-cross fault conditions, the positive
cycle of the transient is clamped to a diode drop above
ground and the fault current directed to ground. The
negative cycle of the transient is steered to battery.
Fault currents are limited by the current-limit circuit.
2.9.2 Current Limiting function
If a lightning strike transient occurs when the device is
in the Idle/Talk state, the current is passed along the
line to the integrated protection circuitry, and restricted
by the dynamic current limit response of the active
switches. During the Idle/Talk state, when a 1000V
10x1000 s lightning pulse (GR-1089-CORE
lightning) is applied to the line though a properly
clamped external protector, the current seen at TLINE
and RLINE will be a pulse with a typical magnitude of
2.5A and a duration less than 0.5s.
If a power-cross fault occurs with the device in the
Idle/Talk state, the current is passed though break
switches, SW1 and SW2, on to the integrated
protection circuit, but is limited by the DC current limit
response of the two break switches. The DC current
limit is dependent on the switch differential voltage, as
shown in “Figure 2: Switches 1-3” on page 17.
Note that the current limit circuitry has a negative
temperature coefficient. As a result, if the device is
subjected to extended heating due to a power cross
fault condition, the measured current at TLINE and
RLINE will decrease as the device temperature
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INTEGRATED CIRCUITS DIVISION
CPC75282
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increases. If the device temperature rises sufficiently,
the temperature shutdown mechanism will activate
and the device will enter the All-Off state.
2.10 Thermal Shutdown
The thermal shutdown mechanism activates when the
device die temperature reaches a minimum of 110°C,
placing the device in the All-Off state regardless of
logic input. During thermal shutdown events the TSDx
pin will output a logic low with a nominal 0V level. A
logic high is output from the TSDx pin during normal
operation with a typical output level equal to VDD.
If presented with a short duration transient, such as a
lightning event, the thermal shutdown feature will
typically not activate. But in an extended power-cross
event, the device temperature will rise and the thermal
shutdown mechanism will activate forcing the switches
to the All-Off state. At this point the current measured
into TLINE or RLINE will drop to zero. Once the device
enters thermal shutdown, it will remain in the All-Off
state until the temperature of the device drops below
the de-activation level of the thermal shutdown circuit.
This permits the device to autonomously return to
normal operation. If the transient has not passed,
current will again flow up to the value allowed by the
dynamic DC current limiting of the switches and
16
heating will resume, reactivating the thermal shutdown
mechanism. This cycle of entering and exiting the
thermal shutdown mode will continue as long as the
fault condition persists. If the magnitude of the fault
condition is great enough, the external secondary
protector will activate, shunting the fault current to
ground.
2.11 External Protection Elements
The CPC75282 requires only over-voltage secondary
protection on the loop side of the device. The
integrated protection feature described above negates
the need for additional external protection on the SLIC
side. The secondary protector must limit voltage
transients to levels that do not exceed the breakdown
voltage or input-output isolation barrier of the
CPC75282. A foldback or crowbar type protector is
recommended to minimize stresses on the
CPC75282.
Consult IXYS Integrated Circuits Division’s application
note, AN-100, “Designing Surge and Power Fault
Protection Circuits for Solid State Subscriber Line
Interfaces,” for equations related to the specifications
of external secondary protectors, fused resistors, and
PTCs.
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3. Typical Performance Characteristics
3.1 Figure 1: Protection Circuit
3.3 Figure 3: Switch 4
+I
DC Current Limit
(Break Switches)
VBAT-3
RON
VBAT
-VOS
-V
<1μA
+V
3V
+VOS
DC Current Limit
(of Break Switches)
-I
3.4 Figure 4: Switches 5-6
3.2 Figure 2: Switches 1-3
ISW
ILIMIT
+I
ILIM1
2/3 RON
2/3 RON
-VMAX -V2 -V1
-ILIM2
VSW
-1.5
ILIM2
RON
1.5
V1
-V
RON
-1.5V
RON
V2 VMAX
+V
1.5V
2/3 RON
-ILIM1
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ILIMIT
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-I
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INTEGRATED CIRCUITS DIVISION
CPC75282
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4. Manufacturing Information
4.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee
proper operation of our devices when handled according to the limitations and information in that standard as well as
to any limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
Device
Moisture Sensitivity Level (MSL) Rating
CPC75282KA
MSL 1
4.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard
JESD-625.
4.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of
J-STD-020 must be observed.
Device
Maximum Temperature x Time
CPC75282KA
260°C for 30 seconds
4.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to
remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or
Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be
used.
Pb
18
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4.5 Mechanical Dimensions
4.5.1 CPC75282KA Package
44-Pin TQFP Package
Recommended PCB Land Pattern
12.00 ± 0.20
(0.472 ± 0.008)
10.00 ± 0.10
(0.394 ± 0.004)
11.50
(0.453)
1.20 Max
(0.047 Max)
10.00 ± 0.10
(0.394 ± 0.004)
12.00 ± 0.20
(0.472 ± 0.008)
0.80
(0.031)
11.50
(0.453)
Pin 44
Pin 1
0.05 Min - 0.15 Max
(0.002 Min - 0.006 Max)
0.37 ± 0.07
(0.014 ± 0.003)
1.00 ± 0.05
(0.039 ± 0.002)
1.00 Ref
(0.039) Ref
0.80
(0.031)
0.55
(0.022)
1.45
(0.057)
Dimensions
mm
(inches)
0.60 ± 0.15
(0.024 ± 0.006)
4.5.2 CPC75282KATR Tape & Reel
330.2 DIA.
(13.00 DIA)
Top Cover
Tape Thickness
0.102 MAX
(0.004 MAX)
9.2
(0.36)
B0=12.35
(0.486)
11.5
(0.453)
W=24.00+0.3
(0.94+0.01)
1.0
(0.039)
Embossed Carrier
K0=1.85
(0.073)
Embossment
9.4
(0.37)
K1=1.35
(0.053)
A0=12.35
(0.486)
16
(0.63)
Dimensions
mm
(inches)
For additional information please visit www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated
Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its
products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe property or
environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice.
Specifications: DS-CPC75282-R00E
© Copyright 2012, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
12/22/2012
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