HSP43881/883 TM Data Sheet May 1999 FN2449.4 Digital Filter Features The HSP43881/883 is a video speed Digital Filter (DF) designed to efficiently implement vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded internally and a shift and add output stage, all in a single integrated circuit. Each filter cell contains a 8 x 8-bit multiplier, three decimation registers and a 26-bit accumulator. The output stage contains an additional 26-bit accumulator which can add the contents of any filter cell accumulator to the output stage accumulator shifted right by 8-bits. The HSP43881/883 has a maximum sample rate of 25.6MHz. The effective multiply accumulate (mac) rate is 204MHz. • This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HSP43881/883 DF can be configured to process expanded coefficient and word sizes. Multiple DFs can be cascaded for larger filter lengths without degrading the sample rate or a single DF can process larger filter lengths at less than 25.6MHz with multiple passes. The architecture permits processing filter lengths of over 1000 taps with the guarantee of no overflows. In practice, most filter coefficients are less than 1.0, making even larger filter lengths possible. The DF provides for 8-bit unsigned or two’s complement arithmetic, independently selectable for coefficients and signal data. • Filter Lengths Up to 1032 Taps Each DF filter cell contains three resampling or decimation registers which permit output sample rate reduction at rates of 1/2, 1/3 or 1/4 the input sample rate. These registers also provide the capability to perform 2-D operations such as matrix multiplication and N x N spatial correlations/convolutions for image processing applications. • Complex Multiply-Add • 0MHz to 25.6MHz Sample Rate • Eight Filter Cells • 8-Bit Coefficients and Signal Data • Low Power CMOS Operation • ICCSB 500µA Maximum • ICCOP 160mA Maximum at 20MHz • 26-Bit Accumulator Per Stage • Expandable Coefficient Size, Data Size and Filter Length • Decimation by 2, 3 or 4 Applications • 1-D and 2-D FIR Filters • Radar/Sonar • Adaptive Filters • Echo Cancellation • Sample Rate Converters Ordering Information PART NUMBER TEMP. RANGE (oC) HSP43881GM-25/883 -55 to 125 PACKAGE 85 Ld PGA PKG. NO. G85.A Block Diagram VCC DIENB CIENB DCMO - 1 ERASE VSS 8 5 8 TCCI CIN0 - 7 RESET CLK ADR0 - 2 DIN0 - DIN7 TCS DF FILTER CELL 0 8 5 8 8 DF FILTER CELL 1 26 5 26 8 8 DF FILTER CELL 2 26 8 8 8 DF FILTER CELL 3 8 26 DF FILTER CELL 4 26 8 8 DF FILTER CELL 5 26 8 8 8 DF FILTER CELL 6 26 8 DF FILTER CELL 7 26 TCCO 8 COUT0 - 7 COENB 3 MUX RESET CLK SHADD SENBL SENBH 26 ADR0, ADR1, ADR2 2 OUTPUT STAGE 2 26 SUM0 - 25 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved HSP43881/883 Pinouts 85 PIN PGA TOP VIEW, PINS DOWN 1 2 3 4 5 6 7 8 9 10 11 A VSS COENB VCC RESET DIN7 DIN6 DIN3 DIN0 TCCI VCC VSS B VCC COUT7 TCCO ERASE TCS DIN1 DIN2 CIENB CIN7 CIN6 CIN4 C COUT5 COUT6 ALIGN PIN DIENB DIN5 DIN4 CIN5 CIN3 D COUT3 COUT4 CIN2 VCC E COUT1 F VSS G COUT2 CIN1 CIN0 SENBL COUT0 SHADD SUM0 VCC VSS ADR2 DCM0 SUM1 SUM3 SUM2 H ADR1 ADR0 SUM5 SUM4 J VCC SUM25 SUM7 VSS K L VSS SENBH SUM24 DCM1 SUM23 2 CLK SUM20 SUM17 SUM16 VSS VCC SUM19 VSS SUM15 SUM12 SUM10 SUM8 SUM6 SUM22 SUM21 SUM18 SUM14 VCC SUM13 VSS SUM11 SUM9 HSP43881/883 Pinouts (Continued) 85 PIN PGA BOTTOM VIEW, PINS UP 1 2 3 4 5 6 7 8 9 10 11 DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 VCC SUM13 VSS SUM11 SUM9 SENBH SUM24 VSS VCC SUM19 VSS SUM15 SUM12 SUM10 SUM8 SUM6 VCC SUM25 SUM20 SUM17 SUM16 SUM7 VSS ADR1 ADR0 SUM5 SUM4 ADR2 DCM0 CLK SUM1 SUM3 SUM2 VSS COUT0 SHADD SUM0 VCC VSS COUT1 VSS COUT2 CIN1 CIN0 SENBL CIN2 VCC CIN5 CIN3 L K J H G F E D COUT3 COUT4 C COUT5 COUT6 ALIGN PIN VCC COUT7 COUT8 VSS COENB VCC DIENB DIN5 DIN4 ERASE TCS DIN1 DIN2 CIENB CIN7 CIN6 CIN4 RESET DIN7 DIN6 DIN3 DIN0 CIN8 VCC VSS B A NOTE: An overbar on a signal name represents an active LOW signal. 3 HSP43881/883 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V Input, Output Voltage . . . . . . . . . . . . . . . . . . GND -0.5 to VCC +0.5V ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) Operating Conditions Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC θJA (oC/W) θJC (oC/W) PGA Package. . . . . . . . . . . . . . . . . . . . 36.0 7.0 Maximum Package Power Dissipation at 125oC PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.44W Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperate Range . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17,762 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS PARAMETER SYMBOL TEST CONDITIONS GROUP A SUBGROUPS TEMPERATURE (oC) MIN MAX UNITS Logical One Input Voltage VIH VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 2.2 - V Logical Zero Input Voltage VIL VCC = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 - 0.8 V Output HIGH Voltage VOH IOH = -400µA VCC = 4.5V (Note 2) 1, 2, 3 -55 ≤ TA ≤ 125 2.6 - V Output LOW Voltage VOL IOH = -400mA VCC = 4.5V (Note 2) 1, 2, 3 -55 ≤ TA ≤ 125 - 0.4 V Input Leakage Current II VIN = VCC or GND VCC = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 -10 +10 µA Output Leakage Current IO VIN = VCC or GND VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 -10 +10 µA Clock Input High VIHC VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 3.0 - V Clock Input Low VILC VCC = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 - 0.8 V Standby Power Supply Current ICCSB VIN = VCC or GND VCC = 5.5V, Outputs Open 1, 2, 3 -55 ≤ TA ≤ 125 - 500 µA Operating Power Supply Supply Current ICCOP f = 20.0MHz VCC = 5.5V (Note 3) 1, 2, 3 -55 ≤ TA ≤ 125 - 160.0 mA 7, 8 -55 ≤ TA ≤ 125 - - Functional Test FT (Note 4) NOTES: 2. Interchanging of force and sense conditions is permitted. 3. Operating supply current is proportional to frequency, typical rating is 8.0mA/MHz. 4. Tested as follows: f = 1MHz, VIH = 2.6, VIL = 0.4, VOH ≥ 1.5V, VOL ≤ 1.5V, VIHC = 3.4V and VILC = 0.4V. 4 HSP43881/883 TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested -25 (25.6MHz) SYMBOL NOTES GROUP A SUBGROUP S Clock Period t CP Note 5 9, 10, 11 -55 ≤ TA ≤ 125 39 - ns Clock Low tCL Note 5 9, 10, 11 -55 ≤ TA ≤ 125 16 - ns Clock High tCH Note 5 9, 10, 11 -55 ≤ TA ≤ 125 16 - ns Input Setup tIS Note 5 9, 10, 11 -55 ≤ TA ≤ 125 17 - ns Input Hold tIH Note 5 9, 10, 11 -55 ≤ TA ≤ 125 0 - ns CLK to Coefficient Output Delay tODC Note 5 9, 10, 11 -55 ≤ TA ≤ 125 - 20 ns Output Enable Delay tOED Note 5 9, 10, 11 -55 ≤ TA ≤ 125 - 15 ns CLK TO SUM Output Delay tODS Note 5 9, 10, 11 -55 ≤ TA ≤ 125 - 25 ns PARAMETER TEMPERATURE (oC) MIN MAX UNITS NOTE: 5. AC Testing: VCC - 4.5V and 5.5V. Inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0”. Input and output timing measurements are made at 1.5V for both a Logic “1” an”). CLK is driven at 4.0V and 0V and measured at 2.0V. TABLE 3. AC ELECTRICAL PERFORMANCE SPECIFICATIONS PARAMETER SYMBOL Input Capacitance CIN TEST CONDITIONS NOTES TEMP (oC) 6 VCC = Open, f = 1MHz All measurements are referenced to device GND -25 (25.6MHz) MIN MAX UNITS TA = 25 - 15 pF Output Capacitance COUT 6 TA = 25 - 15 pF Output Disable Delay t ODD 6, 7 -55 ≤ TA ≤ 125 - 15 ns Output Rise Time t OR 6, 7 -55 ≤ TA ≤ 125 - 6 ns Output Fall Time t OF 6, 7 -55 ≤ TA ≤ 125 - 6 ns NOTES: 6. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 7. Loading is as specified in the test load circuit, CL = 40pF. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 - PDA 100% 1 Final Test 100% 2, 3, 8A, 8B, 10, 11 - 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Samples/5005 1, 7, 9 Group A Groups C and D 5 HSP43881/883 Burn-In Circuit BOTTOM VIEW, PINS UP 1 2 3 4 5 6 7 8 9 10 11 DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 VCC SUM13 VSS SUM11 SUM9 SENBH SUM24 VSS VCC SUM19 VSS SUM15 SUM12 SUM10 SUM8 SUM6 VCC SUM25 SUM20 SUM17 SUM16 SUM7 VSS ADR1 ADR0 SUM5 SUM4 ADR2 DCM0 CLK SUM1 SUM3 SUM2 VSS COUT0 SHADD SUM0 VCC VSS COUT1 VSS COUT2 CIN1 CIN0 SENBL CIN2 VCC CIN5 CIN3 L K J H G F E D COUT3 COUT4 C COUT5 COUT6 ALIGN PIN VCC COUT7 TCCO VSS COENB VCC DIENB DIN5 DIN4 ERASE TCS DIN1 DIN2 CIENB CIN7 CIN6 CIN4 RESET DIN7 DIN6 DIN3 DIN0 TCCI VCC VSS B A 6 HSP43881/883 BURN-IN SIGNALS PGA PIN A1 PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL GND C1 COUT5 VCC/2 F10 VCC VCC K4 VCC VCC VSS A2 COENB F10 C2 COUT6 VCC/2 F11 VSS GND K5 SUM19 VCC/2 A3 VCC VCC C3 ALIGN NC G1 ADR2 F2 K6 VSS GND A4 RESET F11 C5 DIENB F10 G2 DCMO F5 K7 SUM15 VCC/2 A5 DIN7 F8 C6 DIN5 F5 G3 CLK F0 K8 SUM12 VCC/2 A6 DIN6 F6 C7 DIN4 F4 G9 SUM1 VCC/2 K9 SUM10 VCC/2 A7 DIN3 F3 C10 CIN5 F5 G10 SUM3 VCC/2 K10 SUM8 VCC/2 A8 DIN0 F0 C11 CIN3 F3 G11 SUM2 VCC/2 K11 SUM6 VCC/2 A9 CIN8/5CCI F8 D1 COUT3 VCC/2 H1 ADR1 F1 L1 DCM1 F6 A10 VCC VCC D2 COUT4 VCC/2 H2 ADR0 F0 L2 SUM23 VCC/2 A11 VSS GND D10 CIN2 F2 H10 SUM5 VCC/2 L3 SUM22 VCC/2 B1 VCC VCC D11 VCC VCC H11 SUM4 VCC/2 L4 SUM21 VCC/2 B2 COUT7 VCC/2 E1 COUT1 VCC/2 J1 VCC VCC L5 SUM18 VCC/2 B3 COUT8/TCC0 VCC/2 E2 VSS GND J2 SUM25 VCC/2 L6 SUM14 VCC/2 B4 ERASE F10 E3 COUT2 VCC/2 J5 SUM20 VCC/2 L7 VCC VCC B5 DIN8/TCS F7 E9 CIN1 F1 J6 SUM17 VCC/2 L8 SUM13 VCC/2 B6 DIN1 F1 E10 CIN0 F0 J7 SUM16 VCC/2 L9 VSS GND B7 DIN2 F2 E11 SENBL F10 J10 SUM7 VCC/2 L10 SUM11 VCC/2 B8 CIENB F10 F1 VSS GND J11 VSS GND L11 SUM9 VCC/2 B9 CIN7 F7 F2 COUT0 VCC/2 K1 SENBH F10 B10 CIN6 F6 F3 SHADD F9 K2 SUM24 VCC/2 B11 CIN4 F4 F9 SUM0 VCC/2 K3 VSS GND NOTES: 8. VCC/2 (2.7 ±10% used for outputs only. 9. 47kΩ (±20%) resistor connected to all pins except VCC and GND. 10. VCC = 5.5V ±0.5V. 11. 0.1µF (minimum) capacitor between VCC and GND per device. 12. F0 = 100kHz ±10%, F1 = F0/2, F2 = F1/2..., F11 = F10/2, 40% - 60% duty cycle. 13. Input voltage limits: VIL = 0.8V maximum, VIH = 4.5V ±10%. Die Characteristics DIE DIMENSIONS: GLASSIVATION 328 mils x 283 mils x ±1 mil METALLIZATION: Type: Nitrox Silox Thickness: 10kÅ WORST CASE CURRENT DENSITY: Type: Si-Al or Si-AI-Cu Thickness: 8kÅ 1.2 x 105 A/cm2 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7