Features • • • • • • • • • Eight DSPs and 24-bit Audio Router On-chip 32 kHz to 96 kHz Sampling Rate 16-bit Microcontroller On-chip Variety of I/Os, including SmartMedia® and DataFlash® Embedded RAM for Single Chip Operation (768 Kbits) Warm Start Power-down 1µA Typical Deep Power-down, 0.5 mW/MIPS Typical Operating Available in a 64-lead LQFP Package Ideal for Real-time Audio Applications – Professional Effect Processing (Reverb, Chorus, Flanger, Distortion, Equalizer) – Internal Routing and Mixing of 8-input/8-output Channels – Sampling Rate Conversion of Digital Inputs at up to 96 kHz at 24 bits • Typical Applications: Professional Audio, Studio Equipment, Digital Mixer, Effect Devices, Equalizer 1. Description The ATSAM3108B is a member of the new ATSAM3000 family that uses DSP array technology. The ATSAM3108B includes eight 24-bit DSPs, a 24-bit Audio Router and a general-purpose 16-bit on-chip CISC microcontroller. Its high performance and flexibility with 8-input/8-output channels enables implementation of audio applications in professional-quality sound production such as effect processing and digital mixing. A variety of I/Os, including, SmartMedia® and DataFlash® are provided. Sampling rates up to 96 kHz at 24 bits are supported. Audio Processing ATSAM3108B Eight-channel Multiprocessing Audio DSP 6092C–DRMSD–12-Feb-07 2. DSP Array Block Diagram Figure 2-1. ATSAM3108B DSP Array Block Diagram DSP Array (8 P24 DSPs) Embedded RAM 16k x 24 MMU Sync Bus Async Bus 16 bit Processor (P16) I/Os, Timers, UARTs, DataFlash, Ports Router Final ACC MIX Audio OUT Audio IN External I/O ATSAM3108B Audio I/0 Embedded ROM 1k x 16 BIOS and Debug 3. Functional Description 3.1 DSP Array The ATSAM3108B includes eight on-chip DSPs. Each DSP (P24) is built around a 2k x 24 RAM and a 1k x 24 ROM. The RAM contains both data and P24 instructions, the ROM contains typical coefficients such as FFT cosines and windowing. A P24 sends and receives audio samples through the Sync Bus. It can request external data such as compressed audio through the Async Bus. Each P24 RAM can be accessed through the Async Bus. Each P24 is capable of typical MAC operation loops, including auto-indexing, bit reverse and butterfly (multiplication of complex numbers). It also includes specialized audio instructions such as state variable IIR filtering, envelope generation, linear interpolation and wavetable loop. One P24 is sufficient for processing stereo reverb and chorus @48kHz or stereo sampling rate conversion @96kHz. 2 ATSAM3108B 6092C–DRMSD–12-Feb-07 ATSAM3108B 3.2 Sync Bus The Sync Bus transfers data on a frame basis, typical frame rates being 32, 44.1, 48 or 96 kHz. Each frame is divided into 64 time slots. Each slot is divided into 4 bus cycles. Each P24 is assigned a hardwired time slot (8 to 63), during which it may provide 24-bit data to the bus (up to 4 data samples). Each P24 can read data on the bus at any time, allowing inter P24 communication at the current sampling rate. Slots 0 to 7 are reserved for a specific router DSP, which also handles audio out, audio in, and remix send. 3.3 Async Bus The Async Bus has 24-bit data inside the chip and 16-bit data outside. The P16 processor normally masters the Async Bus; it can read/write the P24 memories and the external or embedded ROM/RAM. However, each P24 can request a bus master cycle for accessing external ROM/RAM or other P24 memories. This allows efficient intercommunication between several P24s on asynchronous block basis. Specific P24 instructions FLOAT and FIX convert fixed-point DSP data to floating-point 16 bits. This allows for 20-bit audio dynamic range when using 16-bit external memory. 3.4 16-bit Processor The P16 processor is widely used in ATSAM products. Using the P16 keeps large firmware investments from the ATSAM97xx series. A built-in ROM, connected to the P16 holds basic input/output software (BIOS) for peripherals such as UART, DataFlash, SmartMedia and MPU, as well as a debugger that uses a dedicated asynchronous serial line. The firmware can be downloaded at power-up into the built-in 16k x 24 RAM from serial EEPROM, DataFlash, SmartMedia or host. 3.5 MMU (Memory Management Unit) The MMU handles transfer requests between the embedded RAM/ROM, the P16 and the P24s through the Async Bus. The ATSAM3108B includes 16k x 24 RAM on chip. 3.6 Router: Final ACC, MIX, Audio Out, Audio In This block includes RAM (accessed through the Async Bus) that defines the routing from the Sync Bus to/from the Audio I/O or back to the Sync Bus (mix send). It takes care of mix and accumulation from Sync Bus samples. Eight channels of audio in and eight channels of audio out are provided (4-stereo in/out, I2S format). The stereo audio in channels may have a different sampling rate than the audio out channels. In this case, one (or more) P24 takes care of sampling rate conversion. 3.7 I/O The ATSAM3108B includes very versatile I/Os, that share common pins for reduced pin count and small IC footprint. Most I/Os, when not used for a specific function, remain available as firmware controlled general-purpose pins. The following peripherals are included on chip: • 2 x 8-bit timers • 2 x 16-bit timers • Parallel slave 8-bit port, MPU401 compatible • Parallel master 8-bit port, for connection to SmartMedia and/or LCD display, switches, etc. 3 6092C–DRMSD–12-Feb-07 • 2 x asynchronous bidirectional serial ports • Synchronous serial slave port (SPI type host connection) • SPI master bidirectional port for EEPROM or DataFlash connection • Firmware controlled I/O pins 4. Typical Application Example 4.1 Professional Audio Figure 4-1. Professional Audio Application Atmel DataFlash Switches LCD Display MIDI ATSAM3108B 8-channel Audio Out ADC DAC • Eight channels audio-in, eight channels audio-out @ 96kHz at 24-bit sampling rate • Digital Mixer with the possibility of incoming audio sampling rate converter • Effects • Four Channels 31-band Equalizer • Feedback Canceller 5. DSP Capacity and I/O Configuration 5.1 DSP Considerations The ATSAM3108B includes 8 x P24 DSPs. Table 5-1 below lists the performance achievable by the P24. Table 5-1. P24 Performance Function P24s Required Stereo reverb and chorus @48 kHz 1 Stereo sampling rate conversion @ 96 kHz 1 31-band equalizer @ 96 kHz 3 Stereo 31-band equalizer @48 kHz 3 256 points FFT or IFFT @96 kHz, includes windowing 1 The ATSAM3108B runs firmware directly from the built in 16 x 24 RAM. It has no wave-table synthesis capability. The firmware should be downloaded at power-up. 4 ATSAM3108B 6092C–DRMSD–12-Feb-07 ATSAM3108B • A small 256-Kbit external EEPROM with an SPI interface such as Atmel AT25256 • A DataFlash (current capacities range from 1Mbit to 64 Mbits) if audio storage functions are required • A SmartMedia card (supported capacities from 8 Mbytes to 128 Mbytes) • The parallel MPU type interface. 5.2 I/O Selection Considerations I/Os are organized in groups, which can be mutually exclusive because they share the same IC pins (please refer to the pinout to identify the exclusions). The two main types of operation are host controlled and stand-alone. 5.2.1 Host-controlled Operation There are three main possible ways of communication with a host processor: • 8-bit parallel MPU type bidirectional interface. Signals: D7 - D0, CS, WR, RD, A0, IRQ • Asynchronous serial, MIDI_IN and optionally MIDI_OUT • Synchronous serial. Signals: SDIN, SCLK, SYNC, INT 5.2.2 Stand-alone Operation Possible stand-alone modes are: • Firmware into external EEPROM or DataFlash • Firmware into external SmartMedia. In this case, the firmware should reside in the SmartMedia reserved sectors starting at sector # 1. 5 6092C–DRMSD–12-Feb-07 6. Pinout 6.1 Pin Description In the Pin Description table below: • Identical sharing number indicates multifunction pins. • Pd indicates a pin with built-in pull-down resistor. • Pu indicates a pin with built-in pull-up resistor. Table 6-1. Pinout by Pin Name Pin Number Type Sharin g GND 4, 13, 19, 25, 36, 43, 48, 57 PWR – Digital ground. All of these pins should be returned to a ground plane. VC18 12, 31, 46, 63 PWR – Core power. All of these pins should be returned to nominal 1.8V or to PWROUT if the built-in power switch is used. VC33 3, 32 PWR – Periphery power. All these pins should be returned to nominal 3.3V. PWRIN 18 PWR – Power switch input; should be returned to nominal 1.8V even if the power switch is not used. PWROUT 17 PWR – Power switch output; should be connected to all VC18 pins if the power switch is used D7 - D0 59, 58, 56, 55, 52, 51, 50, 49 I/O 1 Slave 8-bit interface data. Output if CS and RD are low (read from chip), input if CS and WR are low (write to chip). Type of data defined by A0 input. I/O7 - I/O0 59, 58, 56, 55, 52, 51, 50, 49 I/O 1 SmartMedia data or other peripheral data P0.7 - P0.0 59, 58, 56, 55, 52, 51, 50, 49 I/O 1 General-purpose I/O; can be programmed individually as input or output. CLAD3 - 0 59, 58, 56, 55 In 1 Optional bit clocks for digital audio input. Used for sampling rate conversion for external incoming digital audio such as AES/BEU or S/Pdif. WSAD3 - 0 52, 51, 50, 49 In 1 Optional word selects for digital audio input. Used for sampling rate conversion for external incoming digital audio such as AES/BEU or S/Pdif. A0 60 In 2 Slave 8-bit interface address. Indicates data/status or data/ctrl transfer type (CS/RD, low or CS/WR low) SMPD 60 In 2 SmartMedia presence detect P0.10 60 In 2 General-purpose input pin SCLK 60 In 2 Serial slave synchronous interface input clock CS 64 In 3 Slave 8-bit interface chip select, active low. P0.11 64 In 3 General-purpose input pin SYNC 64 In 3 Serial slave synchronous interface input sync signal WR 1 In 4 Slave 8-bit interface write, active low. D7 - D0 data is sampled by chip on WR rising edge if CS is low Pin Name 6 Description ATSAM3108B 6092C–DRMSD–12-Feb-07 ATSAM3108B Table 6-1. Pinout by Pin Name (Continued) Pin Number Type Sharin g SMC 1 In 4 SmartMedia configuration. This pin is sensed after power-up. If found low, it is assumed that a SmartMedia connector is present. The built-in firmware will wait for SmartMedia SMPD. P0.12 1 In 4 General-purpose input pin RD 2 In 5 Slave 8-bit interface read, active low. D7 - D0 data is output when RD goes low and CS is low R|B 2 In 5 SmartMedia Ready Busy/ status P0.13 2 In 5 General-purpose input pin IRQ 8 Out 6 Slave 8-bit interface interrupt request. High when data is ready to be transferred from chip to host. Reset by a read from host (CS = 0 and RD = 0) SMRE 8 Out 6 SmartMedia read enable (RE), active low FS0 8 In 6 Frequency sense, sensed at power up. Together with FS1, allows the firmware to know the operating frequency of the chip (see FS1). P0.8 8 I/O 6 General-purpose I/O pin INT 8 Out 6 Serial slave synchronous interface data request, active low. MIDI_IN 9 In 7 Serial MIDI in P0.14 9 In 7 General-purpose input pin SDIN 9 In 7 Serial slave synchronous interface input data MIDI_OUT 10 Out 8 Serial MIDI out Pin Name Description FS1 10 In 8 Frequency sense, sensed at power up. FS1/FS0 allow firmware to know operating frequency of chip as follows: 00 6.9552 MHz 01 9.6 MHz 10 11.2896 MHz 11 12.288 MHz P0.9 10 I/O 8 General-purpose I/O 42, 41, 40, 39 Out - Four stereo channels of digital audio output, I2S format CLBD 6 Out - Audio bit clock for DABD3 - 0. Audio bit clock for DAAD3 - 0 if the corresponding CLAD3 - 0 is not used. WSBD 7 Out - Audio left/right channel select for DABD3 - 0. Audio left/right channel for DAAD3 - 0 if the corresponding WSAD3 - 0 is not used. CKOUT 5 Out - External DAC/Codec master clock. Same frequency as X2 pin. Can be programmed to be 128xFs, 192xFs, 256xFs, 384xFs, where Fs is the DAC/Codec sampling rate. DAAD0 34 In 9 Stereo audio data input, I2S format. Can operate on CLBD master rate or CLAD0 external rate when sampling rate conversion is requested. P0.15 34 In 9 General-purpose input pin 38, 37, 35 In Pd - Three additional channels of stereo audio input, I2S format. Can individually operate on CLBD master rate or corresponding CLAD3 - 1 when sampling rate conversion is requested. DAAD3 - 1 have built-in pull-downs. They may be left open if not used. DABD3 - 0 DAAD3 - 1 7 6092C–DRMSD–12-Feb-07 Table 6-1. Pinout by Pin Name (Continued) Pin Number Type Sharin g MUTE 11 I/O 10 External DAC/Codec Mute. Sensed at power up. If found high, then MUTE becomes an active high output. If found low, then MUTE becomes an active low output. P1.6 11 I/O 10 General-purpose I/O pin SMCE 29 Out 11 SmartMedia chip enable (CE), active low P1.5 29 I/O 11 General-purpose I/O pin SMALE 28 Out 12 SmartMedia address latch enable (ALE) P1.4 28 I/O 12 General-purpose I/O pin SMWE 27 Out 13 SmartMedia write enable (WE), active low P1.3 27 I/O 13 General-purpose I/O pin SMCLE 26 Out 14 SmartMedia command latch enable (CLE) P1.2 26 I/O 14 General-purpose I/O pin DFCS 14 Out - DataFlash chip select DFSI 16 Out - DataFlash serial input (to DataFlash) DFSO 21 In Pd - DataFlash serial output (from DataFlash). This pin has a built-in pulldown. It may be left open if not used. DFSCK 15 Out - DataFlash data clock 30, 62, 61, 54, 53 I/O Pu - Five general-purpose I/O pins. These pins have built-in pull-ups. They may be left open if not used. Pin Name P1.15 – P1.11 X1 – X2 LFT RESET Description 45, 44 - - External crystal connection. Standard frequencies are 6.9552 MHz, 9.6 MHz, 11.2896 MHz, 12.288 MHz. Max frequency is 12.5 MHz. An external clock (max. 1.8 VPP) can be connected to X1 using AC coupling (22 pF). A built-in PLL multiplies the clock frequency by 4 for internal use. 47 - - PLL decoupling RCR filter - Master reset Schmitt trigger input, active low. RESET should be held low during at least 10 ms after power is applied. On the rising edge of RESET, the chip enters an initialization routine, which may involve firmware download from an external SmartMedia, DataFlash or host. 22 In STIN 23 In Pd - Serial test input. This is a 57.6 Kbaud asynchronous input used for firmware debugging. This pin is tested at power-up. The built-in debugger starts if STIN is found high. STIN has a built-in pull-down. It should be grounded or left open for normal operation. STOUT 24 Out - Serial test output. 57.6 Kbaud async output used for firmware debugging. PDWN 20 In - Power down input, active low. High level on this pin is typ. VC18. When PDWN is low, the oscillator and PLL are stopped, the power switch opens, and the chip enters a deep sleep mode (1 µA typ. consumption when power switch is used). To exit from power down, PDWN has to be set high then RESET applied. Alternate programmable power-downs are available which allow warm restart of the chip. TEST 33 In Pd - Test input. Should be grounded or left open. 8 ATSAM3108B 6092C–DRMSD–12-Feb-07 ATSAM3108B 6.2 Pinout by Pin Number Table 6-2. PiN # ATSAM3108B Pinout by Pin Number Name PiN# Name PiN# Name PiN# Name 1 WR SMC P0.12 17 PWROUT 33 TEST 49 D0 I/O0 P0.0 WSAD0 2 RD R|B P0.13 18 PWRIN 34 DAAD0 P0.15 50 D1 I/O1 P0.1 WSAD1 3 VC33 19 GND 35 DAAD1 51 D2 I/O2 P0.2 WSAD2 4 GND 20 PDWN/ 36 GND 52 D3 I/O3 P0.3 WSAD3 5 CKOUT 21 DFSO 37 DAAD2 53 P1.11 6 CLBD 22 RESET 38 DAAD3 54 P1.12 7 WSBD 23 STIN 39 DABD0 55 D4 I/O4 P0.4 CLAD0 8 IRQ SMRE FS0 P0.8 24 STOUT 40 DABD1 56 D5 I/O5 P0.5 CLAD1 9 MIDI_IN P0.14 SDIN 25 GND 41 DABD2 57 GND 10 MIDI_OUT FS1 P0.9 26 SMCLE P1.2 42 DABD3 58 D6 I/O6 P0.6 CLAD2 11 MUTE P1.6 27 SMWE P1.3 43 GND 59 D7 I/O7 P0.7 CLAD3 12 VC18 28 SMALE P1.4 44 X2 60 A0 SMPD P0.10 SCLK 13 GND 29 SMCE P1.5 45 X1 61 P1.13 14 DFCS 30 P1.15 46 VC18 62 P1.14 15 DFSCK 31 VC18 47 LFT 63 VC18 16 DFSI 32 VC33 48 GND 64 CS P0.11 SSYNC 9 6092C–DRMSD–12-Feb-07 7. Marking FRANCE SAM 3108B Y Y W W 58 A05 B XXXXXXXXX Pin 1 8. Mechanical Dimensions Figure 8-1. 10 Thin Plastic 64-lead Quad Flat Pack (LQFP64) ATSAM3108B 6092C–DRMSD–12-Feb-07 ATSAM3108B Table 8-1. Package Dimensions in mm Denomination Min Nom Max A 1.40 1.50 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 L 0.45 0.60 0.75 D 12.00 D1 10.00 E 12.00 E1 10.00 P 0.50 B 0.17 0.22 0.27 9. Electrical Characteristics 9.1 Absolute Maximum Ratings (*) Ambient Temperature (power applied).............. -40° C to 85° C Storage Temperature ...................................... -65° C to 150° C Voltage on any pin X1, LFT ....................................................... -0.3 to VC18 + 0.3V Others ......................................................... -0.3 to VC33 + 0.3V Supply Voltage.......................................................................... VC18 ....................................................................-0.3V to 1.95V VC3 .......................................................................-0.3V to 3.6V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum IOL per I/O pin................................................. 4 mA 9.2 Recommended Operating Conditions Table 9-1. Recommended Operating Conditions Symbol Parameter Min Typ Max Unit VC18 Supply voltage 1.65 1.8 1.95 V VC33 Supply voltage (1) 3 3.3 VC18 + 1.5 3.6 V PWRIN Supply voltage PWRIN pin 1.75 1.9 1.95 V TA Operating ambient temperature 0 - 70 °C Note: 1. Operation at lower VC33 values down to VC18 is possible, however external timing may be impaired. Contact Atmel in case of use of these circuits with VC33 outside the recommended operating range. 11 6092C–DRMSD–12-Feb-07 9.3 DC Characteristics Table 9-2. DC Characteristics (T A = 25°C, VC18 =1.8V ± 10%, VC33 = 3.3V ± 10%) Symbol Parameter Min Typ Max Unit VIL Low level input voltage -0.3 - 1.0 V VIH High level input voltage, except X1, PDWN 2.3 - VC33 + 0.3 V VIH High level input voltage X1, PDWN 1.2 - VC18 + 0.3 V VOL Low level output voltage IOL = -2 mA - - 0.4 V VOH High level output voltage IOH = 2 mA 2.9 - - V ICC1 VC18 power supply current (crystal freq.=11.2896 MHz, all 8 P24s running) - 63 - mA ICC2 VC18 power supply current (crystal freq. = 11.2896 MHz, all P24s stopped) - 22 - mA ICC3 VC18 power supply current (crystal freq. = 11.2896 MHz, all P24 stopped, warm start power-down active) - 4 - mA ICC4 VC18 deep power down supply current (using power switch) - 1 10 µA PU/PD Built-in pull-up/pull-down resistor 10 - 56 kΩ 12 ATSAM3108B 6092C–DRMSD–12-Feb-07 ATSAM3108B 10. Peripherals and Timings 10.1 8-bit Slave Parallel Interface The Slave Parallel Interface is typically used to connect the chip to a host processor. Pins used: D7 - D0 (I/O), CS (Input), A0 (Input), WR (Input), RD (Input), IRQ (Output). 10.1.1 Timings Figure 10-1. Host Interface Read Cycle A0 t AVCS CS t CSLRDL t PRD t RDHCSH RD t RDLDV t DRH D0 - D7 Figure 10-2. Host Interface Write Cycle A0 t AVCS CS t CSLW RL t PW R t WRHCSH RD t DW S t DW H D0-D7 Table 10-1. Timing Parameters Symbol Parameter Min Typ Max Unit tAVCS Address valid to chip select low 0 - - ns tCSLRDL Chip select low to RD low 5 - - ns tRDHCSH RD high to CS high 5 - - ns tPRD RD pulse width 50 - - ns tRDLDV Data out valid from RD - - 20 ns tDRH Data out hold from RD 5 - 10 ns tCSLRWRL Chip select low to WR low 5 - - ns tWRHCSH WR high to CS high 5 - - ns 13 6092C–DRMSD–12-Feb-07 Table 10-1. 10.1.2 Timing Parameters (Continued) Symbol Parameter Min Typ Max Unit tPWR WR pulse width 50 - - ns tDWS Write data setup time 10 - - ns tDWH Write data hold time 0 - - ns IO Status Register 7 TE 6 RF 5 X 4 X 3 X 2 X 1 X 0 X Status register is read when A0 = 1, RD = 0, CS = 0. • TE: Transmit Empty If 0, data from ATSAM3108B to host is pending and IRQ is high. Reading the data at A0 = 0 will set TE to 1 and clear IRQ. • RF: Receiver full. If 0, then ATSAM3108B is ready to accept DATA from host. Note: If status bit RF is not checked by host, write cycle time should not be lower than 3 µs. 10.2 SmartMedia and Other Peripheral Interfaces The SmartMedia and Other Peripheral Interfaces is a master 8-bit parallel interface that provides connection to SmartMedia or other peripherals such as LCD screens. Pins used: I/O7 - I/O0 (I/O), SMPD (input), SMCE, SMALE, SMCLE, SMRE, SMWE (outputs) All of these pins are fully under firmware control, therefore timing compatibility is ensured by firmware only. 10.3 EEPROM/DataFlash Interface The EEPROM/DataFlash interface is a master synchronous serial interface, operating in SPI mode 0. Pins used: DFCS, DFSI, DFSCK (outputs), DFSO (input) The DFSCK frequency is firmware programmable from fck to fck/64, where fck is the crystal frequency. Thus a large variety of EEPROM/DataFlash devices can be accommodated. Please refer to Atmel DataFlash datasheets for accurate SPI mode 0 timing. Figure 10-3. DataFlash Interface Typical Timing DFSCK DFSI DFSO 14 LSB MSB ATSAM3108B 6092C–DRMSD–12-Feb-07 ATSAM3108B 10.4 Serial Slave Synchronous Interface The ATSAM3108B can be controlled by an external host processor through this unidirectional serial interface. However, no firmware can be downloaded at power-up through this interface. Therefore an external ROM/Flash/EEPROM is required. Pins used: SCLK, SYNC, SDIN (inputs) INT (output) Data is shifted into MSB first. The IC samples an incoming SDIN bit on the rising edge of SCLK, therefore the host should change SDIN on the negative SCLK edge. SYNC allows initial synchronization. The rising edge of SYNC, which should occur with SCLK low, indicates that SDIN will hold MSB data on the next rising SCLK. The data is stored internally into a 256-byte FIFO. When the FIFO count is below 64, the INT output goes low. This allows the host processor to send data in burst mode. The maximum SCLK frequency is tck (tck being the crystal frequency). The minimum time between two bytes is 64 tck periods. The contents of the SDIN data are defined by the firmware. Figure 10-4. Serial Slave Interface Typical Timing SCLK SYNC SDIN 10.5 MSB Digital Audio Pins used: CLBD (output), WSBD (output) DABD3 - 0 (outputs) DAAD3 - 0 (inputs) Optionally: CLAD3 - 0 (inputs), WSAD3 - 0 (inputs) The ATSAM3108B allows for 8 digital audio output channels and 8 digital audio input channels. All audio channels are normally synchronized on single clocks CLBD, WSBD which are derived from the IC crystal oscillator. However, as a firmware option, the DAAD3 - 0 inputs can be synchronized with incoming CLAD3 - 0 and WSAD3 - 0 signals. In this case, the incoming sampling frequencies must be lower or equal to the chip sampling frequency. The digital audio timing follows the I2S standard, with up to 24 bits per sample 15 6092C–DRMSD–12-Feb-07 Figure 10-5. Digital Audio Timing tCW tCW tCLBD WSB CLB tSOD tSOD DABD3 - 0 DAAD3 - 0 Table 10-2. Digital Audio Timing Parameters Symbol Parameter Min Typ Max Unit tCW CLBD rising to WSBD change tC - 10 - - ns tSOD DABD valid prior/after CLBD rising tC - 10 - - ns tCLBD CLBD cycle time - 2 * tC - ns tC is related to tCK, the crystal period at X1 as follows: Table 10-3. Sample Frequency Sample Frequency WSBD Typical Sample Frequency tC CLBD/WSBD Frequency Ratio 1/(tCK * 128) 96 kHz tCK 64 1/(tCK * 192) 64 kHz 2 * tCK 48 1/(tCK * 256) 48 kHz 2 * tCK 64 1/(tCK * 384) 32 kHz 4 * tCK 48 The choice of sample frequency is done by firmware. 10.6 Digital Audio Frame Format, 128 x Fs and 256 x Fs Modes WSB CLDB DABD3 - 0 DAAD3 - 0 MSB 16 LSB (16 bits) LSB (24 bits) MSB ATSAM3108B 6092C–DRMSD–12-Feb-07 ATSAM3108B 10.7 192 x Fs and 384 x Fs Modes WSB CLDB DABD3 - 0 DAAD3 - 0 MSB 10.8 LSB (16 bits) LSB (24 bits) MSB Serial MIDI_IN and MIDI_OUT The serial MIDI IN and OUT signals are asynchronous signals following the MIDI transmission standard: • Baud rate: 31.25 kHz • Format: start, 8 data bits, 1 stop 17 6092C–DRMSD–12-Feb-07 11. Reset and Power-down During power up, the RESET input should be held low until the crystal oscillator and PLL are stabilized, which takes max. 10 ms. After the low to high transition of RESET, the following happens: • All P24s enter an idle state. • P16 program execution starts in built-in ROM. The power-up sequence is as follows: • STIN is sensed. If HIGH, then the built-in debugger is started. • SMC is sensed. If LOW, then the built-in loader waits for SmartMedia presence detect (SMPD). When detected, the firmware is down loaded from SmartMedia reserved sector 1 and started. • An attempt is made to read the first two bytes of an external EEPROM or DataFlash. If "DR" is read, then the built-in loader loads the firmware from the external EEPROM/DataFlash and starts it. • Firmware download from a host processor is assumed. 1. The 0ACh byte is written to the host, this raises IRQ. The host can recognize that the chip is ready to accept program download. Higher speed transfer can be reached by polling the parallel interface status (CS = 0, A0 = 1, RD = 0). 2. The host sends the firmware size (in words) on two bytes (Low byte first). 3. The host sends the ATSAM3108B firmware. The firmware should begin with string "DR". 4. The 0ACh byte is written to the host, this raises IRQ. The host can recognize that the chip has accepted the firmware. 5. ATSAM3108B starts the firmware. If PDWN is asserted low, then the crystal oscillator and PLL will be stopped. If the power switch is used, then the chip enters a deep power down sleep mode, as power is removed from the core. To exit power down, PDWN has to be asserted high, then RESET applied. Other power reduction features allowing warm restart are controlled by firmware: • P24s can be individually stopped. • The clock frequency can be internally divided by 256. 18 ATSAM3108B 6092C–DRMSD–12-Feb-07 ATSAM3108B 12. Recommended Board Layout Like all HCMOS high integration ICs, following simple rules of board layout is mandatory for reliable operations: • GND, VC33, VC18 distribution, decoupling All GND, VC33, VC18 pins should be connected. A GND plane is strongly recommended. The board GND + VC33 distribution should be in grid form. Recommended VC18 decoupling is 0.1 µF at each corner of the IC with an additional 10 µF decoupling close to the crystal. VC33 requires a single 0.1 µF decoupling. • Crystal, LFT The paths between the crystal, the crystal compensation capacitors, the LFT filter R-C-R and the IC should be short and shielded. The ground return from the compensation capacitors and LFT filter should be the GND plane from the IC. • Buses. A ground plane should be implemented below the D0 - D7 bus that connects both to the host and to the IC GND. • Analog Section A specific AGND ground plane should be provided, which connects by a single trace to the GND ground. No digital signals should cross the AGND plane. Refer to the Codec vendor recommended layout for correct implementation of the analog section. 19 6092C–DRMSD–12-Feb-07 13. Recommended Crystal Compensation and LFT Filter Figure 13-1. 20 Recommended Crystal Compensation and LFT Filter ATSAM3108B 6092C–DRMSD–12-Feb-07 ATSAM3108B 14. Product Development and Debugging Atmel provides an integrated product development and debugging tool SamVS. SamVS runs under Windows® (98, ME, 2000, XP). Within the environment, it is possible to: • Edit • Assemble • Debug on real target (In-circuit Emulation) • Program Dataflash, EEPROM, SmartMedia on target. Two dedicated IC pins, STIN and STOUT allow running firmware directly into the target using standard PC COM port communication at 57.6 Kbauds. Thus time-to-market is optimized by testing directly on the final prototype. A library of frequently used functions is available, such as: • Reverb/Chorus • MP3 decode • 31-band equalizer • Parametric equalizer Atmel engineers are available to study customer-specific applications. 21 6092C–DRMSD–12-Feb-07 Revision History Table 14-1. Doc. Rev Comments 6092A First issue; 19-Nov-04 6092B TQFP package ref changed to LQFP 6092C Changed all references ATSAM3108 to ATSAM3108B. Added Section 7. ”Marking” on page 10. 22 Change Request 2639 ATSAM3108B 6092C–DRMSD–12-Feb-07 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 1150 East Cheyenne Mtn. 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