MP7643 4-Channel, Programmable Gain Voltage Output, 15 MHz Input Bandwidth 8-Bit DACs with Multiplying Parallel Digital Data Port FEATURES • DNL = +0.5 LSB, INL = +1 LSB (typ) • DACs Matched to +0.5% (typ) • Low Harmonic Distortion: 0.25% typical with VREF = 1 V p-p @ 1 MHz • Latch-Up Free • ESD Protection: 2000 V Minimum • Programmable Gain • 4 Independent 2-Quadrant Multiplying 8-Bit DACs with Output Amplifiers • Dual Positive (+10 V and +5 V) Supplies or Dual (+5 V) Supplies Capability • High Speed: – 12.5 MHz Digital Clock Rate – VREF to VOUT Settling Time: 150ns to 8-bit (typ) – Voltage Reference Input Bandwidth: 15 MHz • Very Low Noise Gain Control • Low Power: 80mW • Low AC Voltage Reference Feedthrough • Excellent Channel-to-Channel Isolation APPLICATIONS • Direct High-Frequency Automatic Gain Control • Video AGC & CCD Level AGC • Convergence Adjustment for High-Resolution Monitors (Workstations) • Multiplier Replacement GENERAL DESCRIPTION fast output settling time of 150 ns, and excellent VREF feedthrough isolation. The negative feedback terminal of the output op amp is available for user gain control. In addition, low distortion in the order of 0.25% with a 1 V p-p, 1 MHz signal is achieved. The MP7643 is ideal for digital gain control of high frequency analog signals such as video, composite video and CCD. The device includes 4-channels of high speed, wide bandwidth, two quadrant multiplying, 8-bit accurate digital-to-analog converter. It includes an output drive buffer per channel capable of driving a +1mA (typ) load. DNL of better than +0.5 LSB is achieved with a channel-to-channel matching of typically 0.5%. Stability, matching, and precision of the DACs are achieved by using MPS’ thin film technology. Excellent channel-to-channel isolation is also achieved with MPS’ BiCMOS process which cannot be achieved using a typical CMOS technology. The combination of a constant input Z and the ability to vary VREFN within VCC –1.8 V to VEE +1.5 V allows flexibility for optimum system design. The MP7643 is fabricated on a junction isolated, high speed BiCMOS (BiCMOS IVTM) process with thin film resistors. This process enables precision high speed analog/digital (mixedmode) circuits to be fabricated on the same chip. An open loop architecture (patent pending) provides wide small signal bandwidth from VREF to output up to 15 MHz (typ), ORDERING INFORMATION Package Type Temperature Range Part No. INL (LSB) DNL (LSB) Gain Error (% FSR) SOIC –40 to +85°C Plastic Dip MP7643AS +1 +0.5 +1.5 –40 to +85°C MP7643AN +1 +0.5 +1.5 Rev. 1.00 1 MP7643 SIMPLIFIED BLOCK DIAGRAM VDD VCC VEE VREF1 DBO LATCH1 DAC1 DB7 (MSB) VOUT1 INV1 VREF2 LATCH2 DAC2 VOUT2 INV2 VREF3 LATCH3 DAC3 VOUT3 INV3 VREF4 LATCH4 DAC4 INV4 LD A1 VOUT4 Control Logic VREFN A0 DGND Rev. 1.00 2 MP7643 PIN CONFIGURATIONS See Packaging Section for Package Dimensions DB5 DB6 VDD VCC VEE DB7 1 28 2 27 3 26 4 25 5 24 6 23 VREFN DGND INV1 VOUT1 VREF1 VREF2 VOUT2 INV2 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 DB4 DB3 LD DB2 DB1 DB0 A1 A0 INV4 VOUT4 VREF4 VREF3 VOUT3 INV3 DB5 DB6 VDD VCC VEE DB7 1 28 2 27 3 26 4 25 5 24 6 23 VREFN DGND INV1 VOUT1 VREF1 VREF2 VOUT2 INV2 7 22 8 21 9 20 10 19 11 18 12 17 28 Pin PDIP (0.300”) NN28 13 16 14 15 DB4 DB3 LD DB2 DB1 DB0 A1 A0 INV4 VOUT4 VREF4 VREF3 VOUT3 INV3 28 Pin SOIC (Jedec, 0.300”) S28 PIN OUT DEFINITIONS PIN NO. NAME 1 DB5 DESCRIPTION PIN NO. NAME DESCRIPTION Data Input Bit 5 15 INV3 Inverting Input 3 2 DB6 Data Input Bit 6 16 VOUT3 DAC 3 Output 3 VDD Digital Positive Supply 17 VREF3 DAC 3 Positive Reference Input 4 VCC Analog Positive Supply 18 VREF4 DAC 4 Positive Reference Input 5 VEE Analog Negative Supply 19 VOUT4 DAC 4 Output 6 DB7 Data Input Bit 7 20 INV4 Inverting Input 4 7 VREFN Negative Reference Input 21 A0 DAC Address Bit 0 8 DGND Digital Ground 22 A1 DAC Address Bit 1 9 INV1 Inverting Input 1 23 DB0 Data Input Bit 0 10 VOUT1 DAC 1 Output 24 DB1 Data Input Bit 1 11 VREF1 DAC 1 Positive Reference Input 25 DB2 Data Input Bit 2 12 VREF2 DAC 2 Positive Reference Input 26 LD Load Data to Selected DAC 13 VOUT2 DAC 2 Output 27 DB3 Data Input Bit 3 14 INV2 Inverting Input 2 28 DB4 Data Input Bit 4 Rev. 1.00 3 MP7643 ELECTRICAL CHARACTERISTICS TABLE FOR DUAL SUPPLIES Unless Otherwise Noted: VDD = 5 V, VCC = +5 V, VEE = –5 V, VREF = 3 V and –3 V, T = 25°C, Output Load = No Resistive Load, VREFN = DGND = 0 V, Gain = 1 Parameter Symbol Min N DNL INL 8 25°C Typ Max Units +0.8 +1 Bits LSB LSB Test Conditions/Comments DC CHARACTERISTICS Resolution (All Grades) Differential Non-Linearity Integral Non-Linearity Monotonicity Gain Error Zero Scale Offset Output Drive Capability +0.5 +1 Guaranteed GE ZOFS IO +1.5 +50 +1 % FSR mV mA FSR = Full Scale Range1 REFERENCE/INV INPUTS Impedance of VREF Voltage Range INV DC Voltage Range REF VRP VRN 6 VEE +1.5 VEE +1 18 VCC –1.8 0 kΩ V V DYNAMIC CHARACTERISTICS2 Input to Output Bandwidth Input to Output Settling Time5 Small Signal Voltage Reference Input to Output Bandwidth Small Signal Voltage Reference Input to Output Bandwidth Voltage Settling from VREF to VDAC Out Voltage Settling from Digital Code to VDAC Out VREF Feedthrough Group Delay Harmonic Distortion Channel-to-Channel Crosstalk Digital Feedthrough Power Supply Rejection Ratio VREF Max Swing is VREFN +3 V RL = 5 k, CL = 20 pF ƒtr 15 150 15 MHz ns MHz VR = 1.6 V p–p, RL = 5k to VEE VR = 1.6 V p–p, RL = 5k to VEE VOUT=50mV p-p above code 16 ƒtr 15 MHz VOUT=50mV p-p for all codes tsr 300 ns tsd 300 ns VR=0 to VR = 3V Step6 to 1 LSB ZS to FS to 1 LSB FDT GD THD CT Q PSRR TBD TBD TBD TBD TBD +0.05 dB ns % dB nVS %/% Codes=0 @ 1 MHz VREF=1MHz Sine 3V p-p @ 1 MHz, single channel CLK to VOUT ∆V=+5% mA mA mW VREF = 0 V VREF = 0 V VREF = 0 V, Codes = all 1 POWER CONSUMPTION Positive Supply Current Negative Supply Current Power Dissipation ICC IEE 12 12 80 PDISS DIGITAL INPUT CHACTERISTICS Logic High3 Logic Low3 Input Current Input Capacitance2 VIH VIL IL CL 2.4 0.8 +10 8 Rev. 1.00 4 V V µA pF MP7643 ELECTRICAL CHARACTERISTICS TABLE Description Symbol Min tAS tAH tDS tDH tLD tPR 70 0 70 0 70 50 25°C Typ Max Units Conditions DIGITAL TIMING SPECIFICATIONS (2, 4) Address to LD Setup Address to LD Hold Data to LD Setup Data to LD Hold LD Pulse Width PRESET Pulse Width ns ns ns ns ns ns NOTES 1 Full Scale Range (FSR) is 3V. 2 Guaranteed but not production tested. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 See Figure 1. 5 For reference input pulse: tR = tF > 100 ns. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 VCC to VREFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5 V VEE to VREFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6.5 V VCC to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0 V VEE to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6.5 V VREF 1-4 to DGND, VREFN . . . . . . . . . . . . . . . . . . VCC to VEE VOUT 1-4 to DGND, VREFN . . . . . . . . . . . . . . . . . . VCC to VEE Digital Input & Output Voltage to DGND –0.5 to VDD +0.5 V Operating Temperature Range Extended Industrial . . . . . . . . . . . . . . . . . . . –40°C to +85°C Maximum Junction Temperature . . . . . . . . . –65°C to 150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C Package Power Dissipation Rating @ 75°C PDIP, SOIC, PLCC . . . . . . . . . . . . . . . . . . . . . . . 1050mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 14mW/°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. Rev. 1.00 5 MP7643 tAS tAH tDS tDH A1, A0 DB0 to DB7 tLD LD 1/2 LSB tSD VOUT 1/2 LSB Figure 1. Timing Diagram To DAC1 Latch Enable A1 A0 L ↑ L L L L DAC1 Transparent DAC1 Latched To DAC3 Latch Enable L ↑ L L H H DAC2 Transparent DAC2 Latched To DAC4 Latch Enable L ↑ H H L L DAC3 Transparent DAC3 Latched L ↑ H H H H DAC4 Transparent DAC4 Latched H X X No Operation To DAC2 Latch Enable 2-4 Decoder A0, A1 LD LD Figure 2. Input Control Logic (Simplified) Block Diagram Operation Table 1. Truth Table D0 DAC Output Voltage D LSB VOi = VREFN + (VRi – AGND) ( 256 ) D7 MSB D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 0 0 VREFN 0 0 0 0 0 0 0 1 1 (VRi – VREFN) ( 256 ) + VREFN 1 1 1 1 1 1 1 0 254 (VRi – VREFN) ( 256 ) + VREFN 1 1 1 1 1 1 1 1 255 (VRi – VREFN) ( 256 ) + VREFN Note: These outputs must be ratioed up for gain in the output amplifier. Table 2. DAC Transfer Function Analog Output vs. Digital Code (With VREF Shorted to INV) Rev. 1.00 6 MP7643 THEORY OF OPERATION The MP7643 is a 4-channel multiplying D/A converter that incorporates a novel open loop architecture invented by MPS. The design produces the wider bandwidth, faster settling time, more constant group delay, and a lower noise operation compared to the conventional R-2R based architectures. This device is particularly useful in applications where analog multipliers are used to perform the gain adjustment function for high frequency analog signal conditioning. Analog multipliers produce higher noise and offset. This design allows for digital control of gain with constant and very low noise from the low gain through high gain ranges of operation. Power Supplies and Voltage Reference DC Voltage Ranges For the single supply operation, VCC = +10 V, VDD = +5 V, and VEE = GND = 0 V. The VOUT 1-4 and VREF 1-4 range would be VCC –1.8 V (10 – 1.8 = 8.2 V) to VEE +1.5 V (0 + 1.5 = 1.5 V). VREFN is the equivalent of AGND for this DAC. In this mode VREFN can be set at (VCC + VEE)/2 = (10 + 0)/2 = 5 V. VREFN DC range can, however, be set from VEE +1.5 = 1.5 V to VCC – 1.5 = 8.2 V. Refer to Table 2. for the relationship equations. For the dual supply operation, VCC = +5, VDD = +5, and VEE = –5 V. The VOUT 1-4 and VREF 1-4 range would be VCC –1.8 V (5 V –1.8 = 3.2 V) to VEE +1.5 V (–5 + 1.5 = –3.5 V). In this mode VREFN can be set to (VCC + VEE)/2 = (5 – 5)/2 = 0 V. However, VREFN DC range can be set from VEE +1.5 V = 3.5 V to VCC –1.8 = +3.2 V. Refer to Table 2. for the relationship equations. Linearity Characteristics Each DAC achieves DNL +0.5 LSB (typ), INL +1 LSB (typ), and gain error +1.5%. Since all 4 channel D/A converters are fabricated on the same IC, the linearity matching and gain matching of +0.5% (typ) is achieved. About the INV Input and its DC Voltage Range AC and Transient Settling Characteristics VCC The novel subranging architecture delivers a 15 MHz (typ.) –3 dB bandwidth. With all codes = 1 and a 1.6 V step impulse at VREF(1-4), the analog output settles to 8 bits of accuracy in typically 150 ns (with RL = 5k to VEE). Also with VREF = 3 V or –3 V and a FS to ZS or ZS to FS code change, the respective analog output settles to 8 bits typically in 300 ns. Note that the AC performance specifications also match between all 4 channels. The above AC and transient performance is achieved with each channel consuming only 20 mW (typ.) with either 5 V or 0 V to 10 V supplies. VREF 1-4 +1 DAC Q2 Q1 VREFN VOUT 1-4 INV 1-4 I1 VEE Digital Interface Figure 3. Simplified Block Diagram The MP7643 allows direct interface to most microprocessor buses without additional I/O circuitry. Figure 1. and Figure 2. describe the operation, specification and interface characteristics of the logic port. As noted in the specification table, the max DC value of the INV input pin is VO. Figure 3. shows a simplified block diagram of the internal circuitry around INV. If VINV exceeds VO, Q1 will saturate and the amp and consequently the DAC becomes nonfunctional. The address bits A0 and A1 determine which D/A channel is selected. When LD input is low the respective latch of the D/A is enabled (digital input data becomes transparent to the latch and the selected DAC channel), and digital data is loaded into the selected DAC. The min DC range of INV is limited to Vbe (Q1) and VCE (sat) of I1. Therefore, INV (min-DC) = VEE +1 V. Rev. 1.00 7 MP7643 1 Relative Accuracy (LSB) 0.75 0.5 0.25 0 –0.25 –0.5 –0.75 –1 0 64 128 192 Digital Code Graph 1. Relative Accuracy vs. Digital Code DACs 1 to 4 Gain (5dB/DIV) Group Delay (20 ns/DIV) MHz Graph 2. Typical Gain and Group Delay vs. Frequency (with 5K Resistor Across Output to VEE) Rev. 1.00 8 256 MP7643 28 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) NN28 S 28 15 1 14 Q1 E1 E D A1 Seating Plane A L B e B1 α MILLIMETERS INCHES SYMBOL MIN MAX MIN MAX A 0.130 0.230 3.30 5.84 A1 0.015 –– 0.381 –– B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 1.340 1.485 34.04 37.72 E 0.290 0.325 7.37 8.26 E1 0.240 0.310 6.10 7.87 e 0.100 BSC L 0.115 α 0.150 2.54 BSC 2.92 3.81 0° 15° 0° 15° Q1 0.055 0.070 1.40 1.78 S 0.020 0.100 0.508 2.54 Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 1.00 9 C MP7643 28 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S28 D 28 15 E H 14 h x 45° C A Seating Plane α B e A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.097 0.104 2.464 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.483 C 0.0091 0.0125 0.231 0.318 D 0.701 0.711 17.81 18.06 E 0.292 0.299 7.42 7.59 e 0.050 BSC MAX 2.642 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° Rev. 1.00 10 MP7643 Notes Rev. 1.00 11 MP7643 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1995 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 1.00 12