MP8868 High-Efficiency, 10A, 17V, Synchronous Step-Down Converter with I2C Interface The Future of Analog IC Technology DESCRIPTION FEATURES The MP8868 is a high-frequency, synchronous, rectified, stepdown, switch-mode converter with an I2C control interface. Its fully integrated solution achieves a 10A output current with excellent load and line regulation over a wide input-supply range. • • • • Wide 4.5V-to-17V Operating Input Range 1% Internal Reference Accuracy I2C Programmable Reference Output Voltage Range from 0.6V to 1.87V in 10mV Steps with Slew Rate Control I2C Selectable Switching Frequency 200kHz-2MHz Synchronized External Clock OTP, OCP Hiccup Indication Via I2C Selectable PSM and Fs Through I2C Programmable Soft-Start Time Open-Drain Power Good Indicator Small 3x4mm QFN14 Package The reference voltage level is controlled on-thefly by the I2C serial interface with the reference voltage range adjustable from 0.6V to 1.87V in 10mV steps. In addition, the voltage scaling slew rate, the switching frequency, enable, and power-save mode are selectable through the I2C interface. • • • • • • • Current-mode operation provides fast transient response and eases loop stabilization. EN/SYNC supports external clock synchronization, and an open-drain power good pin indicates when the output voltage is in the nominal range. Full protection features include: APPLICATIONS • • • All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. Over-voltage protection (OVP) Hiccup over-current protection (OCP) Thermal shutdown • • • • SoC and Media Processors FPGA-based Systems ASIC Supplies Distributed Power Systems The MP8868 requires a minimal number of readily available, standard, external components, and it is available in a QFN-14 (3x4mm) package. TYPICAL APPLICATION 100 90 80 70 60 50 40 30 0.01 MP8868 Rev.1.1 5/15/2015 0.10 1.00 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 10.00 1 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER ORDERING INFORMATION Part Number* MP8868GLE Package QFN-14 (3mmx4mm) Top Marking See Below * For Tape & Reel, add suffix –Z (e.g. MP8868GLE–Z); TOP MARKING MP: MPS prefix: Y: year code; W: week code: 8868: first four digits of the part number; LLL: lot number; E: product code; PACKAGE REFERENCE QFN-14 (3mmx4mm) MP8868 Rev.1.1 5/15/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 2 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance VIN …………………………….. ........-0.3V to 19V VSW………………………………… -0.3V (-6V for <10ns) to 20V (24V for <10ns) VBST…………………………………. ..... VSW+5.5V All Other Pins……………… ....... -0.3V to 5.5V (2) (3) Continuous Power Dissipation (TA = +25°C) QFN 3x4……………………………………2.6W Junction Temperature…………………….150°C Lead Temperature…………………………260°C Storage Temperature……………-65°C to 150°C QFN (3x4)…. .…….. …….. ..... 48 ...... 11... °C/W Recommended Operating Conditions (4) Supply Voltage VIN…………………..4.5V to 17V Output Voltage VOUT ………………………0.6V to VIN x DMAX or 5.5V(5) Operating Junction Temp. (TJ). -40°C to +125°C MP8868 Rev.1.1 5/15/2015 (6) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) About the details of EN pin’s ABS MAX rating, please refer to Page 15, Enable/SYNC control section. 3) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 4) The device is not guaranteed to function outside of its operating conditions. 5) The output voltage can’t exceed 5.5V absolute maximum value at any input condition. 6) Measured on JESD51-7, 4-layer PCB. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 3 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER ELECTRICAL CHARACTERISTICS VIN = 12V, TJ = -40°C to 125°C(7), unless otherwise noted, typical value is based on average value when TJ=25oC. Parameter Symbol Supply Current (Shutdown) IIN Supply Current (Quiescent) Iq HS Switch-On Resistance LS Switch-On Resistance HSRDS-ON LSRDS-ON Switch Leakage SWLKG High Side Current Limit(8) ILIMIT_H Oscillator Frequency fSW Fold-Back Frequency SYNC Frequency Range fVOUT fSYNC Maximum Duty Cycle DMAX Minimum On Time(8) tON_MIN FB Voltage VOUT FB pin Current A0 pin High Level A0 pin Low Level EN Pull-up Current EN Rising Threshold EN Hysteresis EN Turn Off Delay VIN Under-Voltage Threshold-Rising Lockout VIN Under-Voltage Lockout Threshold-Hysteresis Power Good UV Threshold Rising Power Good Falling MP8868 Rev.1.1 5/15/2015 UV Threshold Condition Min VEN = 0V VEN = 2V, No Switching, PFM mode VBST-SW = 5V VCC = 5V VEN = 0V, VSW =12V or 0V, TJ = 25°C Under 40% Duty Cycle TJ = 25°C TJ = -40°C to 125°C VFB = 150mV 9 13 μA 560 800 μA 11.7 14 400 350 500 VFB = fs=500kHz 500mV, mΩ mΩ 93 570 600 2000 95 4.04 TJ = -40°C to 125°C 4.02 10 TJ = 25°C TJ = -40°C to 125°C TJ = 25°C TJ = -40°C to 125°C 0.4 7.5 4.3 3.2 1.28 1.26 120 100 6.2 1.4 170 8 1.5 1.52 220 240 10 0.85 0.84 0.64 0.63 4.2 660 0.9 0.7 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. fSW kHz ns 606 612 1212 1218 50 2 560 INUVHYS 1200 kHz % 40 600 μA A 0.5 200 TJ = 25°C PGVth-Lo Units 1 594 588 1188 1182 PGVth-Hi Max 26 11 TJ = 25°C VFB TJ = -40°C to 85°C (8) VOUT=1.2V TJ = 25°C VOUT=1.2V TJ = -40°C to 85°C (8) IFB VFB = 620mV VADD_H VADD_L VEN = 0V, TJ = 25°C IEN_PU VEN= 0V, TJ= -40°C to 125°C TJ = 25°C VEN_Rise TJ = -40°C to 125°C TJ = 25°C VEN_HYS TJ = -40°C to 125°C ENtd-off INUVVth Typ mV mV nA V V μA V mV μs 4.36 4.38 740 0.94 0.95 0.73 0.74 V mV VOUT VOUT 4 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, TJ = -40°C to 125°C(7), unless otherwise noted, typical value is based on average value when TJ=25oC. Parameter Symbol Power Good Deglitch time PGTd OVP Discharge Resistor ROV OVP Rising Threshold OVP Falling Threshold VEN_Rise VEN_Fall Soft-Start Current iSS VCC Voltage VCC Thermal Shutdown Thermal Hysteresis (8) Min From VOUT pin to GND VOUT and FB pins, TJ =25°C VOUT and FB pins, TJ = -40°C to 125°C VOUT and FB pins TJ = -40°C to 125°C ICC=5mA VCC Load Regulation (8) Condition Typ Max Units 100 160 μs 35 70 Ω 114% 126% 120% 113% VREF 127% 101% 105% 108% 7 10 12 VREF μA 4.75 4.95 5.1 V 1 3 % °C °C TTSD 160 TTSD_HYS 20 Notes: 7) Not tested in production and guaranteed by over-temperature correlation. 8) Guaranteed by Design and Characterization Test. MP8868 Rev.1.1 5/15/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 5 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER I/O Level Characteristics Parameter Symbol Low-level input voltage VIL High-level input voltage VIH Hysteresis of Schmitt trigger inputs Low-level output voltage(Open drain) at 3mA sink current Low-level output current Condition LS-Mode Min Max 0.3V -0.5 Bus Units V 0.7 VBus VBus+ 0.5 - 0.05 VBus - VBus<2V 0.1 VBus - 0.1 VBus - VBus>2V 0 0.4 0 0.4 VBus<2V 0 0.2 VBus 0 0.2VB - 3 - 3 mA - 50 - 50 Ω VBus>2V VHYS VOL HS-Mode Min Max 0.3 -0.5 VBus 0.7 VBus+ 3VBus 0.5 IOL 0.05V Bus V V V us Transfer gate on resistance for currents between SDA and SCAH, or SCL and SCLH RonL VOL level, IOL=3mA Transfer gate on resistance between SDA and SCAH, or SCL and SCLH RonH Both signals (SDA and SDAH, or SCL and SCLH) at VBus level 50 - 50 - kΩ Pull-up current of the SCLH current source Ics SCLH output levels between 0.3VBus and 0.7VBus 2 6 2 6 mA Capacitive load from 10pF to 100pF 10 40 ns Capacitive load of 400pF 20 80 ns Capacitive load from 10pF to 100pF 10 40 ns Capacitive load of 400pF 20 80 20 250 ns Capacitive load from 10pF to 100pF 10 80 - - ns Capacitive load of 400pF 20 160 20 250 ns Capacitive load from 10pF to 100pF 10 80 - - ns Capacitive load of 400pF 20 160 20 250 ns 0 10 0 50 ns - 10 -10 +10 uA - 10 - 10 pF Rise time of the SCLH or SCL signal Fall time of the SCLH or SCL signal Rise time of SDAH signal Fall time of SDAH signal Pulse width of spikes that must be suppressed by the input filter trCL tfCL trDA tfDA Output rise time (current source enabled) with an external pullup current source of 3mA Output fall time (current source enabled) with an external pullup current source of 3mA tSP Input current each I/O pin Ii Capacitance for each I/O pin Ci Input voltage between 0.1VBus and 0.9VBus Notes: VBus is the I2C Bus Voltage, 3.0V to 3.6V range, 3.3V typical MP8868 Rev.1.1 5/15/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 6 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER I2C Port Signal Characteristics Parameter Symbol Condition SCLH and SCL clock frequency Set-up time for a repeated START condition Hold time (repeated) START condition Low period of the SCL clock High period of the SCL clock Data set-up time Data hold time Rise time of SCLH signal Rise time of SCLH signal after a repeated START condition and after an acknowledge bit Fall time of SCLH signal Rise time of SDAH signal Fall time of SDAH signal Set-up time for STOP condition Bus free time between a STOP and START condition Data Valid Time Data valid acknowledge time Capacitive load for each bus line Noise margin at the LOW level Noise margin at the HIGH level Cb=100pF Min Max Cb=400pF Min Max Units fSCHL 0 3.4 0 0.4 MHz TSU;STA 160 - 600 - ns THD;STA 160 - 600 - ns 160 60 10 0 70 1300 600 100 0 - ns ns ns ns 10 40 20*0.1Cb 300 ns 10 80 20*0.1Cb 300 ns 10 40 20*0.1Cb 300 ns 10 80 20*0.1Cb 300 ns tLOW tHIGH TSU:DAT THD;DAT trCL tfCL1 TfCL tfDA TfDA TSU;STO 10 80 20*0.1Cb 300 ns 160 - 600 - ns TBUF 160 - 1300 - ns TVD;DAT TVD;ACK Cb - 16 160 100 - 90 900 400 ns ns pF - 400 - 400 pF - 0.1VBus 0.1VBus - V - 0.2VBus 0.2VBus - V Ci VnH SDAH and SCLH line SDAH+SDA line and SCLH+SCL line For each connected device For each connected device Notes: VBus is the I2C Bus Voltage, 3.0V to 3.6V range, 3.3V typical MP8868 Rev.1.1 5/15/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 7 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 1V, L = 1.5µH, TA = 25°C, unless otherwise noted. 700 650 600 550 500 450 400 350 300 4.5 6 7.5 9 10.5 12 13.5 15 16.5 15 14 13 12 11 10 9 8 7 6 5 4 4.5 6 7.5 9 10.5 12 13.5 15 16.5 1.6 618 1.55 614 1.5 610 1.35 1.3 1.25 1.2 -40 -20 0 20 40 60 80 100 120125 4.2 4.15 4.1 4.05 4 -40 -20 0 500 594 460 590 440 586 420 582 -40 -20 0 16 15.5 20 40 60 80 100 120125 520 480 16 20 40 60 80 100 120125 400 -40 -20 0 20 40 60 80 100 120125 15 14 14.5 13 14 12 13.5 11 10 13 9 12.5 8 10 4.25 598 17 15 4.3 540 602 1.4 4.35 560 606 1.45 4.4 20 MP8868 Rev.1.1 5/15/2015 30 40 50 60 70 12 -40 -20 0 20 40 60 80 100 120125 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 8 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 1V, L = 1.5µH, TA = 25°C, unless otherwise noted. MP8868 Rev.1.1 5/15/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 9 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board of the Design Example section. VIN = 12V, VOUT = 1V, L = 1.5µH, TA = 25°C, unless otherwise noted. VOUT 500mV/div. VOUT 500mV/div. VPG 5V/div. VPG 5V/div. VSW 10V/div. VSW 10V/div. IL 10A/div. IL 10A/div. VOUT 500mV/div. VEN 5V/div. VPG 5V/div. VSW 10V/div. VOUT 500mV/div. VEN 5V/div. VPG 5V/div. IL 10A/div. VSW 10V/div. IL 5A/div. VOUT 500mV/div. VEN 5V/div. VPG 5V/div. VSW 10V/div. IL 5A/div. VOUT 500mV/div. VEN 5V/div. VPG 5V/div. VSW 10V/div. IL 10A/div. VOUT 500mV/div. VIN 10V/div. VOUT 500mV/div. VIN 10V/div. VPG 5V/div. VSW 10V/div. IL 5A/div. MP8868 Rev.1.1 5/15/2015 VOUT 500mV/div. VIN 10V/div. VPG 5V/div. VSW 10V/div. IL 10A/div. VPG 5V/div. VSW 10V/div. IL 5A/div. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 10 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board of the Design Example section. VIN = 12V, VOUT = 1V, L = 1.5µH, TA = 25°C, unless otherwise noted. VOUT/AC 10mV/div. VOUT/AC 10mV/div. VOUT 500mV/div. VIN 5V/div. VPG 5V/div. VSW 10V/div. VIN/AC 100mV/div. VIN/AC 10mV/div. VSW 10V/div. VSW 10V/div. IL 10A/div. IL 5A/div. VOUT/AC 100mV/div. VOUT 500mV/div. VPG 5V/div. VSW 10V/div. IL 5A/div. VOUT 500mV/div. VPG 5V/div. VSW 10V/div. IL 5A/div. MP8868 Rev.1.1 5/15/2015 IL 500mA/div. VOUT 500mV/div. VPG 5V/div. VSW 10V/div. IL 2A/div. IL 2A/div. VOUT 500mV/div. VPG 5V/div. VSW 10V/div. IL 5A/div. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 11 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER PIN FUNCTIONS QFN14 PIN# Name 1 BST Bootstrap. Requires a capacitor between SW and BST pins to form a floating supply across the high-side switch driver. 2 SW Switch Output. Connect using a wide PCB trace. 3 SCL I2C Serial Clock. 4 SDA I2C Serial Data. 5 EN/SYNC 6 A0 7 PG 8 PGND 9 VIN 10 VOUT 11 FB 12 SS 13 VCC 14 AGND MP8868 Rev.1.1 5/15/2015 Description EN high to enable the MP8868. EN pin has internal 5.4uA pull-up current to 5V, so it can auto startup when EN floating. Apply an external clock can to the EN pin to change the switching frequency. I2C address set pin. Left this pin float or pull it to VCC can set one address. Pull A0 pin to ground can set another different address. Power Good Indication. Open drain structure. PG switches low if the output voltage is out of regulation window. PG only indicates UV condition. System Power Ground. Reference ground of the regulated output voltage. Requires special consideration during PCB layout. Connect to ground plane with copper traces and vias. Supply Voltage. The MP8868 operates from a 4.5V-to-17V input rail. Requires ceramic capacitor to decouple the input rail. Connect using a wide PCB trace. Sense input of output voltage. Connect it to the positive terminal of loading. Feedback. Connect to the tap of an external resistor divider from the output to GND to set the output voltage in FB control loop. Soft start pin. Connect a capacitor from SS to ground can set the soft start time. Internal LDO regulator output. Decouple with 0.47µF capacitor. Signal Ground. AGND is not internally directly connected to System Ground, make sure AGND connected to system Ground in PCB layout. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 12 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER FUNCTIONAL BLOCK DIAGRAM VIN SCL I2C IF & Registers DAC SDA A0 EN/SYNC 55 VOUT PGND FB SS PG AGND Figure 1: Functional Block Diagram MP8868 Rev.1.1 5/15/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 13 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER OPERATION The MP8868 is a high-frequency, synchronous, rectified, step-down, switch-mode converter with built-in power MOSFETs. It offers a very compact solution that achieves a 10A output current with excellent load and line regulation over a wide input supply range. The MP8868 has three working modes: CCM (Continues-Conduction Mode), AAM mode (Advanced Asynchronous Modulation) and DCM (Discontinues-Conduction Mode). The MP8868 default operation mode is CCM. When set MODE bit(reg01[0]) in the I2C register to “0”. MP8868 can works in the AAM mode. CCM Control Operation In CCM the internal clock initiates the PWM cycle, the HS-FET turns on and remains on until VILsense reaches the value set by VCOMP, after a period of dead time, the LS-FET will turn on and remain on until the next clock cycle starts. The device will repeat the same operation in every clock cycle to regulate the output voltage. If within 95% (500kHz switching frequency) of one PWM period, VILsense does not reach the value set by VCOMP, the HS power MOSFET is forced off. AAM Control Operation In the light load condition, MP8868 works in AAM (Advanced Asynchronous Modulation) mode if Mode bit is set to “0”. Refer to Figure 2, the VAAM is an internal fixed voltage when input and output voltages are fixed. VCOMP is the error amplifier output which represents the peak inductor current information. When VCOMP is lower than VAAM, the internal clock is blocked, thus the MP8868 skips some pulses and achieves the light load power save. Refer to AN032 for more detail. The internal clock resets every time when VCOMP is higher than VAAM. At the same time the HSFET(High-Side MOSFET) turns on and remains on until VILsense reaches the value set by VCOMP. The light load feature in this device is optimized for 12V input applications. MP8868 Rev.1.1 5/15/2015 Figure 2: Simplified AAM Control Logic DCM Control Operation The VCOMP voltage ramps up with the increasing of the output current, when its minimum value exceeds VAAM, the device will enter DCM (Discontinues-Conduction Mode). In this mode the internal clock initiates the PWM cycle, the HS-FET turns on and remains on until VILsense reaches the value set by VCOMP, after a period of dead time, the LS-FET (Low-Side MOSFET) will turn on and remain on until the inductor current value decreases to zero. The device will repeat the same operation in every clock cycle to regulate the output voltage. IL Figure 3: DCM Control Operation VCC Regulator A 5V internal regulator powers most of the internal circuitries. This regulator takes the VIN input and operates in the full VIN range. When VIN is greater than 5.0V, the output of the regulator is in full regulation. When VIN is lower than 5.0V, the output voltage decreases and follows the input voltage. A 0.47μF ceramic capacitor for decoupling purpose is required. Error Amplifier The error amplifier compares the FB pin voltage against the internal reference (REF) for FB control loop and outputs the COMP voltage— which controls the power MOSFET current. In I2C mode, the FB pin is opened and VOUT pin is connected to the EA non-inverter input. The optimized internal compensation network www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 14 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER minimizes the external component count and simplifies the control loop design. EN/SYNC Control EN/SYNC is a digital control pin that turns the regulator including I2C block on and off. Drive EN/SYNC high to turn on the regulator; drive it low to turn it off. An internal 5.4µA pull-up current to 5V power supply allows auto startup when EN/SYNC pin is floating. The EN/SYNC pin is clamped internally using a 5.7 V series-Zener-diode as shown in Figure 4. Connecting the EN/SYNC input pin through a pull-up resistor to the voltage on the VIN pin limits the EN/SYNC input current to less than 100µA. For example, with 12V connected to Vin, RPULLUP ≥ (12V – 5.7V) ÷ 100µA = 63kΩ. Connecting the EN/SYNC pin is directly to a voltage source without any pullup resistor requires limiting the amplitude of the voltage source to ≤5.5V to prevent damage to the Zener diode. Figure 4: 5.7V Zener Diode Connection For external clock synchronization, connect a clock with a frequency range between 200kHz and 2MHz to EN/SYNC pin. The internal clock rising edge will synchronize with the external clock rising edge once external clock is present. Set the external clock signal with a pulse width less than 80% of one internal clock cycle time. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) protects the chip from operating at insufficient supply voltage. The MP8868 UVLO comparator monitors the output voltage of the internal regulator, VCC. The UVLO rising threshold is about 4.2V while its falling threshold is 3.54V. Soft-Start The MP8868 employs soft start (SS) mechanism to ensure smooth output during power-up. When the EN pin becomes high, an internal current source (10μA) charges up the MP8868 Rev.1.1 5/15/2015 SS capacitor. The SS capacitor voltage takes over the REF voltage to the PWM comparator. The output voltage smoothly ramps up with the SS voltage. Once the SS voltage reaches the same level as the REF voltage, it keeps ramping up while VREF takes over the PWM comparator. At this point, the soft start finishes and it enters into steady state operation. The SS capacitor value can be determined as follows: CSS ( nF ) = TSS ( ms ) × ISS ( μA ) VREF ( V ) If the output capacitors have large capacitance value, it’s not recommended to set the SS time too small. Otherwise, it’s easy to hit the current limit during SS. Pre-Bias Startup The MP8868 has been designed for monotonic startup into pre-biased output voltage. If the output is pre-biased to a certain voltage during startup, the voltage on the soft-start capacitor will be charged. When the soft-Start capacitor’s voltage exceeds the sensed output voltage at the FB pin (9), the part starts to turn on high side and low side power switches sequentially. Output voltage starts to ramp up following with soft-start slew rate. Note: 2 9) FB pin voltage in FB control loop, or VOUT pin voltage in I C control loop. Power Good Indicator The MP8868 has power good (PG) output used to indicate whether the output voltage of the module is ready or not. The PG pin is an open drain output. Connect PG pin to VCC or other voltage source through a pull up resistor (e.g. 100kΩ). When the input voltage is applied, the PG pin is pulled down to GND. When VFB(9) is above 90% of VREF, the PG pin will be pulled high after 100us delay time. During normal operation, the PG pin will be pulled low when the VFB(9). drops below 70% of VREF after 100us delay. When UVLO or OTP happens, the PG pin will be pulled low immediately; When OC(Over current) happens, the PG pin will be pulled low www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 15 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER when VFB(9). drops below 70% of VREF after 100us delay. threshold, typically 140°C, the chip is enabled again. The PG won’t response to output over voltage condition. Floating Driver and Bootstrap Charging An external bootstrap capacitor powers the floating power MOSFET driver. This floating driver has its own UVLO protection. This UVLO’s rising threshold is 2.2V with a hysteresis of 150mV. The bootstrap capacitor voltage is regulated internally by VIN through D1, M1, C5, L1 and C2 (Figure ). If (VIN-VSW) exceeds 5V, U1 will regulate M1 to maintain a 5V BST voltage across C5. The PG bit in the I2C register have the same indication as the external PG pin. Output over Voltage Protection (OVP) MP8868 monitors both FB pin and VOUT pin to detect over voltage event. When “V_BOOT” bit=1, internal comparator monitors FB pin while “V_BOOT” bit=0, it monitors VOUT pin. When the feedback voltage becomes higher than 120% of the internal reference voltage, the controller will enter linear discharge mode. During this period, there is a 35Ω resistor connected between VOUT pin and ground, this will then discharge the output and try to keep it within the normal range. Once output voltage falls lower than 105% of reference, controller exits linear discharge mode. Over-Current-Protection and Hiccup The MP8868 has a cycle-by-cycle over-current limit. When the inductor current peak value exceeds the set current limit threshold, the HSFET will turn off and the LS-FET will turn on and remains on until the inductor current falls below the internal “valley” current limit threshold. The “valley” current limit circuit is employed to decrease the operation frequency after the “peak” current limit threshold is triggered. Meanwhile, the output voltage drops until VFB(9) is below the Under-Voltage (UV) threshold— typically 30% below the reference. Once UV is triggered, the MP8868 enters hiccup mode to periodically restart the part. This protection mode is especially useful when the output is dead-shorted to ground. The average short circuit current is greatly reduced to alleviate thermal issues and to protect the regulator. The MP8868 exits the hiccup mode once the overcurrent condition is removed. Thermal Shutdown Thermal shutdown prevents the chip from operating at exceedingly high temperatures. When the silicon die reaches temperatures that exceed 160°C, it shuts down the whole chip. When the temperature is less than its lower MP8868 Rev.1.1 5/15/2015 Figure 5: Internal Bootstrap Charging Circuit Startup and Shutdown If both VIN and EN exceed their respective thresholds, the chip starts. The reference block starts first, generating stable reference voltage and currents, and then the internal regulator is enabled. The regulator provides a stable supply for the remaining circuitries. Three events can shut down the chip: EN low, VIN low, and thermal shutdown. In the shutdown procedure, the signaling path is first blocked to avoid any fault triggering. The COMP voltage and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command. I2C Control and Default Output Voltage When the MP8868 is enabled which means EN=high and VIN>UVLO, the chip starts up to an output voltage which is set by FB feedback resistors with programmed soft-start time. After that, the I2C bus can communicate with master. If the chip doesn’t receive I2C communication signal all the time, it works well through FB pin feedback and performs the similar behavior as traditional non-I2C part. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 16 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER Once the I2C receives valid output reference voltage scaling instruction, if V_BOOT=“1”, output voltage is determined by the resistor divider R1, R2 and VREF voltage. VOUT value can be calculated by following equation (VREF default value is 0.6V): VOUT = VREF × (1 + R1 ) R2 If V_BOOT=“0”, the output voltage will be determined by I2C control and the FB feedback loop is disabled. The output reference voltage scaling is realized by adjusting internal reference voltage V_REF which is the non-invert input of error amplifier. After MP8868 receives a valid data byte of output reference voltage setting, it searches the corresponding reference voltage from the truth table and then sends the command of adjusting Vref with controlled slew rate. The slew rate is determined by 3 bits of another register which can be read and write accordingly. MP8868 Rev.1.1 5/15/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 17 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER I2C INTERFACE I2C Serial Interface Description I2C is a 2-wire, bidirectional serial interface, consisting of a data line (SDA) and a clock line (SCL). The lines are externally pulled to a bus voltage when they are “idle”. Connecting to the line, a master device generates the SCL signal and device address and arranges the communication sequence. MP8868 interface is an I2C slave. The I2C interface adds flexibility to the power supply solution. The output voltage, transition slew rate or other interesting parameters can be instantaneously controlled by I2C interface. The default I2C address of MP8868 is “62” (HEX) or “1100010” (BINARY) and is “6A” (HEX) or “1101010” if pull A0 pin to ground. Data validity One clock pulse is generated for each data bit transferred. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (see Figure.6). SDA SCL data line stable; data valid change of data allowed Figure 6: Bit transfer on the I2C-bus The START and STOP are signaled by the master device which signifies the beginning and the end of the I2C transfer. The START condition is defined as the SDA signal transitioning from HIGH to LOW while the SCL is HIGH. The STOP condition is defined as the SDA signal transitioning from LOW to HIGH while the SCL is HIGH as shown in Figure 7. SDA SDA SCL SCL S P START condition STOP condition Figure 7: START and STOP Conditions MP8868 Rev.1.1 5/15/2015 START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again after a minimum of 4.7uS after the STOP condition. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. The START (S) and repeated START (Sr) conditions are functionally identical. Transfer Data Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. Data transfers follow the format shown in Figure 8. After the START condition (S), a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W) - a ‘zero’ indicates a transmission (WRITE), a ‘one’ indicates a request for data (READ). A data transfer is always terminated by a STOP condition (P) generated by the master. However, if a master still wishes to communicate on the bus, it can generate a repeated START condition (Sr) and address another slave without first generating a STOP condition. SDA SCL 1 7 8 9 R/W ACK 1 7 8 9 1 7 8 9 P S START condition ADDRESS DATA ACK DATA ACK STOP condition Figure 8: A complete data transfer The MP8868 requires a start condition, a valid I2C address, a register address byte, and a data byte for a single data update. After receipt of each byte, MP8868 acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the MP8868. MP8868 performs an update on the falling edge of the LSB byte. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 18 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER REGISER DESCRIPTION Register Map ADD 00 NAME VSEL R/W R/W D7 V_BOOT 01 SysCntlreg1 R/W EN 02 03 ID1 Status R R D6 D5 GO_BIT Vendor ID Reserved D4 D3 D2 D1 Output Reference Switching Slew Rate Frequency Die id VID_OK OC OTEW OT D0 Mode PG Register Description 1. Reg00 VSEL NAME BITS DEFAULT V_BOOT D7 1 Output Reference D[6:0] 0000000 DESCRIPTION “FB” control loop enable bit. V_BOOT=”1” means the output voltage is determined by resistor divider connecting to “FB” (FB control loop). V_BOOT=”0” means the output voltage is controlled by I2C through “VOUT” (I2C control loop). This bit is helpful for the default output voltage setting before I2C signal comes. If the I2C is not used, the part works well with “FB” pin. Set output voltage from 0.6V to 1.87V as Table 1. Default value is 0.6V. Table 1 Output Voltage Chart D[6:0] 000 0000 000 0001 000 0010 000 0011 000 0100 000 0101 000 0110 000 0111 000 1000 000 1001 000 1010 000 1011 000 1100 000 1101 000 1110 000 1111 001 0000 001 0001 001 0010 001 0011 001 0100 001 0101 001 0110 001 0111 001 1000 001 1001 001 1010 001 1011 001 1100 001 1101 001 1110 001 1111 MP8868 Rev.1.1 5/15/2015 VOUT 0.60 0.61 0.62 0.63 0.64 0.65 0.66 0.67 0.68 0.69 0.70 0.71 0.72 0.73 0.74 0.75 0.76 0.77 0.78 0.79 0.80 0.81 0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.90 0.91 D[6:0] 010 0000 010 0001 010 0010 010 0011 010 0100 010 0101 010 0110 010 0111 010 1000 010 1001 010 1010 010 1011 010 1100 010 1101 010 1110 010 1111 011 0000 011 0001 011 0010 011 0011 011 0100 011 0101 011 0110 011 0111 011 1000 011 1001 011 1010 011 1011 011 1100 011 1101 011 1110 011 1111 VOUT 0.92 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11 1.12 1.13 1.14 1.15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 D[6:0] 100 0000 100 0001 100 0010 100 0011 100 0100 100 0101 100 0110 100 0111 100 1000 100 1001 100 1010 100 1011 100 1100 100 1101 100 1110 100 1111 101 0000 101 0001 101 0010 101 0011 101 0100 101 0101 101 0110 101 0111 101 1000 101 1001 101 1010 101 1011 101 1100 101 1101 101 1110 101 1111 VOUT 1.24 1.25 1.26 1.27 1.28 1.29 1.30 1.31 1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 1.40 1.41 1.42 1.43 1.44 1.45 1.46 1.47 1.48 1.49 1.50 1.51 1.52 1.53 1.54 1.55 D[6:0] 110 0000 110 0001 110 0010 110 0011 110 0100 110 0101 110 0110 110 0111 110 1000 110 1001 110 1010 110 1011 110 1100 110 1101 110 1110 110 1111 111 0000 111 0001 111 0010 111 0011 111 0100 111 0101 111 0110 111 0111 111 1000 111 1001 111 1010 111 1011 111 1100 111 1101 111 1110 111 1111 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. VOUT 1.56 1.57 1.58 1.59 1.60 1.61 1.62 1.63 1.64 1.65 1.66 1.67 1.68 1.69 1.70 1.71 1.72 1.73 1.74 1.75 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1.84 1.85 1.86 1.87 19 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER 2. Reg01 SysCntlreg1 NAME BITS DEFAULT EN D[7] 1 GO_BIT D[6] 0 Slew Rate D[5:3] 100 Switching Frequency D[2:1] 00 Mode D0 1 DESCRIPTION I2C controlled turn-on or turn-off the part. When external EN pin is low, the converter is off and I2C is also shutdown. When EN pin is high, the EN bit will take over. The default EN bit is “1”. Switch bit of I2C writing authority for output reference command only. Set GO_BIT=”1” to enable the I2C authority of writing output reference. When the command is finished, GO_BIT will auto reset to “0” to prevent false operation of VOUT scaling. If reference adjust is within 50mV, GO_BIT won’t be auto reset to “0”. In this case need manually set GO_BIT to “0”. Suggest writing GO_BIT=”1” first, then write the output reference voltage. D[5:3] SLEW RATE D[5:3] SLEW RATE 000 64 mV/uS 100 4 mV/uS 001 32 mV/uS 101 2 mV/uS 010 16 mV/uS 110 1 mV/uS 011 8 mV/uS 111 0.5 mV/uS D[2:1] Fs 00 500kHz 01 750KHz 10 1MHz 11 1.5MHz A “0” enables PFM mode, a high disables PFM mode. Default in force CCM. 3. Reg02 ID1 NAME Vendor ID IC Revision ID BITS D[7:4] DESCRIPTION 1000 D[3:0] IC Revision 4. Reg03 Status NAME Reserved VID_OK BITS D[7:5] D[4] OC OTEW D[3] OT D[1] PG D[0] MP8868 Rev.1.1 5/15/2015 D[2] DESCRIPTION Reserved for future use. Always set at 0 I2C controlled voltage adjustment is done. Internal circuit compares DAC output with “VOUT” pin voltage, if “VOUT” is in the 90%-110% range of DAC output, VID_OK bit is high which means the voltage scaling is finished. Otherwise, VID_OK=”0”. VID_OK compares DAC with VOUT/FB. UV 90%+-3%, OV 110%+-3% Output over current indication. When bit is high, IC is in hiccup mode. Die temperature early warning bit. When the bit is high, the die temperature is higher than 120˚C. Over temperature indication. When bit is high the IC is in thermal shutdown Output power good indication. When bit is high the VOUT power is good now. It means the VOUT is higher than 90% of designed regulation voltage. See details in “Power Good Indicator” Section. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 20 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER APPLICATION INFORMATION Setting the Output Voltage in FB control Loop Reference voltage and external resistor divider and can set the output voltage through FB. The feedback resistor R1 and R3 also sets the feedback loop bandwidth with the internal compensation capacitor. Choose R1 value firstly, R2 is then given by (10): R2 = R1 VOUT −1 VREF Notes: 10) VREF is 0.6V when Power up or EN on. After MP8868 is 2 enabled, VREF can be programmed through I C. Set V_BOOT=1 to enable FB control loop. The T-type network (as shown in Figure 10) is highly recommended. Setting the Output Voltage in I2C control Loop Besides setting the output voltage through FB loop, I2C loop also can set the output voltage through VOUT pin by setting V_BOOT=0. In this case, output voltage is the set reference voltage. Please refer to Table 1 for more details about output voltage setting. Output Voltage Dynamic Scale To dynamic scale the output voltage during MP8868 normal operating, it suggests following below two steps and referring to the Figure 10: Step1: Write the GO_Bit (reg01[6]) to “1”; Step2: Write reg00 to select the feedback loop by setting V_BOOT(reg00[7]) and set reference voltage by Output Reference (reg00[0:6]) simultaneously. If reference adjust is within 50mV, GO_BIT won’t be auto reset to “0”, in this case it needs manually set GO_BIT to “0”. Repeat above two steps if need dynamic scale to other voltage. Voltage Scaling Start Figure 9: T-Type Network Table 2 lists the recommended feedback resistors value for common output voltages. Table 2: Resistor Selection for Common Output Voltages with Default 0.6V VREF(11) R1 R2 R3 C6 L VOUT (V) (kΩ) (kΩ) (kΩ) (pF) (µH) 80.6 162 51 0.9 22 1.5 (1%) (1%) (1%) 80.6 120 51 1.0 22 1.5 (1%) (1%) (1%) 80.6 80.6 40.2 1.2 22 1.5 (1%) (1%) (1%) 60.4 19.1 30 2.5 22 2.2 (1%) (1%) (1%) 60.4 13.3 20 3.3 33 3.3 (1%) (1%) (1%) 60.4 8.25 20 5 33 3.3 (1%) (1%) (1%) Write reg01[6] “GO_Bit”=1 Loop selection FB control loop (FB pin sense feedback) Write reg00(Set “V_BOOT”=1 & “Vref” code) I2C control loop (VOUT pin direct sense feedback) Write reg00(Set “V_BOOT”=0 & “Vref” code) Note: 11) The recommended parameters is basing on 12V input voltage and 22µFx4 output capacitor, different input voltage and output capacitor value may affect the selection of R1, R2, R3, C6. For other components’ parameters, please refer to TYPICAL APPLICATION CIRCUITS on page 26. MP8868 Rev.1.1 5/15/2015 Figure 10: Output Voltage Dynamic Scale Flow Chart www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 21 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER Selecting the Inductor Use a 0.47µH-to-10µH inductor with a DC current rating of at least 25% percent higher than the maximum load current for most applications. For highest efficiency, use an inductor with a DC resistance less than 15mΩ. For most designs, the inductance value can be derived from the following equation. L1 = VOUT × (VIN − VOUT ) VIN × ΔIL × fOSC The input capacitor can be electrolytic, tantalum or ceramic. When using electrolytic or tantalum capacitors, add a small, high quality ceramic capacitor (e.g. 0.1μF) placed as close to the IC as possible. When using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at input. The input voltage ripple caused by capacitance can be estimated by: ΔVIN = Where ΔIL is the inductor ripple current. Choose the inductor ripple current to be approximately 30% of the maximum load current. The maximum inductor peak current is: IL(MAX) = ILOAD + ΔIL 2 Use a larger inductor for improved efficiency under light-load conditions—below 100mA. Selecting the Input Capacitor The input current to the step-down converter is discontinuous, therefore requires a capacitor is to supply the AC current to the step-down converter while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Use ceramic capacitors with X5R or X7R dielectrics for best results because of their low ESR and small temperature coefficients. For most applications, use two piece 22µF capacitors. Since C1 absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated by: I C1 = ILOAD VOUT ⎛⎜ VOUT × 1− × VIN ⎜⎝ VIN ⎞ ⎟ ⎟ ⎠ The worse case condition occurs at VIN = 2VOUT, where: I C1 = ILOAD 2 For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load current. MP8868 Rev.1.1 5/15/2015 ILOAD VOUT ⎛ VOUT ⎞ × × ⎜1− ⎟ fS × C1 VIN ⎝ VIN ⎠ Selecting the Output Capacitor The output capacitor (C2) maintains the DC output voltage. Use ceramic, tantalum, or lowESR electrolytic capacitors. For best results, use low ESR capacitors to keep the output voltage ripple low. The output voltage ripple can be estimated by: ΔVOUT = ⎞ VOUT ⎛ VOUT ⎞ ⎛ 1 × ⎜1− ⎟ ⎟ × ⎜ RESR + fS × L1 ⎝ VIN ⎠ ⎝ 8 × fS × C2 ⎠ Where L1 is the inductor value and RESR is the equivalent series resistance (ESR) value of the output capacitor. For ceramic capacitors, the capacitance dominates the impedance at the switching frequency, and the capacitance causes the majority of the output voltage ripple. For simplification, the output voltage ripple can be estimated by: ΔVOUT = ⎛ V ⎞ VOUT × ⎜ 1 − OUT ⎟ VIN ⎠ 8 × fS × L1 × C2 ⎝ 2 For tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated to: ΔVOUT = VOUT ⎛ VOUT × 1− fS × L1 ⎜⎝ VIN ⎞ ⎟ × RESR ⎠ The characteristics of the output capacitor also affect the stability of the regulation system. The MP8868 can be optimized for a wide range of capacitance and ESR values. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 22 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER 4. Put the decoupling capacitor as close to the VCC and GND pins as possible. 5. The external feedback resistors should be placed next to the FB pin. Make sure that there is no via on the FB trace. 6. Keep the switching node SW short and away from the feedback network. 7. Keep the BST voltage path (BST, C5, and SW) as short as possible. 8. Four-layer layout is strongly recommended to achieve better thermal performance. PC Board Layout (12) PCB layout is very important for stable operation. Follow these guidelines for best results. 1. The high current paths (PGND, VIN, and SW) should be placed very close to the device with short, direct and wide traces. 2. Keep the IN and GND pads connected with large copper and use at least two layers for IN and GND trace to achieve better thermal performance. Also, add several Vias close to the IN and GND pads to help on thermal dissipation. 3. Put the input capacitors as close to the VIN and GND pins as possible. Notes: 12) The recommended layout is based on the Figure 13 Typical Application circuit in page26. DO NOT CONNECT TO PGND HERE R2 AGND KELVIN CONNECT TO PGND AT VCC CAP C5 14 13 12 11 10 ANGD AGND VCC SS FB VOUT R4 C6 C3 R1 R3 C C4 R5 1BST VIN VIN 9 PGND 8 2 SW VIN C1 SW VOUT sense wire shouldn’t be too narrow, it will conduct output discharge current At least two layers should be applied for Vin and PGND and place >20 vias close to the part for a better thermal performance 3 10 L1 SCL SDA EN/ SYNC A0 PG 3 4 5 6 7 --Top Layer --Inner PGND Layer --Inner Layer2 --Bottom Vin Layer VOUT --Bottom Layer C2 --Via PGND --Via For AGND Figure 11: Recommend Layout MP8868 Rev.1.1 5/15/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 23 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER Design Example Below is a design example following the application guidelines for the specifications: Table 3 Design Example VIN VOUT IO 12V 1V 10A The detailed application schematics are shown in Figure 13. The typical performance and circuit waveforms have been shown in the Typical Performance Characteristics section. For more device applications, please refer to the related Evaluation Board Datasheets. MP8868 Rev.1.1 5/15/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 24 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER TYPICAL APPLICATION CIRCUITS (13) Figure 12: VIN=4.5-17V, VOUT=0.9V, IOUT=10A Figure 13: VIN=4.5-17V, VOUT=1V, IOUT=10A Figure 14: VIN=4.5-17V, VOUT=1.2V, IOUT=10A Notes: 13) All circuits are basing on 0.6V default reference voltage. MP8868 Rev.1.1 5/15/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 25 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER Figure 15: VIN=4.5-17V, VOUT=2.5V, IOUT=10A Figure 16: VIN=6-17V, VOUT=3.3V, IOUT=10A(14) R5 0Ω VIN 1 8V-17V C1 22µF 9 C1A 22µF C1B 0.1µF 5 13 C3 0.47μF EN PG SDA SCL A0 C5 0.1µF SW VCC VOUT C2 22µF VOUT 10 FB 11 SS 12 C2A 22µF C2B 22µF C2C 22µF MP8868 7 PG 4 SDA SCL A0 6 5V/10A 2 EN/SYNC R4 100kΩ 3 L1 3.3µH BST VIN AGND 14 R3 20kΩ R1 60.4kΩ C6 33pF R2 8.25kΩ PGND 8 C4 22nF Figure 17: VIN=8-17V, VOUT=5V, IOUT=10A(14) Notes: 14) Basing on Evaluation Board test result at 25℃ ambient temperature, lower input voltage will trigger over temperature protection with full load. MP8868 Rev.1.1 5/15/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 26 MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER PACKAGE INFORMATION QFN14 (3x4mm) NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP8868 Rev.1.1 5/15/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 27